1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains hardware definitions that are common between i.MX21 and
6 * i.MX27.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23 #ifndef __ASM_ARCH_MXC_MX2x_H__
24 #define __ASM_ARCH_MXC_MX2x_H__
25
26 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
27 #error "Do not include directly."
28 #endif
29
30 /* The following addresses are common between i.MX21 and i.MX27 */
31
32 /* Register offests */
33 #define AIPI_BASE_ADDR 0x10000000
34 #define AIPI_BASE_ADDR_VIRT 0xF4000000
35 #define AIPI_SIZE SZ_1M
36
37 #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
38 #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
39 #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
40 #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
41 #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
42 #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
43 #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
44 #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
45 #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
46 #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
47 #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
48 #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
49 #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
50 #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
51 #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
52 #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
53 #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
54 #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
55 #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
56 #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
57 #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
58 #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
59 #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
60 #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
61 #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
62 #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
63 #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
64 #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
65 #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
66 #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
67 #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
68 #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
69
70 #define AVIC_BASE_ADDR 0x10040000
71
72 #define SAHB1_BASE_ADDR 0x80000000
73 #define SAHB1_BASE_ADDR_VIRT 0xF4100000
74 #define SAHB1_SIZE SZ_1M
75
76 #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
77
78 /*
79 * This macro defines the physical to virtual address mapping for all the
80 * peripheral modules. It is used by passing in the physical address as x
81 * and returning the virtual address. If the physical address is not mapped,
82 * it returns 0xDEADBEEF
83 */
84 #define IO_ADDRESS(x) \
85 (void __force __iomem *) \
86 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
87 AIPI_IO_ADDRESS(x) : \
88 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
89 SAHB1_IO_ADDRESS(x) : \
90 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
91 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
92
93 /* define the address mapping macros: in physical address order */
94 #define AIPI_IO_ADDRESS(x) \
95 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
96
97 #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
98
99 #define SAHB1_IO_ADDRESS(x) \
100 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
101
102 #define CS4_IO_ADDRESS(x) \
103 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
104
105 #define X_MEMC_IO_ADDRESS(x) \
106 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
107
108 #define PCMCIA_IO_ADDRESS(x) \
109 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
110
111 /* fixed interrupt numbers */
112 #define MXC_INT_LCDC 61
113 #define MXC_INT_SLCDC 60
114 #define MXC_INT_EMMAPP 52
115 #define MXC_INT_EMMAPRP 51
116 #define MXC_INT_DMACH15 47
117 #define MXC_INT_DMACH14 46
118 #define MXC_INT_DMACH13 45
119 #define MXC_INT_DMACH12 44
120 #define MXC_INT_DMACH11 43
121 #define MXC_INT_DMACH10 42
122 #define MXC_INT_DMACH9 41
123 #define MXC_INT_DMACH8 40
124 #define MXC_INT_DMACH7 39
125 #define MXC_INT_DMACH6 38
126 #define MXC_INT_DMACH5 37
127 #define MXC_INT_DMACH4 36
128 #define MXC_INT_DMACH3 35
129 #define MXC_INT_DMACH2 34
130 #define MXC_INT_DMACH1 33
131 #define MXC_INT_DMACH0 32
132 #define MXC_INT_CSI 31
133 #define MXC_INT_NANDFC 29
134 #define MXC_INT_PCMCIA 28
135 #define MXC_INT_WDOG 27
136 #define MXC_INT_GPT1 26
137 #define MXC_INT_GPT2 25
138 #define MXC_INT_GPT3 24
139 #define MXC_INT_GPT INT_GPT1
140 #define MXC_INT_PWM 23
141 #define MXC_INT_RTC 22
142 #define MXC_INT_KPP 21
143 #define MXC_INT_UART1 20
144 #define MXC_INT_UART2 19
145 #define MXC_INT_UART3 18
146 #define MXC_INT_UART4 17
147 #define MXC_INT_CSPI1 16
148 #define MXC_INT_CSPI2 15
149 #define MXC_INT_SSI1 14
150 #define MXC_INT_SSI2 13
151 #define MXC_INT_I2C 12
152 #define MXC_INT_SDHC1 11
153 #define MXC_INT_SDHC2 10
154 #define MXC_INT_GPIO 8
155 #define MXC_INT_CSPI3 6
156
157 /* gpio and gpio based interrupt handling */
158 #define GPIO_DR 0x1C
159 #define GPIO_GDIR 0x00
160 #define GPIO_PSR 0x24
161 #define GPIO_ICR1 0x28
162 #define GPIO_ICR2 0x2C
163 #define GPIO_IMR 0x30
164 #define GPIO_ISR 0x34
165 #define GPIO_INT_LOW_LEV 0x3
166 #define GPIO_INT_HIGH_LEV 0x2
167 #define GPIO_INT_RISE_EDGE 0x0
168 #define GPIO_INT_FALL_EDGE 0x1
169 #define GPIO_INT_NONE 0x4
170
171 /* fixed DMA request numbers */
172 #define DMA_REQ_CSI_RX 31
173 #define DMA_REQ_CSI_STAT 30
174 #define DMA_REQ_UART1_TX 27
175 #define DMA_REQ_UART1_RX 26
176 #define DMA_REQ_UART2_TX 25
177 #define DMA_REQ_UART2_RX 24
178 #define DMA_REQ_UART3_TX 23
179 #define DMA_REQ_UART3_RX 22
180 #define DMA_REQ_UART4_TX 21
181 #define DMA_REQ_UART4_RX 20
182 #define DMA_REQ_CSPI1_TX 19
183 #define DMA_REQ_CSPI1_RX 18
184 #define DMA_REQ_CSPI2_TX 17
185 #define DMA_REQ_CSPI2_RX 16
186 #define DMA_REQ_SSI1_TX1 15
187 #define DMA_REQ_SSI1_RX1 14
188 #define DMA_REQ_SSI1_TX0 13
189 #define DMA_REQ_SSI1_RX0 12
190 #define DMA_REQ_SSI2_TX1 11
191 #define DMA_REQ_SSI2_RX1 10
192 #define DMA_REQ_SSI2_TX0 9
193 #define DMA_REQ_SSI2_RX0 8
194 #define DMA_REQ_SDHC1 7
195 #define DMA_REQ_SDHC2 6
196 #define DMA_REQ_EXT 3
197 #define DMA_REQ_CSPI3_TX 2
198 #define DMA_REQ_CSPI3_RX 1
199
200 #endif /* __ASM_ARCH_MXC_MX2x_H__ */
201
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