1 /*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5 /*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14 #ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
15 #define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
16
17 /*
18 * MXC UART EVB board level configurations
19 */
20 #define MXC_LL_UART_PADDR UART1_BASE_ADDR
21 #define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
22
23 /*
24 * Memory-mapped I/O on MX21ADS base board
25 */
26 #define MX21ADS_MMIO_BASE_ADDR 0xF5000000
27 #define MX21ADS_MMIO_SIZE SZ_16M
28
29 #define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
30 (MX21ADS_MMIO_BASE_ADDR + (offset))
31
32 #define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
33 #define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
34 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
35 #define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
36 #define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
37
38 /* MX21ADS_IO_REG bit definitions */
39 #define MX21ADS_IO_SD_WP 0x0001 /* read */
40 #define MX21ADS_IO_TP6 0x0001 /* write */
41 #define MX21ADS_IO_SW_SEL 0x0002 /* read */
42 #define MX21ADS_IO_TP7 0x0002 /* write */
43 #define MX21ADS_IO_RESET_E_UART 0x0004
44 #define MX21ADS_IO_RESET_BASE 0x0008
45 #define MX21ADS_IO_CSI_CTL2 0x0010
46 #define MX21ADS_IO_CSI_CTL1 0x0020
47 #define MX21ADS_IO_CSI_CTL0 0x0040
48 #define MX21ADS_IO_UART1_EN 0x0080
49 #define MX21ADS_IO_UART4_EN 0x0100
50 #define MX21ADS_IO_LCDON 0x0200
51 #define MX21ADS_IO_IRDA_EN 0x0400
52 #define MX21ADS_IO_IRDA_FIR_SEL 0x0800
53 #define MX21ADS_IO_IRDA_MD0_B 0x1000
54 #define MX21ADS_IO_IRDA_MD1 0x2000
55 #define MX21ADS_IO_LED4_ON 0x4000
56 #define MX21ADS_IO_LED3_ON 0x8000
57
58 #endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
59
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