1 /*
2 * linux/arch/arm/mach-sa1100/irq.c
3 *
4 * Copyright (C) 1999-2001 Nicolas Pitre
5 *
6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/ioport.h>
17 #include <linux/sysdev.h>
18
19 #include <asm/hardware.h>
20 #include <asm/mach/irq.h>
21
22 #include "generic.h"
23
24
25 /*
26 * SA1100 GPIO edge detection for IRQs:
27 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
28 * Use this instead of directly setting GRER/GFER.
29 */
30 static int GPIO_IRQ_rising_edge;
31 static int GPIO_IRQ_falling_edge;
32 static int GPIO_IRQ_mask = (1 << 11) - 1;
33
34 /*
35 * To get the GPIO number from an IRQ number
36 */
37 #define GPIO_11_27_IRQ(i) ((i) - 21)
38 #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
39
40 static int sa1100_gpio_type(unsigned int irq, unsigned int type)
41 {
42 unsigned int mask;
43
44 if (irq <= 10)
45 mask = 1 << irq;
46 else
47 mask = GPIO11_27_MASK(irq);
48
49 if (type == IRQT_PROBE) {
50 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
51 return 0;
52 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
53 }
54
55 if (type & __IRQT_RISEDGE) {
56 GPIO_IRQ_rising_edge |= mask;
57 } else
58 GPIO_IRQ_rising_edge &= ~mask;
59 if (type & __IRQT_FALEDGE) {
60 GPIO_IRQ_falling_edge |= mask;
61 } else
62 GPIO_IRQ_falling_edge &= ~mask;
63
64 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
65 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
66
67 return 0;
68 }
69
70 /*
71 * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
72 */
73 static void sa1100_low_gpio_ack(unsigned int irq)
74 {
75 GEDR = (1 << irq);
76 }
77
78 static void sa1100_low_gpio_mask(unsigned int irq)
79 {
80 ICMR &= ~(1 << irq);
81 }
82
83 static void sa1100_low_gpio_unmask(unsigned int irq)
84 {
85 ICMR |= 1 << irq;
86 }
87
88 static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
89 {
90 if (on)
91 PWER |= 1 << irq;
92 else
93 PWER &= ~(1 << irq);
94 return 0;
95 }
96
97 static struct irq_chip sa1100_low_gpio_chip = {
98 .name = "GPIO-l",
99 .ack = sa1100_low_gpio_ack,
100 .mask = sa1100_low_gpio_mask,
101 .unmask = sa1100_low_gpio_unmask,
102 .set_type = sa1100_gpio_type,
103 .set_wake = sa1100_low_gpio_wake,
104 };
105
106 /*
107 * IRQ11 (GPIO11 through 27) handler. We enter here with the
108 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
109 * and call the handler.
110 */
111 static void
112 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
113 {
114 unsigned int mask;
115
116 mask = GEDR & 0xfffff800;
117 do {
118 /*
119 * clear down all currently active IRQ sources.
120 * We will be processing them all.
121 */
122 GEDR = mask;
123
124 irq = IRQ_GPIO11;
125 desc = irq_desc + irq;
126 mask >>= 11;
127 do {
128 if (mask & 1)
129 desc_handle_irq(irq, desc);
130 mask >>= 1;
131 irq++;
132 desc++;
133 } while (mask);
134
135 mask = GEDR & 0xfffff800;
136 } while (mask);
137 }
138
139 /*
140 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
141 * In addition, the IRQs are all collected up into one bit in the
142 * interrupt controller registers.
143 */
144 static void sa1100_high_gpio_ack(unsigned int irq)
145 {
146 unsigned int mask = GPIO11_27_MASK(irq);
147
148 GEDR = mask;
149 }
150
151 static void sa1100_high_gpio_mask(unsigned int irq)
152 {
153 unsigned int mask = GPIO11_27_MASK(irq);
154
155 GPIO_IRQ_mask &= ~mask;
156
157 GRER &= ~mask;
158 GFER &= ~mask;
159 }
160
161 static void sa1100_high_gpio_unmask(unsigned int irq)
162 {
163 unsigned int mask = GPIO11_27_MASK(irq);
164
165 GPIO_IRQ_mask |= mask;
166
167 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
168 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
169 }
170
171 static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
172 {
173 if (on)
174 PWER |= GPIO11_27_MASK(irq);
175 else
176 PWER &= ~GPIO11_27_MASK(irq);
177 return 0;
178 }
179
180 static struct irq_chip sa1100_high_gpio_chip = {
181 .name = "GPIO-h",
182 .ack = sa1100_high_gpio_ack,
183 .mask = sa1100_high_gpio_mask,
184 .unmask = sa1100_high_gpio_unmask,
185 .set_type = sa1100_gpio_type,
186 .set_wake = sa1100_high_gpio_wake,
187 };
188
189 /*
190 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
191 * this is for internal IRQs i.e. from 11 to 31.
192 */
193 static void sa1100_mask_irq(unsigned int irq)
194 {
195 ICMR &= ~(1 << irq);
196 }
197
198 static void sa1100_unmask_irq(unsigned int irq)
199 {
200 ICMR |= (1 << irq);
201 }
202
203 /*
204 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
205 */
206 static int sa1100_set_wake(unsigned int irq, unsigned int on)
207 {
208 if (irq == IRQ_RTCAlrm) {
209 if (on)
210 PWER |= PWER_RTC;
211 else
212 PWER &= ~PWER_RTC;
213 return 0;
214 }
215 return -EINVAL;
216 }
217
218 static struct irq_chip sa1100_normal_chip = {
219 .name = "SC",
220 .ack = sa1100_mask_irq,
221 .mask = sa1100_mask_irq,
222 .unmask = sa1100_unmask_irq,
223 .set_wake = sa1100_set_wake,
224 };
225
226 static struct resource irq_resource = {
227 .name = "irqs",
228 .start = 0x90050000,
229 .end = 0x9005ffff,
230 };
231
232 static struct sa1100irq_state {
233 unsigned int saved;
234 unsigned int icmr;
235 unsigned int iclr;
236 unsigned int iccr;
237 } sa1100irq_state;
238
239 static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
240 {
241 struct sa1100irq_state *st = &sa1100irq_state;
242
243 st->saved = 1;
244 st->icmr = ICMR;
245 st->iclr = ICLR;
246 st->iccr = ICCR;
247
248 /*
249 * Disable all GPIO-based interrupts.
250 */
251 ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
252 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
253 IC_GPIO1|IC_GPIO0);
254
255 /*
256 * Set the appropriate edges for wakeup.
257 */
258 GRER = PWER & GPIO_IRQ_rising_edge;
259 GFER = PWER & GPIO_IRQ_falling_edge;
260
261 /*
262 * Clear any pending GPIO interrupts.
263 */
264 GEDR = GEDR;
265
266 return 0;
267 }
268
269 static int sa1100irq_resume(struct sys_device *dev)
270 {
271 struct sa1100irq_state *st = &sa1100irq_state;
272
273 if (st->saved) {
274 ICCR = st->iccr;
275 ICLR = st->iclr;
276
277 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
278 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
279
280 ICMR = st->icmr;
281 }
282 return 0;
283 }
284
285 static struct sysdev_class sa1100irq_sysclass = {
286 .name = "sa11x0-irq",
287 .suspend = sa1100irq_suspend,
288 .resume = sa1100irq_resume,
289 };
290
291 static struct sys_device sa1100irq_device = {
292 .id = 0,
293 .cls = &sa1100irq_sysclass,
294 };
295
296 static int __init sa1100irq_init_devicefs(void)
297 {
298 sysdev_class_register(&sa1100irq_sysclass);
299 return sysdev_register(&sa1100irq_device);
300 }
301
302 device_initcall(sa1100irq_init_devicefs);
303
304 void __init sa1100_init_irq(void)
305 {
306 unsigned int irq;
307
308 request_resource(&iomem_resource, &irq_resource);
309
310 /* disable all IRQs */
311 ICMR = 0;
312
313 /* all IRQs are IRQ, not FIQ */
314 ICLR = 0;
315
316 /* clear all GPIO edge detects */
317 GFER = 0;
318 GRER = 0;
319 GEDR = -1;
320
321 /*
322 * Whatever the doc says, this has to be set for the wait-on-irq
323 * instruction to work... on a SA1100 rev 9 at least.
324 */
325 ICCR = 1;
326
327 for (irq = 0; irq <= 10; irq++) {
328 set_irq_chip(irq, &sa1100_low_gpio_chip);
329 set_irq_handler(irq, handle_edge_irq);
330 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
331 }
332
333 for (irq = 12; irq <= 31; irq++) {
334 set_irq_chip(irq, &sa1100_normal_chip);
335 set_irq_handler(irq, handle_level_irq);
336 set_irq_flags(irq, IRQF_VALID);
337 }
338
339 for (irq = 32; irq <= 48; irq++) {
340 set_irq_chip(irq, &sa1100_high_gpio_chip);
341 set_irq_handler(irq, handle_edge_irq);
342 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
343 }
344
345 /*
346 * Install handler for GPIO 11-27 edge detect interrupts
347 */
348 set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
349 set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
350 }
351
|
This page was automatically generated by the
LXR engine.
|