1 /* linux/arch/arm/mach-s3c2412/s3c2412.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/sysdev.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
26 #include <asm/mach/irq.h>
27
28 #include <asm/hardware.h>
29 #include <asm/proc-fns.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #include <asm/arch/reset.h>
34 #include <asm/arch/idle.h>
35
36 #include <asm/arch/regs-clock.h>
37 #include <asm/plat-s3c/regs-serial.h>
38 #include <asm/arch/regs-power.h>
39 #include <asm/arch/regs-gpio.h>
40 #include <asm/arch/regs-gpioj.h>
41 #include <asm/arch/regs-dsc.h>
42 #include <asm/plat-s3c24xx/regs-spi.h>
43 #include <asm/arch/regs-s3c2412.h>
44
45 #include <asm/plat-s3c24xx/s3c2412.h>
46 #include <asm/plat-s3c24xx/cpu.h>
47 #include <asm/plat-s3c24xx/devs.h>
48 #include <asm/plat-s3c24xx/clock.h>
49 #include <asm/plat-s3c24xx/pm.h>
50
51 #ifndef CONFIG_CPU_S3C2412_ONLY
52 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
53
54 static inline void s3c2412_init_gpio2(void)
55 {
56 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
57 }
58 #else
59 #define s3c2412_init_gpio2() do { } while(0)
60 #endif
61
62 /* Initial IO mappings */
63
64 static struct map_desc s3c2412_iodesc[] __initdata = {
65 IODESC_ENT(CLKPWR),
66 IODESC_ENT(TIMER),
67 IODESC_ENT(WATCHDOG),
68 };
69
70 /* uart registration process */
71
72 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
73 {
74 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
75
76 /* rename devices that are s3c2412/s3c2413 specific */
77 s3c_device_sdi.name = "s3c2412-sdi";
78 s3c_device_lcd.name = "s3c2412-lcd";
79 s3c_device_nand.name = "s3c2412-nand";
80
81 /* alter IRQ of SDI controller */
82
83 s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
84 s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
85
86 /* spi channel related changes, s3c2412/13 specific */
87 s3c_device_spi0.name = "s3c2412-spi";
88 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
89 s3c_device_spi1.name = "s3c2412-spi";
90 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
91 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
92
93 }
94
95 /* s3c2412_idle
96 *
97 * use the standard idle call by ensuring the idle mode
98 * in power config, then issuing the idle co-processor
99 * instruction
100 */
101
102 static void s3c2412_idle(void)
103 {
104 unsigned long tmp;
105
106 /* ensure our idle mode is to go to idle */
107
108 tmp = __raw_readl(S3C2412_PWRCFG);
109 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
110 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
111 __raw_writel(tmp, S3C2412_PWRCFG);
112
113 cpu_do_idle();
114 }
115
116 static void s3c2412_hard_reset(void)
117 {
118 /* errata "Watch-dog/Software Reset Problem" specifies that
119 * this reset must be done with the SYSCLK sourced from
120 * EXTCLK instead of FOUT to avoid a glitch in the reset
121 * mechanism.
122 *
123 * See the watchdog section of the S3C2412 manual for more
124 * information on this fix.
125 */
126
127 __raw_writel(0x00, S3C2412_CLKSRC);
128 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
129
130 mdelay(1);
131 }
132
133 /* s3c2412_map_io
134 *
135 * register the standard cpu IO areas, and any passed in from the
136 * machine specific initialisation.
137 */
138
139 void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
140 {
141 /* move base of IO */
142
143 s3c2412_init_gpio2();
144
145 /* set our idle function */
146
147 s3c24xx_idle = s3c2412_idle;
148
149 /* set custom reset hook */
150
151 s3c24xx_reset_hook = s3c2412_hard_reset;
152
153 /* register our io-tables */
154
155 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
156 iotable_init(mach_desc, mach_size);
157 }
158
159 void __init s3c2412_init_clocks(int xtal)
160 {
161 unsigned long tmp;
162 unsigned long fclk;
163 unsigned long hclk;
164 unsigned long pclk;
165
166 /* now we've got our machine bits initialised, work out what
167 * clocks we've got */
168
169 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
170
171 clk_mpll.rate = fclk;
172
173 tmp = __raw_readl(S3C2410_CLKDIVN);
174
175 /* work out clock scalings */
176
177 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
178 hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
179 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
180
181 /* print brieft summary of clocks, etc */
182
183 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
184 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
185
186 /* initialise the clocks here, to allow other things like the
187 * console to use them
188 */
189
190 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
191 s3c2412_baseclk_add();
192 }
193
194 /* need to register class before we actually register the device, and
195 * we also need to ensure that it has been initialised before any of the
196 * drivers even try to use it (even if not on an s3c2412 based system)
197 * as a driver which may support both 2410 and 2440 may try and use it.
198 */
199
200 struct sysdev_class s3c2412_sysclass = {
201 .name = "s3c2412-core",
202 };
203
204 static int __init s3c2412_core_init(void)
205 {
206 return sysdev_class_register(&s3c2412_sysclass);
207 }
208
209 core_initcall(s3c2412_core_init);
210
211 static struct sys_device s3c2412_sysdev = {
212 .cls = &s3c2412_sysclass,
213 };
214
215 int __init s3c2412_init(void)
216 {
217 printk("S3C2412: Initialising architecture\n");
218
219 return sysdev_register(&s3c2412_sysdev);
220 }
221
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