1 /* linux/arch/arm/mach-s3c2412/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/sysdev.h>
18 #include <linux/serial_core.h>
19 #include <linux/io.h>
20
21 #include <mach/dma.h>
22
23 #include <plat/dma-plat.h>
24 #include <plat/cpu.h>
25
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <plat/regs-dma.h>
30 #include <mach/regs-mem.h>
31 #include <mach/regs-lcd.h>
32 #include <mach/regs-sdi.h>
33 #include <plat/regs-s3c2412-iis.h>
34 #include <plat/regs-iis.h>
35 #include <plat/regs-spi.h>
36
37 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
38
39 static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
40 [DMACH_XD0] = {
41 .name = "xdreq0",
42 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
43 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0),
44 },
45 [DMACH_XD1] = {
46 .name = "xdreq1",
47 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
48 .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1),
49 },
50 [DMACH_SDI] = {
51 .name = "sdi",
52 .channels = MAP(S3C2412_DMAREQSEL_SDI),
53 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
54 .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
55 .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
56 },
57 [DMACH_SPI0] = {
58 .name = "spi0",
59 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
60 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
61 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
62 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
63 },
64 [DMACH_SPI1] = {
65 .name = "spi1",
66 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
67 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
68 .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
69 .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
70 },
71 [DMACH_UART0] = {
72 .name = "uart0",
73 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
74 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
75 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
77 },
78 [DMACH_UART1] = {
79 .name = "uart1",
80 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
81 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
82 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
83 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
84 },
85 [DMACH_UART2] = {
86 .name = "uart2",
87 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
88 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
89 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
90 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
91 },
92 [DMACH_UART0_SRC2] = {
93 .name = "uart0",
94 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
95 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
96 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
97 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
98 },
99 [DMACH_UART1_SRC2] = {
100 .name = "uart1",
101 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
102 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
103 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
104 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
105 },
106 [DMACH_UART2_SRC2] = {
107 .name = "uart2",
108 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
109 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
110 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
111 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
112 },
113 [DMACH_TIMER] = {
114 .name = "timer",
115 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
116 .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER),
117 },
118 [DMACH_I2S_IN] = {
119 .name = "i2s-sdi",
120 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
121 .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX),
122 .hw_addr.from = S3C2410_PA_IIS + S3C2412_IISRXD,
123 },
124 [DMACH_I2S_OUT] = {
125 .name = "i2s-sdo",
126 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
127 .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX),
128 .hw_addr.to = S3C2410_PA_IIS + S3C2412_IISTXD,
129 },
130 [DMACH_USB_EP1] = {
131 .name = "usb-ep1",
132 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
133 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1),
134 },
135 [DMACH_USB_EP2] = {
136 .name = "usb-ep2",
137 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
138 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2),
139 },
140 [DMACH_USB_EP3] = {
141 .name = "usb-ep3",
142 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
143 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3),
144 },
145 [DMACH_USB_EP4] = {
146 .name = "usb-ep4",
147 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
148 .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4),
149 },
150 };
151
152 static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
153 struct s3c24xx_dma_map *map,
154 enum s3c2410_dmasrc dir)
155 {
156 unsigned long chsel;
157
158 if (dir == S3C2410_DMASRC_HW)
159 chsel = map->channels_rx[0];
160 else
161 chsel = map->channels[0];
162
163 chsel &= ~DMA_CH_VALID;
164 chsel |= S3C2412_DMAREQSEL_HW;
165
166 writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
167 }
168
169 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
170 struct s3c24xx_dma_map *map)
171 {
172 s3c2412_dma_direction(chan, map, chan->source);
173 }
174
175 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
176 .select = s3c2412_dma_select,
177 .direction = s3c2412_dma_direction,
178 .dcon_mask = 0,
179 .map = s3c2412_dma_mappings,
180 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
181 };
182
183 static int __init s3c2412_dma_add(struct sys_device *sysdev)
184 {
185 s3c2410_dma_init();
186 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
187 }
188
189 static struct sysdev_driver s3c2412_dma_driver = {
190 .add = s3c2412_dma_add,
191 };
192
193 static int __init s3c2412_dma_init(void)
194 {
195 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
196 }
197
198 arch_initcall(s3c2412_dma_init);
199
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