1 /* arch/arm/mach-s3c2410/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11 */
12
13 #ifndef __ASM_ARM_REGS_CLOCK
14 #define __ASM_ARM_REGS_CLOCK
15
16 #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18 #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
19
20 #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
21 #define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
22 #define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
23 #define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
24 #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
25 #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
26
27 #define S3C2410_CLKCON_IDLE (1<<2)
28 #define S3C2410_CLKCON_POWER (1<<3)
29 #define S3C2410_CLKCON_NAND (1<<4)
30 #define S3C2410_CLKCON_LCDC (1<<5)
31 #define S3C2410_CLKCON_USBH (1<<6)
32 #define S3C2410_CLKCON_USBD (1<<7)
33 #define S3C2410_CLKCON_PWMT (1<<8)
34 #define S3C2410_CLKCON_SDI (1<<9)
35 #define S3C2410_CLKCON_UART0 (1<<10)
36 #define S3C2410_CLKCON_UART1 (1<<11)
37 #define S3C2410_CLKCON_UART2 (1<<12)
38 #define S3C2410_CLKCON_GPIO (1<<13)
39 #define S3C2410_CLKCON_RTC (1<<14)
40 #define S3C2410_CLKCON_ADC (1<<15)
41 #define S3C2410_CLKCON_IIC (1<<16)
42 #define S3C2410_CLKCON_IIS (1<<17)
43 #define S3C2410_CLKCON_SPI (1<<18)
44
45 /* DCLKCON register addresses in gpio.h */
46
47 #define S3C2410_DCLKCON_DCLK0EN (1<<0)
48 #define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
49 #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
50 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
51 #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
52 #define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
53 #define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
54
55 #define S3C2410_DCLKCON_DCLK1EN (1<<16)
56 #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
57 #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
58 #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
59 #define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
60 #define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
61 #define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
62
63 #define S3C2410_CLKDIVN_PDIVN (1<<0)
64 #define S3C2410_CLKDIVN_HDIVN (1<<1)
65
66 #define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
67 #define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
68 #define S3C2410_CLKSLOW_SLOW (1<<4)
69 #define S3C2410_CLKSLOW_SLOWVAL(x) (x)
70 #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
71
72 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
73
74 /* extra registers */
75 #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
76
77 #define S3C2440_CLKCON_CAMERA (1<<19)
78 #define S3C2440_CLKCON_AC97 (1<<20)
79
80 #define S3C2440_CLKDIVN_PDIVN (1<<0)
81 #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
82 #define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
83 #define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
84 #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
85 #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
86 #define S3C2440_CLKDIVN_UCLK (1<<3)
87
88 #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
89 #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
90 #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
91 #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
92 #define S3C2440_CAMDIVN_DVSEN (1<<12)
93
94 #define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
95
96 #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
97
98 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
99
100 #define S3C2412_OSCSET S3C2410_CLKREG(0x18)
101 #define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
102
103 #define S3C2412_PLLCON_OFF (1<<20)
104
105 #define S3C2412_CLKDIVN_PDIVN (1<<2)
106 #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
107 #define S3C2412_CLKDIVN_ARMDIVN (1<<3)
108 #define S3C2412_CLKDIVN_DVSEN (1<<4)
109 #define S3C2412_CLKDIVN_HALFHCLK (1<<5)
110 #define S3C2412_CLKDIVN_USB48DIV (1<<6)
111 #define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
112 #define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
113 #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
114 #define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
115 #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
116 #define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
117
118 #define S3C2412_CLKCON_WDT (1<<28)
119 #define S3C2412_CLKCON_SPI (1<<27)
120 #define S3C2412_CLKCON_IIS (1<<26)
121 #define S3C2412_CLKCON_IIC (1<<25)
122 #define S3C2412_CLKCON_ADC (1<<24)
123 #define S3C2412_CLKCON_RTC (1<<23)
124 #define S3C2412_CLKCON_GPIO (1<<22)
125 #define S3C2412_CLKCON_UART2 (1<<21)
126 #define S3C2412_CLKCON_UART1 (1<<20)
127 #define S3C2412_CLKCON_UART0 (1<<19)
128 #define S3C2412_CLKCON_SDI (1<<18)
129 #define S3C2412_CLKCON_PWMT (1<<17)
130 #define S3C2412_CLKCON_USBD (1<<16)
131 #define S3C2412_CLKCON_CAMCLK (1<<15)
132 #define S3C2412_CLKCON_UARTCLK (1<<14)
133 /* missing 13 */
134 #define S3C2412_CLKCON_USB_HOST48 (1<<12)
135 #define S3C2412_CLKCON_USB_DEV48 (1<<11)
136 #define S3C2412_CLKCON_HCLKdiv2 (1<<10)
137 #define S3C2412_CLKCON_HCLKx2 (1<<9)
138 #define S3C2412_CLKCON_SDRAM (1<<8)
139 /* missing 7 */
140 #define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
141 #define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
142 #define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
143 #define S3C2412_CLKCON_DMA3 (1<<3)
144 #define S3C2412_CLKCON_DMA2 (1<<2)
145 #define S3C2412_CLKCON_DMA1 (1<<1)
146 #define S3C2412_CLKCON_DMA0 (1<<0)
147
148 /* clock sourec controls */
149
150 #define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
151 #define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
152 #define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
153 #define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
154 #define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
155 #define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
156 #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
157 #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
158 #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
159 #define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
160 #define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
161
162 #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
163
164 #endif /* __ASM_ARM_REGS_CLOCK */
165
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