1 /*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
30
31 #include <asm/system.h>
32 #include <asm/hardware.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/leds.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
38
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/mmc.h>
44
45 #include <asm/hardware/gic.h>
46
47 #include "core.h"
48 #include "clock.h"
49
50 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
51
52 /* used by entry-macro.S */
53 void __iomem *gic_cpu_base_addr;
54
55 /*
56 * This is the RealView sched_clock implementation. This has
57 * a resolution of 41.7ns, and a maximum value of about 179s.
58 */
59 unsigned long long sched_clock(void)
60 {
61 unsigned long long v;
62
63 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
64 do_div(v, 3);
65
66 return v;
67 }
68
69
70 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
71
72 static int realview_flash_init(void)
73 {
74 u32 val;
75
76 val = __raw_readl(REALVIEW_FLASHCTRL);
77 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
78 __raw_writel(val, REALVIEW_FLASHCTRL);
79
80 return 0;
81 }
82
83 static void realview_flash_exit(void)
84 {
85 u32 val;
86
87 val = __raw_readl(REALVIEW_FLASHCTRL);
88 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
89 __raw_writel(val, REALVIEW_FLASHCTRL);
90 }
91
92 static void realview_flash_set_vpp(int on)
93 {
94 u32 val;
95
96 val = __raw_readl(REALVIEW_FLASHCTRL);
97 if (on)
98 val |= REALVIEW_FLASHPROG_FLVPPEN;
99 else
100 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
101 __raw_writel(val, REALVIEW_FLASHCTRL);
102 }
103
104 static struct flash_platform_data realview_flash_data = {
105 .map_name = "cfi_probe",
106 .width = 4,
107 .init = realview_flash_init,
108 .exit = realview_flash_exit,
109 .set_vpp = realview_flash_set_vpp,
110 };
111
112 static struct resource realview_flash_resource = {
113 .start = REALVIEW_FLASH_BASE,
114 .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
115 .flags = IORESOURCE_MEM,
116 };
117
118 struct platform_device realview_flash_device = {
119 .name = "armflash",
120 .id = 0,
121 .dev = {
122 .platform_data = &realview_flash_data,
123 },
124 .num_resources = 1,
125 .resource = &realview_flash_resource,
126 };
127
128 static struct resource realview_i2c_resource = {
129 .start = REALVIEW_I2C_BASE,
130 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
131 .flags = IORESOURCE_MEM,
132 };
133
134 struct platform_device realview_i2c_device = {
135 .name = "versatile-i2c",
136 .id = -1,
137 .num_resources = 1,
138 .resource = &realview_i2c_resource,
139 };
140
141 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
142
143 static unsigned int realview_mmc_status(struct device *dev)
144 {
145 struct amba_device *adev = container_of(dev, struct amba_device, dev);
146 u32 mask;
147
148 if (adev->res.start == REALVIEW_MMCI0_BASE)
149 mask = 1;
150 else
151 mask = 2;
152
153 return readl(REALVIEW_SYSMCI) & mask;
154 }
155
156 struct mmc_platform_data realview_mmc0_plat_data = {
157 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
158 .status = realview_mmc_status,
159 };
160
161 struct mmc_platform_data realview_mmc1_plat_data = {
162 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
163 .status = realview_mmc_status,
164 };
165
166 /*
167 * Clock handling
168 */
169 static const struct icst307_params realview_oscvco_params = {
170 .ref = 24000,
171 .vco_max = 200000,
172 .vd_min = 4 + 8,
173 .vd_max = 511 + 8,
174 .rd_min = 1 + 2,
175 .rd_max = 127 + 2,
176 };
177
178 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
179 {
180 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
181 void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
182 u32 val;
183
184 val = readl(sys_osc) & ~0x7ffff;
185 val |= vco.v | (vco.r << 9) | (vco.s << 16);
186
187 writel(0xa05f, sys_lock);
188 writel(val, sys_osc);
189 writel(0, sys_lock);
190 }
191
192 struct clk realview_clcd_clk = {
193 .name = "CLCDCLK",
194 .params = &realview_oscvco_params,
195 .setvco = realview_oscvco_set,
196 };
197
198 /*
199 * CLCD support.
200 */
201 #define SYS_CLCD_NLCDIOON (1 << 2)
202 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
203 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
204 #define SYS_CLCD_ID_MASK (0x1f << 8)
205 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
206 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
207 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
208 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
209 #define SYS_CLCD_ID_VGA (0x1f << 8)
210
211 static struct clcd_panel vga = {
212 .mode = {
213 .name = "VGA",
214 .refresh = 60,
215 .xres = 640,
216 .yres = 480,
217 .pixclock = 39721,
218 .left_margin = 40,
219 .right_margin = 24,
220 .upper_margin = 32,
221 .lower_margin = 11,
222 .hsync_len = 96,
223 .vsync_len = 2,
224 .sync = 0,
225 .vmode = FB_VMODE_NONINTERLACED,
226 },
227 .width = -1,
228 .height = -1,
229 .tim2 = TIM2_BCD | TIM2_IPC,
230 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
231 .bpp = 16,
232 };
233
234 static struct clcd_panel sanyo_3_8_in = {
235 .mode = {
236 .name = "Sanyo QVGA",
237 .refresh = 116,
238 .xres = 320,
239 .yres = 240,
240 .pixclock = 100000,
241 .left_margin = 6,
242 .right_margin = 6,
243 .upper_margin = 5,
244 .lower_margin = 5,
245 .hsync_len = 6,
246 .vsync_len = 6,
247 .sync = 0,
248 .vmode = FB_VMODE_NONINTERLACED,
249 },
250 .width = -1,
251 .height = -1,
252 .tim2 = TIM2_BCD,
253 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
254 .bpp = 16,
255 };
256
257 static struct clcd_panel sanyo_2_5_in = {
258 .mode = {
259 .name = "Sanyo QVGA Portrait",
260 .refresh = 116,
261 .xres = 240,
262 .yres = 320,
263 .pixclock = 100000,
264 .left_margin = 20,
265 .right_margin = 10,
266 .upper_margin = 2,
267 .lower_margin = 2,
268 .hsync_len = 10,
269 .vsync_len = 2,
270 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
271 .vmode = FB_VMODE_NONINTERLACED,
272 },
273 .width = -1,
274 .height = -1,
275 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
276 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
277 .bpp = 16,
278 };
279
280 static struct clcd_panel epson_2_2_in = {
281 .mode = {
282 .name = "Epson QCIF",
283 .refresh = 390,
284 .xres = 176,
285 .yres = 220,
286 .pixclock = 62500,
287 .left_margin = 3,
288 .right_margin = 2,
289 .upper_margin = 1,
290 .lower_margin = 0,
291 .hsync_len = 3,
292 .vsync_len = 2,
293 .sync = 0,
294 .vmode = FB_VMODE_NONINTERLACED,
295 },
296 .width = -1,
297 .height = -1,
298 .tim2 = TIM2_BCD | TIM2_IPC,
299 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
300 .bpp = 16,
301 };
302
303 /*
304 * Detect which LCD panel is connected, and return the appropriate
305 * clcd_panel structure. Note: we do not have any information on
306 * the required timings for the 8.4in panel, so we presently assume
307 * VGA timings.
308 */
309 static struct clcd_panel *realview_clcd_panel(void)
310 {
311 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
312 struct clcd_panel *panel = &vga;
313 u32 val;
314
315 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
316 if (val == SYS_CLCD_ID_SANYO_3_8)
317 panel = &sanyo_3_8_in;
318 else if (val == SYS_CLCD_ID_SANYO_2_5)
319 panel = &sanyo_2_5_in;
320 else if (val == SYS_CLCD_ID_EPSON_2_2)
321 panel = &epson_2_2_in;
322 else if (val == SYS_CLCD_ID_VGA)
323 panel = &vga;
324 else {
325 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
326 val);
327 panel = &vga;
328 }
329
330 return panel;
331 }
332
333 /*
334 * Disable all display connectors on the interface module.
335 */
336 static void realview_clcd_disable(struct clcd_fb *fb)
337 {
338 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
339 u32 val;
340
341 val = readl(sys_clcd);
342 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
343 writel(val, sys_clcd);
344 }
345
346 /*
347 * Enable the relevant connector on the interface module.
348 */
349 static void realview_clcd_enable(struct clcd_fb *fb)
350 {
351 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
352 u32 val;
353
354 /*
355 * Enable the PSUs
356 */
357 val = readl(sys_clcd);
358 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
359 writel(val, sys_clcd);
360 }
361
362 static unsigned long framesize = SZ_1M;
363
364 static int realview_clcd_setup(struct clcd_fb *fb)
365 {
366 dma_addr_t dma;
367
368 fb->panel = realview_clcd_panel();
369
370 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
371 &dma, GFP_KERNEL);
372 if (!fb->fb.screen_base) {
373 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
374 return -ENOMEM;
375 }
376
377 fb->fb.fix.smem_start = dma;
378 fb->fb.fix.smem_len = framesize;
379
380 return 0;
381 }
382
383 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
384 {
385 return dma_mmap_writecombine(&fb->dev->dev, vma,
386 fb->fb.screen_base,
387 fb->fb.fix.smem_start,
388 fb->fb.fix.smem_len);
389 }
390
391 static void realview_clcd_remove(struct clcd_fb *fb)
392 {
393 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
394 fb->fb.screen_base, fb->fb.fix.smem_start);
395 }
396
397 struct clcd_board clcd_plat_data = {
398 .name = "RealView",
399 .check = clcdfb_check,
400 .decode = clcdfb_decode,
401 .disable = realview_clcd_disable,
402 .enable = realview_clcd_enable,
403 .setup = realview_clcd_setup,
404 .mmap = realview_clcd_mmap,
405 .remove = realview_clcd_remove,
406 };
407
408 #ifdef CONFIG_LEDS
409 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
410
411 void realview_leds_event(led_event_t ledevt)
412 {
413 unsigned long flags;
414 u32 val;
415
416 local_irq_save(flags);
417 val = readl(VA_LEDS_BASE);
418
419 switch (ledevt) {
420 case led_idle_start:
421 val = val & ~REALVIEW_SYS_LED0;
422 break;
423
424 case led_idle_end:
425 val = val | REALVIEW_SYS_LED0;
426 break;
427
428 case led_timer:
429 val = val ^ REALVIEW_SYS_LED1;
430 break;
431
432 case led_halted:
433 val = 0;
434 break;
435
436 default:
437 break;
438 }
439
440 writel(val, VA_LEDS_BASE);
441 local_irq_restore(flags);
442 }
443 #endif /* CONFIG_LEDS */
444
445 /*
446 * Where is the timer (VA)?
447 */
448 #define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
449 #define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
450 #define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
451 #define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
452
453 /*
454 * How long is the timer interval?
455 */
456 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
457 #if TIMER_INTERVAL >= 0x100000
458 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
459 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
460 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
461 #elif TIMER_INTERVAL >= 0x10000
462 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
463 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
464 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
465 #else
466 #define TIMER_RELOAD (TIMER_INTERVAL)
467 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
468 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
469 #endif
470
471 static void timer_set_mode(enum clock_event_mode mode,
472 struct clock_event_device *clk)
473 {
474 unsigned long ctrl;
475
476 switch(mode) {
477 case CLOCK_EVT_MODE_PERIODIC:
478 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
479
480 ctrl = TIMER_CTRL_PERIODIC;
481 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
482 break;
483 case CLOCK_EVT_MODE_ONESHOT:
484 /* period set, and timer enabled in 'next_event' hook */
485 ctrl = TIMER_CTRL_ONESHOT;
486 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
487 break;
488 case CLOCK_EVT_MODE_UNUSED:
489 case CLOCK_EVT_MODE_SHUTDOWN:
490 default:
491 ctrl = 0;
492 }
493
494 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
495 }
496
497 static int timer_set_next_event(unsigned long evt,
498 struct clock_event_device *unused)
499 {
500 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
501
502 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
503 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
504
505 return 0;
506 }
507
508 static struct clock_event_device timer0_clockevent = {
509 .name = "timer0",
510 .shift = 32,
511 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
512 .set_mode = timer_set_mode,
513 .set_next_event = timer_set_next_event,
514 .rating = 300,
515 .cpumask = CPU_MASK_ALL,
516 };
517
518 static void __init realview_clockevents_init(unsigned int timer_irq)
519 {
520 timer0_clockevent.irq = timer_irq;
521 timer0_clockevent.mult =
522 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
523 timer0_clockevent.max_delta_ns =
524 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
525 timer0_clockevent.min_delta_ns =
526 clockevent_delta2ns(0xf, &timer0_clockevent);
527
528 clockevents_register_device(&timer0_clockevent);
529 }
530
531 /*
532 * IRQ handler for the timer
533 */
534 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
535 {
536 struct clock_event_device *evt = &timer0_clockevent;
537
538 /* clear the interrupt */
539 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
540
541 evt->event_handler(evt);
542
543 return IRQ_HANDLED;
544 }
545
546 static struct irqaction realview_timer_irq = {
547 .name = "RealView Timer Tick",
548 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
549 .handler = realview_timer_interrupt,
550 };
551
552 static cycle_t realview_get_cycles(void)
553 {
554 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
555 }
556
557 static struct clocksource clocksource_realview = {
558 .name = "timer3",
559 .rating = 200,
560 .read = realview_get_cycles,
561 .mask = CLOCKSOURCE_MASK(32),
562 .shift = 20,
563 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
564 };
565
566 static void __init realview_clocksource_init(void)
567 {
568 /* setup timer 0 as free-running clocksource */
569 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
570 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
571 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
572 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
573 TIMER3_VA_BASE + TIMER_CTRL);
574
575 clocksource_realview.mult =
576 clocksource_khz2mult(1000, clocksource_realview.shift);
577 clocksource_register(&clocksource_realview);
578 }
579
580 /*
581 * Set up the clock source and clock events devices
582 */
583 void __init realview_timer_init(unsigned int timer_irq)
584 {
585 u32 val;
586
587 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
588 /*
589 * The dummy clock device has to be registered before the main device
590 * so that the latter will broadcast the clock events
591 */
592 local_timer_setup(smp_processor_id());
593 #endif
594
595 /*
596 * set clock frequency:
597 * REALVIEW_REFCLK is 32KHz
598 * REALVIEW_TIMCLK is 1MHz
599 */
600 val = readl(__io_address(REALVIEW_SCTL_BASE));
601 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
602 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
603 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
604 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
605 __io_address(REALVIEW_SCTL_BASE));
606
607 /*
608 * Initialise to a known state (all timers off)
609 */
610 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
611 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
612 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
613 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
614
615 /*
616 * Make irqs happen for the system timer
617 */
618 setup_irq(timer_irq, &realview_timer_irq);
619
620 realview_clocksource_init();
621 realview_clockevents_init(timer_irq);
622 }
623
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