1 /*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/pm.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/sysdev.h>
24
25 #include <asm/hardware.h>
26 #include <asm/arch/pxa3xx-regs.h>
27 #include <asm/arch/ohci.h>
28 #include <asm/arch/pm.h>
29 #include <asm/arch/dma.h>
30 #include <asm/arch/ssp.h>
31
32 #include "generic.h"
33 #include "devices.h"
34 #include "clock.h"
35
36 /* Crystal clock: 13MHz */
37 #define BASE_CLK 13000000
38
39 /* Ring Oscillator Clock: 60MHz */
40 #define RO_CLK 60000000
41
42 #define ACCR_D0CS (1 << 26)
43 #define ACCR_PCCE (1 << 11)
44
45 /* crystal frequency to static memory controller multiplier (SMCFS) */
46 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
47
48 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
49 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
50
51 /*
52 * Get the clock frequency as reflected by CCSR and the turbo flag.
53 * We assume these values have been applied via a fcs.
54 * If info is not 0 we also display the current settings.
55 */
56 unsigned int pxa3xx_get_clk_frequency_khz(int info)
57 {
58 unsigned long acsr, xclkcfg;
59 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
60
61 /* Read XCLKCFG register turbo bit */
62 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
63 t = xclkcfg & 0x1;
64
65 acsr = ACSR;
66
67 xl = acsr & 0x1f;
68 xn = (acsr >> 8) & 0x7;
69 hss = (acsr >> 14) & 0x3;
70
71 XL = xl * BASE_CLK;
72 XN = xn * XL;
73
74 ro = acsr & ACCR_D0CS;
75
76 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
77 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
78
79 if (info) {
80 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
81 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
82 (ro) ? "" : "in");
83 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
84 XL / 1000000, (XL % 1000000) / 10000, xl);
85 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
86 XN / 1000000, (XN % 1000000) / 10000, xn,
87 (t) ? "" : "in");
88 pr_info("HSIO bus clock: %d.%02dMHz\n",
89 HSS / 1000000, (HSS % 1000000) / 10000);
90 }
91
92 return CLK / 1000;
93 }
94
95 /*
96 * Return the current static memory controller clock frequency
97 * in units of 10kHz
98 */
99 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
100 {
101 unsigned long acsr;
102 unsigned int smcfs, clk = 0;
103
104 acsr = ACSR;
105
106 smcfs = (acsr >> 23) & 0x7;
107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
108
109 return (clk / 10000);
110 }
111
112 /*
113 * Return the current HSIO bus clock frequency
114 */
115 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
116 {
117 unsigned long acsr;
118 unsigned int hss, hsio_clk;
119
120 acsr = ACSR;
121
122 hss = (acsr >> 14) & 0x3;
123 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
124
125 return hsio_clk;
126 }
127
128 static void clk_pxa3xx_cken_enable(struct clk *clk)
129 {
130 unsigned long mask = 1ul << (clk->cken & 0x1f);
131
132 if (clk->cken < 32)
133 CKENA |= mask;
134 else
135 CKENB |= mask;
136 }
137
138 static void clk_pxa3xx_cken_disable(struct clk *clk)
139 {
140 unsigned long mask = 1ul << (clk->cken & 0x1f);
141
142 if (clk->cken < 32)
143 CKENA &= ~mask;
144 else
145 CKENB &= ~mask;
146 }
147
148 static const struct clkops clk_pxa3xx_cken_ops = {
149 .enable = clk_pxa3xx_cken_enable,
150 .disable = clk_pxa3xx_cken_disable,
151 };
152
153 static const struct clkops clk_pxa3xx_hsio_ops = {
154 .enable = clk_pxa3xx_cken_enable,
155 .disable = clk_pxa3xx_cken_disable,
156 .getrate = clk_pxa3xx_hsio_getrate,
157 };
158
159 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
160 { \
161 .name = _name, \
162 .dev = _dev, \
163 .ops = &clk_pxa3xx_cken_ops, \
164 .rate = _rate, \
165 .cken = CKEN_##_cken, \
166 .delay = _delay, \
167 }
168
169 #define PXA3xx_CK(_name, _cken, _ops, _dev) \
170 { \
171 .name = _name, \
172 .dev = _dev, \
173 .ops = _ops, \
174 .cken = CKEN_##_cken, \
175 }
176
177 static struct clk pxa3xx_clks[] = {
178 PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
179 PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
180
181 PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
182 PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
183 PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
184
185 PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
186 PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
187 PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
188
189 PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
190 PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
191 PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
192 PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
193
194 PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
195 PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
196 PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
197 };
198
199 #ifdef CONFIG_PM
200
201 #define ISRAM_START 0x5c000000
202 #define ISRAM_SIZE SZ_256K
203
204 static void __iomem *sram;
205 static unsigned long wakeup_src;
206
207 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
208 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
209
210 enum { SLEEP_SAVE_START = 0,
211 SLEEP_SAVE_CKENA,
212 SLEEP_SAVE_CKENB,
213 SLEEP_SAVE_ACCR,
214
215 SLEEP_SAVE_SIZE,
216 };
217
218 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
219 {
220 SAVE(CKENA);
221 SAVE(CKENB);
222 SAVE(ACCR);
223 }
224
225 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
226 {
227 RESTORE(ACCR);
228 RESTORE(CKENA);
229 RESTORE(CKENB);
230 }
231
232 /*
233 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
234 * memory controller has to be reinitialised, so we place some code
235 * in the SRAM to perform this function.
236 *
237 * We disable FIQs across the standby - otherwise, we might receive a
238 * FIQ while the SDRAM is unavailable.
239 */
240 static void pxa3xx_cpu_standby(unsigned int pwrmode)
241 {
242 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
243 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
244
245 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
246 pm_enter_standby_end - pm_enter_standby_start);
247
248 AD2D0SR = ~0;
249 AD2D1SR = ~0;
250 AD2D0ER = wakeup_src;
251 AD2D1ER = 0;
252 ASCR = ASCR;
253 ARSR = ARSR;
254
255 local_fiq_disable();
256 fn(pwrmode);
257 local_fiq_enable();
258
259 AD2D0ER = 0;
260 AD2D1ER = 0;
261 }
262
263 /*
264 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
265 * PXA3xx development kits assumes that the resuming process continues
266 * with the address stored within the first 4 bytes of SDRAM. The PSPR
267 * register is used privately by BootROM and OBM, and _must_ be set to
268 * 0x5c014000 for the moment.
269 */
270 static void pxa3xx_cpu_pm_suspend(void)
271 {
272 volatile unsigned long *p = (volatile void *)0xc0000000;
273 unsigned long saved_data = *p;
274
275 extern void pxa3xx_cpu_suspend(void);
276 extern void pxa3xx_cpu_resume(void);
277
278 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
279 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
280 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
281
282 /* clear and setup wakeup source */
283 AD3SR = ~0;
284 AD3ER = wakeup_src;
285 ASCR = ASCR;
286 ARSR = ARSR;
287
288 PCFR |= (1u << 13); /* L1_DIS */
289 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
290
291 PSPR = 0x5c014000;
292
293 /* overwrite with the resume address */
294 *p = virt_to_phys(pxa3xx_cpu_resume);
295
296 pxa3xx_cpu_suspend();
297
298 *p = saved_data;
299
300 AD3ER = 0;
301 }
302
303 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
304 {
305 /*
306 * Don't sleep if no wakeup sources are defined
307 */
308 if (wakeup_src == 0)
309 return;
310
311 switch (state) {
312 case PM_SUSPEND_STANDBY:
313 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
314 break;
315
316 case PM_SUSPEND_MEM:
317 pxa3xx_cpu_pm_suspend();
318 break;
319 }
320 }
321
322 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
323 {
324 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
325 }
326
327 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
328 .save_size = SLEEP_SAVE_SIZE,
329 .save = pxa3xx_cpu_pm_save,
330 .restore = pxa3xx_cpu_pm_restore,
331 .valid = pxa3xx_cpu_pm_valid,
332 .enter = pxa3xx_cpu_pm_enter,
333 };
334
335 static void __init pxa3xx_init_pm(void)
336 {
337 sram = ioremap(ISRAM_START, ISRAM_SIZE);
338 if (!sram) {
339 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
340 return;
341 }
342
343 /*
344 * Since we copy wakeup code into the SRAM, we need to ensure
345 * that it is preserved over the low power modes. Note: bit 8
346 * is undocumented in the developer manual, but must be set.
347 */
348 AD1R |= ADXR_L2 | ADXR_R0;
349 AD2R |= ADXR_L2 | ADXR_R0;
350 AD3R |= ADXR_L2 | ADXR_R0;
351
352 /*
353 * Clear the resume enable registers.
354 */
355 AD1D0ER = 0;
356 AD2D0ER = 0;
357 AD2D1ER = 0;
358 AD3ER = 0;
359
360 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
361 }
362
363 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
364 {
365 unsigned long flags, mask = 0;
366
367 switch (irq) {
368 case IRQ_SSP3:
369 mask = ADXER_MFP_WSSP3;
370 break;
371 case IRQ_MSL:
372 mask = ADXER_WMSL0;
373 break;
374 case IRQ_USBH2:
375 case IRQ_USBH1:
376 mask = ADXER_WUSBH;
377 break;
378 case IRQ_KEYPAD:
379 mask = ADXER_WKP;
380 break;
381 case IRQ_AC97:
382 mask = ADXER_MFP_WAC97;
383 break;
384 case IRQ_USIM:
385 mask = ADXER_WUSIM0;
386 break;
387 case IRQ_SSP2:
388 mask = ADXER_MFP_WSSP2;
389 break;
390 case IRQ_I2C:
391 mask = ADXER_MFP_WI2C;
392 break;
393 case IRQ_STUART:
394 mask = ADXER_MFP_WUART3;
395 break;
396 case IRQ_BTUART:
397 mask = ADXER_MFP_WUART2;
398 break;
399 case IRQ_FFUART:
400 mask = ADXER_MFP_WUART1;
401 break;
402 case IRQ_MMC:
403 mask = ADXER_MFP_WMMC1;
404 break;
405 case IRQ_SSP:
406 mask = ADXER_MFP_WSSP1;
407 break;
408 case IRQ_RTCAlrm:
409 mask = ADXER_WRTC;
410 break;
411 case IRQ_SSP4:
412 mask = ADXER_MFP_WSSP4;
413 break;
414 case IRQ_TSI:
415 mask = ADXER_WTSI;
416 break;
417 case IRQ_USIM2:
418 mask = ADXER_WUSIM1;
419 break;
420 case IRQ_MMC2:
421 mask = ADXER_MFP_WMMC2;
422 break;
423 case IRQ_NAND:
424 mask = ADXER_MFP_WFLASH;
425 break;
426 case IRQ_USB2:
427 mask = ADXER_WUSB2;
428 break;
429 case IRQ_WAKEUP0:
430 mask = ADXER_WEXTWAKE0;
431 break;
432 case IRQ_WAKEUP1:
433 mask = ADXER_WEXTWAKE1;
434 break;
435 case IRQ_MMC3:
436 mask = ADXER_MFP_GEN12;
437 break;
438 }
439
440 local_irq_save(flags);
441 if (on)
442 wakeup_src |= mask;
443 else
444 wakeup_src &= ~mask;
445 local_irq_restore(flags);
446
447 return 0;
448 }
449
450 static void pxa3xx_init_irq_pm(void)
451 {
452 pxa_init_irq_set_wake(pxa3xx_set_wake);
453 }
454
455 #else
456 static inline void pxa3xx_init_pm(void) {}
457 static inline void pxa3xx_init_irq_pm(void) {}
458 #endif
459
460 void __init pxa3xx_init_irq(void)
461 {
462 /* enable CP6 access */
463 u32 value;
464 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
465 value |= (1 << 6);
466 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
467
468 pxa_init_irq_low();
469 pxa_init_irq_high();
470 pxa_init_irq_gpio(128);
471 pxa3xx_init_irq_pm();
472 }
473
474 /*
475 * device registration specific to PXA3xx.
476 */
477
478 static struct platform_device *devices[] __initdata = {
479 &pxa_device_udc,
480 &pxa_device_ffuart,
481 &pxa_device_btuart,
482 &pxa_device_stuart,
483 &pxa_device_i2s,
484 &pxa_device_rtc,
485 &pxa27x_device_ssp1,
486 &pxa27x_device_ssp2,
487 &pxa27x_device_ssp3,
488 &pxa3xx_device_ssp4,
489 };
490
491 static struct sys_device pxa3xx_sysdev[] = {
492 {
493 .id = 0,
494 .cls = &pxa_irq_sysclass,
495 }, {
496 .id = 1,
497 .cls = &pxa_irq_sysclass,
498 }, {
499 .cls = &pxa_gpio_sysclass,
500 },
501 };
502
503 static int __init pxa3xx_init(void)
504 {
505 int i, ret = 0;
506
507 if (cpu_is_pxa3xx()) {
508 /*
509 * clear RDH bit every time after reset
510 *
511 * Note: the last 3 bits DxS are write-1-to-clear so carefully
512 * preserve them here in case they will be referenced later
513 */
514 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
515
516 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
517
518 if ((ret = pxa_init_dma(32)))
519 return ret;
520
521 pxa3xx_init_pm();
522
523 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
524 ret = sysdev_register(&pxa3xx_sysdev[i]);
525 if (ret)
526 pr_err("failed to register sysdev[%d]\n", i);
527 }
528
529 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
530 }
531
532 return ret;
533 }
534
535 subsys_initcall(pxa3xx_init);
536
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