1 /*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/platform_device.h>
19 #include <linux/sysdev.h>
20
21 #include <asm/hardware.h>
22 #include <asm/irq.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/pxa-regs.h>
25 #include <asm/arch/pxa2xx-regs.h>
26 #include <asm/arch/ohci.h>
27 #include <asm/arch/pm.h>
28 #include <asm/arch/dma.h>
29 #include <asm/arch/i2c.h>
30
31 #include "generic.h"
32 #include "devices.h"
33 #include "clock.h"
34
35 /* Crystal clock: 13MHz */
36 #define BASE_CLK 13000000
37
38 /*
39 * Get the clock frequency as reflected by CCSR and the turbo flag.
40 * We assume these values have been applied via a fcs.
41 * If info is not 0 we also display the current settings.
42 */
43 unsigned int pxa27x_get_clk_frequency_khz(int info)
44 {
45 unsigned long ccsr, clkcfg;
46 unsigned int l, L, m, M, n2, N, S;
47 int cccr_a, t, ht, b;
48
49 ccsr = CCSR;
50 cccr_a = CCCR & (1 << 25);
51
52 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
53 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
54 t = clkcfg & (1 << 0);
55 ht = clkcfg & (1 << 2);
56 b = clkcfg & (1 << 3);
57
58 l = ccsr & 0x1f;
59 n2 = (ccsr>>7) & 0xf;
60 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
61
62 L = l * BASE_CLK;
63 N = (L * n2) / 2;
64 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
65 S = (b) ? L : (L/2);
66
67 if (info) {
68 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
69 L / 1000000, (L % 1000000) / 10000, l );
70 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
71 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
72 (t) ? "" : "in" );
73 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
74 M / 1000000, (M % 1000000) / 10000, m );
75 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
76 S / 1000000, (S % 1000000) / 10000 );
77 }
78
79 return (t) ? (N/1000) : (L/1000);
80 }
81
82 /*
83 * Return the current mem clock frequency in units of 10kHz as
84 * reflected by CCCR[A], B, and L
85 */
86 unsigned int pxa27x_get_memclk_frequency_10khz(void)
87 {
88 unsigned long ccsr, clkcfg;
89 unsigned int l, L, m, M;
90 int cccr_a, b;
91
92 ccsr = CCSR;
93 cccr_a = CCCR & (1 << 25);
94
95 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
96 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
97 b = clkcfg & (1 << 3);
98
99 l = ccsr & 0x1f;
100 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
101
102 L = l * BASE_CLK;
103 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
104
105 return (M / 10000);
106 }
107
108 /*
109 * Return the current LCD clock frequency in units of 10kHz as
110 */
111 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
112 {
113 unsigned long ccsr;
114 unsigned int l, L, k, K;
115
116 ccsr = CCSR;
117
118 l = ccsr & 0x1f;
119 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
120
121 L = l * BASE_CLK;
122 K = L / k;
123
124 return (K / 10000);
125 }
126
127 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
128 {
129 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
130 }
131
132 static const struct clkops clk_pxa27x_lcd_ops = {
133 .enable = clk_cken_enable,
134 .disable = clk_cken_disable,
135 .getrate = clk_pxa27x_lcd_getrate,
136 };
137
138 static struct clk pxa27x_clks[] = {
139 INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
140 INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
141
142 INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
143 INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
144 INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
145
146 INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
147 INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
148 INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
149 INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
150 INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
151
152 INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
153 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
154 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
155
156 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
157 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
158 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
159
160 /*
161 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
162 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
163 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
164 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
165 INIT_CKEN("IMCLK", IM, 0, 0, NULL),
166 INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
167 */
168 };
169
170 #ifdef CONFIG_PM
171
172 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
173 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
174
175 /*
176 * List of global PXA peripheral registers to preserve.
177 * More ones like CP and general purpose register values are preserved
178 * with the stack pointer in sleep.S.
179 */
180 enum { SLEEP_SAVE_START = 0,
181
182 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
183
184 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
185 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
186 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
187 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
188
189 SLEEP_SAVE_PSTR,
190
191 SLEEP_SAVE_CKEN,
192
193 SLEEP_SAVE_MDREFR,
194 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
195 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
196
197 SLEEP_SAVE_SIZE
198 };
199
200 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
201 {
202 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
203
204 SAVE(GAFR0_L); SAVE(GAFR0_U);
205 SAVE(GAFR1_L); SAVE(GAFR1_U);
206 SAVE(GAFR2_L); SAVE(GAFR2_U);
207 SAVE(GAFR3_L); SAVE(GAFR3_U);
208
209 SAVE(MDREFR);
210 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
211 SAVE(PFER); SAVE(PKWR);
212
213 SAVE(CKEN);
214 SAVE(PSTR);
215 }
216
217 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
218 {
219 /* ensure not to come back here if it wasn't intended */
220 PSPR = 0;
221
222 /* restore registers */
223 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
224 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
225 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
226 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
227 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
228
229 RESTORE(MDREFR);
230 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
231 RESTORE(PFER); RESTORE(PKWR);
232
233 PSSR = PSSR_RDH | PSSR_PH;
234
235 RESTORE(CKEN);
236
237 RESTORE(PSTR);
238 }
239
240 void pxa27x_cpu_pm_enter(suspend_state_t state)
241 {
242 extern void pxa_cpu_standby(void);
243
244 /* ensure voltage-change sequencer not initiated, which hangs */
245 PCFR &= ~PCFR_FVC;
246
247 /* Clear edge-detect status register. */
248 PEDR = 0xDF12FE1B;
249
250 switch (state) {
251 case PM_SUSPEND_STANDBY:
252 pxa_cpu_standby();
253 break;
254 case PM_SUSPEND_MEM:
255 /* set resume return address */
256 PSPR = virt_to_phys(pxa_cpu_resume);
257 pxa27x_cpu_suspend(PWRMODE_SLEEP);
258 break;
259 }
260 }
261
262 static int pxa27x_cpu_pm_valid(suspend_state_t state)
263 {
264 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
265 }
266
267 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
268 .save_size = SLEEP_SAVE_SIZE,
269 .save = pxa27x_cpu_pm_save,
270 .restore = pxa27x_cpu_pm_restore,
271 .valid = pxa27x_cpu_pm_valid,
272 .enter = pxa27x_cpu_pm_enter,
273 };
274
275 static void __init pxa27x_init_pm(void)
276 {
277 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
278 }
279 #else
280 static inline void pxa27x_init_pm(void) {}
281 #endif
282
283 /* PXA27x: Various gpios can issue wakeup events. This logic only
284 * handles the simple cases, not the WEMUX2 and WEMUX3 options
285 */
286 #define PXA27x_GPIO_NOWAKE_MASK \
287 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
288 #define WAKEMASK(gpio) \
289 (((gpio) <= 15) \
290 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
291 : ((gpio == 35) ? (1 << 24) : 0))
292
293 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
294 {
295 int gpio = IRQ_TO_GPIO(irq);
296 uint32_t mask;
297
298 if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
299 if (WAKEMASK(gpio) == 0)
300 return -EINVAL;
301
302 mask = WAKEMASK(gpio);
303
304 if (on) {
305 if (GRER(gpio) | GPIO_bit(gpio))
306 PRER |= mask;
307 else
308 PRER &= ~mask;
309
310 if (GFER(gpio) | GPIO_bit(gpio))
311 PFER |= mask;
312 else
313 PFER &= ~mask;
314 }
315 goto set_pwer;
316 }
317
318 switch (irq) {
319 case IRQ_RTCAlrm:
320 mask = PWER_RTC;
321 break;
322 case IRQ_USB:
323 mask = 1u << 26;
324 break;
325 default:
326 return -EINVAL;
327 }
328
329 set_pwer:
330 if (on)
331 PWER |= mask;
332 else
333 PWER &=~mask;
334
335 return 0;
336 }
337
338 void __init pxa27x_init_irq(void)
339 {
340 pxa_init_irq_low();
341 pxa_init_irq_high();
342 pxa_init_irq_gpio(128);
343 pxa_init_irq_set_wake(pxa27x_set_wake);
344 }
345
346 /*
347 * device registration specific to PXA27x.
348 */
349
350 static struct resource i2c_power_resources[] = {
351 {
352 .start = 0x40f00180,
353 .end = 0x40f001a3,
354 .flags = IORESOURCE_MEM,
355 }, {
356 .start = IRQ_PWRI2C,
357 .end = IRQ_PWRI2C,
358 .flags = IORESOURCE_IRQ,
359 },
360 };
361
362 struct platform_device pxa27x_device_i2c_power = {
363 .name = "pxa2xx-i2c",
364 .id = 1,
365 .resource = i2c_power_resources,
366 .num_resources = ARRAY_SIZE(i2c_power_resources),
367 };
368
369 void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
370 {
371 pxa27x_device_i2c_power.dev.platform_data = info;
372 }
373
374 static struct platform_device *devices[] __initdata = {
375 &pxa_device_udc,
376 &pxa_device_ffuart,
377 &pxa_device_btuart,
378 &pxa_device_stuart,
379 &pxa_device_i2s,
380 &pxa_device_rtc,
381 &pxa27x_device_i2c_power,
382 &pxa27x_device_ssp1,
383 &pxa27x_device_ssp2,
384 &pxa27x_device_ssp3,
385 };
386
387 static struct sys_device pxa27x_sysdev[] = {
388 {
389 .id = 0,
390 .cls = &pxa_irq_sysclass,
391 }, {
392 .id = 1,
393 .cls = &pxa_irq_sysclass,
394 }, {
395 .cls = &pxa_gpio_sysclass,
396 },
397 };
398
399 static int __init pxa27x_init(void)
400 {
401 int i, ret = 0;
402
403 if (cpu_is_pxa27x()) {
404 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
405
406 if ((ret = pxa_init_dma(32)))
407 return ret;
408
409 pxa27x_init_pm();
410
411 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
412 ret = sysdev_register(&pxa27x_sysdev[i]);
413 if (ret)
414 pr_err("failed to register sysdev[%d]\n", i);
415 }
416
417 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
418 }
419
420 return ret;
421 }
422
423 subsys_initcall(pxa27x_init);
424
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