1 /*
2 * linux/arch/arm/mach-pxa/pxa25x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA21x/25x/26x variants.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
17 * need be.
18 */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
24 #include <linux/sysdev.h>
25
26 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <mach/pxa25x.h>
30 #include <mach/reset.h>
31 #include <mach/pm.h>
32 #include <mach/dma.h>
33
34 #include "generic.h"
35 #include "devices.h"
36 #include "clock.h"
37
38 /*
39 * Various clock factors driven by the CCCR register.
40 */
41
42 /* Crystal Frequency to Memory Frequency Multiplier (L) */
43 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
44
45 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
46 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
47
48 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
49 /* Note: we store the value N * 2 here. */
50 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
51
52 /* Crystal clock */
53 #define BASE_CLK 3686400
54
55 /*
56 * Get the clock frequency as reflected by CCCR and the turbo flag.
57 * We assume these values have been applied via a fcs.
58 * If info is not 0 we also display the current settings.
59 */
60 unsigned int pxa25x_get_clk_frequency_khz(int info)
61 {
62 unsigned long cccr, turbo;
63 unsigned int l, L, m, M, n2, N;
64
65 cccr = CCCR;
66 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
67
68 l = L_clk_mult[(cccr >> 0) & 0x1f];
69 m = M_clk_mult[(cccr >> 5) & 0x03];
70 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
71
72 L = l * BASE_CLK;
73 M = m * L;
74 N = n2 * M / 2;
75
76 if(info)
77 {
78 L += 5000;
79 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
80 L / 1000000, (L % 1000000) / 10000, l );
81 M += 5000;
82 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
83 M / 1000000, (M % 1000000) / 10000, m );
84 N += 5000;
85 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
86 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
87 (turbo & 1) ? "" : "in" );
88 }
89
90 return (turbo & 1) ? (N/1000) : (M/1000);
91 }
92
93 /*
94 * Return the current memory clock frequency in units of 10kHz
95 */
96 unsigned int pxa25x_get_memclk_frequency_10khz(void)
97 {
98 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
99 }
100
101 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
102 {
103 return pxa25x_get_memclk_frequency_10khz() * 10000;
104 }
105
106 static const struct clkops clk_pxa25x_lcd_ops = {
107 .enable = clk_cken_enable,
108 .disable = clk_cken_disable,
109 .getrate = clk_pxa25x_lcd_getrate,
110 };
111
112 static unsigned long gpio12_config_32k[] = {
113 GPIO12_32KHz,
114 };
115
116 static unsigned long gpio12_config_gpio[] = {
117 GPIO12_GPIO,
118 };
119
120 static void clk_gpio12_enable(struct clk *clk)
121 {
122 pxa2xx_mfp_config(gpio12_config_32k, 1);
123 }
124
125 static void clk_gpio12_disable(struct clk *clk)
126 {
127 pxa2xx_mfp_config(gpio12_config_gpio, 1);
128 }
129
130 static const struct clkops clk_pxa25x_gpio12_ops = {
131 .enable = clk_gpio12_enable,
132 .disable = clk_gpio12_disable,
133 };
134
135 static unsigned long gpio11_config_3m6[] = {
136 GPIO11_3_6MHz,
137 };
138
139 static unsigned long gpio11_config_gpio[] = {
140 GPIO11_GPIO,
141 };
142
143 static void clk_gpio11_enable(struct clk *clk)
144 {
145 pxa2xx_mfp_config(gpio11_config_3m6, 1);
146 }
147
148 static void clk_gpio11_disable(struct clk *clk)
149 {
150 pxa2xx_mfp_config(gpio11_config_gpio, 1);
151 }
152
153 static const struct clkops clk_pxa25x_gpio11_ops = {
154 .enable = clk_gpio11_enable,
155 .disable = clk_gpio11_disable,
156 };
157
158 /*
159 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
160 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
161 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
162 */
163 static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
164
165 static struct clk_lookup pxa25x_hwuart_clkreg =
166 INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
167
168 /*
169 * PXA 2xx clock declarations.
170 */
171 static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
172 static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
173 static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
174 static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
175 static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
176 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
177 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
178 static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
179 static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
180 static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
181 static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
182 static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
183 static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
184 static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
185 static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
186 static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
187 static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
188
189 static struct clk_lookup pxa25x_clkregs[] = {
190 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
191 INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
192 INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
193 INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
194 INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
195 INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
196 INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
197 INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
198 INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
199 INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
200 INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
201 INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
202 INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
203 INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
204 INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
205 INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
206 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
207 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
208 };
209
210 #ifdef CONFIG_PM
211
212 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
213 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
214
215 /*
216 * List of global PXA peripheral registers to preserve.
217 * More ones like CP and general purpose register values are preserved
218 * with the stack pointer in sleep.S.
219 */
220 enum {
221 SLEEP_SAVE_PSTR,
222 SLEEP_SAVE_CKEN,
223 SLEEP_SAVE_COUNT
224 };
225
226
227 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
228 {
229 SAVE(CKEN);
230 SAVE(PSTR);
231 }
232
233 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
234 {
235 RESTORE(CKEN);
236 RESTORE(PSTR);
237 }
238
239 static void pxa25x_cpu_pm_enter(suspend_state_t state)
240 {
241 /* Clear reset status */
242 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
243
244 switch (state) {
245 case PM_SUSPEND_MEM:
246 pxa25x_cpu_suspend(PWRMODE_SLEEP);
247 break;
248 }
249 }
250
251 static int pxa25x_cpu_pm_prepare(void)
252 {
253 /* set resume return address */
254 PSPR = virt_to_phys(pxa_cpu_resume);
255 return 0;
256 }
257
258 static void pxa25x_cpu_pm_finish(void)
259 {
260 /* ensure not to come back here if it wasn't intended */
261 PSPR = 0;
262 }
263
264 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
265 .save_count = SLEEP_SAVE_COUNT,
266 .valid = suspend_valid_only_mem,
267 .save = pxa25x_cpu_pm_save,
268 .restore = pxa25x_cpu_pm_restore,
269 .enter = pxa25x_cpu_pm_enter,
270 .prepare = pxa25x_cpu_pm_prepare,
271 .finish = pxa25x_cpu_pm_finish,
272 };
273
274 static void __init pxa25x_init_pm(void)
275 {
276 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
277 }
278 #else
279 static inline void pxa25x_init_pm(void) {}
280 #endif
281
282 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
283 */
284
285 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
286 {
287 int gpio = IRQ_TO_GPIO(irq);
288 uint32_t mask = 0;
289
290 if (gpio >= 0 && gpio < 85)
291 return gpio_set_wake(gpio, on);
292
293 if (irq == IRQ_RTCAlrm) {
294 mask = PWER_RTC;
295 goto set_pwer;
296 }
297
298 return -EINVAL;
299
300 set_pwer:
301 if (on)
302 PWER |= mask;
303 else
304 PWER &=~mask;
305
306 return 0;
307 }
308
309 void __init pxa25x_init_irq(void)
310 {
311 pxa_init_irq(32, pxa25x_set_wake);
312 pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
313 }
314
315 #ifdef CONFIG_CPU_PXA26x
316 void __init pxa26x_init_irq(void)
317 {
318 pxa_init_irq(32, pxa25x_set_wake);
319 pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
320 }
321 #endif
322
323 static struct platform_device *pxa25x_devices[] __initdata = {
324 &pxa25x_device_udc,
325 &pxa_device_ffuart,
326 &pxa_device_btuart,
327 &pxa_device_stuart,
328 &pxa_device_i2s,
329 &sa1100_device_rtc,
330 &pxa25x_device_ssp,
331 &pxa25x_device_nssp,
332 &pxa25x_device_assp,
333 &pxa25x_device_pwm0,
334 &pxa25x_device_pwm1,
335 };
336
337 static struct sys_device pxa25x_sysdev[] = {
338 {
339 .cls = &pxa_irq_sysclass,
340 }, {
341 .cls = &pxa2xx_mfp_sysclass,
342 }, {
343 .cls = &pxa_gpio_sysclass,
344 },
345 };
346
347 static int __init pxa25x_init(void)
348 {
349 int i, ret = 0;
350
351 if (cpu_is_pxa25x()) {
352
353 reset_status = RCSR;
354
355 clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
356
357 if ((ret = pxa_init_dma(IRQ_DMA, 16)))
358 return ret;
359
360 pxa25x_init_pm();
361
362 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
363 ret = sysdev_register(&pxa25x_sysdev[i]);
364 if (ret)
365 pr_err("failed to register sysdev[%d]\n", i);
366 }
367
368 ret = platform_add_devices(pxa25x_devices,
369 ARRAY_SIZE(pxa25x_devices));
370 if (ret)
371 return ret;
372 }
373
374 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
375 if (cpu_is_pxa255()) {
376 clks_register(&pxa25x_hwuart_clkreg, 1);
377 ret = platform_device_register(&pxa_device_hwuart);
378 }
379
380 return ret;
381 }
382
383 postcore_initcall(pxa25x_init);
384
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