1 /*
2 * arch/arm/mach-ixp2000/include/mach/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #ifndef __ASM_ARM_ARCH_IO_H
16 #define __ASM_ARM_ARCH_IO_H
17
18 #include <mach/hardware.h>
19
20 #define IO_SPACE_LIMIT 0xffffffff
21 #define __mem_pci(a) (a)
22
23 /*
24 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
25 * transactions the other way round (MEM transactions don't have this
26 * issue), so if we want to support those models, we need to override
27 * the standard I/O functions.
28 *
29 * B0 and later have a bit that can be set to 1 to get the proper
30 * behavior for I/O transactions, which then allows us to use the
31 * standard I/O functions. This is what we do if the user does not
32 * explicitly ask for support for pre-B0.
33 */
34 #ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
35 #define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
36
37 #define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
38 #define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
39
40 #define outb(v,p) __raw_writeb((v),alignb(___io(p)))
41 #define outw(v,p) __raw_writew((v),alignw(___io(p)))
42 #define outl(v,p) __raw_writel((v),___io(p))
43
44 #define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
45 #define inw(p) \
46 ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
47 #define inl(p) \
48 ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
49
50 #define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
51 #define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
52 #define outsl(p,d,l) __raw_writesl(___io(p),d,l)
53
54 #define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
55 #define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
56 #define insl(p,d,l) __raw_readsl(___io(p),d,l)
57
58 #define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
59
60 #define ioread8(p) \
61 ({ \
62 unsigned int __v; \
63 \
64 if (__is_io_address(p)) { \
65 __v = __raw_readb(alignb(p)); \
66 } else { \
67 __v = __raw_readb(p); \
68 } \
69 \
70 __v; \
71 }) \
72
73 #define ioread16(p) \
74 ({ \
75 unsigned int __v; \
76 \
77 if (__is_io_address(p)) { \
78 __v = __raw_readw(alignw(p)); \
79 } else { \
80 __v = le16_to_cpu(__raw_readw(p)); \
81 } \
82 \
83 __v; \
84 })
85
86 #define ioread32(p) \
87 ({ \
88 unsigned int __v; \
89 \
90 if (__is_io_address(p)) { \
91 __v = __raw_readl(p); \
92 } else { \
93 __v = le32_to_cpu(__raw_readl(p)); \
94 } \
95 \
96 __v; \
97 })
98
99 #define iowrite8(v,p) \
100 ({ \
101 if (__is_io_address(p)) { \
102 __raw_writeb((v), alignb(p)); \
103 } else { \
104 __raw_writeb((v), p); \
105 } \
106 })
107
108 #define iowrite16(v,p) \
109 ({ \
110 if (__is_io_address(p)) { \
111 __raw_writew((v), alignw(p)); \
112 } else { \
113 __raw_writew(cpu_to_le16(v), p); \
114 } \
115 })
116
117 #define iowrite32(v,p) \
118 ({ \
119 if (__is_io_address(p)) { \
120 __raw_writel((v), p); \
121 } else { \
122 __raw_writel(cpu_to_le32(v), p); \
123 } \
124 })
125
126 #define ioport_map(port, nr) ___io(port)
127
128 #define ioport_unmap(addr)
129 #else
130 #define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
131 #endif
132
133
134 #endif
135
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