1 /*
2 * linux/arch/arm/mach-integrator/core.c
3 *
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/device.h>
14 #include <linux/spinlock.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/termios.h>
20 #include <linux/amba/bus.h>
21 #include <linux/amba/serial.h>
22 #include <linux/io.h>
23
24 #include <asm/clkdev.h>
25 #include <mach/clkdev.h>
26 #include <mach/hardware.h>
27 #include <asm/irq.h>
28 #include <asm/hardware/arm_timer.h>
29 #include <mach/cm.h>
30 #include <asm/system.h>
31 #include <asm/leds.h>
32 #include <asm/mach/time.h>
33
34 #include "common.h"
35
36 static struct amba_pl010_data integrator_uart_data;
37
38 static struct amba_device rtc_device = {
39 .dev = {
40 .init_name = "mb:15",
41 },
42 .res = {
43 .start = INTEGRATOR_RTC_BASE,
44 .end = INTEGRATOR_RTC_BASE + SZ_4K - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 .irq = { IRQ_RTCINT, NO_IRQ },
48 .periphid = 0x00041030,
49 };
50
51 static struct amba_device uart0_device = {
52 .dev = {
53 .init_name = "mb:16",
54 .platform_data = &integrator_uart_data,
55 },
56 .res = {
57 .start = INTEGRATOR_UART0_BASE,
58 .end = INTEGRATOR_UART0_BASE + SZ_4K - 1,
59 .flags = IORESOURCE_MEM,
60 },
61 .irq = { IRQ_UARTINT0, NO_IRQ },
62 .periphid = 0x0041010,
63 };
64
65 static struct amba_device uart1_device = {
66 .dev = {
67 .init_name = "mb:17",
68 .platform_data = &integrator_uart_data,
69 },
70 .res = {
71 .start = INTEGRATOR_UART1_BASE,
72 .end = INTEGRATOR_UART1_BASE + SZ_4K - 1,
73 .flags = IORESOURCE_MEM,
74 },
75 .irq = { IRQ_UARTINT1, NO_IRQ },
76 .periphid = 0x0041010,
77 };
78
79 static struct amba_device kmi0_device = {
80 .dev = {
81 .init_name = "mb:18",
82 },
83 .res = {
84 .start = KMI0_BASE,
85 .end = KMI0_BASE + SZ_4K - 1,
86 .flags = IORESOURCE_MEM,
87 },
88 .irq = { IRQ_KMIINT0, NO_IRQ },
89 .periphid = 0x00041050,
90 };
91
92 static struct amba_device kmi1_device = {
93 .dev = {
94 .init_name = "mb:19",
95 },
96 .res = {
97 .start = KMI1_BASE,
98 .end = KMI1_BASE + SZ_4K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 .irq = { IRQ_KMIINT1, NO_IRQ },
102 .periphid = 0x00041050,
103 };
104
105 static struct amba_device *amba_devs[] __initdata = {
106 &rtc_device,
107 &uart0_device,
108 &uart1_device,
109 &kmi0_device,
110 &kmi1_device,
111 };
112
113 /*
114 * These are fixed clocks.
115 */
116 static struct clk clk24mhz = {
117 .rate = 24000000,
118 };
119
120 static struct clk uartclk = {
121 .rate = 14745600,
122 };
123
124 static struct clk_lookup lookups[] = {
125 { /* UART0 */
126 .dev_id = "mb:16",
127 .clk = &uartclk,
128 }, { /* UART1 */
129 .dev_id = "mb:17",
130 .clk = &uartclk,
131 }, { /* KMI0 */
132 .dev_id = "mb:18",
133 .clk = &clk24mhz,
134 }, { /* KMI1 */
135 .dev_id = "mb:19",
136 .clk = &clk24mhz,
137 }, { /* MMCI - IntegratorCP */
138 .dev_id = "mb:1c",
139 .clk = &uartclk,
140 }
141 };
142
143 static int __init integrator_init(void)
144 {
145 int i;
146
147 for (i = 0; i < ARRAY_SIZE(lookups); i++)
148 clkdev_add(&lookups[i]);
149
150 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
151 struct amba_device *d = amba_devs[i];
152 amba_device_register(d, &iomem_resource);
153 }
154
155 return 0;
156 }
157
158 arch_initcall(integrator_init);
159
160 /*
161 * On the Integrator platform, the port RTS and DTR are provided by
162 * bits in the following SC_CTRLS register bits:
163 * RTS DTR
164 * UART0 7 6
165 * UART1 5 4
166 */
167 #define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
168 #define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
169
170 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
171 {
172 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
173
174 if (dev == &uart0_device) {
175 rts_mask = 1 << 4;
176 dtr_mask = 1 << 5;
177 } else {
178 rts_mask = 1 << 6;
179 dtr_mask = 1 << 7;
180 }
181
182 if (mctrl & TIOCM_RTS)
183 ctrlc |= rts_mask;
184 else
185 ctrls |= rts_mask;
186
187 if (mctrl & TIOCM_DTR)
188 ctrlc |= dtr_mask;
189 else
190 ctrls |= dtr_mask;
191
192 __raw_writel(ctrls, SC_CTRLS);
193 __raw_writel(ctrlc, SC_CTRLC);
194 }
195
196 static struct amba_pl010_data integrator_uart_data = {
197 .set_mctrl = integrator_uart_set_mctrl,
198 };
199
200 #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET
201
202 static DEFINE_SPINLOCK(cm_lock);
203
204 /**
205 * cm_control - update the CM_CTRL register.
206 * @mask: bits to change
207 * @set: bits to set
208 */
209 void cm_control(u32 mask, u32 set)
210 {
211 unsigned long flags;
212 u32 val;
213
214 spin_lock_irqsave(&cm_lock, flags);
215 val = readl(CM_CTRL) & ~mask;
216 writel(val | set, CM_CTRL);
217 spin_unlock_irqrestore(&cm_lock, flags);
218 }
219
220 EXPORT_SYMBOL(cm_control);
221
222 /*
223 * Where is the timer (VA)?
224 */
225 #define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000)
226 #define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100)
227 #define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200)
228 #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
229
230 /*
231 * How long is the timer interval?
232 */
233 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
234 #if TIMER_INTERVAL >= 0x100000
235 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
236 #elif TIMER_INTERVAL >= 0x10000
237 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
238 #else
239 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
240 #endif
241
242 static unsigned long timer_reload;
243
244 /*
245 * Returns number of ms since last clock interrupt. Note that interrupts
246 * will have been disabled by do_gettimeoffset()
247 */
248 unsigned long integrator_gettimeoffset(void)
249 {
250 unsigned long ticks1, ticks2, status;
251
252 /*
253 * Get the current number of ticks. Note that there is a race
254 * condition between us reading the timer and checking for
255 * an interrupt. We get around this by ensuring that the
256 * counter has not reloaded between our two reads.
257 */
258 ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
259 do {
260 ticks1 = ticks2;
261 status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS);
262 ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
263 } while (ticks2 > ticks1);
264
265 /*
266 * Number of ticks since last interrupt.
267 */
268 ticks1 = timer_reload - ticks2;
269
270 /*
271 * Interrupt pending? If so, we've reloaded once already.
272 */
273 if (status & (1 << IRQ_TIMERINT1))
274 ticks1 += timer_reload;
275
276 /*
277 * Convert the ticks to usecs
278 */
279 return TICKS2USECS(ticks1);
280 }
281
282 /*
283 * IRQ handler for the timer
284 */
285 static irqreturn_t
286 integrator_timer_interrupt(int irq, void *dev_id)
287 {
288 /*
289 * clear the interrupt
290 */
291 writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
292
293 timer_tick();
294
295 return IRQ_HANDLED;
296 }
297
298 static struct irqaction integrator_timer_irq = {
299 .name = "Integrator Timer Tick",
300 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
301 .handler = integrator_timer_interrupt,
302 };
303
304 /*
305 * Set up timer interrupt, and return the current time in seconds.
306 */
307 void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
308 {
309 unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
310
311 timer_reload = reload;
312 timer_ctrl |= ctrl;
313
314 if (timer_reload > 0x100000) {
315 timer_reload >>= 8;
316 timer_ctrl |= TIMER_CTRL_DIV256;
317 } else if (timer_reload > 0x010000) {
318 timer_reload >>= 4;
319 timer_ctrl |= TIMER_CTRL_DIV16;
320 }
321
322 /*
323 * Initialise to a known state (all timers off)
324 */
325 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
326 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
327 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
328
329 writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD);
330 writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE);
331 writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL);
332
333 /*
334 * Make irqs happen for the system timer
335 */
336 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
337 }
338
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