1 /*
2 * Clock and PLL control for DaVinci devices
3 *
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/mutex.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22
23 #include <mach/hardware.h>
24
25 #include <mach/psc.h>
26 #include <mach/cputype.h>
27 #include "clock.h"
28
29 static LIST_HEAD(clocks);
30 static DEFINE_MUTEX(clocks_mutex);
31 static DEFINE_SPINLOCK(clockfw_lock);
32
33 static unsigned psc_domain(struct clk *clk)
34 {
35 return (clk->flags & PSC_DSP)
36 ? DAVINCI_GPSC_DSPDOMAIN
37 : DAVINCI_GPSC_ARMDOMAIN;
38 }
39
40 static void __clk_enable(struct clk *clk)
41 {
42 if (clk->parent)
43 __clk_enable(clk->parent);
44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
45 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
46 clk->lpsc, 1);
47 }
48
49 static void __clk_disable(struct clk *clk)
50 {
51 if (WARN_ON(clk->usecount == 0))
52 return;
53 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
54 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
55 clk->lpsc, 0);
56 if (clk->parent)
57 __clk_disable(clk->parent);
58 }
59
60 int clk_enable(struct clk *clk)
61 {
62 unsigned long flags;
63
64 if (clk == NULL || IS_ERR(clk))
65 return -EINVAL;
66
67 spin_lock_irqsave(&clockfw_lock, flags);
68 __clk_enable(clk);
69 spin_unlock_irqrestore(&clockfw_lock, flags);
70
71 return 0;
72 }
73 EXPORT_SYMBOL(clk_enable);
74
75 void clk_disable(struct clk *clk)
76 {
77 unsigned long flags;
78
79 if (clk == NULL || IS_ERR(clk))
80 return;
81
82 spin_lock_irqsave(&clockfw_lock, flags);
83 __clk_disable(clk);
84 spin_unlock_irqrestore(&clockfw_lock, flags);
85 }
86 EXPORT_SYMBOL(clk_disable);
87
88 unsigned long clk_get_rate(struct clk *clk)
89 {
90 if (clk == NULL || IS_ERR(clk))
91 return -EINVAL;
92
93 return clk->rate;
94 }
95 EXPORT_SYMBOL(clk_get_rate);
96
97 long clk_round_rate(struct clk *clk, unsigned long rate)
98 {
99 if (clk == NULL || IS_ERR(clk))
100 return -EINVAL;
101
102 return clk->rate;
103 }
104 EXPORT_SYMBOL(clk_round_rate);
105
106 int clk_set_rate(struct clk *clk, unsigned long rate)
107 {
108 if (clk == NULL || IS_ERR(clk))
109 return -EINVAL;
110
111 /* changing the clk rate is not supported */
112 return -EINVAL;
113 }
114 EXPORT_SYMBOL(clk_set_rate);
115
116 int clk_register(struct clk *clk)
117 {
118 if (clk == NULL || IS_ERR(clk))
119 return -EINVAL;
120
121 if (WARN(clk->parent && !clk->parent->rate,
122 "CLK: %s parent %s has no rate!\n",
123 clk->name, clk->parent->name))
124 return -EINVAL;
125
126 mutex_lock(&clocks_mutex);
127 list_add_tail(&clk->node, &clocks);
128 mutex_unlock(&clocks_mutex);
129
130 /* If rate is already set, use it */
131 if (clk->rate)
132 return 0;
133
134 /* Otherwise, default to parent rate */
135 if (clk->parent)
136 clk->rate = clk->parent->rate;
137
138 return 0;
139 }
140 EXPORT_SYMBOL(clk_register);
141
142 void clk_unregister(struct clk *clk)
143 {
144 if (clk == NULL || IS_ERR(clk))
145 return;
146
147 mutex_lock(&clocks_mutex);
148 list_del(&clk->node);
149 mutex_unlock(&clocks_mutex);
150 }
151 EXPORT_SYMBOL(clk_unregister);
152
153 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
154 /*
155 * Disable any unused clocks left on by the bootloader
156 */
157 static int __init clk_disable_unused(void)
158 {
159 struct clk *ck;
160
161 spin_lock_irq(&clockfw_lock);
162 list_for_each_entry(ck, &clocks, node) {
163 if (ck->usecount > 0)
164 continue;
165 if (!(ck->flags & CLK_PSC))
166 continue;
167
168 /* ignore if in Disabled or SwRstDisable states */
169 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
170 continue;
171
172 pr_info("Clocks: disable unused %s\n", ck->name);
173 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
174 }
175 spin_unlock_irq(&clockfw_lock);
176
177 return 0;
178 }
179 late_initcall(clk_disable_unused);
180 #endif
181
182 static void clk_sysclk_recalc(struct clk *clk)
183 {
184 u32 v, plldiv;
185 struct pll_data *pll;
186
187 /* If this is the PLL base clock, no more calculations needed */
188 if (clk->pll_data)
189 return;
190
191 if (WARN_ON(!clk->parent))
192 return;
193
194 clk->rate = clk->parent->rate;
195
196 /* Otherwise, the parent must be a PLL */
197 if (WARN_ON(!clk->parent->pll_data))
198 return;
199
200 pll = clk->parent->pll_data;
201
202 /* If pre-PLL, source clock is before the multiplier and divider(s) */
203 if (clk->flags & PRE_PLL)
204 clk->rate = pll->input_rate;
205
206 if (!clk->div_reg)
207 return;
208
209 v = __raw_readl(pll->base + clk->div_reg);
210 if (v & PLLDIV_EN) {
211 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
212 if (plldiv)
213 clk->rate /= plldiv;
214 }
215 }
216
217 static void __init clk_pll_init(struct clk *clk)
218 {
219 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
220 u8 bypass;
221 struct pll_data *pll = clk->pll_data;
222
223 pll->base = IO_ADDRESS(pll->phys_base);
224 ctrl = __raw_readl(pll->base + PLLCTL);
225 clk->rate = pll->input_rate = clk->parent->rate;
226
227 if (ctrl & PLLCTL_PLLEN) {
228 bypass = 0;
229 mult = __raw_readl(pll->base + PLLM);
230 mult = (mult & PLLM_PLLM_MASK) + 1;
231 } else
232 bypass = 1;
233
234 if (pll->flags & PLL_HAS_PREDIV) {
235 prediv = __raw_readl(pll->base + PREDIV);
236 if (prediv & PLLDIV_EN)
237 prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
238 else
239 prediv = 1;
240 }
241
242 /* pre-divider is fixed, but (some?) chips won't report that */
243 if (cpu_is_davinci_dm355() && pll->num == 1)
244 prediv = 8;
245
246 if (pll->flags & PLL_HAS_POSTDIV) {
247 postdiv = __raw_readl(pll->base + POSTDIV);
248 if (postdiv & PLLDIV_EN)
249 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
250 else
251 postdiv = 1;
252 }
253
254 if (!bypass) {
255 clk->rate /= prediv;
256 clk->rate *= mult;
257 clk->rate /= postdiv;
258 }
259
260 pr_debug("PLL%d: input = %lu MHz [ ",
261 pll->num, clk->parent->rate / 1000000);
262 if (bypass)
263 pr_debug("bypass ");
264 if (prediv > 1)
265 pr_debug("/ %d ", prediv);
266 if (mult > 1)
267 pr_debug("* %d ", mult);
268 if (postdiv > 1)
269 pr_debug("/ %d ", postdiv);
270 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
271 }
272
273 int __init davinci_clk_init(struct davinci_clk *clocks)
274 {
275 struct davinci_clk *c;
276 struct clk *clk;
277
278 for (c = clocks; c->lk.clk; c++) {
279 clk = c->lk.clk;
280
281 if (clk->pll_data)
282 clk_pll_init(clk);
283
284 /* Calculate rates for PLL-derived clocks */
285 else if (clk->flags & CLK_PLL)
286 clk_sysclk_recalc(clk);
287
288 if (clk->lpsc)
289 clk->flags |= CLK_PSC;
290
291 clkdev_add(&c->lk);
292 clk_register(clk);
293
294 /* Turn on clocks that Linux doesn't otherwise manage */
295 if (clk->flags & ALWAYS_ENABLED)
296 clk_enable(clk);
297 }
298
299 return 0;
300 }
301
302 #ifdef CONFIG_PROC_FS
303 #include <linux/proc_fs.h>
304 #include <linux/seq_file.h>
305
306 static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
307 {
308 return *pos < 1 ? (void *)1 : NULL;
309 }
310
311 static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
312 {
313 ++*pos;
314 return NULL;
315 }
316
317 static void davinci_ck_stop(struct seq_file *m, void *v)
318 {
319 }
320
321 #define CLKNAME_MAX 10 /* longest clock name */
322 #define NEST_DELTA 2
323 #define NEST_MAX 4
324
325 static void
326 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
327 {
328 char *state;
329 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
330 struct clk *clk;
331 unsigned i;
332
333 if (parent->flags & CLK_PLL)
334 state = "pll";
335 else if (parent->flags & CLK_PSC)
336 state = "psc";
337 else
338 state = "";
339
340 /* <nest spaces> name <pad to end> */
341 memset(buf, ' ', sizeof(buf) - 1);
342 buf[sizeof(buf) - 1] = 0;
343 i = strlen(parent->name);
344 memcpy(buf + nest, parent->name,
345 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
346
347 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
348 buf, parent->usecount, state, clk_get_rate(parent));
349 /* REVISIT show device associations too */
350
351 /* cost is now small, but not linear... */
352 list_for_each_entry(clk, &clocks, node) {
353 if (clk->parent == parent)
354 dump_clock(s, nest + NEST_DELTA, clk);
355 }
356 }
357
358 static int davinci_ck_show(struct seq_file *m, void *v)
359 {
360 /* Show clock tree; we know the main oscillator is first.
361 * We trust nonzero usecounts equate to PSC enables...
362 */
363 mutex_lock(&clocks_mutex);
364 if (!list_empty(&clocks))
365 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
366 mutex_unlock(&clocks_mutex);
367
368 return 0;
369 }
370
371 static const struct seq_operations davinci_ck_op = {
372 .start = davinci_ck_start,
373 .next = davinci_ck_next,
374 .stop = davinci_ck_stop,
375 .show = davinci_ck_show
376 };
377
378 static int davinci_ck_open(struct inode *inode, struct file *file)
379 {
380 return seq_open(file, &davinci_ck_op);
381 }
382
383 static const struct file_operations proc_davinci_ck_operations = {
384 .open = davinci_ck_open,
385 .read = seq_read,
386 .llseek = seq_lseek,
387 .release = seq_release,
388 };
389
390 static int __init davinci_ck_proc_init(void)
391 {
392 proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
393 return 0;
394
395 }
396 __initcall(davinci_ck_proc_init);
397 #endif /* CONFIG_DEBUG_PROC_FS */
398
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