1 /*
2 * linux/arch/arm/mach-at91/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/debugfs.h>
17 #include <linux/seq_file.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/io.h>
22
23 #include <mach/hardware.h>
24 #include <mach/at91_pio.h>
25 #include <mach/gpio.h>
26
27 #include <asm/gpio.h>
28
29 #include "generic.h"
30
31 struct at91_gpio_chip {
32 struct gpio_chip chip;
33 struct at91_gpio_chip *next; /* Bank sharing same clock */
34 struct at91_gpio_bank *bank; /* Bank definition */
35 void __iomem *regbase; /* Base of register bank */
36 };
37
38 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
39
40 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
41 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
42 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
43 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
44 unsigned offset, int val);
45 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
46 unsigned offset);
47 static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
48
49 #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \
50 { \
51 .chip = { \
52 .label = name, \
53 .request = at91_gpiolib_request, \
54 .direction_input = at91_gpiolib_direction_input, \
55 .direction_output = at91_gpiolib_direction_output, \
56 .get = at91_gpiolib_get, \
57 .set = at91_gpiolib_set, \
58 .dbg_show = at91_gpiolib_dbg_show, \
59 .base = base_gpio, \
60 .ngpio = nr_gpio, \
61 }, \
62 }
63
64 static struct at91_gpio_chip gpio_chip[] = {
65 AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
66 AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
67 AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
68 AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
69 AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
70 };
71
72 static int gpio_banks;
73
74 static inline void __iomem *pin_to_controller(unsigned pin)
75 {
76 pin -= PIN_BASE;
77 pin /= 32;
78 if (likely(pin < gpio_banks))
79 return gpio_chip[pin].regbase;
80
81 return NULL;
82 }
83
84 static inline unsigned pin_to_mask(unsigned pin)
85 {
86 pin -= PIN_BASE;
87 return 1 << (pin % 32);
88 }
89
90
91 /*--------------------------------------------------------------------------*/
92
93 /* Not all hardware capabilities are exposed through these calls; they
94 * only encapsulate the most common features and modes. (So if you
95 * want to change signals in groups, do it directly.)
96 *
97 * Bootloaders will usually handle some of the pin multiplexing setup.
98 * The intent is certainly that by the time Linux is fully booted, all
99 * pins should have been fully initialized. These setup calls should
100 * only be used by board setup routines, or possibly in driver probe().
101 *
102 * For bootloaders doing all that setup, these calls could be inlined
103 * as NOPs so Linux won't duplicate any setup code
104 */
105
106
107 /*
108 * mux the pin to the "GPIO" peripheral role.
109 */
110 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
111 {
112 void __iomem *pio = pin_to_controller(pin);
113 unsigned mask = pin_to_mask(pin);
114
115 if (!pio)
116 return -EINVAL;
117 __raw_writel(mask, pio + PIO_IDR);
118 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
119 __raw_writel(mask, pio + PIO_PER);
120 return 0;
121 }
122 EXPORT_SYMBOL(at91_set_GPIO_periph);
123
124
125 /*
126 * mux the pin to the "A" internal peripheral role.
127 */
128 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
129 {
130 void __iomem *pio = pin_to_controller(pin);
131 unsigned mask = pin_to_mask(pin);
132
133 if (!pio)
134 return -EINVAL;
135
136 __raw_writel(mask, pio + PIO_IDR);
137 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
138 __raw_writel(mask, pio + PIO_ASR);
139 __raw_writel(mask, pio + PIO_PDR);
140 return 0;
141 }
142 EXPORT_SYMBOL(at91_set_A_periph);
143
144
145 /*
146 * mux the pin to the "B" internal peripheral role.
147 */
148 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
149 {
150 void __iomem *pio = pin_to_controller(pin);
151 unsigned mask = pin_to_mask(pin);
152
153 if (!pio)
154 return -EINVAL;
155
156 __raw_writel(mask, pio + PIO_IDR);
157 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
158 __raw_writel(mask, pio + PIO_BSR);
159 __raw_writel(mask, pio + PIO_PDR);
160 return 0;
161 }
162 EXPORT_SYMBOL(at91_set_B_periph);
163
164
165 /*
166 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
167 * configure it for an input.
168 */
169 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
170 {
171 void __iomem *pio = pin_to_controller(pin);
172 unsigned mask = pin_to_mask(pin);
173
174 if (!pio)
175 return -EINVAL;
176
177 __raw_writel(mask, pio + PIO_IDR);
178 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
179 __raw_writel(mask, pio + PIO_ODR);
180 __raw_writel(mask, pio + PIO_PER);
181 return 0;
182 }
183 EXPORT_SYMBOL(at91_set_gpio_input);
184
185
186 /*
187 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
188 * and configure it for an output.
189 */
190 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
191 {
192 void __iomem *pio = pin_to_controller(pin);
193 unsigned mask = pin_to_mask(pin);
194
195 if (!pio)
196 return -EINVAL;
197
198 __raw_writel(mask, pio + PIO_IDR);
199 __raw_writel(mask, pio + PIO_PUDR);
200 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
201 __raw_writel(mask, pio + PIO_OER);
202 __raw_writel(mask, pio + PIO_PER);
203 return 0;
204 }
205 EXPORT_SYMBOL(at91_set_gpio_output);
206
207
208 /*
209 * enable/disable the glitch filter; mostly used with IRQ handling.
210 */
211 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
212 {
213 void __iomem *pio = pin_to_controller(pin);
214 unsigned mask = pin_to_mask(pin);
215
216 if (!pio)
217 return -EINVAL;
218 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
219 return 0;
220 }
221 EXPORT_SYMBOL(at91_set_deglitch);
222
223 /*
224 * enable/disable the multi-driver; This is only valid for output and
225 * allows the output pin to run as an open collector output.
226 */
227 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
228 {
229 void __iomem *pio = pin_to_controller(pin);
230 unsigned mask = pin_to_mask(pin);
231
232 if (!pio)
233 return -EINVAL;
234
235 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
236 return 0;
237 }
238 EXPORT_SYMBOL(at91_set_multi_drive);
239
240 /*
241 * assuming the pin is muxed as a gpio output, set its value.
242 */
243 int at91_set_gpio_value(unsigned pin, int value)
244 {
245 void __iomem *pio = pin_to_controller(pin);
246 unsigned mask = pin_to_mask(pin);
247
248 if (!pio)
249 return -EINVAL;
250 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
251 return 0;
252 }
253 EXPORT_SYMBOL(at91_set_gpio_value);
254
255
256 /*
257 * read the pin's value (works even if it's not muxed as a gpio).
258 */
259 int at91_get_gpio_value(unsigned pin)
260 {
261 void __iomem *pio = pin_to_controller(pin);
262 unsigned mask = pin_to_mask(pin);
263 u32 pdsr;
264
265 if (!pio)
266 return -EINVAL;
267 pdsr = __raw_readl(pio + PIO_PDSR);
268 return (pdsr & mask) != 0;
269 }
270 EXPORT_SYMBOL(at91_get_gpio_value);
271
272 /*--------------------------------------------------------------------------*/
273
274 #ifdef CONFIG_PM
275
276 static u32 wakeups[MAX_GPIO_BANKS];
277 static u32 backups[MAX_GPIO_BANKS];
278
279 static int gpio_irq_set_wake(unsigned pin, unsigned state)
280 {
281 unsigned mask = pin_to_mask(pin);
282 unsigned bank = (pin - PIN_BASE) / 32;
283
284 if (unlikely(bank >= MAX_GPIO_BANKS))
285 return -EINVAL;
286
287 if (state)
288 wakeups[bank] |= mask;
289 else
290 wakeups[bank] &= ~mask;
291
292 set_irq_wake(gpio_chip[bank].bank->id, state);
293
294 return 0;
295 }
296
297 void at91_gpio_suspend(void)
298 {
299 int i;
300
301 for (i = 0; i < gpio_banks; i++) {
302 void __iomem *pio = gpio_chip[i].regbase;
303
304 backups[i] = __raw_readl(pio + PIO_IMR);
305 __raw_writel(backups[i], pio + PIO_IDR);
306 __raw_writel(wakeups[i], pio + PIO_IER);
307
308 if (!wakeups[i])
309 clk_disable(gpio_chip[i].bank->clock);
310 else {
311 #ifdef CONFIG_PM_DEBUG
312 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
313 #endif
314 }
315 }
316 }
317
318 void at91_gpio_resume(void)
319 {
320 int i;
321
322 for (i = 0; i < gpio_banks; i++) {
323 void __iomem *pio = gpio_chip[i].regbase;
324
325 if (!wakeups[i])
326 clk_enable(gpio_chip[i].bank->clock);
327
328 __raw_writel(wakeups[i], pio + PIO_IDR);
329 __raw_writel(backups[i], pio + PIO_IER);
330 }
331 }
332
333 #else
334 #define gpio_irq_set_wake NULL
335 #endif
336
337
338 /* Several AIC controller irqs are dispatched through this GPIO handler.
339 * To use any AT91_PIN_* as an externally triggered IRQ, first call
340 * at91_set_gpio_input() then maybe enable its glitch filter.
341 * Then just request_irq() with the pin ID; it works like any ARM IRQ
342 * handler, though it always triggers on rising and falling edges.
343 *
344 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
345 * configuring them with at91_set_a_periph() or at91_set_b_periph().
346 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
347 */
348
349 static void gpio_irq_mask(unsigned pin)
350 {
351 void __iomem *pio = pin_to_controller(pin);
352 unsigned mask = pin_to_mask(pin);
353
354 if (pio)
355 __raw_writel(mask, pio + PIO_IDR);
356 }
357
358 static void gpio_irq_unmask(unsigned pin)
359 {
360 void __iomem *pio = pin_to_controller(pin);
361 unsigned mask = pin_to_mask(pin);
362
363 if (pio)
364 __raw_writel(mask, pio + PIO_IER);
365 }
366
367 static int gpio_irq_type(unsigned pin, unsigned type)
368 {
369 switch (type) {
370 case IRQ_TYPE_NONE:
371 case IRQ_TYPE_EDGE_BOTH:
372 return 0;
373 default:
374 return -EINVAL;
375 }
376 }
377
378 static struct irq_chip gpio_irqchip = {
379 .name = "GPIO",
380 .mask = gpio_irq_mask,
381 .unmask = gpio_irq_unmask,
382 .set_type = gpio_irq_type,
383 .set_wake = gpio_irq_set_wake,
384 };
385
386 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
387 {
388 unsigned pin;
389 struct irq_desc *gpio;
390 struct at91_gpio_chip *at91_gpio;
391 void __iomem *pio;
392 u32 isr;
393
394 at91_gpio = get_irq_chip_data(irq);
395 pio = at91_gpio->regbase;
396
397 /* temporarily mask (level sensitive) parent IRQ */
398 desc->chip->ack(irq);
399 for (;;) {
400 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
401 * When there none are pending, we're finished unless we need
402 * to process multiple banks (like ID_PIOCDE on sam9263).
403 */
404 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
405 if (!isr) {
406 if (!at91_gpio->next)
407 break;
408 at91_gpio = at91_gpio->next;
409 pio = at91_gpio->regbase;
410 continue;
411 }
412
413 pin = at91_gpio->chip.base;
414 gpio = &irq_desc[pin];
415
416 while (isr) {
417 if (isr & 1) {
418 if (unlikely(gpio->depth)) {
419 /*
420 * The core ARM interrupt handler lazily disables IRQs so
421 * another IRQ must be generated before it actually gets
422 * here to be disabled on the GPIO controller.
423 */
424 gpio_irq_mask(pin);
425 }
426 else
427 generic_handle_irq(pin);
428 }
429 pin++;
430 gpio++;
431 isr >>= 1;
432 }
433 }
434 desc->chip->unmask(irq);
435 /* now it may re-trigger */
436 }
437
438 /*--------------------------------------------------------------------------*/
439
440 #ifdef CONFIG_DEBUG_FS
441
442 static int at91_gpio_show(struct seq_file *s, void *unused)
443 {
444 int bank, j;
445
446 /* print heading */
447 seq_printf(s, "Pin\t");
448 for (bank = 0; bank < gpio_banks; bank++) {
449 seq_printf(s, "PIO%c\t", 'A' + bank);
450 };
451 seq_printf(s, "\n\n");
452
453 /* print pin status */
454 for (j = 0; j < 32; j++) {
455 seq_printf(s, "%i:\t", j);
456
457 for (bank = 0; bank < gpio_banks; bank++) {
458 unsigned pin = PIN_BASE + (32 * bank) + j;
459 void __iomem *pio = pin_to_controller(pin);
460 unsigned mask = pin_to_mask(pin);
461
462 if (__raw_readl(pio + PIO_PSR) & mask)
463 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "");
464 else
465 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
466
467 seq_printf(s, "\t");
468 }
469
470 seq_printf(s, "\n");
471 }
472
473 return 0;
474 }
475
476 static int at91_gpio_open(struct inode *inode, struct file *file)
477 {
478 return single_open(file, at91_gpio_show, NULL);
479 }
480
481 static const struct file_operations at91_gpio_operations = {
482 .open = at91_gpio_open,
483 .read = seq_read,
484 .llseek = seq_lseek,
485 .release = single_release,
486 };
487
488 static int __init at91_gpio_debugfs_init(void)
489 {
490 /* /sys/kernel/debug/at91_gpio */
491 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
492 return 0;
493 }
494 postcore_initcall(at91_gpio_debugfs_init);
495
496 #endif
497
498 /*--------------------------------------------------------------------------*/
499
500 /*
501 * This lock class tells lockdep that GPIO irqs are in a different
502 * category than their parents, so it won't report false recursion.
503 */
504 static struct lock_class_key gpio_lock_class;
505
506 /*
507 * Called from the processor-specific init to enable GPIO interrupt support.
508 */
509 void __init at91_gpio_irq_setup(void)
510 {
511 unsigned pioc, pin;
512 struct at91_gpio_chip *this, *prev;
513
514 for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
515 pioc++ < gpio_banks;
516 prev = this, this++) {
517 unsigned id = this->bank->id;
518 unsigned i;
519
520 __raw_writel(~0, this->regbase + PIO_IDR);
521
522 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
523 lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
524
525 /*
526 * Can use the "simple" and not "edge" handler since it's
527 * shorter, and the AIC handles interrupts sanely.
528 */
529 set_irq_chip(pin, &gpio_irqchip);
530 set_irq_handler(pin, handle_simple_irq);
531 set_irq_flags(pin, IRQF_VALID);
532 }
533
534 /* The toplevel handler handles one bank of GPIOs, except
535 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
536 * the list, so we only set up that handler.
537 */
538 if (prev && prev->next == this)
539 continue;
540
541 set_irq_chip_data(id, this);
542 set_irq_chained_handler(id, gpio_irq_handler);
543 }
544 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
545 }
546
547 /* gpiolib support */
548 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
549 unsigned offset)
550 {
551 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
552 void __iomem *pio = at91_gpio->regbase;
553 unsigned mask = 1 << offset;
554
555 __raw_writel(mask, pio + PIO_ODR);
556 return 0;
557 }
558
559 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
560 unsigned offset, int val)
561 {
562 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
563 void __iomem *pio = at91_gpio->regbase;
564 unsigned mask = 1 << offset;
565
566 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
567 __raw_writel(mask, pio + PIO_OER);
568 return 0;
569 }
570
571 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
572 {
573 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
574 void __iomem *pio = at91_gpio->regbase;
575 unsigned mask = 1 << offset;
576 u32 pdsr;
577
578 pdsr = __raw_readl(pio + PIO_PDSR);
579 return (pdsr & mask) != 0;
580 }
581
582 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
583 {
584 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
585 void __iomem *pio = at91_gpio->regbase;
586 unsigned mask = 1 << offset;
587
588 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
589 }
590
591 static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
592 {
593 unsigned pin = chip->base + offset;
594 void __iomem *pio = pin_to_controller(pin);
595 unsigned mask = pin_to_mask(pin);
596
597 /* Cannot request GPIOs that are in alternate function mode */
598 if (!(__raw_readl(pio + PIO_PSR) & mask))
599 return -EPERM;
600
601 return 0;
602 }
603
604 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
605 {
606 int i;
607
608 for (i = 0; i < chip->ngpio; i++) {
609 unsigned pin = chip->base + i;
610 void __iomem *pio = pin_to_controller(pin);
611 unsigned mask = pin_to_mask(pin);
612 const char *gpio_label;
613
614 gpio_label = gpiochip_is_requested(chip, i);
615 if (gpio_label) {
616 seq_printf(s, "[%s] GPIO%s%d: ",
617 gpio_label, chip->label, i);
618 if (__raw_readl(pio + PIO_PSR) & mask)
619 seq_printf(s, "[gpio] %s\n",
620 at91_get_gpio_value(pin) ?
621 "set" : "clear");
622 else
623 seq_printf(s, "[periph %s]\n",
624 __raw_readl(pio + PIO_ABSR) &
625 mask ? "B" : "A");
626 }
627 }
628 }
629
630 /*
631 * Called from the processor-specific init to enable GPIO pin support.
632 */
633 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
634 {
635 unsigned i;
636 struct at91_gpio_chip *at91_gpio, *last = NULL;
637
638 BUG_ON(nr_banks > MAX_GPIO_BANKS);
639
640 gpio_banks = nr_banks;
641
642 for (i = 0; i < nr_banks; i++) {
643 at91_gpio = &gpio_chip[i];
644
645 at91_gpio->bank = &data[i];
646 at91_gpio->chip.base = PIN_BASE + i * 32;
647 at91_gpio->regbase = at91_gpio->bank->offset +
648 (void __iomem *)AT91_VA_BASE_SYS;
649
650 /* enable PIO controller's clock */
651 clk_enable(at91_gpio->bank->clock);
652
653 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
654 if (last && last->bank->id == at91_gpio->bank->id)
655 last->next = at91_gpio;
656 last = at91_gpio;
657
658 gpiochip_add(&at91_gpio->chip);
659 }
660 }
661
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