1 /*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pm.h>
14
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <mach/cpu.h>
19 #include <mach/at91sam9rl.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
22 #include <mach/at91_shdwc.h>
23
24 #include "generic.h"
25 #include "clock.h"
26
27 static struct map_desc at91sam9rl_io_desc[] __initdata = {
28 {
29 .virtual = AT91_VA_BASE_SYS,
30 .pfn = __phys_to_pfn(AT91_BASE_SYS),
31 .length = SZ_16K,
32 .type = MT_DEVICE,
33 },
34 };
35
36 static struct map_desc at91sam9rl_sram_desc[] __initdata = {
37 {
38 .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
39 .type = MT_DEVICE,
40 }
41 };
42
43 /* --------------------------------------------------------------------
44 * Clocks
45 * -------------------------------------------------------------------- */
46
47 /*
48 * The peripheral clocks.
49 */
50 static struct clk pioA_clk = {
51 .name = "pioA_clk",
52 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
53 .type = CLK_TYPE_PERIPHERAL,
54 };
55 static struct clk pioB_clk = {
56 .name = "pioB_clk",
57 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
58 .type = CLK_TYPE_PERIPHERAL,
59 };
60 static struct clk pioC_clk = {
61 .name = "pioC_clk",
62 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
63 .type = CLK_TYPE_PERIPHERAL,
64 };
65 static struct clk pioD_clk = {
66 .name = "pioD_clk",
67 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
68 .type = CLK_TYPE_PERIPHERAL,
69 };
70 static struct clk usart0_clk = {
71 .name = "usart0_clk",
72 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
73 .type = CLK_TYPE_PERIPHERAL,
74 };
75 static struct clk usart1_clk = {
76 .name = "usart1_clk",
77 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
78 .type = CLK_TYPE_PERIPHERAL,
79 };
80 static struct clk usart2_clk = {
81 .name = "usart2_clk",
82 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
83 .type = CLK_TYPE_PERIPHERAL,
84 };
85 static struct clk usart3_clk = {
86 .name = "usart3_clk",
87 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
88 .type = CLK_TYPE_PERIPHERAL,
89 };
90 static struct clk mmc_clk = {
91 .name = "mci_clk",
92 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
93 .type = CLK_TYPE_PERIPHERAL,
94 };
95 static struct clk twi0_clk = {
96 .name = "twi0_clk",
97 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
98 .type = CLK_TYPE_PERIPHERAL,
99 };
100 static struct clk twi1_clk = {
101 .name = "twi1_clk",
102 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
103 .type = CLK_TYPE_PERIPHERAL,
104 };
105 static struct clk spi_clk = {
106 .name = "spi_clk",
107 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
108 .type = CLK_TYPE_PERIPHERAL,
109 };
110 static struct clk ssc0_clk = {
111 .name = "ssc0_clk",
112 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
113 .type = CLK_TYPE_PERIPHERAL,
114 };
115 static struct clk ssc1_clk = {
116 .name = "ssc1_clk",
117 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
118 .type = CLK_TYPE_PERIPHERAL,
119 };
120 static struct clk tc0_clk = {
121 .name = "tc0_clk",
122 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
123 .type = CLK_TYPE_PERIPHERAL,
124 };
125 static struct clk tc1_clk = {
126 .name = "tc1_clk",
127 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
128 .type = CLK_TYPE_PERIPHERAL,
129 };
130 static struct clk tc2_clk = {
131 .name = "tc2_clk",
132 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
133 .type = CLK_TYPE_PERIPHERAL,
134 };
135 static struct clk pwm_clk = {
136 .name = "pwm_clk",
137 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
138 .type = CLK_TYPE_PERIPHERAL,
139 };
140 static struct clk tsc_clk = {
141 .name = "tsc_clk",
142 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
143 .type = CLK_TYPE_PERIPHERAL,
144 };
145 static struct clk dma_clk = {
146 .name = "dma_clk",
147 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
148 .type = CLK_TYPE_PERIPHERAL,
149 };
150 static struct clk udphs_clk = {
151 .name = "udphs_clk",
152 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
153 .type = CLK_TYPE_PERIPHERAL,
154 };
155 static struct clk lcdc_clk = {
156 .name = "lcdc_clk",
157 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
158 .type = CLK_TYPE_PERIPHERAL,
159 };
160 static struct clk ac97_clk = {
161 .name = "ac97_clk",
162 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
163 .type = CLK_TYPE_PERIPHERAL,
164 };
165
166 static struct clk *periph_clocks[] __initdata = {
167 &pioA_clk,
168 &pioB_clk,
169 &pioC_clk,
170 &pioD_clk,
171 &usart0_clk,
172 &usart1_clk,
173 &usart2_clk,
174 &usart3_clk,
175 &mmc_clk,
176 &twi0_clk,
177 &twi1_clk,
178 &spi_clk,
179 &ssc0_clk,
180 &ssc1_clk,
181 &tc0_clk,
182 &tc1_clk,
183 &tc2_clk,
184 &pwm_clk,
185 &tsc_clk,
186 &dma_clk,
187 &udphs_clk,
188 &lcdc_clk,
189 &ac97_clk,
190 // irq0
191 };
192
193 /*
194 * The two programmable clocks.
195 * You must configure pin multiplexing to bring these signals out.
196 */
197 static struct clk pck0 = {
198 .name = "pck0",
199 .pmc_mask = AT91_PMC_PCK0,
200 .type = CLK_TYPE_PROGRAMMABLE,
201 .id = 0,
202 };
203 static struct clk pck1 = {
204 .name = "pck1",
205 .pmc_mask = AT91_PMC_PCK1,
206 .type = CLK_TYPE_PROGRAMMABLE,
207 .id = 1,
208 };
209
210 static void __init at91sam9rl_register_clocks(void)
211 {
212 int i;
213
214 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
215 clk_register(periph_clocks[i]);
216
217 clk_register(&pck0);
218 clk_register(&pck1);
219 }
220
221 /* --------------------------------------------------------------------
222 * GPIO
223 * -------------------------------------------------------------------- */
224
225 static struct at91_gpio_bank at91sam9rl_gpio[] = {
226 {
227 .id = AT91SAM9RL_ID_PIOA,
228 .offset = AT91_PIOA,
229 .clock = &pioA_clk,
230 }, {
231 .id = AT91SAM9RL_ID_PIOB,
232 .offset = AT91_PIOB,
233 .clock = &pioB_clk,
234 }, {
235 .id = AT91SAM9RL_ID_PIOC,
236 .offset = AT91_PIOC,
237 .clock = &pioC_clk,
238 }, {
239 .id = AT91SAM9RL_ID_PIOD,
240 .offset = AT91_PIOD,
241 .clock = &pioD_clk,
242 }
243 };
244
245 static void at91sam9rl_reset(void)
246 {
247 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
248 }
249
250 static void at91sam9rl_poweroff(void)
251 {
252 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
253 }
254
255
256 /* --------------------------------------------------------------------
257 * AT91SAM9RL processor initialization
258 * -------------------------------------------------------------------- */
259
260 void __init at91sam9rl_initialize(unsigned long main_clock)
261 {
262 unsigned long cidr, sram_size;
263
264 /* Map peripherals */
265 iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
266
267 cidr = at91_sys_read(AT91_DBGU_CIDR);
268
269 switch (cidr & AT91_CIDR_SRAMSIZ) {
270 case AT91_CIDR_SRAMSIZ_32K:
271 sram_size = 2 * SZ_16K;
272 break;
273 case AT91_CIDR_SRAMSIZ_16K:
274 default:
275 sram_size = SZ_16K;
276 }
277
278 at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
279 at91sam9rl_sram_desc->length = sram_size;
280
281 /* Map SRAM */
282 iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
283
284 at91_arch_reset = at91sam9rl_reset;
285 pm_power_off = at91sam9rl_poweroff;
286 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
287
288 /* Init clock subsystem */
289 at91_clock_init(main_clock);
290
291 /* Register the processor-specific clocks */
292 at91sam9rl_register_clocks();
293
294 /* Register GPIO subsystem */
295 at91_gpio_init(at91sam9rl_gpio, 4);
296 }
297
298 /* --------------------------------------------------------------------
299 * Interrupt initialization
300 * -------------------------------------------------------------------- */
301
302 /*
303 * The default interrupt priority levels (0 = lowest, 7 = highest).
304 */
305 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
306 7, /* Advanced Interrupt Controller */
307 7, /* System Peripherals */
308 1, /* Parallel IO Controller A */
309 1, /* Parallel IO Controller B */
310 1, /* Parallel IO Controller C */
311 1, /* Parallel IO Controller D */
312 5, /* USART 0 */
313 5, /* USART 1 */
314 5, /* USART 2 */
315 5, /* USART 3 */
316 0, /* Multimedia Card Interface */
317 6, /* Two-Wire Interface 0 */
318 6, /* Two-Wire Interface 1 */
319 5, /* Serial Peripheral Interface */
320 4, /* Serial Synchronous Controller 0 */
321 4, /* Serial Synchronous Controller 1 */
322 0, /* Timer Counter 0 */
323 0, /* Timer Counter 1 */
324 0, /* Timer Counter 2 */
325 0,
326 0, /* Touch Screen Controller */
327 0, /* DMA Controller */
328 2, /* USB Device High speed port */
329 2, /* LCD Controller */
330 6, /* AC97 Controller */
331 0,
332 0,
333 0,
334 0,
335 0,
336 0,
337 0, /* Advanced Interrupt Controller */
338 };
339
340 void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
341 {
342 if (!priority)
343 priority = at91sam9rl_default_irq_priority;
344
345 /* Initialize the AIC interrupt controller */
346 at91_aic_init(priority);
347
348 /* Enable GPIO interrupts */
349 at91_gpio_irq_setup();
350 }
351
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