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1 /* 1 /*
2 * ALSA driver for RME Digi96, Digi96/8 and 2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces 3 * interfaces
4 * 4 *
5 * Copyright (c) 2000, 2001 Anders Torger 5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 * 6 *
7 * Thanks to Henk Hesselink <henk@anda.nl 7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code. 8 * code.
9 * 9 *
10 * This program is free software; you can re 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Pub 11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either vers 12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version. 13 * (at your option) any later version.
14 * 14 *
15 * This program is distributed in the hope t 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even th 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICUL 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more detai 18 * GNU General Public License for more details.
19 * 19 *
20 * You should have received a copy of the GN 20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * 23 *
24 */ 24 */
25 25
>> 26 #include <sound/driver.h>
26 #include <linux/delay.h> 27 #include <linux/delay.h>
27 #include <linux/init.h> 28 #include <linux/init.h>
28 #include <linux/interrupt.h> 29 #include <linux/interrupt.h>
29 #include <linux/pci.h> 30 #include <linux/pci.h>
30 #include <linux/slab.h> 31 #include <linux/slab.h>
31 #include <linux/moduleparam.h> 32 #include <linux/moduleparam.h>
32 33
33 #include <sound/core.h> 34 #include <sound/core.h>
34 #include <sound/info.h> 35 #include <sound/info.h>
35 #include <sound/control.h> 36 #include <sound/control.h>
36 #include <sound/pcm.h> 37 #include <sound/pcm.h>
37 #include <sound/pcm_params.h> 38 #include <sound/pcm_params.h>
38 #include <sound/asoundef.h> 39 #include <sound/asoundef.h>
39 #include <sound/initval.h> 40 #include <sound/initval.h>
40 41
41 #include <asm/io.h> 42 #include <asm/io.h>
42 43
43 /* note, two last pcis should be equal, it is 44 /* note, two last pcis should be equal, it is not a bug */
44 45
45 MODULE_AUTHOR("Anders Torger <torger@ludd.luth 46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
46 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi 47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
47 "Digi96/8 PAD"); 48 "Digi96/8 PAD");
48 MODULE_LICENSE("GPL"); 49 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{RME,Digi96}," 50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
50 "{RME,Digi96/8}," 51 "{RME,Digi96/8},"
51 "{RME,Digi96/8 PRO}," 52 "{RME,Digi96/8 PRO},"
52 "{RME,Digi96/8 PST}," 53 "{RME,Digi96/8 PST},"
53 "{RME,Digi96/8 PAD}}"); 54 "{RME,Digi96/8 PAD}}");
54 55
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_ 56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_S 57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT 58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
58 59
59 module_param_array(index, int, NULL, 0444); 60 module_param_array(index, int, NULL, 0444);
60 MODULE_PARM_DESC(index, "Index value for RME D 61 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
61 module_param_array(id, charp, NULL, 0444); 62 module_param_array(id, charp, NULL, 0444);
62 MODULE_PARM_DESC(id, "ID string for RME Digi96 63 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
63 module_param_array(enable, bool, NULL, 0444); 64 module_param_array(enable, bool, NULL, 0444);
64 MODULE_PARM_DESC(enable, "Enable RME Digi96 so 65 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
65 66
66 /* 67 /*
67 * Defines for RME Digi96 series, from interna 68 * Defines for RME Digi96 series, from internal RME reference documents
68 * dated 12.01.00 69 * dated 12.01.00
69 */ 70 */
70 71
71 #define RME96_SPDIF_NCHANNELS 2 72 #define RME96_SPDIF_NCHANNELS 2
72 73
73 /* Playback and capture buffer size */ 74 /* Playback and capture buffer size */
74 #define RME96_BUFFER_SIZE 0x10000 75 #define RME96_BUFFER_SIZE 0x10000
75 76
76 /* IO area size */ 77 /* IO area size */
77 #define RME96_IO_SIZE 0x60000 78 #define RME96_IO_SIZE 0x60000
78 79
79 /* IO area offsets */ 80 /* IO area offsets */
80 #define RME96_IO_PLAY_BUFFER 0x0 81 #define RME96_IO_PLAY_BUFFER 0x0
81 #define RME96_IO_REC_BUFFER 0x10000 82 #define RME96_IO_REC_BUFFER 0x10000
82 #define RME96_IO_CONTROL_REGISTER 0x20000 83 #define RME96_IO_CONTROL_REGISTER 0x20000
83 #define RME96_IO_ADDITIONAL_REG 0x20004 84 #define RME96_IO_ADDITIONAL_REG 0x20004
84 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 85 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
85 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 86 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
86 #define RME96_IO_SET_PLAY_POS 0x40000 87 #define RME96_IO_SET_PLAY_POS 0x40000
87 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 88 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
88 #define RME96_IO_SET_REC_POS 0x50000 89 #define RME96_IO_SET_REC_POS 0x50000
89 #define RME96_IO_RESET_REC_POS 0x5FFFC 90 #define RME96_IO_RESET_REC_POS 0x5FFFC
90 #define RME96_IO_GET_PLAY_POS 0x20000 91 #define RME96_IO_GET_PLAY_POS 0x20000
91 #define RME96_IO_GET_REC_POS 0x30000 92 #define RME96_IO_GET_REC_POS 0x30000
92 93
93 /* Write control register bits */ 94 /* Write control register bits */
94 #define RME96_WCR_START (1 << 0) 95 #define RME96_WCR_START (1 << 0)
95 #define RME96_WCR_START_2 (1 << 1) 96 #define RME96_WCR_START_2 (1 << 1)
96 #define RME96_WCR_GAIN_0 (1 << 2) 97 #define RME96_WCR_GAIN_0 (1 << 2)
97 #define RME96_WCR_GAIN_1 (1 << 3) 98 #define RME96_WCR_GAIN_1 (1 << 3)
98 #define RME96_WCR_MODE24 (1 << 4) 99 #define RME96_WCR_MODE24 (1 << 4)
99 #define RME96_WCR_MODE24_2 (1 << 5) 100 #define RME96_WCR_MODE24_2 (1 << 5)
100 #define RME96_WCR_BM (1 << 6) 101 #define RME96_WCR_BM (1 << 6)
101 #define RME96_WCR_BM_2 (1 << 7) 102 #define RME96_WCR_BM_2 (1 << 7)
102 #define RME96_WCR_ADAT (1 << 8) 103 #define RME96_WCR_ADAT (1 << 8)
103 #define RME96_WCR_FREQ_0 (1 << 9) 104 #define RME96_WCR_FREQ_0 (1 << 9)
104 #define RME96_WCR_FREQ_1 (1 << 10) 105 #define RME96_WCR_FREQ_1 (1 << 10)
105 #define RME96_WCR_DS (1 << 11) 106 #define RME96_WCR_DS (1 << 11)
106 #define RME96_WCR_PRO (1 << 12) 107 #define RME96_WCR_PRO (1 << 12)
107 #define RME96_WCR_EMP (1 << 13) 108 #define RME96_WCR_EMP (1 << 13)
108 #define RME96_WCR_SEL (1 << 14) 109 #define RME96_WCR_SEL (1 << 14)
109 #define RME96_WCR_MASTER (1 << 15) 110 #define RME96_WCR_MASTER (1 << 15)
110 #define RME96_WCR_PD (1 << 16) 111 #define RME96_WCR_PD (1 << 16)
111 #define RME96_WCR_INP_0 (1 << 17) 112 #define RME96_WCR_INP_0 (1 << 17)
112 #define RME96_WCR_INP_1 (1 << 18) 113 #define RME96_WCR_INP_1 (1 << 18)
113 #define RME96_WCR_THRU_0 (1 << 19) 114 #define RME96_WCR_THRU_0 (1 << 19)
114 #define RME96_WCR_THRU_1 (1 << 20) 115 #define RME96_WCR_THRU_1 (1 << 20)
115 #define RME96_WCR_THRU_2 (1 << 21) 116 #define RME96_WCR_THRU_2 (1 << 21)
116 #define RME96_WCR_THRU_3 (1 << 22) 117 #define RME96_WCR_THRU_3 (1 << 22)
117 #define RME96_WCR_THRU_4 (1 << 23) 118 #define RME96_WCR_THRU_4 (1 << 23)
118 #define RME96_WCR_THRU_5 (1 << 24) 119 #define RME96_WCR_THRU_5 (1 << 24)
119 #define RME96_WCR_THRU_6 (1 << 25) 120 #define RME96_WCR_THRU_6 (1 << 25)
120 #define RME96_WCR_THRU_7 (1 << 26) 121 #define RME96_WCR_THRU_7 (1 << 26)
121 #define RME96_WCR_DOLBY (1 << 27) 122 #define RME96_WCR_DOLBY (1 << 27)
122 #define RME96_WCR_MONITOR_0 (1 << 28) 123 #define RME96_WCR_MONITOR_0 (1 << 28)
123 #define RME96_WCR_MONITOR_1 (1 << 29) 124 #define RME96_WCR_MONITOR_1 (1 << 29)
124 #define RME96_WCR_ISEL (1 << 30) 125 #define RME96_WCR_ISEL (1 << 30)
125 #define RME96_WCR_IDIS (1 << 31) 126 #define RME96_WCR_IDIS (1 << 31)
126 127
127 #define RME96_WCR_BITPOS_GAIN_0 2 128 #define RME96_WCR_BITPOS_GAIN_0 2
128 #define RME96_WCR_BITPOS_GAIN_1 3 129 #define RME96_WCR_BITPOS_GAIN_1 3
129 #define RME96_WCR_BITPOS_FREQ_0 9 130 #define RME96_WCR_BITPOS_FREQ_0 9
130 #define RME96_WCR_BITPOS_FREQ_1 10 131 #define RME96_WCR_BITPOS_FREQ_1 10
131 #define RME96_WCR_BITPOS_INP_0 17 132 #define RME96_WCR_BITPOS_INP_0 17
132 #define RME96_WCR_BITPOS_INP_1 18 133 #define RME96_WCR_BITPOS_INP_1 18
133 #define RME96_WCR_BITPOS_MONITOR_0 28 134 #define RME96_WCR_BITPOS_MONITOR_0 28
134 #define RME96_WCR_BITPOS_MONITOR_1 29 135 #define RME96_WCR_BITPOS_MONITOR_1 29
135 136
136 /* Read control register bits */ 137 /* Read control register bits */
137 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 138 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
138 #define RME96_RCR_IRQ_2 (1 << 16) 139 #define RME96_RCR_IRQ_2 (1 << 16)
139 #define RME96_RCR_T_OUT (1 << 17) 140 #define RME96_RCR_T_OUT (1 << 17)
140 #define RME96_RCR_DEV_ID_0 (1 << 21) 141 #define RME96_RCR_DEV_ID_0 (1 << 21)
141 #define RME96_RCR_DEV_ID_1 (1 << 22) 142 #define RME96_RCR_DEV_ID_1 (1 << 22)
142 #define RME96_RCR_LOCK (1 << 23) 143 #define RME96_RCR_LOCK (1 << 23)
143 #define RME96_RCR_VERF (1 << 26) 144 #define RME96_RCR_VERF (1 << 26)
144 #define RME96_RCR_F0 (1 << 27) 145 #define RME96_RCR_F0 (1 << 27)
145 #define RME96_RCR_F1 (1 << 28) 146 #define RME96_RCR_F1 (1 << 28)
146 #define RME96_RCR_F2 (1 << 29) 147 #define RME96_RCR_F2 (1 << 29)
147 #define RME96_RCR_AUTOSYNC (1 << 30) 148 #define RME96_RCR_AUTOSYNC (1 << 30)
148 #define RME96_RCR_IRQ (1 << 31) 149 #define RME96_RCR_IRQ (1 << 31)
149 150
150 #define RME96_RCR_BITPOS_F0 27 151 #define RME96_RCR_BITPOS_F0 27
151 #define RME96_RCR_BITPOS_F1 28 152 #define RME96_RCR_BITPOS_F1 28
152 #define RME96_RCR_BITPOS_F2 29 153 #define RME96_RCR_BITPOS_F2 29
153 154
154 /* Additonal register bits */ 155 /* Additonal register bits */
155 #define RME96_AR_WSEL (1 << 0) 156 #define RME96_AR_WSEL (1 << 0)
156 #define RME96_AR_ANALOG (1 << 1) 157 #define RME96_AR_ANALOG (1 << 1)
157 #define RME96_AR_FREQPAD_0 (1 << 2) 158 #define RME96_AR_FREQPAD_0 (1 << 2)
158 #define RME96_AR_FREQPAD_1 (1 << 3) 159 #define RME96_AR_FREQPAD_1 (1 << 3)
159 #define RME96_AR_FREQPAD_2 (1 << 4) 160 #define RME96_AR_FREQPAD_2 (1 << 4)
160 #define RME96_AR_PD2 (1 << 5) 161 #define RME96_AR_PD2 (1 << 5)
161 #define RME96_AR_DAC_EN (1 << 6) 162 #define RME96_AR_DAC_EN (1 << 6)
162 #define RME96_AR_CLATCH (1 << 7) 163 #define RME96_AR_CLATCH (1 << 7)
163 #define RME96_AR_CCLK (1 << 8) 164 #define RME96_AR_CCLK (1 << 8)
164 #define RME96_AR_CDATA (1 << 9) 165 #define RME96_AR_CDATA (1 << 9)
165 166
166 #define RME96_AR_BITPOS_F0 2 167 #define RME96_AR_BITPOS_F0 2
167 #define RME96_AR_BITPOS_F1 3 168 #define RME96_AR_BITPOS_F1 3
168 #define RME96_AR_BITPOS_F2 4 169 #define RME96_AR_BITPOS_F2 4
169 170
170 /* Monitor tracks */ 171 /* Monitor tracks */
171 #define RME96_MONITOR_TRACKS_1_2 0 172 #define RME96_MONITOR_TRACKS_1_2 0
172 #define RME96_MONITOR_TRACKS_3_4 1 173 #define RME96_MONITOR_TRACKS_3_4 1
173 #define RME96_MONITOR_TRACKS_5_6 2 174 #define RME96_MONITOR_TRACKS_5_6 2
174 #define RME96_MONITOR_TRACKS_7_8 3 175 #define RME96_MONITOR_TRACKS_7_8 3
175 176
176 /* Attenuation */ 177 /* Attenuation */
177 #define RME96_ATTENUATION_0 0 178 #define RME96_ATTENUATION_0 0
178 #define RME96_ATTENUATION_6 1 179 #define RME96_ATTENUATION_6 1
179 #define RME96_ATTENUATION_12 2 180 #define RME96_ATTENUATION_12 2
180 #define RME96_ATTENUATION_18 3 181 #define RME96_ATTENUATION_18 3
181 182
182 /* Input types */ 183 /* Input types */
183 #define RME96_INPUT_OPTICAL 0 184 #define RME96_INPUT_OPTICAL 0
184 #define RME96_INPUT_COAXIAL 1 185 #define RME96_INPUT_COAXIAL 1
185 #define RME96_INPUT_INTERNAL 2 186 #define RME96_INPUT_INTERNAL 2
186 #define RME96_INPUT_XLR 3 187 #define RME96_INPUT_XLR 3
187 #define RME96_INPUT_ANALOG 4 188 #define RME96_INPUT_ANALOG 4
188 189
189 /* Clock modes */ 190 /* Clock modes */
190 #define RME96_CLOCKMODE_SLAVE 0 191 #define RME96_CLOCKMODE_SLAVE 0
191 #define RME96_CLOCKMODE_MASTER 1 192 #define RME96_CLOCKMODE_MASTER 1
192 #define RME96_CLOCKMODE_WORDCLOCK 2 193 #define RME96_CLOCKMODE_WORDCLOCK 2
193 194
194 /* Block sizes in bytes */ 195 /* Block sizes in bytes */
195 #define RME96_SMALL_BLOCK_SIZE 2048 196 #define RME96_SMALL_BLOCK_SIZE 2048
196 #define RME96_LARGE_BLOCK_SIZE 8192 197 #define RME96_LARGE_BLOCK_SIZE 8192
197 198
198 /* Volume control */ 199 /* Volume control */
199 #define RME96_AD1852_VOL_BITS 14 200 #define RME96_AD1852_VOL_BITS 14
200 #define RME96_AD1855_VOL_BITS 10 201 #define RME96_AD1855_VOL_BITS 10
201 202
>> 203 /*
>> 204 * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
>> 205 * therefore #ifndef is used.
>> 206 */
>> 207 #ifndef PCI_VENDOR_ID_XILINX
>> 208 #define PCI_VENDOR_ID_XILINX 0x10ee
>> 209 #endif
>> 210 #ifndef PCI_DEVICE_ID_DIGI96
>> 211 #define PCI_DEVICE_ID_DIGI96 0x3fc0
>> 212 #endif
>> 213 #ifndef PCI_DEVICE_ID_DIGI96_8
>> 214 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1
>> 215 #endif
>> 216 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO
>> 217 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
>> 218 #endif
>> 219 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
>> 220 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
>> 221 #endif
202 222
203 struct rme96 { !! 223 typedef struct snd_rme96 {
204 spinlock_t lock; 224 spinlock_t lock;
205 int irq; 225 int irq;
206 unsigned long port; 226 unsigned long port;
207 void __iomem *iobase; 227 void __iomem *iobase;
208 228
209 u32 wcreg; /* cached write control 229 u32 wcreg; /* cached write control register value */
210 u32 wcreg_spdif; /* S/P 230 u32 wcreg_spdif; /* S/PDIF setup */
211 u32 wcreg_spdif_stream; /* S/P 231 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
212 u32 rcreg; /* cached read control r 232 u32 rcreg; /* cached read control register value */
213 u32 areg; /* cached additional reg 233 u32 areg; /* cached additional register value */
214 u16 vol[2]; /* cached volume of analog 234 u16 vol[2]; /* cached volume of analog output */
215 235
216 u8 rev; /* card revision number */ 236 u8 rev; /* card revision number */
217 237
218 struct snd_pcm_substream *playback_sub !! 238 snd_pcm_substream_t *playback_substream;
219 struct snd_pcm_substream *capture_subs !! 239 snd_pcm_substream_t *capture_substream;
220 240
221 int playback_frlog; /* log2 of framesi 241 int playback_frlog; /* log2 of framesize */
222 int capture_frlog; 242 int capture_frlog;
223 243
224 size_t playback_periodsize; /* in byte 244 size_t playback_periodsize; /* in bytes, zero if not used */
225 size_t capture_periodsize; /* in bytes 245 size_t capture_periodsize; /* in bytes, zero if not used */
226 246
227 struct snd_card *card; !! 247 snd_card_t *card;
228 struct snd_pcm *spdif_pcm; !! 248 snd_pcm_t *spdif_pcm;
229 struct snd_pcm *adat_pcm; !! 249 snd_pcm_t *adat_pcm;
230 struct pci_dev *pci; 250 struct pci_dev *pci;
231 struct snd_kcontrol *spdif_ctl; !! 251 snd_kcontrol_t *spdif_ctl;
232 }; !! 252 } rme96_t;
233 253
234 static struct pci_device_id snd_rme96_ids[] = 254 static struct pci_device_id snd_rme96_ids[] = {
235 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RM !! 255 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
236 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RM !! 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
237 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RM !! 257 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
238 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RM !! 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
>> 259 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
>> 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
>> 261 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
>> 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
239 { 0, } 263 { 0, }
240 }; 264 };
241 265
242 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 266 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
243 267
244 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg 268 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
245 #define RME96_ISRECORDING(rme96) ((rme96)->wcr 269 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
246 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->p !! 270 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
247 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)-> !! 271 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
248 (rme96)-> !! 272 (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
249 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_AN 273 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
250 #define RME96_DAC_IS_1855(rme96) (((rme96)->pc !! 274 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
251 ((rme96)->pc !! 275 ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
252 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME9 276 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
253 277
254 static int 278 static int
255 snd_rme96_playback_prepare(struct snd_pcm_subs !! 279 snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
256 280
257 static int 281 static int
258 snd_rme96_capture_prepare(struct snd_pcm_subst !! 282 snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
259 283
260 static int 284 static int
261 snd_rme96_playback_trigger(struct snd_pcm_subs !! 285 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
262 int cmd); 286 int cmd);
263 287
264 static int 288 static int
265 snd_rme96_capture_trigger(struct snd_pcm_subst !! 289 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
266 int cmd); 290 int cmd);
267 291
268 static snd_pcm_uframes_t 292 static snd_pcm_uframes_t
269 snd_rme96_playback_pointer(struct snd_pcm_subs !! 293 snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
270 294
271 static snd_pcm_uframes_t 295 static snd_pcm_uframes_t
272 snd_rme96_capture_pointer(struct snd_pcm_subst !! 296 snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
273 297
274 static void __devinit 298 static void __devinit
275 snd_rme96_proc_init(struct rme96 *rme96); !! 299 snd_rme96_proc_init(rme96_t *rme96);
276 300
277 static int 301 static int
278 snd_rme96_create_switches(struct snd_card *car !! 302 snd_rme96_create_switches(snd_card_t *card,
279 struct rme96 *rme96) !! 303 rme96_t *rme96);
280 304
281 static int 305 static int
282 snd_rme96_getinputtype(struct rme96 *rme96); !! 306 snd_rme96_getinputtype(rme96_t *rme96);
283 307
284 static inline unsigned int 308 static inline unsigned int
285 snd_rme96_playback_ptr(struct rme96 *rme96) !! 309 snd_rme96_playback_ptr(rme96_t *rme96)
286 { 310 {
287 return (readl(rme96->iobase + RME96_IO 311 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
288 & RME96_RCR_AUDIO_ADDR_MASK) > 312 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
289 } 313 }
290 314
291 static inline unsigned int 315 static inline unsigned int
292 snd_rme96_capture_ptr(struct rme96 *rme96) !! 316 snd_rme96_capture_ptr(rme96_t *rme96)
293 { 317 {
294 return (readl(rme96->iobase + RME96_IO 318 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
295 & RME96_RCR_AUDIO_ADDR_MASK) > 319 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
296 } 320 }
297 321
298 static int 322 static int
299 snd_rme96_playback_silence(struct snd_pcm_subs !! 323 snd_rme96_ratecode(int rate)
>> 324 {
>> 325 switch (rate) {
>> 326 case 32000: return SNDRV_PCM_RATE_32000;
>> 327 case 44100: return SNDRV_PCM_RATE_44100;
>> 328 case 48000: return SNDRV_PCM_RATE_48000;
>> 329 case 64000: return SNDRV_PCM_RATE_64000;
>> 330 case 88200: return SNDRV_PCM_RATE_88200;
>> 331 case 96000: return SNDRV_PCM_RATE_96000;
>> 332 }
>> 333 return 0;
>> 334 }
>> 335
>> 336 static int
>> 337 snd_rme96_playback_silence(snd_pcm_substream_t *substream,
300 int channel, /* not 338 int channel, /* not used (interleaved data) */
301 snd_pcm_uframes_t p 339 snd_pcm_uframes_t pos,
302 snd_pcm_uframes_t c 340 snd_pcm_uframes_t count)
303 { 341 {
304 struct rme96 *rme96 = snd_pcm_substrea !! 342 rme96_t *rme96 = snd_pcm_substream_chip(substream);
305 count <<= rme96->playback_frlog; 343 count <<= rme96->playback_frlog;
306 pos <<= rme96->playback_frlog; 344 pos <<= rme96->playback_frlog;
307 memset_io(rme96->iobase + RME96_IO_PLA 345 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
308 0, count); 346 0, count);
309 return 0; 347 return 0;
310 } 348 }
311 349
312 static int 350 static int
313 snd_rme96_playback_copy(struct snd_pcm_substre !! 351 snd_rme96_playback_copy(snd_pcm_substream_t *substream,
314 int channel, /* not us 352 int channel, /* not used (interleaved data) */
315 snd_pcm_uframes_t pos, 353 snd_pcm_uframes_t pos,
316 void __user *src, 354 void __user *src,
317 snd_pcm_uframes_t coun 355 snd_pcm_uframes_t count)
318 { 356 {
319 struct rme96 *rme96 = snd_pcm_substrea !! 357 rme96_t *rme96 = snd_pcm_substream_chip(substream);
320 count <<= rme96->playback_frlog; 358 count <<= rme96->playback_frlog;
321 pos <<= rme96->playback_frlog; 359 pos <<= rme96->playback_frlog;
322 copy_from_user_toio(rme96->iobase + RM 360 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
323 count); 361 count);
324 return 0; 362 return 0;
325 } 363 }
326 364
327 static int 365 static int
328 snd_rme96_capture_copy(struct snd_pcm_substrea !! 366 snd_rme96_capture_copy(snd_pcm_substream_t *substream,
329 int channel, /* not use 367 int channel, /* not used (interleaved data) */
330 snd_pcm_uframes_t pos, 368 snd_pcm_uframes_t pos,
331 void __user *dst, 369 void __user *dst,
332 snd_pcm_uframes_t count 370 snd_pcm_uframes_t count)
333 { 371 {
334 struct rme96 *rme96 = snd_pcm_substrea !! 372 rme96_t *rme96 = snd_pcm_substream_chip(substream);
335 count <<= rme96->capture_frlog; 373 count <<= rme96->capture_frlog;
336 pos <<= rme96->capture_frlog; 374 pos <<= rme96->capture_frlog;
337 copy_to_user_fromio(dst, rme96->iobase 375 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
338 count); 376 count);
339 return 0; 377 return 0;
340 } 378 }
341 379
342 /* 380 /*
343 * Digital output capabilities (S/PDIF) !! 381 * Digital output capabilites (S/PDIF)
344 */ 382 */
345 static struct snd_pcm_hardware snd_rme96_playb !! 383 static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
346 { 384 {
347 .info = (SNDRV_PCM_INFO_M 385 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
348 SNDRV_PCM_INFO_M 386 SNDRV_PCM_INFO_MMAP_VALID |
349 SNDRV_PCM_INFO_I 387 SNDRV_PCM_INFO_INTERLEAVED |
350 SNDRV_PCM_INFO_P 388 SNDRV_PCM_INFO_PAUSE),
351 .formats = (SNDRV_PCM_FMTBIT 389 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
352 SNDRV_PCM_FMTBIT 390 SNDRV_PCM_FMTBIT_S32_LE),
353 .rates = (SNDRV_PCM_RATE_3 391 .rates = (SNDRV_PCM_RATE_32000 |
354 SNDRV_PCM_RATE_4 392 SNDRV_PCM_RATE_44100 |
355 SNDRV_PCM_RATE_4 393 SNDRV_PCM_RATE_48000 |
356 SNDRV_PCM_RATE_6 394 SNDRV_PCM_RATE_64000 |
357 SNDRV_PCM_RATE_8 395 SNDRV_PCM_RATE_88200 |
358 SNDRV_PCM_RATE_9 396 SNDRV_PCM_RATE_96000),
359 .rate_min = 32000, 397 .rate_min = 32000,
360 .rate_max = 96000, 398 .rate_max = 96000,
361 .channels_min = 2, 399 .channels_min = 2,
362 .channels_max = 2, 400 .channels_max = 2,
363 .buffer_bytes_max = RME96_BUFFER_SIZE 401 .buffer_bytes_max = RME96_BUFFER_SIZE,
364 .period_bytes_min = RME96_SMALL_BLOCK 402 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
365 .period_bytes_max = RME96_LARGE_BLOCK 403 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
366 .periods_min = RME96_BUFFER_SIZE 404 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
367 .periods_max = RME96_BUFFER_SIZE 405 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
368 .fifo_size = 0, 406 .fifo_size = 0,
369 }; 407 };
370 408
371 /* 409 /*
372 * Digital input capabilities (S/PDIF) !! 410 * Digital input capabilites (S/PDIF)
373 */ 411 */
374 static struct snd_pcm_hardware snd_rme96_captu !! 412 static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
375 { 413 {
376 .info = (SNDRV_PCM_INFO_M 414 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
377 SNDRV_PCM_INFO_M 415 SNDRV_PCM_INFO_MMAP_VALID |
378 SNDRV_PCM_INFO_I 416 SNDRV_PCM_INFO_INTERLEAVED |
379 SNDRV_PCM_INFO_P 417 SNDRV_PCM_INFO_PAUSE),
380 .formats = (SNDRV_PCM_FMTBIT 418 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
381 SNDRV_PCM_FMTBIT 419 SNDRV_PCM_FMTBIT_S32_LE),
382 .rates = (SNDRV_PCM_RATE_3 420 .rates = (SNDRV_PCM_RATE_32000 |
383 SNDRV_PCM_RATE_4 421 SNDRV_PCM_RATE_44100 |
384 SNDRV_PCM_RATE_4 422 SNDRV_PCM_RATE_48000 |
385 SNDRV_PCM_RATE_6 423 SNDRV_PCM_RATE_64000 |
386 SNDRV_PCM_RATE_8 424 SNDRV_PCM_RATE_88200 |
387 SNDRV_PCM_RATE_9 425 SNDRV_PCM_RATE_96000),
388 .rate_min = 32000, 426 .rate_min = 32000,
389 .rate_max = 96000, 427 .rate_max = 96000,
390 .channels_min = 2, 428 .channels_min = 2,
391 .channels_max = 2, 429 .channels_max = 2,
392 .buffer_bytes_max = RME96_BUFFER_SIZE 430 .buffer_bytes_max = RME96_BUFFER_SIZE,
393 .period_bytes_min = RME96_SMALL_BLOCK 431 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
394 .period_bytes_max = RME96_LARGE_BLOCK 432 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
395 .periods_min = RME96_BUFFER_SIZE 433 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
396 .periods_max = RME96_BUFFER_SIZE 434 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
397 .fifo_size = 0, 435 .fifo_size = 0,
398 }; 436 };
399 437
400 /* 438 /*
401 * Digital output capabilities (ADAT) !! 439 * Digital output capabilites (ADAT)
402 */ 440 */
403 static struct snd_pcm_hardware snd_rme96_playb !! 441 static snd_pcm_hardware_t snd_rme96_playback_adat_info =
404 { 442 {
405 .info = (SNDRV_PCM_INFO_M 443 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
406 SNDRV_PCM_INFO_M 444 SNDRV_PCM_INFO_MMAP_VALID |
407 SNDRV_PCM_INFO_I 445 SNDRV_PCM_INFO_INTERLEAVED |
408 SNDRV_PCM_INFO_P 446 SNDRV_PCM_INFO_PAUSE),
409 .formats = (SNDRV_PCM_FMTBIT 447 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
410 SNDRV_PCM_FMTBIT 448 SNDRV_PCM_FMTBIT_S32_LE),
411 .rates = (SNDRV_PCM_RATE_4 449 .rates = (SNDRV_PCM_RATE_44100 |
412 SNDRV_PCM_RATE_4 450 SNDRV_PCM_RATE_48000),
413 .rate_min = 44100, 451 .rate_min = 44100,
414 .rate_max = 48000, 452 .rate_max = 48000,
415 .channels_min = 8, 453 .channels_min = 8,
416 .channels_max = 8, 454 .channels_max = 8,
417 .buffer_bytes_max = RME96_BUFFER_SIZE 455 .buffer_bytes_max = RME96_BUFFER_SIZE,
418 .period_bytes_min = RME96_SMALL_BLOCK 456 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
419 .period_bytes_max = RME96_LARGE_BLOCK 457 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
420 .periods_min = RME96_BUFFER_SIZE 458 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
421 .periods_max = RME96_BUFFER_SIZE 459 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
422 .fifo_size = 0, 460 .fifo_size = 0,
423 }; 461 };
424 462
425 /* 463 /*
426 * Digital input capabilities (ADAT) !! 464 * Digital input capabilites (ADAT)
427 */ 465 */
428 static struct snd_pcm_hardware snd_rme96_captu !! 466 static snd_pcm_hardware_t snd_rme96_capture_adat_info =
429 { 467 {
430 .info = (SNDRV_PCM_INFO_M 468 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
431 SNDRV_PCM_INFO_M 469 SNDRV_PCM_INFO_MMAP_VALID |
432 SNDRV_PCM_INFO_I 470 SNDRV_PCM_INFO_INTERLEAVED |
433 SNDRV_PCM_INFO_P 471 SNDRV_PCM_INFO_PAUSE),
434 .formats = (SNDRV_PCM_FMTBIT 472 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
435 SNDRV_PCM_FMTBIT 473 SNDRV_PCM_FMTBIT_S32_LE),
436 .rates = (SNDRV_PCM_RATE_4 474 .rates = (SNDRV_PCM_RATE_44100 |
437 SNDRV_PCM_RATE_4 475 SNDRV_PCM_RATE_48000),
438 .rate_min = 44100, 476 .rate_min = 44100,
439 .rate_max = 48000, 477 .rate_max = 48000,
440 .channels_min = 8, 478 .channels_min = 8,
441 .channels_max = 8, 479 .channels_max = 8,
442 .buffer_bytes_max = RME96_BUFFER_SIZE 480 .buffer_bytes_max = RME96_BUFFER_SIZE,
443 .period_bytes_min = RME96_SMALL_BLOCK 481 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
444 .period_bytes_max = RME96_LARGE_BLOCK 482 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
445 .periods_min = RME96_BUFFER_SIZE 483 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
446 .periods_max = RME96_BUFFER_SIZE 484 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
447 .fifo_size = 0, 485 .fifo_size = 0,
448 }; 486 };
449 487
450 /* 488 /*
451 * The CDATA, CCLK and CLATCH bits can be used 489 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
452 * of the AD1852 or AD1852 D/A converter on th 490 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
453 * on the falling edge of CCLK and be stable o 491 * on the falling edge of CCLK and be stable on the rising edge. The rising
454 * edge of CLATCH after the last data bit cloc 492 * edge of CLATCH after the last data bit clocks in the whole data word.
455 * A fast processor could probably drive the S 493 * A fast processor could probably drive the SPI interface faster than the
456 * DAC can handle (3MHz for the 1855, unknown 494 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
457 * limits the data rate to 500KHz and only cau 495 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
458 * 496 *
459 * NOTE: increased delay from 1 to 10, since t 497 * NOTE: increased delay from 1 to 10, since there where problems setting
460 * the volume. 498 * the volume.
461 */ 499 */
462 static void 500 static void
463 snd_rme96_write_SPI(struct rme96 *rme96, u16 v !! 501 snd_rme96_write_SPI(rme96_t *rme96, u16 val)
464 { 502 {
465 int i; 503 int i;
466 504
467 for (i = 0; i < 16; i++) { 505 for (i = 0; i < 16; i++) {
468 if (val & 0x8000) { 506 if (val & 0x8000) {
469 rme96->areg |= RME96_A 507 rme96->areg |= RME96_AR_CDATA;
470 } else { 508 } else {
471 rme96->areg &= ~RME96_ 509 rme96->areg &= ~RME96_AR_CDATA;
472 } 510 }
473 rme96->areg &= ~(RME96_AR_CCLK 511 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
474 writel(rme96->areg, rme96->iob 512 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
475 udelay(10); 513 udelay(10);
476 rme96->areg |= RME96_AR_CCLK; 514 rme96->areg |= RME96_AR_CCLK;
477 writel(rme96->areg, rme96->iob 515 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
478 udelay(10); 516 udelay(10);
479 val <<= 1; 517 val <<= 1;
480 } 518 }
481 rme96->areg &= ~(RME96_AR_CCLK | RME96 519 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
482 rme96->areg |= RME96_AR_CLATCH; 520 rme96->areg |= RME96_AR_CLATCH;
483 writel(rme96->areg, rme96->iobase + RM 521 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
484 udelay(10); 522 udelay(10);
485 rme96->areg &= ~RME96_AR_CLATCH; 523 rme96->areg &= ~RME96_AR_CLATCH;
486 writel(rme96->areg, rme96->iobase + RM 524 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
487 } 525 }
488 526
489 static void 527 static void
490 snd_rme96_apply_dac_volume(struct rme96 *rme96 !! 528 snd_rme96_apply_dac_volume(rme96_t *rme96)
491 { 529 {
492 if (RME96_DAC_IS_1852(rme96)) { 530 if (RME96_DAC_IS_1852(rme96)) {
493 snd_rme96_write_SPI(rme96, (rm 531 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
494 snd_rme96_write_SPI(rme96, (rm 532 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
495 } else if (RME96_DAC_IS_1855(rme96)) { 533 } else if (RME96_DAC_IS_1855(rme96)) {
496 snd_rme96_write_SPI(rme96, (rm 534 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
497 snd_rme96_write_SPI(rme96, (rm 535 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
498 } 536 }
499 } 537 }
500 538
501 static void 539 static void
502 snd_rme96_reset_dac(struct rme96 *rme96) !! 540 snd_rme96_reset_dac(rme96_t *rme96)
503 { 541 {
504 writel(rme96->wcreg | RME96_WCR_PD, 542 writel(rme96->wcreg | RME96_WCR_PD,
505 rme96->iobase + RME96_IO_CONTRO 543 rme96->iobase + RME96_IO_CONTROL_REGISTER);
506 writel(rme96->wcreg, rme96->iobase + R 544 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
507 } 545 }
508 546
509 static int 547 static int
510 snd_rme96_getmontracks(struct rme96 *rme96) !! 548 snd_rme96_getmontracks(rme96_t *rme96)
511 { 549 {
512 return ((rme96->wcreg >> RME96_WCR_BIT 550 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
513 (((rme96->wcreg >> RME96_WCR_B 551 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
514 } 552 }
515 553
516 static int 554 static int
517 snd_rme96_setmontracks(struct rme96 *rme96, !! 555 snd_rme96_setmontracks(rme96_t *rme96,
518 int montracks) 556 int montracks)
519 { 557 {
520 if (montracks & 1) { 558 if (montracks & 1) {
521 rme96->wcreg |= RME96_WCR_MONI 559 rme96->wcreg |= RME96_WCR_MONITOR_0;
522 } else { 560 } else {
523 rme96->wcreg &= ~RME96_WCR_MON 561 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
524 } 562 }
525 if (montracks & 2) { 563 if (montracks & 2) {
526 rme96->wcreg |= RME96_WCR_MONI 564 rme96->wcreg |= RME96_WCR_MONITOR_1;
527 } else { 565 } else {
528 rme96->wcreg &= ~RME96_WCR_MON 566 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
529 } 567 }
530 writel(rme96->wcreg, rme96->iobase + R 568 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
531 return 0; 569 return 0;
532 } 570 }
533 571
534 static int 572 static int
535 snd_rme96_getattenuation(struct rme96 *rme96) !! 573 snd_rme96_getattenuation(rme96_t *rme96)
536 { 574 {
537 return ((rme96->wcreg >> RME96_WCR_BIT 575 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
538 (((rme96->wcreg >> RME96_WCR_B 576 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
539 } 577 }
540 578
541 static int 579 static int
542 snd_rme96_setattenuation(struct rme96 *rme96, !! 580 snd_rme96_setattenuation(rme96_t *rme96,
543 int attenuation) 581 int attenuation)
544 { 582 {
545 switch (attenuation) { 583 switch (attenuation) {
546 case 0: 584 case 0:
547 rme96->wcreg = (rme96->wcreg & 585 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
548 ~RME96_WCR_GAIN_1; 586 ~RME96_WCR_GAIN_1;
549 break; 587 break;
550 case 1: 588 case 1:
551 rme96->wcreg = (rme96->wcreg | 589 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
552 ~RME96_WCR_GAIN_1; 590 ~RME96_WCR_GAIN_1;
553 break; 591 break;
554 case 2: 592 case 2:
555 rme96->wcreg = (rme96->wcreg & 593 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
556 RME96_WCR_GAIN_1; 594 RME96_WCR_GAIN_1;
557 break; 595 break;
558 case 3: 596 case 3:
559 rme96->wcreg = (rme96->wcreg | 597 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
560 RME96_WCR_GAIN_1; 598 RME96_WCR_GAIN_1;
561 break; 599 break;
562 default: 600 default:
563 return -EINVAL; 601 return -EINVAL;
564 } 602 }
565 writel(rme96->wcreg, rme96->iobase + R 603 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
566 return 0; 604 return 0;
567 } 605 }
568 606
569 static int 607 static int
570 snd_rme96_capture_getrate(struct rme96 *rme96, !! 608 snd_rme96_capture_getrate(rme96_t *rme96,
571 int *is_adat) 609 int *is_adat)
572 { 610 {
573 int n, rate; 611 int n, rate;
574 612
575 *is_adat = 0; 613 *is_adat = 0;
576 if (rme96->areg & RME96_AR_ANALOG) { 614 if (rme96->areg & RME96_AR_ANALOG) {
577 /* Analog input, overrides S/P 615 /* Analog input, overrides S/PDIF setting */
578 n = ((rme96->areg >> RME96_AR_ 616 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
579 (((rme96->areg >> RME9 617 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
580 switch (n) { 618 switch (n) {
581 case 1: 619 case 1:
582 rate = 32000; 620 rate = 32000;
583 break; 621 break;
584 case 2: 622 case 2:
585 rate = 44100; 623 rate = 44100;
586 break; 624 break;
587 case 3: 625 case 3:
588 rate = 48000; 626 rate = 48000;
589 break; 627 break;
590 default: 628 default:
591 return -1; 629 return -1;
592 } 630 }
593 return (rme96->areg & RME96_AR 631 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
594 } 632 }
595 633
596 rme96->rcreg = readl(rme96->iobase + R 634 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
597 if (rme96->rcreg & RME96_RCR_LOCK) { 635 if (rme96->rcreg & RME96_RCR_LOCK) {
598 /* ADAT rate */ 636 /* ADAT rate */
599 *is_adat = 1; 637 *is_adat = 1;
600 if (rme96->rcreg & RME96_RCR_T 638 if (rme96->rcreg & RME96_RCR_T_OUT) {
601 return 48000; 639 return 48000;
602 } 640 }
603 return 44100; 641 return 44100;
604 } 642 }
605 643
606 if (rme96->rcreg & RME96_RCR_VERF) { 644 if (rme96->rcreg & RME96_RCR_VERF) {
607 return -1; 645 return -1;
608 } 646 }
609 647
610 /* S/PDIF rate */ 648 /* S/PDIF rate */
611 n = ((rme96->rcreg >> RME96_RCR_BITPOS 649 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
612 (((rme96->rcreg >> RME96_RCR_B 650 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
613 (((rme96->rcreg >> RME96_RCR_B 651 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
614 652
615 switch (n) { 653 switch (n) {
616 case 0: 654 case 0:
617 if (rme96->rcreg & RME96_RCR_T 655 if (rme96->rcreg & RME96_RCR_T_OUT) {
618 return 64000; 656 return 64000;
619 } 657 }
620 return -1; 658 return -1;
621 case 3: return 96000; 659 case 3: return 96000;
622 case 4: return 88200; 660 case 4: return 88200;
623 case 5: return 48000; 661 case 5: return 48000;
624 case 6: return 44100; 662 case 6: return 44100;
625 case 7: return 32000; 663 case 7: return 32000;
626 default: 664 default:
627 break; 665 break;
628 } 666 }
629 return -1; 667 return -1;
630 } 668 }
631 669
632 static int 670 static int
633 snd_rme96_playback_getrate(struct rme96 *rme96 !! 671 snd_rme96_playback_getrate(rme96_t *rme96)
634 { 672 {
635 int rate, dummy; 673 int rate, dummy;
636 674
637 if (!(rme96->wcreg & RME96_WCR_MASTER) 675 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
638 snd_rme96_getinputtype(rme96) != R 676 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
639 (rate = snd_rme96_capture_getrate( 677 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
640 { 678 {
641 /* slave clock */ 679 /* slave clock */
642 return rate; 680 return rate;
643 } 681 }
644 rate = ((rme96->wcreg >> RME96_WCR_BIT 682 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
645 (((rme96->wcreg >> RME96_WCR_B 683 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
646 switch (rate) { 684 switch (rate) {
647 case 1: 685 case 1:
648 rate = 32000; 686 rate = 32000;
649 break; 687 break;
650 case 2: 688 case 2:
651 rate = 44100; 689 rate = 44100;
652 break; 690 break;
653 case 3: 691 case 3:
654 rate = 48000; 692 rate = 48000;
655 break; 693 break;
656 default: 694 default:
657 return -1; 695 return -1;
658 } 696 }
659 return (rme96->wcreg & RME96_WCR_DS) ? 697 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
660 } 698 }
661 699
662 static int 700 static int
663 snd_rme96_playback_setrate(struct rme96 *rme96 !! 701 snd_rme96_playback_setrate(rme96_t *rme96,
664 int rate) 702 int rate)
665 { 703 {
666 int ds; 704 int ds;
667 705
668 ds = rme96->wcreg & RME96_WCR_DS; 706 ds = rme96->wcreg & RME96_WCR_DS;
669 switch (rate) { 707 switch (rate) {
670 case 32000: 708 case 32000:
671 rme96->wcreg &= ~RME96_WCR_DS; 709 rme96->wcreg &= ~RME96_WCR_DS;
672 rme96->wcreg = (rme96->wcreg | 710 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
673 ~RME96_WCR_FREQ_1; 711 ~RME96_WCR_FREQ_1;
674 break; 712 break;
675 case 44100: 713 case 44100:
676 rme96->wcreg &= ~RME96_WCR_DS; 714 rme96->wcreg &= ~RME96_WCR_DS;
677 rme96->wcreg = (rme96->wcreg | 715 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
678 ~RME96_WCR_FREQ_0; 716 ~RME96_WCR_FREQ_0;
679 break; 717 break;
680 case 48000: 718 case 48000:
681 rme96->wcreg &= ~RME96_WCR_DS; 719 rme96->wcreg &= ~RME96_WCR_DS;
682 rme96->wcreg = (rme96->wcreg | 720 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
683 RME96_WCR_FREQ_1; 721 RME96_WCR_FREQ_1;
684 break; 722 break;
685 case 64000: 723 case 64000:
686 rme96->wcreg |= RME96_WCR_DS; 724 rme96->wcreg |= RME96_WCR_DS;
687 rme96->wcreg = (rme96->wcreg | 725 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
688 ~RME96_WCR_FREQ_1; 726 ~RME96_WCR_FREQ_1;
689 break; 727 break;
690 case 88200: 728 case 88200:
691 rme96->wcreg |= RME96_WCR_DS; 729 rme96->wcreg |= RME96_WCR_DS;
692 rme96->wcreg = (rme96->wcreg | 730 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
693 ~RME96_WCR_FREQ_0; 731 ~RME96_WCR_FREQ_0;
694 break; 732 break;
695 case 96000: 733 case 96000:
696 rme96->wcreg |= RME96_WCR_DS; 734 rme96->wcreg |= RME96_WCR_DS;
697 rme96->wcreg = (rme96->wcreg | 735 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
698 RME96_WCR_FREQ_1; 736 RME96_WCR_FREQ_1;
699 break; 737 break;
700 default: 738 default:
701 return -EINVAL; 739 return -EINVAL;
702 } 740 }
703 if ((!ds && rme96->wcreg & RME96_WCR_D 741 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
704 (ds && !(rme96->wcreg & RME96_WCR_ 742 (ds && !(rme96->wcreg & RME96_WCR_DS)))
705 { 743 {
706 /* change to/from double-speed 744 /* change to/from double-speed: reset the DAC (if available) */
707 snd_rme96_reset_dac(rme96); 745 snd_rme96_reset_dac(rme96);
708 } else { 746 } else {
709 writel(rme96->wcreg, rme96->io 747 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
710 } 748 }
711 return 0; 749 return 0;
712 } 750 }
713 751
714 static int 752 static int
715 snd_rme96_capture_analog_setrate(struct rme96 !! 753 snd_rme96_capture_analog_setrate(rme96_t *rme96,
716 int rate) 754 int rate)
717 { 755 {
718 switch (rate) { 756 switch (rate) {
719 case 32000: 757 case 32000:
720 rme96->areg = ((rme96->areg | 758 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
721 ~RME96_AR_FREQP 759 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
722 break; 760 break;
723 case 44100: 761 case 44100:
724 rme96->areg = ((rme96->areg & 762 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
725 RME96_AR_FREQPA 763 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
726 break; 764 break;
727 case 48000: 765 case 48000:
728 rme96->areg = ((rme96->areg | 766 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
729 RME96_AR_FREQPA 767 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
730 break; 768 break;
731 case 64000: 769 case 64000:
732 if (rme96->rev < 4) { 770 if (rme96->rev < 4) {
733 return -EINVAL; 771 return -EINVAL;
734 } 772 }
735 rme96->areg = ((rme96->areg | 773 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
736 ~RME96_AR_FREQP 774 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
737 break; 775 break;
738 case 88200: 776 case 88200:
739 if (rme96->rev < 4) { 777 if (rme96->rev < 4) {
740 return -EINVAL; 778 return -EINVAL;
741 } 779 }
742 rme96->areg = ((rme96->areg & 780 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
743 RME96_AR_FREQPA 781 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
744 break; 782 break;
745 case 96000: 783 case 96000:
746 rme96->areg = ((rme96->areg | 784 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
747 RME96_AR_FREQPA 785 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
748 break; 786 break;
749 default: 787 default:
750 return -EINVAL; 788 return -EINVAL;
751 } 789 }
752 writel(rme96->areg, rme96->iobase + RM 790 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
753 return 0; 791 return 0;
754 } 792 }
755 793
756 static int 794 static int
757 snd_rme96_setclockmode(struct rme96 *rme96, !! 795 snd_rme96_setclockmode(rme96_t *rme96,
758 int mode) 796 int mode)
759 { 797 {
760 switch (mode) { 798 switch (mode) {
761 case RME96_CLOCKMODE_SLAVE: 799 case RME96_CLOCKMODE_SLAVE:
762 /* AutoSync */ 800 /* AutoSync */
763 rme96->wcreg &= ~RME96_WCR_MAS 801 rme96->wcreg &= ~RME96_WCR_MASTER;
764 rme96->areg &= ~RME96_AR_WSEL; 802 rme96->areg &= ~RME96_AR_WSEL;
765 break; 803 break;
766 case RME96_CLOCKMODE_MASTER: 804 case RME96_CLOCKMODE_MASTER:
767 /* Internal */ 805 /* Internal */
768 rme96->wcreg |= RME96_WCR_MAST 806 rme96->wcreg |= RME96_WCR_MASTER;
769 rme96->areg &= ~RME96_AR_WSEL; 807 rme96->areg &= ~RME96_AR_WSEL;
770 break; 808 break;
771 case RME96_CLOCKMODE_WORDCLOCK: 809 case RME96_CLOCKMODE_WORDCLOCK:
772 /* Word clock is a master mode 810 /* Word clock is a master mode */
773 rme96->wcreg |= RME96_WCR_MAST 811 rme96->wcreg |= RME96_WCR_MASTER;
774 rme96->areg |= RME96_AR_WSEL; 812 rme96->areg |= RME96_AR_WSEL;
775 break; 813 break;
776 default: 814 default:
777 return -EINVAL; 815 return -EINVAL;
778 } 816 }
779 writel(rme96->wcreg, rme96->iobase + R 817 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
780 writel(rme96->areg, rme96->iobase + RM 818 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
781 return 0; 819 return 0;
782 } 820 }
783 821
784 static int 822 static int
785 snd_rme96_getclockmode(struct rme96 *rme96) !! 823 snd_rme96_getclockmode(rme96_t *rme96)
786 { 824 {
787 if (rme96->areg & RME96_AR_WSEL) { 825 if (rme96->areg & RME96_AR_WSEL) {
788 return RME96_CLOCKMODE_WORDCLO 826 return RME96_CLOCKMODE_WORDCLOCK;
789 } 827 }
790 return (rme96->wcreg & RME96_WCR_MASTE 828 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
791 RME96_CLOCKMODE_SLAVE; 829 RME96_CLOCKMODE_SLAVE;
792 } 830 }
793 831
794 static int 832 static int
795 snd_rme96_setinputtype(struct rme96 *rme96, !! 833 snd_rme96_setinputtype(rme96_t *rme96,
796 int type) 834 int type)
797 { 835 {
798 int n; 836 int n;
799 837
800 switch (type) { 838 switch (type) {
801 case RME96_INPUT_OPTICAL: 839 case RME96_INPUT_OPTICAL:
802 rme96->wcreg = (rme96->wcreg & 840 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
803 ~RME96_WCR_INP_1; 841 ~RME96_WCR_INP_1;
804 break; 842 break;
805 case RME96_INPUT_COAXIAL: 843 case RME96_INPUT_COAXIAL:
806 rme96->wcreg = (rme96->wcreg | 844 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
807 ~RME96_WCR_INP_1; 845 ~RME96_WCR_INP_1;
808 break; 846 break;
809 case RME96_INPUT_INTERNAL: 847 case RME96_INPUT_INTERNAL:
810 rme96->wcreg = (rme96->wcreg & 848 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
811 RME96_WCR_INP_1; 849 RME96_WCR_INP_1;
812 break; 850 break;
813 case RME96_INPUT_XLR: 851 case RME96_INPUT_XLR:
814 if ((rme96->pci->device != PCI !! 852 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
815 rme96->pci->device != PCI !! 853 rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) ||
816 (rme96->pci->device == PCI !! 854 (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
817 rme96->rev > 4)) 855 rme96->rev > 4))
818 { 856 {
819 /* Only Digi96/8 PRO a 857 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
820 return -EINVAL; 858 return -EINVAL;
821 } 859 }
822 rme96->wcreg = (rme96->wcreg | 860 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
823 RME96_WCR_INP_1; 861 RME96_WCR_INP_1;
824 break; 862 break;
825 case RME96_INPUT_ANALOG: 863 case RME96_INPUT_ANALOG:
826 if (!RME96_HAS_ANALOG_IN(rme96 864 if (!RME96_HAS_ANALOG_IN(rme96)) {
827 return -EINVAL; 865 return -EINVAL;
828 } 866 }
829 rme96->areg |= RME96_AR_ANALOG 867 rme96->areg |= RME96_AR_ANALOG;
830 writel(rme96->areg, rme96->iob 868 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
831 if (rme96->rev < 4) { 869 if (rme96->rev < 4) {
832 /* 870 /*
833 * Revision less than 871 * Revision less than 004 does not support 64 and
834 * 88.2 kHz 872 * 88.2 kHz
835 */ 873 */
836 if (snd_rme96_capture_ 874 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
837 snd_rme96_capt 875 snd_rme96_capture_analog_setrate(rme96, 44100);
838 } 876 }
839 if (snd_rme96_capture_ 877 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
840 snd_rme96_capt 878 snd_rme96_capture_analog_setrate(rme96, 32000);
841 } 879 }
842 } 880 }
843 return 0; 881 return 0;
844 default: 882 default:
845 return -EINVAL; 883 return -EINVAL;
846 } 884 }
847 if (type != RME96_INPUT_ANALOG && RME9 885 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
848 rme96->areg &= ~RME96_AR_ANALO 886 rme96->areg &= ~RME96_AR_ANALOG;
849 writel(rme96->areg, rme96->iob 887 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
850 } 888 }
851 writel(rme96->wcreg, rme96->iobase + R 889 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
852 return 0; 890 return 0;
853 } 891 }
854 892
855 static int 893 static int
856 snd_rme96_getinputtype(struct rme96 *rme96) !! 894 snd_rme96_getinputtype(rme96_t *rme96)
857 { 895 {
858 if (rme96->areg & RME96_AR_ANALOG) { 896 if (rme96->areg & RME96_AR_ANALOG) {
859 return RME96_INPUT_ANALOG; 897 return RME96_INPUT_ANALOG;
860 } 898 }
861 return ((rme96->wcreg >> RME96_WCR_BIT 899 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
862 (((rme96->wcreg >> RME96_WCR_B 900 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
863 } 901 }
864 902
865 static void 903 static void
866 snd_rme96_setframelog(struct rme96 *rme96, !! 904 snd_rme96_setframelog(rme96_t *rme96,
867 int n_channels, 905 int n_channels,
868 int is_playback) 906 int is_playback)
869 { 907 {
870 int frlog; 908 int frlog;
871 909
872 if (n_channels == 2) { 910 if (n_channels == 2) {
873 frlog = 1; 911 frlog = 1;
874 } else { 912 } else {
875 /* assume 8 channels */ 913 /* assume 8 channels */
876 frlog = 3; 914 frlog = 3;
877 } 915 }
878 if (is_playback) { 916 if (is_playback) {
879 frlog += (rme96->wcreg & RME96 917 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
880 rme96->playback_frlog = frlog; 918 rme96->playback_frlog = frlog;
881 } else { 919 } else {
882 frlog += (rme96->wcreg & RME96 920 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
883 rme96->capture_frlog = frlog; 921 rme96->capture_frlog = frlog;
884 } 922 }
885 } 923 }
886 924
887 static int 925 static int
888 snd_rme96_playback_setformat(struct rme96 *rme !! 926 snd_rme96_playback_setformat(rme96_t *rme96,
889 int format) 927 int format)
890 { 928 {
891 switch (format) { 929 switch (format) {
892 case SNDRV_PCM_FORMAT_S16_LE: 930 case SNDRV_PCM_FORMAT_S16_LE:
893 rme96->wcreg &= ~RME96_WCR_MOD 931 rme96->wcreg &= ~RME96_WCR_MODE24;
894 break; 932 break;
895 case SNDRV_PCM_FORMAT_S32_LE: 933 case SNDRV_PCM_FORMAT_S32_LE:
896 rme96->wcreg |= RME96_WCR_MODE 934 rme96->wcreg |= RME96_WCR_MODE24;
897 break; 935 break;
898 default: 936 default:
899 return -EINVAL; 937 return -EINVAL;
900 } 938 }
901 writel(rme96->wcreg, rme96->iobase + R 939 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
902 return 0; 940 return 0;
903 } 941 }
904 942
905 static int 943 static int
906 snd_rme96_capture_setformat(struct rme96 *rme9 !! 944 snd_rme96_capture_setformat(rme96_t *rme96,
907 int format) 945 int format)
908 { 946 {
909 switch (format) { 947 switch (format) {
910 case SNDRV_PCM_FORMAT_S16_LE: 948 case SNDRV_PCM_FORMAT_S16_LE:
911 rme96->wcreg &= ~RME96_WCR_MOD 949 rme96->wcreg &= ~RME96_WCR_MODE24_2;
912 break; 950 break;
913 case SNDRV_PCM_FORMAT_S32_LE: 951 case SNDRV_PCM_FORMAT_S32_LE:
914 rme96->wcreg |= RME96_WCR_MODE 952 rme96->wcreg |= RME96_WCR_MODE24_2;
915 break; 953 break;
916 default: 954 default:
917 return -EINVAL; 955 return -EINVAL;
918 } 956 }
919 writel(rme96->wcreg, rme96->iobase + R 957 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
920 return 0; 958 return 0;
921 } 959 }
922 960
923 static void 961 static void
924 snd_rme96_set_period_properties(struct rme96 * !! 962 snd_rme96_set_period_properties(rme96_t *rme96,
925 size_t period_ 963 size_t period_bytes)
926 { 964 {
927 switch (period_bytes) { 965 switch (period_bytes) {
928 case RME96_LARGE_BLOCK_SIZE: 966 case RME96_LARGE_BLOCK_SIZE:
929 rme96->wcreg &= ~RME96_WCR_ISE 967 rme96->wcreg &= ~RME96_WCR_ISEL;
930 break; 968 break;
931 case RME96_SMALL_BLOCK_SIZE: 969 case RME96_SMALL_BLOCK_SIZE:
932 rme96->wcreg |= RME96_WCR_ISEL 970 rme96->wcreg |= RME96_WCR_ISEL;
933 break; 971 break;
934 default: 972 default:
935 snd_BUG(); 973 snd_BUG();
936 break; 974 break;
937 } 975 }
938 rme96->wcreg &= ~RME96_WCR_IDIS; 976 rme96->wcreg &= ~RME96_WCR_IDIS;
939 writel(rme96->wcreg, rme96->iobase + R 977 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
940 } 978 }
941 979
942 static int 980 static int
943 snd_rme96_playback_hw_params(struct snd_pcm_su !! 981 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
944 struct snd_pcm_hw !! 982 snd_pcm_hw_params_t *params)
945 { 983 {
946 struct rme96 *rme96 = snd_pcm_substrea !! 984 rme96_t *rme96 = snd_pcm_substream_chip(substream);
947 struct snd_pcm_runtime *runtime = subs !! 985 snd_pcm_runtime_t *runtime = substream->runtime;
948 int err, rate, dummy; 986 int err, rate, dummy;
949 987
950 runtime->dma_area = (void __force *)(r !! 988 runtime->dma_area = (void *)(rme96->iobase + RME96_IO_PLAY_BUFFER);
951 R <<
952 runtime->dma_addr = rme96->port + RME9 989 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
953 runtime->dma_bytes = RME96_BUFFER_SIZE 990 runtime->dma_bytes = RME96_BUFFER_SIZE;
954 991
955 spin_lock_irq(&rme96->lock); 992 spin_lock_irq(&rme96->lock);
956 if (!(rme96->wcreg & RME96_WCR_MASTER) 993 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
957 snd_rme96_getinputtype(rme96) != R 994 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
958 (rate = snd_rme96_capture_getrate( 995 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
959 { 996 {
960 /* slave clock */ 997 /* slave clock */
961 if ((int)params_rate(params) ! 998 if ((int)params_rate(params) != rate) {
962 spin_unlock_irq(&rme96 999 spin_unlock_irq(&rme96->lock);
963 return -EIO; 1000 return -EIO;
964 } 1001 }
965 } else if ((err = snd_rme96_playback_s 1002 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
966 spin_unlock_irq(&rme96->lock); 1003 spin_unlock_irq(&rme96->lock);
967 return err; 1004 return err;
968 } 1005 }
969 if ((err = snd_rme96_playback_setforma 1006 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
970 spin_unlock_irq(&rme96->lock); 1007 spin_unlock_irq(&rme96->lock);
971 return err; 1008 return err;
972 } 1009 }
973 snd_rme96_setframelog(rme96, params_ch 1010 snd_rme96_setframelog(rme96, params_channels(params), 1);
974 if (rme96->capture_periodsize != 0) { 1011 if (rme96->capture_periodsize != 0) {
975 if (params_period_size(params) 1012 if (params_period_size(params) << rme96->playback_frlog !=
976 rme96->capture_periodsize) 1013 rme96->capture_periodsize)
977 { 1014 {
978 spin_unlock_irq(&rme96 1015 spin_unlock_irq(&rme96->lock);
979 return -EBUSY; 1016 return -EBUSY;
980 } 1017 }
981 } 1018 }
982 rme96->playback_periodsize = 1019 rme96->playback_periodsize =
983 params_period_size(params) << 1020 params_period_size(params) << rme96->playback_frlog;
984 snd_rme96_set_period_properties(rme96, 1021 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
985 /* S/PDIF setup */ 1022 /* S/PDIF setup */
986 if ((rme96->wcreg & RME96_WCR_ADAT) == 1023 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
987 rme96->wcreg &= ~(RME96_WCR_PR 1024 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
988 writel(rme96->wcreg |= rme96-> 1025 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
989 } 1026 }
990 spin_unlock_irq(&rme96->lock); 1027 spin_unlock_irq(&rme96->lock);
991 1028
992 return 0; 1029 return 0;
993 } 1030 }
994 1031
995 static int 1032 static int
996 snd_rme96_capture_hw_params(struct snd_pcm_sub !! 1033 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
997 struct snd_pcm_hw_ !! 1034 snd_pcm_hw_params_t *params)
998 { 1035 {
999 struct rme96 *rme96 = snd_pcm_substrea !! 1036 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1000 struct snd_pcm_runtime *runtime = sub !! 1037 snd_pcm_runtime_t *runtime = substream->runtime;
1001 int err, isadat, rate; 1038 int err, isadat, rate;
1002 1039
1003 runtime->dma_area = (void __force *)( !! 1040 runtime->dma_area = (void *)(rme96->iobase + RME96_IO_REC_BUFFER);
1004 <<
1005 runtime->dma_addr = rme96->port + RME 1041 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1006 runtime->dma_bytes = RME96_BUFFER_SIZ 1042 runtime->dma_bytes = RME96_BUFFER_SIZE;
1007 1043
1008 spin_lock_irq(&rme96->lock); 1044 spin_lock_irq(&rme96->lock);
1009 if ((err = snd_rme96_capture_setforma 1045 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1010 spin_unlock_irq(&rme96->lock) 1046 spin_unlock_irq(&rme96->lock);
1011 return err; 1047 return err;
1012 } 1048 }
1013 if (snd_rme96_getinputtype(rme96) == 1049 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1014 if ((err = snd_rme96_capture_ 1050 if ((err = snd_rme96_capture_analog_setrate(rme96,
1015 1051 params_rate(params))) < 0)
1016 { 1052 {
1017 spin_unlock_irq(&rme9 1053 spin_unlock_irq(&rme96->lock);
1018 return err; 1054 return err;
1019 } 1055 }
1020 } else if ((rate = snd_rme96_capture_ 1056 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1021 if ((int)params_rate(params) 1057 if ((int)params_rate(params) != rate) {
1022 spin_unlock_irq(&rme9 1058 spin_unlock_irq(&rme96->lock);
1023 return -EIO; 1059 return -EIO;
1024 } 1060 }
1025 if ((isadat && runtime->hw.ch 1061 if ((isadat && runtime->hw.channels_min == 2) ||
1026 (!isadat && runtime->hw.c 1062 (!isadat && runtime->hw.channels_min == 8))
1027 { 1063 {
1028 spin_unlock_irq(&rme9 1064 spin_unlock_irq(&rme96->lock);
1029 return -EIO; 1065 return -EIO;
1030 } 1066 }
1031 } 1067 }
1032 snd_rme96_setframelog(rme96, params_c 1068 snd_rme96_setframelog(rme96, params_channels(params), 0);
1033 if (rme96->playback_periodsize != 0) 1069 if (rme96->playback_periodsize != 0) {
1034 if (params_period_size(params 1070 if (params_period_size(params) << rme96->capture_frlog !=
1035 rme96->playback_periodsiz 1071 rme96->playback_periodsize)
1036 { 1072 {
1037 spin_unlock_irq(&rme9 1073 spin_unlock_irq(&rme96->lock);
1038 return -EBUSY; 1074 return -EBUSY;
1039 } 1075 }
1040 } 1076 }
1041 rme96->capture_periodsize = 1077 rme96->capture_periodsize =
1042 params_period_size(params) << 1078 params_period_size(params) << rme96->capture_frlog;
1043 snd_rme96_set_period_properties(rme96 1079 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1044 spin_unlock_irq(&rme96->lock); 1080 spin_unlock_irq(&rme96->lock);
1045 1081
1046 return 0; 1082 return 0;
1047 } 1083 }
1048 1084
1049 static void 1085 static void
1050 snd_rme96_playback_start(struct rme96 *rme96, !! 1086 snd_rme96_playback_start(rme96_t *rme96,
1051 int from_pause) 1087 int from_pause)
1052 { 1088 {
1053 if (!from_pause) { 1089 if (!from_pause) {
1054 writel(0, rme96->iobase + RME 1090 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1055 } 1091 }
1056 1092
1057 rme96->wcreg |= RME96_WCR_START; 1093 rme96->wcreg |= RME96_WCR_START;
1058 writel(rme96->wcreg, rme96->iobase + 1094 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1059 } 1095 }
1060 1096
1061 static void 1097 static void
1062 snd_rme96_capture_start(struct rme96 *rme96, !! 1098 snd_rme96_capture_start(rme96_t *rme96,
1063 int from_pause) 1099 int from_pause)
1064 { 1100 {
1065 if (!from_pause) { 1101 if (!from_pause) {
1066 writel(0, rme96->iobase + RME 1102 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1067 } 1103 }
1068 1104
1069 rme96->wcreg |= RME96_WCR_START_2; 1105 rme96->wcreg |= RME96_WCR_START_2;
1070 writel(rme96->wcreg, rme96->iobase + 1106 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1071 } 1107 }
1072 1108
1073 static void 1109 static void
1074 snd_rme96_playback_stop(struct rme96 *rme96) !! 1110 snd_rme96_playback_stop(rme96_t *rme96)
1075 { 1111 {
1076 /* 1112 /*
1077 * Check if there is an unconfirmed I 1113 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1078 * the hardware will not stop generat 1114 * the hardware will not stop generating interrupts
1079 */ 1115 */
1080 rme96->rcreg = readl(rme96->iobase + 1116 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1081 if (rme96->rcreg & RME96_RCR_IRQ) { 1117 if (rme96->rcreg & RME96_RCR_IRQ) {
1082 writel(0, rme96->iobase + RME 1118 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1083 } 1119 }
1084 rme96->wcreg &= ~RME96_WCR_START; 1120 rme96->wcreg &= ~RME96_WCR_START;
1085 writel(rme96->wcreg, rme96->iobase + 1121 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1086 } 1122 }
1087 1123
1088 static void 1124 static void
1089 snd_rme96_capture_stop(struct rme96 *rme96) !! 1125 snd_rme96_capture_stop(rme96_t *rme96)
1090 { 1126 {
1091 rme96->rcreg = readl(rme96->iobase + 1127 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1092 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1128 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1093 writel(0, rme96->iobase + RME 1129 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1094 } 1130 }
1095 rme96->wcreg &= ~RME96_WCR_START_2; 1131 rme96->wcreg &= ~RME96_WCR_START_2;
1096 writel(rme96->wcreg, rme96->iobase + 1132 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1097 } 1133 }
1098 1134
1099 static irqreturn_t 1135 static irqreturn_t
1100 snd_rme96_interrupt(int irq, 1136 snd_rme96_interrupt(int irq,
1101 void *dev_id) !! 1137 void *dev_id,
>> 1138 struct pt_regs *regs)
1102 { 1139 {
1103 struct rme96 *rme96 = (struct rme96 * !! 1140 rme96_t *rme96 = (rme96_t *)dev_id;
1104 1141
1105 rme96->rcreg = readl(rme96->iobase + 1142 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1106 /* fastpath out, to ease interrupt sh 1143 /* fastpath out, to ease interrupt sharing */
1107 if (!((rme96->rcreg & RME96_RCR_IRQ) 1144 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1108 (rme96->rcreg & RME96_RCR_IRQ_2 1145 (rme96->rcreg & RME96_RCR_IRQ_2)))
1109 { 1146 {
1110 return IRQ_NONE; 1147 return IRQ_NONE;
1111 } 1148 }
1112 1149
1113 if (rme96->rcreg & RME96_RCR_IRQ) { 1150 if (rme96->rcreg & RME96_RCR_IRQ) {
1114 /* playback */ 1151 /* playback */
1115 snd_pcm_period_elapsed(rme96- 1152 snd_pcm_period_elapsed(rme96->playback_substream);
1116 writel(0, rme96->iobase + RME 1153 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1117 } 1154 }
1118 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1155 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1119 /* capture */ 1156 /* capture */
1120 snd_pcm_period_elapsed(rme96- 1157 snd_pcm_period_elapsed(rme96->capture_substream);
1121 writel(0, rme96->iobase + RME 1158 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1122 } 1159 }
1123 return IRQ_HANDLED; 1160 return IRQ_HANDLED;
1124 } 1161 }
1125 1162
1126 static unsigned int period_bytes[] = { RME96_ 1163 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1127 1164
1128 static struct snd_pcm_hw_constraint_list hw_c !! 1165 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1129 .count = ARRAY_SIZE(period_bytes), 1166 .count = ARRAY_SIZE(period_bytes),
1130 .list = period_bytes, 1167 .list = period_bytes,
1131 .mask = 0 1168 .mask = 0
1132 }; 1169 };
1133 1170
1134 static void <<
1135 rme96_set_buffer_size_constraint(struct rme96 <<
1136 struct snd_p <<
1137 { <<
1138 unsigned int size; <<
1139 <<
1140 snd_pcm_hw_constraint_minmax(runtime, <<
1141 RME96_BU <<
1142 if ((size = rme96->playback_periodsiz <<
1143 (size = rme96->capture_periodsize <<
1144 snd_pcm_hw_constraint_minmax( <<
1145 <<
1146 <<
1147 else <<
1148 snd_pcm_hw_constraint_list(ru <<
1149 SN <<
1150 &h <<
1151 } <<
1152 <<
1153 static int 1171 static int
1154 snd_rme96_playback_spdif_open(struct snd_pcm_ !! 1172 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1155 { 1173 {
1156 int rate, dummy; 1174 int rate, dummy;
1157 struct rme96 *rme96 = snd_pcm_substre !! 1175 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1158 struct snd_pcm_runtime *runtime = sub !! 1176 snd_pcm_runtime_t *runtime = substream->runtime;
>> 1177
>> 1178 snd_pcm_set_sync(substream);
1159 1179
1160 spin_lock_irq(&rme96->lock); 1180 spin_lock_irq(&rme96->lock);
1161 if (rme96->playback_substream != NULL 1181 if (rme96->playback_substream != NULL) {
1162 spin_unlock_irq(&rme96->lock) 1182 spin_unlock_irq(&rme96->lock);
1163 return -EBUSY; 1183 return -EBUSY;
1164 } 1184 }
1165 rme96->wcreg &= ~RME96_WCR_ADAT; 1185 rme96->wcreg &= ~RME96_WCR_ADAT;
1166 writel(rme96->wcreg, rme96->iobase + 1186 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1167 rme96->playback_substream = substream 1187 rme96->playback_substream = substream;
1168 spin_unlock_irq(&rme96->lock); 1188 spin_unlock_irq(&rme96->lock);
1169 1189
1170 runtime->hw = snd_rme96_playback_spdi 1190 runtime->hw = snd_rme96_playback_spdif_info;
1171 if (!(rme96->wcreg & RME96_WCR_MASTER 1191 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1172 snd_rme96_getinputtype(rme96) != 1192 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1173 (rate = snd_rme96_capture_getrate 1193 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1174 { 1194 {
1175 /* slave clock */ 1195 /* slave clock */
1176 runtime->hw.rates = snd_pcm_r !! 1196 runtime->hw.rates = snd_rme96_ratecode(rate);
1177 runtime->hw.rate_min = rate; 1197 runtime->hw.rate_min = rate;
1178 runtime->hw.rate_max = rate; 1198 runtime->hw.rate_max = rate;
1179 } 1199 }
1180 rme96_set_buffer_size_constraint(rme9 !! 1200 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
>> 1201 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1181 1202
1182 rme96->wcreg_spdif_stream = rme96->wc 1203 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1183 rme96->spdif_ctl->vd[0].access &= ~SN 1204 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1184 snd_ctl_notify(rme96->card, SNDRV_CTL 1205 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1185 SNDRV_CTL_EVENT_MASK_I 1206 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1186 return 0; 1207 return 0;
1187 } 1208 }
1188 1209
1189 static int 1210 static int
1190 snd_rme96_capture_spdif_open(struct snd_pcm_s !! 1211 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1191 { 1212 {
1192 int isadat, rate; 1213 int isadat, rate;
1193 struct rme96 *rme96 = snd_pcm_substre !! 1214 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1194 struct snd_pcm_runtime *runtime = sub !! 1215 snd_pcm_runtime_t *runtime = substream->runtime;
>> 1216
>> 1217 snd_pcm_set_sync(substream);
1195 1218
1196 runtime->hw = snd_rme96_capture_spdif 1219 runtime->hw = snd_rme96_capture_spdif_info;
1197 if (snd_rme96_getinputtype(rme96) != 1220 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1198 (rate = snd_rme96_capture_getrate 1221 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1199 { 1222 {
1200 if (isadat) { 1223 if (isadat) {
1201 return -EIO; 1224 return -EIO;
1202 } 1225 }
1203 runtime->hw.rates = snd_pcm_r !! 1226 runtime->hw.rates = snd_rme96_ratecode(rate);
1204 runtime->hw.rate_min = rate; 1227 runtime->hw.rate_min = rate;
1205 runtime->hw.rate_max = rate; 1228 runtime->hw.rate_max = rate;
1206 } 1229 }
1207 1230
1208 spin_lock_irq(&rme96->lock); 1231 spin_lock_irq(&rme96->lock);
1209 if (rme96->capture_substream != NULL) 1232 if (rme96->capture_substream != NULL) {
1210 spin_unlock_irq(&rme96->lock) 1233 spin_unlock_irq(&rme96->lock);
1211 return -EBUSY; 1234 return -EBUSY;
1212 } 1235 }
1213 rme96->capture_substream = substream; 1236 rme96->capture_substream = substream;
1214 spin_unlock_irq(&rme96->lock); 1237 spin_unlock_irq(&rme96->lock);
1215 1238
1216 rme96_set_buffer_size_constraint(rme9 !! 1239 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
>> 1240 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
>> 1241
1217 return 0; 1242 return 0;
1218 } 1243 }
1219 1244
1220 static int 1245 static int
1221 snd_rme96_playback_adat_open(struct snd_pcm_s !! 1246 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1222 { 1247 {
1223 int rate, dummy; 1248 int rate, dummy;
1224 struct rme96 *rme96 = snd_pcm_substre !! 1249 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1225 struct snd_pcm_runtime *runtime = sub !! 1250 snd_pcm_runtime_t *runtime = substream->runtime;
1226 1251
>> 1252 snd_pcm_set_sync(substream);
>> 1253
1227 spin_lock_irq(&rme96->lock); 1254 spin_lock_irq(&rme96->lock);
1228 if (rme96->playback_substream != NULL 1255 if (rme96->playback_substream != NULL) {
1229 spin_unlock_irq(&rme96->lock) 1256 spin_unlock_irq(&rme96->lock);
1230 return -EBUSY; 1257 return -EBUSY;
1231 } 1258 }
1232 rme96->wcreg |= RME96_WCR_ADAT; 1259 rme96->wcreg |= RME96_WCR_ADAT;
1233 writel(rme96->wcreg, rme96->iobase + 1260 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1234 rme96->playback_substream = substream 1261 rme96->playback_substream = substream;
1235 spin_unlock_irq(&rme96->lock); 1262 spin_unlock_irq(&rme96->lock);
1236 1263
1237 runtime->hw = snd_rme96_playback_adat 1264 runtime->hw = snd_rme96_playback_adat_info;
1238 if (!(rme96->wcreg & RME96_WCR_MASTER 1265 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1239 snd_rme96_getinputtype(rme96) != 1266 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1240 (rate = snd_rme96_capture_getrate 1267 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1241 { 1268 {
1242 /* slave clock */ 1269 /* slave clock */
1243 runtime->hw.rates = snd_pcm_r !! 1270 runtime->hw.rates = snd_rme96_ratecode(rate);
1244 runtime->hw.rate_min = rate; 1271 runtime->hw.rate_min = rate;
1245 runtime->hw.rate_max = rate; 1272 runtime->hw.rate_max = rate;
1246 } 1273 }
1247 rme96_set_buffer_size_constraint(rme9 !! 1274 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
>> 1275 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1248 return 0; 1276 return 0;
1249 } 1277 }
1250 1278
1251 static int 1279 static int
1252 snd_rme96_capture_adat_open(struct snd_pcm_su !! 1280 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1253 { 1281 {
1254 int isadat, rate; 1282 int isadat, rate;
1255 struct rme96 *rme96 = snd_pcm_substre !! 1283 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1256 struct snd_pcm_runtime *runtime = sub !! 1284 snd_pcm_runtime_t *runtime = substream->runtime;
>> 1285
>> 1286 snd_pcm_set_sync(substream);
1257 1287
1258 runtime->hw = snd_rme96_capture_adat_ 1288 runtime->hw = snd_rme96_capture_adat_info;
1259 if (snd_rme96_getinputtype(rme96) == 1289 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1260 /* makes no sense to use anal 1290 /* makes no sense to use analog input. Note that analog
1261 expension cards AEB4/8-I a 1291 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1262 return -EIO; 1292 return -EIO;
1263 } 1293 }
1264 if ((rate = snd_rme96_capture_getrate 1294 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1265 if (!isadat) { 1295 if (!isadat) {
1266 return -EIO; 1296 return -EIO;
1267 } 1297 }
1268 runtime->hw.rates = snd_pcm_r !! 1298 runtime->hw.rates = snd_rme96_ratecode(rate);
1269 runtime->hw.rate_min = rate; 1299 runtime->hw.rate_min = rate;
1270 runtime->hw.rate_max = rate; 1300 runtime->hw.rate_max = rate;
1271 } 1301 }
1272 1302
1273 spin_lock_irq(&rme96->lock); 1303 spin_lock_irq(&rme96->lock);
1274 if (rme96->capture_substream != NULL) 1304 if (rme96->capture_substream != NULL) {
1275 spin_unlock_irq(&rme96->lock) 1305 spin_unlock_irq(&rme96->lock);
1276 return -EBUSY; 1306 return -EBUSY;
1277 } 1307 }
1278 rme96->capture_substream = substream; 1308 rme96->capture_substream = substream;
1279 spin_unlock_irq(&rme96->lock); 1309 spin_unlock_irq(&rme96->lock);
1280 1310
1281 rme96_set_buffer_size_constraint(rme9 !! 1311 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
>> 1312 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1282 return 0; 1313 return 0;
1283 } 1314 }
1284 1315
1285 static int 1316 static int
1286 snd_rme96_playback_close(struct snd_pcm_subst !! 1317 snd_rme96_playback_close(snd_pcm_substream_t *substream)
1287 { 1318 {
1288 struct rme96 *rme96 = snd_pcm_substre !! 1319 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1289 int spdif = 0; 1320 int spdif = 0;
1290 1321
1291 spin_lock_irq(&rme96->lock); 1322 spin_lock_irq(&rme96->lock);
1292 if (RME96_ISPLAYING(rme96)) { 1323 if (RME96_ISPLAYING(rme96)) {
1293 snd_rme96_playback_stop(rme96 1324 snd_rme96_playback_stop(rme96);
1294 } 1325 }
1295 rme96->playback_substream = NULL; 1326 rme96->playback_substream = NULL;
1296 rme96->playback_periodsize = 0; 1327 rme96->playback_periodsize = 0;
1297 spdif = (rme96->wcreg & RME96_WCR_ADA 1328 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1298 spin_unlock_irq(&rme96->lock); 1329 spin_unlock_irq(&rme96->lock);
1299 if (spdif) { 1330 if (spdif) {
1300 rme96->spdif_ctl->vd[0].acces 1331 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1301 snd_ctl_notify(rme96->card, S 1332 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1302 SNDRV_CTL_EVEN 1333 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1303 } 1334 }
1304 return 0; 1335 return 0;
1305 } 1336 }
1306 1337
1307 static int 1338 static int
1308 snd_rme96_capture_close(struct snd_pcm_substr !! 1339 snd_rme96_capture_close(snd_pcm_substream_t *substream)
1309 { 1340 {
1310 struct rme96 *rme96 = snd_pcm_substre !! 1341 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1311 1342
1312 spin_lock_irq(&rme96->lock); 1343 spin_lock_irq(&rme96->lock);
1313 if (RME96_ISRECORDING(rme96)) { 1344 if (RME96_ISRECORDING(rme96)) {
1314 snd_rme96_capture_stop(rme96) 1345 snd_rme96_capture_stop(rme96);
1315 } 1346 }
1316 rme96->capture_substream = NULL; 1347 rme96->capture_substream = NULL;
1317 rme96->capture_periodsize = 0; 1348 rme96->capture_periodsize = 0;
1318 spin_unlock_irq(&rme96->lock); 1349 spin_unlock_irq(&rme96->lock);
1319 return 0; 1350 return 0;
1320 } 1351 }
1321 1352
1322 static int 1353 static int
1323 snd_rme96_playback_prepare(struct snd_pcm_sub !! 1354 snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1324 { 1355 {
1325 struct rme96 *rme96 = snd_pcm_substre !! 1356 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1326 1357
1327 spin_lock_irq(&rme96->lock); 1358 spin_lock_irq(&rme96->lock);
1328 if (RME96_ISPLAYING(rme96)) { 1359 if (RME96_ISPLAYING(rme96)) {
1329 snd_rme96_playback_stop(rme96 1360 snd_rme96_playback_stop(rme96);
1330 } 1361 }
1331 writel(0, rme96->iobase + RME96_IO_RE 1362 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1332 spin_unlock_irq(&rme96->lock); 1363 spin_unlock_irq(&rme96->lock);
1333 return 0; 1364 return 0;
1334 } 1365 }
1335 1366
1336 static int 1367 static int
1337 snd_rme96_capture_prepare(struct snd_pcm_subs !! 1368 snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1338 { 1369 {
1339 struct rme96 *rme96 = snd_pcm_substre !! 1370 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1340 1371
1341 spin_lock_irq(&rme96->lock); 1372 spin_lock_irq(&rme96->lock);
1342 if (RME96_ISRECORDING(rme96)) { 1373 if (RME96_ISRECORDING(rme96)) {
1343 snd_rme96_capture_stop(rme96) 1374 snd_rme96_capture_stop(rme96);
1344 } 1375 }
1345 writel(0, rme96->iobase + RME96_IO_RE 1376 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1346 spin_unlock_irq(&rme96->lock); 1377 spin_unlock_irq(&rme96->lock);
1347 return 0; 1378 return 0;
1348 } 1379 }
1349 1380
1350 static int 1381 static int
1351 snd_rme96_playback_trigger(struct snd_pcm_sub !! 1382 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1352 int cmd) 1383 int cmd)
1353 { 1384 {
1354 struct rme96 *rme96 = snd_pcm_substre !! 1385 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1355 1386
1356 switch (cmd) { 1387 switch (cmd) {
1357 case SNDRV_PCM_TRIGGER_START: 1388 case SNDRV_PCM_TRIGGER_START:
1358 if (!RME96_ISPLAYING(rme96)) 1389 if (!RME96_ISPLAYING(rme96)) {
1359 if (substream != rme9 1390 if (substream != rme96->playback_substream) {
1360 return -EBUSY 1391 return -EBUSY;
1361 } 1392 }
1362 snd_rme96_playback_st 1393 snd_rme96_playback_start(rme96, 0);
1363 } 1394 }
1364 break; 1395 break;
1365 1396
1366 case SNDRV_PCM_TRIGGER_STOP: 1397 case SNDRV_PCM_TRIGGER_STOP:
1367 if (RME96_ISPLAYING(rme96)) { 1398 if (RME96_ISPLAYING(rme96)) {
1368 if (substream != rme9 1399 if (substream != rme96->playback_substream) {
1369 return -EBUSY 1400 return -EBUSY;
1370 } 1401 }
1371 snd_rme96_playback_st 1402 snd_rme96_playback_stop(rme96);
1372 } 1403 }
1373 break; 1404 break;
1374 1405
1375 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1406 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1376 if (RME96_ISPLAYING(rme96)) { 1407 if (RME96_ISPLAYING(rme96)) {
1377 snd_rme96_playback_st 1408 snd_rme96_playback_stop(rme96);
1378 } 1409 }
1379 break; 1410 break;
1380 1411
1381 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1412 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1382 if (!RME96_ISPLAYING(rme96)) 1413 if (!RME96_ISPLAYING(rme96)) {
1383 snd_rme96_playback_st 1414 snd_rme96_playback_start(rme96, 1);
1384 } 1415 }
1385 break; 1416 break;
1386 1417
1387 default: 1418 default:
1388 return -EINVAL; 1419 return -EINVAL;
1389 } 1420 }
1390 return 0; 1421 return 0;
1391 } 1422 }
1392 1423
1393 static int 1424 static int
1394 snd_rme96_capture_trigger(struct snd_pcm_subs !! 1425 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1395 int cmd) 1426 int cmd)
1396 { 1427 {
1397 struct rme96 *rme96 = snd_pcm_substre !! 1428 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1398 1429
1399 switch (cmd) { 1430 switch (cmd) {
1400 case SNDRV_PCM_TRIGGER_START: 1431 case SNDRV_PCM_TRIGGER_START:
1401 if (!RME96_ISRECORDING(rme96) 1432 if (!RME96_ISRECORDING(rme96)) {
1402 if (substream != rme9 1433 if (substream != rme96->capture_substream) {
1403 return -EBUSY 1434 return -EBUSY;
1404 } 1435 }
1405 snd_rme96_capture_sta 1436 snd_rme96_capture_start(rme96, 0);
1406 } 1437 }
1407 break; 1438 break;
1408 1439
1409 case SNDRV_PCM_TRIGGER_STOP: 1440 case SNDRV_PCM_TRIGGER_STOP:
1410 if (RME96_ISRECORDING(rme96)) 1441 if (RME96_ISRECORDING(rme96)) {
1411 if (substream != rme9 1442 if (substream != rme96->capture_substream) {
1412 return -EBUSY 1443 return -EBUSY;
1413 } 1444 }
1414 snd_rme96_capture_sto 1445 snd_rme96_capture_stop(rme96);
1415 } 1446 }
1416 break; 1447 break;
1417 1448
1418 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1449 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1419 if (RME96_ISRECORDING(rme96)) 1450 if (RME96_ISRECORDING(rme96)) {
1420 snd_rme96_capture_sto 1451 snd_rme96_capture_stop(rme96);
1421 } 1452 }
1422 break; 1453 break;
1423 1454
1424 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1455 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1425 if (!RME96_ISRECORDING(rme96) 1456 if (!RME96_ISRECORDING(rme96)) {
1426 snd_rme96_capture_sta 1457 snd_rme96_capture_start(rme96, 1);
1427 } 1458 }
1428 break; 1459 break;
1429 1460
1430 default: 1461 default:
1431 return -EINVAL; 1462 return -EINVAL;
1432 } 1463 }
1433 1464
1434 return 0; 1465 return 0;
1435 } 1466 }
1436 1467
1437 static snd_pcm_uframes_t 1468 static snd_pcm_uframes_t
1438 snd_rme96_playback_pointer(struct snd_pcm_sub !! 1469 snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1439 { 1470 {
1440 struct rme96 *rme96 = snd_pcm_substre !! 1471 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1441 return snd_rme96_playback_ptr(rme96); 1472 return snd_rme96_playback_ptr(rme96);
1442 } 1473 }
1443 1474
1444 static snd_pcm_uframes_t 1475 static snd_pcm_uframes_t
1445 snd_rme96_capture_pointer(struct snd_pcm_subs !! 1476 snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1446 { 1477 {
1447 struct rme96 *rme96 = snd_pcm_substre !! 1478 rme96_t *rme96 = snd_pcm_substream_chip(substream);
1448 return snd_rme96_capture_ptr(rme96); 1479 return snd_rme96_capture_ptr(rme96);
1449 } 1480 }
1450 1481
1451 static struct snd_pcm_ops snd_rme96_playback_ !! 1482 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1452 .open = snd_rme96_playback_sp 1483 .open = snd_rme96_playback_spdif_open,
1453 .close = snd_rme96_playback_cl 1484 .close = snd_rme96_playback_close,
1454 .ioctl = snd_pcm_lib_ioctl, 1485 .ioctl = snd_pcm_lib_ioctl,
1455 .hw_params = snd_rme96_playback_hw 1486 .hw_params = snd_rme96_playback_hw_params,
1456 .prepare = snd_rme96_playback_pr 1487 .prepare = snd_rme96_playback_prepare,
1457 .trigger = snd_rme96_playback_tr 1488 .trigger = snd_rme96_playback_trigger,
1458 .pointer = snd_rme96_playback_po 1489 .pointer = snd_rme96_playback_pointer,
1459 .copy = snd_rme96_playback_co 1490 .copy = snd_rme96_playback_copy,
1460 .silence = snd_rme96_playback_si 1491 .silence = snd_rme96_playback_silence,
1461 .mmap = snd_pcm_lib_mmap_iome 1492 .mmap = snd_pcm_lib_mmap_iomem,
1462 }; 1493 };
1463 1494
1464 static struct snd_pcm_ops snd_rme96_capture_s !! 1495 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1465 .open = snd_rme96_capture_spd 1496 .open = snd_rme96_capture_spdif_open,
1466 .close = snd_rme96_capture_clo 1497 .close = snd_rme96_capture_close,
1467 .ioctl = snd_pcm_lib_ioctl, 1498 .ioctl = snd_pcm_lib_ioctl,
1468 .hw_params = snd_rme96_capture_hw_ 1499 .hw_params = snd_rme96_capture_hw_params,
1469 .prepare = snd_rme96_capture_pre 1500 .prepare = snd_rme96_capture_prepare,
1470 .trigger = snd_rme96_capture_tri 1501 .trigger = snd_rme96_capture_trigger,
1471 .pointer = snd_rme96_capture_poi 1502 .pointer = snd_rme96_capture_pointer,
1472 .copy = snd_rme96_capture_cop 1503 .copy = snd_rme96_capture_copy,
1473 .mmap = snd_pcm_lib_mmap_iome 1504 .mmap = snd_pcm_lib_mmap_iomem,
1474 }; 1505 };
1475 1506
1476 static struct snd_pcm_ops snd_rme96_playback_ !! 1507 static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1477 .open = snd_rme96_playback_ad 1508 .open = snd_rme96_playback_adat_open,
1478 .close = snd_rme96_playback_cl 1509 .close = snd_rme96_playback_close,
1479 .ioctl = snd_pcm_lib_ioctl, 1510 .ioctl = snd_pcm_lib_ioctl,
1480 .hw_params = snd_rme96_playback_hw 1511 .hw_params = snd_rme96_playback_hw_params,
1481 .prepare = snd_rme96_playback_pr 1512 .prepare = snd_rme96_playback_prepare,
1482 .trigger = snd_rme96_playback_tr 1513 .trigger = snd_rme96_playback_trigger,
1483 .pointer = snd_rme96_playback_po 1514 .pointer = snd_rme96_playback_pointer,
1484 .copy = snd_rme96_playback_co 1515 .copy = snd_rme96_playback_copy,
1485 .silence = snd_rme96_playback_si 1516 .silence = snd_rme96_playback_silence,
1486 .mmap = snd_pcm_lib_mmap_iome 1517 .mmap = snd_pcm_lib_mmap_iomem,
1487 }; 1518 };
1488 1519
1489 static struct snd_pcm_ops snd_rme96_capture_a !! 1520 static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1490 .open = snd_rme96_capture_ada 1521 .open = snd_rme96_capture_adat_open,
1491 .close = snd_rme96_capture_clo 1522 .close = snd_rme96_capture_close,
1492 .ioctl = snd_pcm_lib_ioctl, 1523 .ioctl = snd_pcm_lib_ioctl,
1493 .hw_params = snd_rme96_capture_hw_ 1524 .hw_params = snd_rme96_capture_hw_params,
1494 .prepare = snd_rme96_capture_pre 1525 .prepare = snd_rme96_capture_prepare,
1495 .trigger = snd_rme96_capture_tri 1526 .trigger = snd_rme96_capture_trigger,
1496 .pointer = snd_rme96_capture_poi 1527 .pointer = snd_rme96_capture_pointer,
1497 .copy = snd_rme96_capture_cop 1528 .copy = snd_rme96_capture_copy,
1498 .mmap = snd_pcm_lib_mmap_iome 1529 .mmap = snd_pcm_lib_mmap_iomem,
1499 }; 1530 };
1500 1531
1501 static void 1532 static void
1502 snd_rme96_free(void *private_data) 1533 snd_rme96_free(void *private_data)
1503 { 1534 {
1504 struct rme96 *rme96 = (struct rme96 * !! 1535 rme96_t *rme96 = (rme96_t *)private_data;
1505 1536
1506 if (rme96 == NULL) { 1537 if (rme96 == NULL) {
1507 return; 1538 return;
1508 } 1539 }
1509 if (rme96->irq >= 0) { 1540 if (rme96->irq >= 0) {
1510 snd_rme96_playback_stop(rme96 1541 snd_rme96_playback_stop(rme96);
1511 snd_rme96_capture_stop(rme96) 1542 snd_rme96_capture_stop(rme96);
1512 rme96->areg &= ~RME96_AR_DAC_ 1543 rme96->areg &= ~RME96_AR_DAC_EN;
1513 writel(rme96->areg, rme96->io 1544 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1514 free_irq(rme96->irq, (void *) 1545 free_irq(rme96->irq, (void *)rme96);
1515 rme96->irq = -1; 1546 rme96->irq = -1;
1516 } 1547 }
1517 if (rme96->iobase) { 1548 if (rme96->iobase) {
1518 iounmap(rme96->iobase); 1549 iounmap(rme96->iobase);
1519 rme96->iobase = NULL; 1550 rme96->iobase = NULL;
1520 } 1551 }
1521 if (rme96->port) { 1552 if (rme96->port) {
1522 pci_release_regions(rme96->pc 1553 pci_release_regions(rme96->pci);
1523 rme96->port = 0; 1554 rme96->port = 0;
1524 } 1555 }
1525 pci_disable_device(rme96->pci); 1556 pci_disable_device(rme96->pci);
1526 } 1557 }
1527 1558
1528 static void 1559 static void
1529 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) !! 1560 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1530 { 1561 {
1531 struct rme96 *rme96 = (struct rme96 * !! 1562 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1532 rme96->spdif_pcm = NULL; 1563 rme96->spdif_pcm = NULL;
1533 } 1564 }
1534 1565
1535 static void 1566 static void
1536 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) !! 1567 snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1537 { 1568 {
1538 struct rme96 *rme96 = (struct rme96 * !! 1569 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1539 rme96->adat_pcm = NULL; 1570 rme96->adat_pcm = NULL;
1540 } 1571 }
1541 1572
1542 static int __devinit 1573 static int __devinit
1543 snd_rme96_create(struct rme96 *rme96) !! 1574 snd_rme96_create(rme96_t *rme96)
1544 { 1575 {
1545 struct pci_dev *pci = rme96->pci; 1576 struct pci_dev *pci = rme96->pci;
1546 int err; 1577 int err;
1547 1578
1548 rme96->irq = -1; 1579 rme96->irq = -1;
1549 spin_lock_init(&rme96->lock); 1580 spin_lock_init(&rme96->lock);
1550 1581
1551 if ((err = pci_enable_device(pci)) < 1582 if ((err = pci_enable_device(pci)) < 0)
1552 return err; 1583 return err;
1553 1584
1554 if ((err = pci_request_regions(pci, " 1585 if ((err = pci_request_regions(pci, "RME96")) < 0)
1555 return err; 1586 return err;
1556 rme96->port = pci_resource_start(rme9 1587 rme96->port = pci_resource_start(rme96->pci, 0);
1557 1588
1558 rme96->iobase = ioremap_nocache(rme96 !! 1589 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1559 if (!rme96->iobase) { !! 1590 snd_printk("unable to grab IRQ %d\n", pci->irq);
1560 snd_printk(KERN_ERR "unable t <<
1561 return -ENOMEM; <<
1562 } <<
1563 <<
1564 if (request_irq(pci->irq, snd_rme96_i <<
1565 "RME96", rme96)) { <<
1566 snd_printk(KERN_ERR "unable t <<
1567 return -EBUSY; 1591 return -EBUSY;
1568 } 1592 }
1569 rme96->irq = pci->irq; 1593 rme96->irq = pci->irq;
1570 1594
>> 1595 if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
>> 1596 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
>> 1597 return -ENOMEM;
>> 1598 }
>> 1599
1571 /* read the card's revision number */ 1600 /* read the card's revision number */
1572 pci_read_config_byte(pci, 8, &rme96-> 1601 pci_read_config_byte(pci, 8, &rme96->rev);
1573 1602
1574 /* set up ALSA pcm device for S/PDIF 1603 /* set up ALSA pcm device for S/PDIF */
1575 if ((err = snd_pcm_new(rme96->card, " 1604 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1576 1, 1, &rme96-> 1605 1, 1, &rme96->spdif_pcm)) < 0)
1577 { 1606 {
1578 return err; 1607 return err;
1579 } 1608 }
1580 rme96->spdif_pcm->private_data = rme9 1609 rme96->spdif_pcm->private_data = rme96;
1581 rme96->spdif_pcm->private_free = snd_ 1610 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1582 strcpy(rme96->spdif_pcm->name, "Digi9 1611 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1583 snd_pcm_set_ops(rme96->spdif_pcm, SND 1612 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1584 snd_pcm_set_ops(rme96->spdif_pcm, SND 1613 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1585 1614
1586 rme96->spdif_pcm->info_flags = 0; 1615 rme96->spdif_pcm->info_flags = 0;
1587 1616
1588 /* set up ALSA pcm device for ADAT */ 1617 /* set up ALSA pcm device for ADAT */
1589 if (pci->device == PCI_DEVICE_ID_RME_ !! 1618 if (pci->device == PCI_DEVICE_ID_DIGI96) {
1590 /* ADAT is not available on t 1619 /* ADAT is not available on the base model */
1591 rme96->adat_pcm = NULL; 1620 rme96->adat_pcm = NULL;
1592 } else { 1621 } else {
1593 if ((err = snd_pcm_new(rme96- 1622 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1594 1, 1, 1623 1, 1, &rme96->adat_pcm)) < 0)
1595 { 1624 {
1596 return err; 1625 return err;
1597 } 1626 }
1598 rme96->adat_pcm->private_data 1627 rme96->adat_pcm->private_data = rme96;
1599 rme96->adat_pcm->private_free 1628 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1600 strcpy(rme96->adat_pcm->name, 1629 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1601 snd_pcm_set_ops(rme96->adat_p 1630 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1602 snd_pcm_set_ops(rme96->adat_p 1631 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1603 1632
1604 rme96->adat_pcm->info_flags = 1633 rme96->adat_pcm->info_flags = 0;
1605 } 1634 }
1606 1635
1607 rme96->playback_periodsize = 0; 1636 rme96->playback_periodsize = 0;
1608 rme96->capture_periodsize = 0; 1637 rme96->capture_periodsize = 0;
1609 1638
1610 /* make sure playback/capture is stop 1639 /* make sure playback/capture is stopped, if by some reason active */
1611 snd_rme96_playback_stop(rme96); 1640 snd_rme96_playback_stop(rme96);
1612 snd_rme96_capture_stop(rme96); 1641 snd_rme96_capture_stop(rme96);
1613 1642
1614 /* set default values in registers */ 1643 /* set default values in registers */
1615 rme96->wcreg = 1644 rme96->wcreg =
1616 RME96_WCR_FREQ_1 | /* set 44. 1645 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1617 RME96_WCR_SEL | /* normal 1646 RME96_WCR_SEL | /* normal playback */
1618 RME96_WCR_MASTER | /* set to 1647 RME96_WCR_MASTER | /* set to master clock mode */
1619 RME96_WCR_INP_0; /* set coa 1648 RME96_WCR_INP_0; /* set coaxial input */
1620 1649
1621 rme96->areg = RME96_AR_FREQPAD_1; /* 1650 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1622 1651
1623 writel(rme96->wcreg, rme96->iobase + 1652 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1624 writel(rme96->areg, rme96->iobase + R 1653 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1625 1654
1626 /* reset the ADC */ 1655 /* reset the ADC */
1627 writel(rme96->areg | RME96_AR_PD2, 1656 writel(rme96->areg | RME96_AR_PD2,
1628 rme96->iobase + RME96_IO_ADDIT 1657 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1629 writel(rme96->areg, rme96->iobase + R 1658 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1630 1659
1631 /* reset and enable the DAC (order is 1660 /* reset and enable the DAC (order is important). */
1632 snd_rme96_reset_dac(rme96); 1661 snd_rme96_reset_dac(rme96);
1633 rme96->areg |= RME96_AR_DAC_EN; 1662 rme96->areg |= RME96_AR_DAC_EN;
1634 writel(rme96->areg, rme96->iobase + R 1663 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1635 1664
1636 /* reset playback and record buffer p 1665 /* reset playback and record buffer pointers */
1637 writel(0, rme96->iobase + RME96_IO_RE 1666 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1638 writel(0, rme96->iobase + RME96_IO_RE 1667 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1639 1668
1640 /* reset volume */ 1669 /* reset volume */
1641 rme96->vol[0] = rme96->vol[1] = 0; 1670 rme96->vol[0] = rme96->vol[1] = 0;
1642 if (RME96_HAS_ANALOG_OUT(rme96)) { 1671 if (RME96_HAS_ANALOG_OUT(rme96)) {
1643 snd_rme96_apply_dac_volume(rm 1672 snd_rme96_apply_dac_volume(rme96);
1644 } 1673 }
1645 1674
1646 /* init switch interface */ 1675 /* init switch interface */
1647 if ((err = snd_rme96_create_switches( 1676 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1648 return err; 1677 return err;
1649 } 1678 }
1650 1679
1651 /* init proc interface */ 1680 /* init proc interface */
1652 snd_rme96_proc_init(rme96); 1681 snd_rme96_proc_init(rme96);
1653 1682
1654 return 0; 1683 return 0;
1655 } 1684 }
1656 1685
1657 /* 1686 /*
1658 * proc interface 1687 * proc interface
1659 */ 1688 */
1660 1689
1661 static void 1690 static void
1662 snd_rme96_proc_read(struct snd_info_entry *en !! 1691 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1663 { 1692 {
1664 int n; 1693 int n;
1665 struct rme96 *rme96 = (struct rme96 * !! 1694 rme96_t *rme96 = (rme96_t *)entry->private_data;
1666 1695
1667 rme96->rcreg = readl(rme96->iobase + 1696 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1668 1697
1669 snd_iprintf(buffer, rme96->card->long 1698 snd_iprintf(buffer, rme96->card->longname);
1670 snd_iprintf(buffer, " (index #%d)\n", 1699 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1671 1700
1672 snd_iprintf(buffer, "\nGeneral settin 1701 snd_iprintf(buffer, "\nGeneral settings\n");
1673 if (rme96->wcreg & RME96_WCR_IDIS) { 1702 if (rme96->wcreg & RME96_WCR_IDIS) {
1674 snd_iprintf(buffer, " period 1703 snd_iprintf(buffer, " period size: N/A (interrupts "
1675 "disabled)\n"); 1704 "disabled)\n");
1676 } else if (rme96->wcreg & RME96_WCR_I 1705 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1677 snd_iprintf(buffer, " period 1706 snd_iprintf(buffer, " period size: 2048 bytes\n");
1678 } else { 1707 } else {
1679 snd_iprintf(buffer, " period 1708 snd_iprintf(buffer, " period size: 8192 bytes\n");
1680 } 1709 }
1681 snd_iprintf(buffer, "\nInput settings 1710 snd_iprintf(buffer, "\nInput settings\n");
1682 switch (snd_rme96_getinputtype(rme96) 1711 switch (snd_rme96_getinputtype(rme96)) {
1683 case RME96_INPUT_OPTICAL: 1712 case RME96_INPUT_OPTICAL:
1684 snd_iprintf(buffer, " input: 1713 snd_iprintf(buffer, " input: optical");
1685 break; 1714 break;
1686 case RME96_INPUT_COAXIAL: 1715 case RME96_INPUT_COAXIAL:
1687 snd_iprintf(buffer, " input: 1716 snd_iprintf(buffer, " input: coaxial");
1688 break; 1717 break;
1689 case RME96_INPUT_INTERNAL: 1718 case RME96_INPUT_INTERNAL:
1690 snd_iprintf(buffer, " input: 1719 snd_iprintf(buffer, " input: internal");
1691 break; 1720 break;
1692 case RME96_INPUT_XLR: 1721 case RME96_INPUT_XLR:
1693 snd_iprintf(buffer, " input: 1722 snd_iprintf(buffer, " input: XLR");
1694 break; 1723 break;
1695 case RME96_INPUT_ANALOG: 1724 case RME96_INPUT_ANALOG:
1696 snd_iprintf(buffer, " input: 1725 snd_iprintf(buffer, " input: analog");
1697 break; 1726 break;
1698 } 1727 }
1699 if (snd_rme96_capture_getrate(rme96, 1728 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1700 snd_iprintf(buffer, "\n samp 1729 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1701 } else { 1730 } else {
1702 if (n) { 1731 if (n) {
1703 snd_iprintf(buffer, " 1732 snd_iprintf(buffer, " (8 channels)\n");
1704 } else { 1733 } else {
1705 snd_iprintf(buffer, " 1734 snd_iprintf(buffer, " (2 channels)\n");
1706 } 1735 }
1707 snd_iprintf(buffer, " sample 1736 snd_iprintf(buffer, " sample rate: %d Hz\n",
1708 snd_rme96_capture 1737 snd_rme96_capture_getrate(rme96, &n));
1709 } 1738 }
1710 if (rme96->wcreg & RME96_WCR_MODE24_2 1739 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1711 snd_iprintf(buffer, " sample 1740 snd_iprintf(buffer, " sample format: 24 bit\n");
1712 } else { 1741 } else {
1713 snd_iprintf(buffer, " sample 1742 snd_iprintf(buffer, " sample format: 16 bit\n");
1714 } 1743 }
1715 1744
1716 snd_iprintf(buffer, "\nOutput setting 1745 snd_iprintf(buffer, "\nOutput settings\n");
1717 if (rme96->wcreg & RME96_WCR_SEL) { 1746 if (rme96->wcreg & RME96_WCR_SEL) {
1718 snd_iprintf(buffer, " output 1747 snd_iprintf(buffer, " output signal: normal playback\n");
1719 } else { 1748 } else {
1720 snd_iprintf(buffer, " output 1749 snd_iprintf(buffer, " output signal: same as input\n");
1721 } 1750 }
1722 snd_iprintf(buffer, " sample rate: % 1751 snd_iprintf(buffer, " sample rate: %d Hz\n",
1723 snd_rme96_playback_getrat 1752 snd_rme96_playback_getrate(rme96));
1724 if (rme96->wcreg & RME96_WCR_MODE24) 1753 if (rme96->wcreg & RME96_WCR_MODE24) {
1725 snd_iprintf(buffer, " sample 1754 snd_iprintf(buffer, " sample format: 24 bit\n");
1726 } else { 1755 } else {
1727 snd_iprintf(buffer, " sample 1756 snd_iprintf(buffer, " sample format: 16 bit\n");
1728 } 1757 }
1729 if (rme96->areg & RME96_AR_WSEL) { 1758 if (rme96->areg & RME96_AR_WSEL) {
1730 snd_iprintf(buffer, " sample 1759 snd_iprintf(buffer, " sample clock source: word clock\n");
1731 } else if (rme96->wcreg & RME96_WCR_M 1760 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1732 snd_iprintf(buffer, " sample 1761 snd_iprintf(buffer, " sample clock source: internal\n");
1733 } else if (snd_rme96_getinputtype(rme 1762 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1734 snd_iprintf(buffer, " sample 1763 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1735 } else if (snd_rme96_capture_getrate( 1764 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1736 snd_iprintf(buffer, " sample 1765 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1737 } else { 1766 } else {
1738 snd_iprintf(buffer, " sample 1767 snd_iprintf(buffer, " sample clock source: autosync\n");
1739 } 1768 }
1740 if (rme96->wcreg & RME96_WCR_PRO) { 1769 if (rme96->wcreg & RME96_WCR_PRO) {
1741 snd_iprintf(buffer, " format 1770 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1742 } else { 1771 } else {
1743 snd_iprintf(buffer, " format 1772 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1744 } 1773 }
1745 if (rme96->wcreg & RME96_WCR_EMP) { 1774 if (rme96->wcreg & RME96_WCR_EMP) {
1746 snd_iprintf(buffer, " emphas 1775 snd_iprintf(buffer, " emphasis: on\n");
1747 } else { 1776 } else {
1748 snd_iprintf(buffer, " emphas 1777 snd_iprintf(buffer, " emphasis: off\n");
1749 } 1778 }
1750 if (rme96->wcreg & RME96_WCR_DOLBY) { 1779 if (rme96->wcreg & RME96_WCR_DOLBY) {
1751 snd_iprintf(buffer, " non-au 1780 snd_iprintf(buffer, " non-audio (dolby): on\n");
1752 } else { 1781 } else {
1753 snd_iprintf(buffer, " non-au 1782 snd_iprintf(buffer, " non-audio (dolby): off\n");
1754 } 1783 }
1755 if (RME96_HAS_ANALOG_IN(rme96)) { 1784 if (RME96_HAS_ANALOG_IN(rme96)) {
1756 snd_iprintf(buffer, "\nAnalog 1785 snd_iprintf(buffer, "\nAnalog output settings\n");
1757 switch (snd_rme96_getmontrack 1786 switch (snd_rme96_getmontracks(rme96)) {
1758 case RME96_MONITOR_TRACKS_1_2 1787 case RME96_MONITOR_TRACKS_1_2:
1759 snd_iprintf(buffer, " 1788 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1760 break; 1789 break;
1761 case RME96_MONITOR_TRACKS_3_4 1790 case RME96_MONITOR_TRACKS_3_4:
1762 snd_iprintf(buffer, " 1791 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1763 break; 1792 break;
1764 case RME96_MONITOR_TRACKS_5_6 1793 case RME96_MONITOR_TRACKS_5_6:
1765 snd_iprintf(buffer, " 1794 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1766 break; 1795 break;
1767 case RME96_MONITOR_TRACKS_7_8 1796 case RME96_MONITOR_TRACKS_7_8:
1768 snd_iprintf(buffer, " 1797 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1769 break; 1798 break;
1770 } 1799 }
1771 switch (snd_rme96_getattenuat 1800 switch (snd_rme96_getattenuation(rme96)) {
1772 case RME96_ATTENUATION_0: 1801 case RME96_ATTENUATION_0:
1773 snd_iprintf(buffer, " 1802 snd_iprintf(buffer, " attenuation: 0 dB\n");
1774 break; 1803 break;
1775 case RME96_ATTENUATION_6: 1804 case RME96_ATTENUATION_6:
1776 snd_iprintf(buffer, " 1805 snd_iprintf(buffer, " attenuation: -6 dB\n");
1777 break; 1806 break;
1778 case RME96_ATTENUATION_12: 1807 case RME96_ATTENUATION_12:
1779 snd_iprintf(buffer, " 1808 snd_iprintf(buffer, " attenuation: -12 dB\n");
1780 break; 1809 break;
1781 case RME96_ATTENUATION_18: 1810 case RME96_ATTENUATION_18:
1782 snd_iprintf(buffer, " 1811 snd_iprintf(buffer, " attenuation: -18 dB\n");
1783 break; 1812 break;
1784 } 1813 }
1785 snd_iprintf(buffer, " volume 1814 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1786 snd_iprintf(buffer, " volume 1815 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1787 } 1816 }
1788 } 1817 }
1789 1818
1790 static void __devinit 1819 static void __devinit
1791 snd_rme96_proc_init(struct rme96 *rme96) !! 1820 snd_rme96_proc_init(rme96_t *rme96)
1792 { 1821 {
1793 struct snd_info_entry *entry; !! 1822 snd_info_entry_t *entry;
1794 1823
1795 if (! snd_card_proc_new(rme96->card, 1824 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1796 snd_info_set_text_ops(entry, !! 1825 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1797 } 1826 }
1798 1827
1799 /* 1828 /*
1800 * control interface 1829 * control interface
1801 */ 1830 */
1802 1831
1803 #define snd_rme96_info_loopback_control <<
1804 <<
1805 static int 1832 static int
1806 snd_rme96_get_loopback_control(struct snd_kco !! 1833 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
>> 1834 {
>> 1835 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
>> 1836 uinfo->count = 1;
>> 1837 uinfo->value.integer.min = 0;
>> 1838 uinfo->value.integer.max = 1;
>> 1839 return 0;
>> 1840 }
>> 1841 static int
>> 1842 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1807 { 1843 {
1808 struct rme96 *rme96 = snd_kcontrol_ch !! 1844 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1809 1845
1810 spin_lock_irq(&rme96->lock); 1846 spin_lock_irq(&rme96->lock);
1811 ucontrol->value.integer.value[0] = rm 1847 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1812 spin_unlock_irq(&rme96->lock); 1848 spin_unlock_irq(&rme96->lock);
1813 return 0; 1849 return 0;
1814 } 1850 }
1815 static int 1851 static int
1816 snd_rme96_put_loopback_control(struct snd_kco !! 1852 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1817 { 1853 {
1818 struct rme96 *rme96 = snd_kcontrol_ch !! 1854 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1819 unsigned int val; 1855 unsigned int val;
1820 int change; 1856 int change;
1821 1857
1822 val = ucontrol->value.integer.value[0 1858 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1823 spin_lock_irq(&rme96->lock); 1859 spin_lock_irq(&rme96->lock);
1824 val = (rme96->wcreg & ~RME96_WCR_SEL) 1860 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1825 change = val != rme96->wcreg; 1861 change = val != rme96->wcreg;
1826 rme96->wcreg = val; 1862 rme96->wcreg = val;
1827 writel(val, rme96->iobase + RME96_IO_ 1863 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1828 spin_unlock_irq(&rme96->lock); 1864 spin_unlock_irq(&rme96->lock);
1829 return change; 1865 return change;
1830 } 1866 }
1831 1867
1832 static int 1868 static int
1833 snd_rme96_info_inputtype_control(struct snd_k !! 1869 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1834 { 1870 {
1835 static char *_texts[5] = { "Optical", 1871 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1836 struct rme96 *rme96 = snd_kcontrol_ch !! 1872 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1837 char *texts[5] = { _texts[0], _texts[ 1873 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1838 1874
1839 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENU 1875 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1840 uinfo->count = 1; 1876 uinfo->count = 1;
1841 switch (rme96->pci->device) { 1877 switch (rme96->pci->device) {
1842 case PCI_DEVICE_ID_RME_DIGI96: !! 1878 case PCI_DEVICE_ID_DIGI96:
1843 case PCI_DEVICE_ID_RME_DIGI96_8: !! 1879 case PCI_DEVICE_ID_DIGI96_8:
1844 uinfo->value.enumerated.items 1880 uinfo->value.enumerated.items = 3;
1845 break; 1881 break;
1846 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: !! 1882 case PCI_DEVICE_ID_DIGI96_8_PRO:
1847 uinfo->value.enumerated.items 1883 uinfo->value.enumerated.items = 4;
1848 break; 1884 break;
1849 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_O !! 1885 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1850 if (rme96->rev > 4) { 1886 if (rme96->rev > 4) {
1851 /* PST */ 1887 /* PST */
1852 uinfo->value.enumerat 1888 uinfo->value.enumerated.items = 4;
1853 texts[3] = _texts[4]; 1889 texts[3] = _texts[4]; /* Analog instead of XLR */
1854 } else { 1890 } else {
1855 /* PAD */ 1891 /* PAD */
1856 uinfo->value.enumerat 1892 uinfo->value.enumerated.items = 5;
1857 } 1893 }
1858 break; 1894 break;
1859 default: 1895 default:
1860 snd_BUG(); 1896 snd_BUG();
1861 break; 1897 break;
1862 } 1898 }
1863 if (uinfo->value.enumerated.item > ui 1899 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1864 uinfo->value.enumerated.item 1900 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1865 } 1901 }
1866 strcpy(uinfo->value.enumerated.name, 1902 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1867 return 0; 1903 return 0;
1868 } 1904 }
1869 static int 1905 static int
1870 snd_rme96_get_inputtype_control(struct snd_kc !! 1906 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1871 { 1907 {
1872 struct rme96 *rme96 = snd_kcontrol_ch !! 1908 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1873 unsigned int items = 3; 1909 unsigned int items = 3;
1874 1910
1875 spin_lock_irq(&rme96->lock); 1911 spin_lock_irq(&rme96->lock);
1876 ucontrol->value.enumerated.item[0] = 1912 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1877 1913
1878 switch (rme96->pci->device) { 1914 switch (rme96->pci->device) {
1879 case PCI_DEVICE_ID_RME_DIGI96: !! 1915 case PCI_DEVICE_ID_DIGI96:
1880 case PCI_DEVICE_ID_RME_DIGI96_8: !! 1916 case PCI_DEVICE_ID_DIGI96_8:
1881 items = 3; 1917 items = 3;
1882 break; 1918 break;
1883 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: !! 1919 case PCI_DEVICE_ID_DIGI96_8_PRO:
1884 items = 4; 1920 items = 4;
1885 break; 1921 break;
1886 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_O !! 1922 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1887 if (rme96->rev > 4) { 1923 if (rme96->rev > 4) {
1888 /* for handling PST c 1924 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1889 if (ucontrol->value.e 1925 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1890 ucontrol->val 1926 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1891 } 1927 }
1892 items = 4; 1928 items = 4;
1893 } else { 1929 } else {
1894 items = 5; 1930 items = 5;
1895 } 1931 }
1896 break; 1932 break;
1897 default: 1933 default:
1898 snd_BUG(); 1934 snd_BUG();
1899 break; 1935 break;
1900 } 1936 }
1901 if (ucontrol->value.enumerated.item[0 1937 if (ucontrol->value.enumerated.item[0] >= items) {
1902 ucontrol->value.enumerated.it 1938 ucontrol->value.enumerated.item[0] = items - 1;
1903 } 1939 }
1904 1940
1905 spin_unlock_irq(&rme96->lock); 1941 spin_unlock_irq(&rme96->lock);
1906 return 0; 1942 return 0;
1907 } 1943 }
1908 static int 1944 static int
1909 snd_rme96_put_inputtype_control(struct snd_kc !! 1945 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1910 { 1946 {
1911 struct rme96 *rme96 = snd_kcontrol_ch !! 1947 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1912 unsigned int val; 1948 unsigned int val;
1913 int change, items = 3; 1949 int change, items = 3;
1914 1950
1915 switch (rme96->pci->device) { 1951 switch (rme96->pci->device) {
1916 case PCI_DEVICE_ID_RME_DIGI96: !! 1952 case PCI_DEVICE_ID_DIGI96:
1917 case PCI_DEVICE_ID_RME_DIGI96_8: !! 1953 case PCI_DEVICE_ID_DIGI96_8:
1918 items = 3; 1954 items = 3;
1919 break; 1955 break;
1920 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: !! 1956 case PCI_DEVICE_ID_DIGI96_8_PRO:
1921 items = 4; 1957 items = 4;
1922 break; 1958 break;
1923 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_O !! 1959 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1924 if (rme96->rev > 4) { 1960 if (rme96->rev > 4) {
1925 items = 4; 1961 items = 4;
1926 } else { 1962 } else {
1927 items = 5; 1963 items = 5;
1928 } 1964 }
1929 break; 1965 break;
1930 default: 1966 default:
1931 snd_BUG(); 1967 snd_BUG();
1932 break; 1968 break;
1933 } 1969 }
1934 val = ucontrol->value.enumerated.item 1970 val = ucontrol->value.enumerated.item[0] % items;
1935 1971
1936 /* special case for PST */ 1972 /* special case for PST */
1937 if (rme96->pci->device == PCI_DEVICE_ !! 1973 if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1938 if (val == RME96_INPUT_XLR) { 1974 if (val == RME96_INPUT_XLR) {
1939 val = RME96_INPUT_ANA 1975 val = RME96_INPUT_ANALOG;
1940 } 1976 }
1941 } 1977 }
1942 1978
1943 spin_lock_irq(&rme96->lock); 1979 spin_lock_irq(&rme96->lock);
1944 change = (int)val != snd_rme96_getinp 1980 change = (int)val != snd_rme96_getinputtype(rme96);
1945 snd_rme96_setinputtype(rme96, val); 1981 snd_rme96_setinputtype(rme96, val);
1946 spin_unlock_irq(&rme96->lock); 1982 spin_unlock_irq(&rme96->lock);
1947 return change; 1983 return change;
1948 } 1984 }
1949 1985
1950 static int 1986 static int
1951 snd_rme96_info_clockmode_control(struct snd_k !! 1987 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1952 { 1988 {
1953 static char *texts[3] = { "AutoSync", 1989 static char *texts[3] = { "AutoSync", "Internal", "Word" };
1954 1990
1955 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENU 1991 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1956 uinfo->count = 1; 1992 uinfo->count = 1;
1957 uinfo->value.enumerated.items = 3; 1993 uinfo->value.enumerated.items = 3;
1958 if (uinfo->value.enumerated.item > 2) 1994 if (uinfo->value.enumerated.item > 2) {
1959 uinfo->value.enumerated.item 1995 uinfo->value.enumerated.item = 2;
1960 } 1996 }
1961 strcpy(uinfo->value.enumerated.name, 1997 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1962 return 0; 1998 return 0;
1963 } 1999 }
1964 static int 2000 static int
1965 snd_rme96_get_clockmode_control(struct snd_kc !! 2001 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1966 { 2002 {
1967 struct rme96 *rme96 = snd_kcontrol_ch !! 2003 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1968 2004
1969 spin_lock_irq(&rme96->lock); 2005 spin_lock_irq(&rme96->lock);
1970 ucontrol->value.enumerated.item[0] = 2006 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1971 spin_unlock_irq(&rme96->lock); 2007 spin_unlock_irq(&rme96->lock);
1972 return 0; 2008 return 0;
1973 } 2009 }
1974 static int 2010 static int
1975 snd_rme96_put_clockmode_control(struct snd_kc !! 2011 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1976 { 2012 {
1977 struct rme96 *rme96 = snd_kcontrol_ch !! 2013 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1978 unsigned int val; 2014 unsigned int val;
1979 int change; 2015 int change;
1980 2016
1981 val = ucontrol->value.enumerated.item 2017 val = ucontrol->value.enumerated.item[0] % 3;
1982 spin_lock_irq(&rme96->lock); 2018 spin_lock_irq(&rme96->lock);
1983 change = (int)val != snd_rme96_getclo 2019 change = (int)val != snd_rme96_getclockmode(rme96);
1984 snd_rme96_setclockmode(rme96, val); 2020 snd_rme96_setclockmode(rme96, val);
1985 spin_unlock_irq(&rme96->lock); 2021 spin_unlock_irq(&rme96->lock);
1986 return change; 2022 return change;
1987 } 2023 }
1988 2024
1989 static int 2025 static int
1990 snd_rme96_info_attenuation_control(struct snd !! 2026 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1991 { 2027 {
1992 static char *texts[4] = { "0 dB", "-6 2028 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
1993 2029
1994 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENU 2030 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1995 uinfo->count = 1; 2031 uinfo->count = 1;
1996 uinfo->value.enumerated.items = 4; 2032 uinfo->value.enumerated.items = 4;
1997 if (uinfo->value.enumerated.item > 3) 2033 if (uinfo->value.enumerated.item > 3) {
1998 uinfo->value.enumerated.item 2034 uinfo->value.enumerated.item = 3;
1999 } 2035 }
2000 strcpy(uinfo->value.enumerated.name, 2036 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2001 return 0; 2037 return 0;
2002 } 2038 }
2003 static int 2039 static int
2004 snd_rme96_get_attenuation_control(struct snd_ !! 2040 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2005 { 2041 {
2006 struct rme96 *rme96 = snd_kcontrol_ch !! 2042 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2007 2043
2008 spin_lock_irq(&rme96->lock); 2044 spin_lock_irq(&rme96->lock);
2009 ucontrol->value.enumerated.item[0] = 2045 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2010 spin_unlock_irq(&rme96->lock); 2046 spin_unlock_irq(&rme96->lock);
2011 return 0; 2047 return 0;
2012 } 2048 }
2013 static int 2049 static int
2014 snd_rme96_put_attenuation_control(struct snd_ !! 2050 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2015 { 2051 {
2016 struct rme96 *rme96 = snd_kcontrol_ch !! 2052 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2017 unsigned int val; 2053 unsigned int val;
2018 int change; 2054 int change;
2019 2055
2020 val = ucontrol->value.enumerated.item 2056 val = ucontrol->value.enumerated.item[0] % 4;
2021 spin_lock_irq(&rme96->lock); 2057 spin_lock_irq(&rme96->lock);
2022 2058
2023 change = (int)val != snd_rme96_getatt 2059 change = (int)val != snd_rme96_getattenuation(rme96);
2024 snd_rme96_setattenuation(rme96, val); 2060 snd_rme96_setattenuation(rme96, val);
2025 spin_unlock_irq(&rme96->lock); 2061 spin_unlock_irq(&rme96->lock);
2026 return change; 2062 return change;
2027 } 2063 }
2028 2064
2029 static int 2065 static int
2030 snd_rme96_info_montracks_control(struct snd_k !! 2066 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2031 { 2067 {
2032 static char *texts[4] = { "1+2", "3+4 2068 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2033 2069
2034 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENU 2070 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2035 uinfo->count = 1; 2071 uinfo->count = 1;
2036 uinfo->value.enumerated.items = 4; 2072 uinfo->value.enumerated.items = 4;
2037 if (uinfo->value.enumerated.item > 3) 2073 if (uinfo->value.enumerated.item > 3) {
2038 uinfo->value.enumerated.item 2074 uinfo->value.enumerated.item = 3;
2039 } 2075 }
2040 strcpy(uinfo->value.enumerated.name, 2076 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2041 return 0; 2077 return 0;
2042 } 2078 }
2043 static int 2079 static int
2044 snd_rme96_get_montracks_control(struct snd_kc !! 2080 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2045 { 2081 {
2046 struct rme96 *rme96 = snd_kcontrol_ch !! 2082 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2047 2083
2048 spin_lock_irq(&rme96->lock); 2084 spin_lock_irq(&rme96->lock);
2049 ucontrol->value.enumerated.item[0] = 2085 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2050 spin_unlock_irq(&rme96->lock); 2086 spin_unlock_irq(&rme96->lock);
2051 return 0; 2087 return 0;
2052 } 2088 }
2053 static int 2089 static int
2054 snd_rme96_put_montracks_control(struct snd_kc !! 2090 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2055 { 2091 {
2056 struct rme96 *rme96 = snd_kcontrol_ch !! 2092 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2057 unsigned int val; 2093 unsigned int val;
2058 int change; 2094 int change;
2059 2095
2060 val = ucontrol->value.enumerated.item 2096 val = ucontrol->value.enumerated.item[0] % 4;
2061 spin_lock_irq(&rme96->lock); 2097 spin_lock_irq(&rme96->lock);
2062 change = (int)val != snd_rme96_getmon 2098 change = (int)val != snd_rme96_getmontracks(rme96);
2063 snd_rme96_setmontracks(rme96, val); 2099 snd_rme96_setmontracks(rme96, val);
2064 spin_unlock_irq(&rme96->lock); 2100 spin_unlock_irq(&rme96->lock);
2065 return change; 2101 return change;
2066 } 2102 }
2067 2103
2068 static u32 snd_rme96_convert_from_aes(struct !! 2104 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2069 { 2105 {
2070 u32 val = 0; 2106 u32 val = 0;
2071 val |= (aes->status[0] & IEC958_AES0_ 2107 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2072 val |= (aes->status[0] & IEC958_AES0_ 2108 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2073 if (val & RME96_WCR_PRO) 2109 if (val & RME96_WCR_PRO)
2074 val |= (aes->status[0] & IEC9 2110 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2075 else 2111 else
2076 val |= (aes->status[0] & IEC9 2112 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2077 return val; 2113 return val;
2078 } 2114 }
2079 2115
2080 static void snd_rme96_convert_to_aes(struct s !! 2116 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2081 { 2117 {
2082 aes->status[0] = ((val & RME96_WCR_PR 2118 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2083 ((val & RME96_WCR_DO 2119 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2084 if (val & RME96_WCR_PRO) 2120 if (val & RME96_WCR_PRO)
2085 aes->status[0] |= (val & RME9 2121 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2086 else 2122 else
2087 aes->status[0] |= (val & RME9 2123 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2088 } 2124 }
2089 2125
2090 static int snd_rme96_control_spdif_info(struc !! 2126 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2091 { 2127 {
2092 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC 2128 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2093 uinfo->count = 1; 2129 uinfo->count = 1;
2094 return 0; 2130 return 0;
2095 } 2131 }
2096 2132
2097 static int snd_rme96_control_spdif_get(struct !! 2133 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2098 { 2134 {
2099 struct rme96 *rme96 = snd_kcontrol_ch !! 2135 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2100 2136
2101 snd_rme96_convert_to_aes(&ucontrol->v 2137 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2102 return 0; 2138 return 0;
2103 } 2139 }
2104 2140
2105 static int snd_rme96_control_spdif_put(struct !! 2141 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2106 { 2142 {
2107 struct rme96 *rme96 = snd_kcontrol_ch !! 2143 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2108 int change; 2144 int change;
2109 u32 val; 2145 u32 val;
2110 2146
2111 val = snd_rme96_convert_from_aes(&uco 2147 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2112 spin_lock_irq(&rme96->lock); 2148 spin_lock_irq(&rme96->lock);
2113 change = val != rme96->wcreg_spdif; 2149 change = val != rme96->wcreg_spdif;
2114 rme96->wcreg_spdif = val; 2150 rme96->wcreg_spdif = val;
2115 spin_unlock_irq(&rme96->lock); 2151 spin_unlock_irq(&rme96->lock);
2116 return change; 2152 return change;
2117 } 2153 }
2118 2154
2119 static int snd_rme96_control_spdif_stream_inf !! 2155 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2120 { 2156 {
2121 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC 2157 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2122 uinfo->count = 1; 2158 uinfo->count = 1;
2123 return 0; 2159 return 0;
2124 } 2160 }
2125 2161
2126 static int snd_rme96_control_spdif_stream_get !! 2162 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2127 { 2163 {
2128 struct rme96 *rme96 = snd_kcontrol_ch !! 2164 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2129 2165
2130 snd_rme96_convert_to_aes(&ucontrol->v 2166 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2131 return 0; 2167 return 0;
2132 } 2168 }
2133 2169
2134 static int snd_rme96_control_spdif_stream_put !! 2170 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2135 { 2171 {
2136 struct rme96 *rme96 = snd_kcontrol_ch !! 2172 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2137 int change; 2173 int change;
2138 u32 val; 2174 u32 val;
2139 2175
2140 val = snd_rme96_convert_from_aes(&uco 2176 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2141 spin_lock_irq(&rme96->lock); 2177 spin_lock_irq(&rme96->lock);
2142 change = val != rme96->wcreg_spdif_st 2178 change = val != rme96->wcreg_spdif_stream;
2143 rme96->wcreg_spdif_stream = val; 2179 rme96->wcreg_spdif_stream = val;
2144 rme96->wcreg &= ~(RME96_WCR_PRO | RME 2180 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2145 rme96->wcreg |= val; 2181 rme96->wcreg |= val;
2146 writel(rme96->wcreg, rme96->iobase + 2182 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2147 spin_unlock_irq(&rme96->lock); 2183 spin_unlock_irq(&rme96->lock);
2148 return change; 2184 return change;
2149 } 2185 }
2150 2186
2151 static int snd_rme96_control_spdif_mask_info( !! 2187 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2152 { 2188 {
2153 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC 2189 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2154 uinfo->count = 1; 2190 uinfo->count = 1;
2155 return 0; 2191 return 0;
2156 } 2192 }
2157 2193
2158 static int snd_rme96_control_spdif_mask_get(s !! 2194 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2159 { 2195 {
2160 ucontrol->value.iec958.status[0] = kc 2196 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2161 return 0; 2197 return 0;
2162 } 2198 }
2163 2199
2164 static int 2200 static int
2165 snd_rme96_dac_volume_info(struct snd_kcontrol !! 2201 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2166 { 2202 {
2167 struct rme96 *rme96 = snd_kcontrol_ch !! 2203 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2168 2204
2169 uinfo->type = SNDRV_CTL_ELEM_TYPE_INT 2205 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2170 uinfo->count = 2; 2206 uinfo->count = 2;
2171 uinfo->value.integer.min = 0; 2207 uinfo->value.integer.min = 0;
2172 uinfo->value.integer.max = RME96_185X 2208 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2173 return 0; 2209 return 0;
2174 } 2210 }
2175 2211
2176 static int 2212 static int
2177 snd_rme96_dac_volume_get(struct snd_kcontrol !! 2213 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2178 { 2214 {
2179 struct rme96 *rme96 = snd_kcontrol_ch !! 2215 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2180 2216
2181 spin_lock_irq(&rme96->lock); 2217 spin_lock_irq(&rme96->lock);
2182 u->value.integer.value[0] = rme96->vo 2218 u->value.integer.value[0] = rme96->vol[0];
2183 u->value.integer.value[1] = rme96->vo 2219 u->value.integer.value[1] = rme96->vol[1];
2184 spin_unlock_irq(&rme96->lock); 2220 spin_unlock_irq(&rme96->lock);
2185 2221
2186 return 0; 2222 return 0;
2187 } 2223 }
2188 2224
2189 static int 2225 static int
2190 snd_rme96_dac_volume_put(struct snd_kcontrol !! 2226 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2191 { 2227 {
2192 struct rme96 *rme96 = snd_kcontrol_ch !! 2228 rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2193 int change = 0; 2229 int change = 0;
2194 unsigned int vol, maxvol; <<
2195 2230
2196 !! 2231 if (!RME96_HAS_ANALOG_OUT(rme96)) {
2197 if (!RME96_HAS_ANALOG_OUT(rme96)) <<
2198 return -EINVAL; 2232 return -EINVAL;
2199 maxvol = RME96_185X_MAX_OUT(rme96); <<
2200 spin_lock_irq(&rme96->lock); <<
2201 vol = u->value.integer.value[0]; <<
2202 if (vol != rme96->vol[0] && vol <= ma <<
2203 rme96->vol[0] = vol; <<
2204 change = 1; <<
2205 } <<
2206 vol = u->value.integer.value[1]; <<
2207 if (vol != rme96->vol[1] && vol <= ma <<
2208 rme96->vol[1] = vol; <<
2209 change = 1; <<
2210 } 2233 }
2211 if (change) !! 2234 spin_lock_irq(&rme96->lock);
>> 2235 if (u->value.integer.value[0] != rme96->vol[0]) {
>> 2236 rme96->vol[0] = u->value.integer.value[0];
>> 2237 change = 1;
>> 2238 }
>> 2239 if (u->value.integer.value[1] != rme96->vol[1]) {
>> 2240 rme96->vol[1] = u->value.integer.value[1];
>> 2241 change = 1;
>> 2242 }
>> 2243 if (change) {
2212 snd_rme96_apply_dac_volume(rm 2244 snd_rme96_apply_dac_volume(rme96);
>> 2245 }
2213 spin_unlock_irq(&rme96->lock); 2246 spin_unlock_irq(&rme96->lock);
2214 2247
2215 return change; 2248 return change;
2216 } 2249 }
2217 2250
2218 static struct snd_kcontrol_new snd_rme96_cont !! 2251 static snd_kcontrol_new_t snd_rme96_controls[] = {
2219 { 2252 {
2220 .iface = SNDRV_CTL_ELEM_IFACE_ 2253 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2221 .name = SNDRV_CTL_NAME_IEC958 2254 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2222 .info = snd_rme96_control_spd 2255 .info = snd_rme96_control_spdif_info,
2223 .get = snd_rme96_control_spd 2256 .get = snd_rme96_control_spdif_get,
2224 .put = snd_rme96_control_spd 2257 .put = snd_rme96_control_spdif_put
2225 }, 2258 },
2226 { 2259 {
2227 .access = SNDRV_CTL_ELEM_ACCESS 2260 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2228 .iface = SNDRV_CTL_ELEM_IFACE_ 2261 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2229 .name = SNDRV_CTL_NAME_IEC958 2262 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2230 .info = snd_rme96_control_spd 2263 .info = snd_rme96_control_spdif_stream_info,
2231 .get = snd_rme96_control_spd 2264 .get = snd_rme96_control_spdif_stream_get,
2232 .put = snd_rme96_control_spd 2265 .put = snd_rme96_control_spdif_stream_put
2233 }, 2266 },
2234 { 2267 {
2235 .access = SNDRV_CTL_ELEM_ACCESS 2268 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2236 .iface = SNDRV_CTL_ELEM_IFACE_ !! 2269 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2237 .name = SNDRV_CTL_NAME_IEC958 2270 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2238 .info = snd_rme96_control_spd 2271 .info = snd_rme96_control_spdif_mask_info,
2239 .get = snd_rme96_control_spd 2272 .get = snd_rme96_control_spdif_mask_get,
2240 .private_value = IEC958_AES0_NONAUDIO 2273 .private_value = IEC958_AES0_NONAUDIO |
2241 IEC958_AES0_PROFESSIO 2274 IEC958_AES0_PROFESSIONAL |
2242 IEC958_AES0_CON_EMPHA 2275 IEC958_AES0_CON_EMPHASIS
2243 }, 2276 },
2244 { 2277 {
2245 .access = SNDRV_CTL_ELEM_ACCESS 2278 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2246 .iface = SNDRV_CTL_ELEM_IFACE_ !! 2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2247 .name = SNDRV_CTL_NAME_IEC958 2280 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2248 .info = snd_rme96_control_spd 2281 .info = snd_rme96_control_spdif_mask_info,
2249 .get = snd_rme96_control_spd 2282 .get = snd_rme96_control_spdif_mask_get,
2250 .private_value = IEC958_AES0_NONAUDIO 2283 .private_value = IEC958_AES0_NONAUDIO |
2251 IEC958_AES0_PROFESSIO 2284 IEC958_AES0_PROFESSIONAL |
2252 IEC958_AES0_PRO_EMPHA 2285 IEC958_AES0_PRO_EMPHASIS
2253 }, 2286 },
2254 { 2287 {
2255 .iface = SNDRV_CTL_ELEM_IFACE_ 2288 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2256 .name = "Input Connector", 2289 .name = "Input Connector",
2257 .info = snd_rme96_info_inputt 2290 .info = snd_rme96_info_inputtype_control,
2258 .get = snd_rme96_get_inputty 2291 .get = snd_rme96_get_inputtype_control,
2259 .put = snd_rme96_put_inputty 2292 .put = snd_rme96_put_inputtype_control
2260 }, 2293 },
2261 { 2294 {
2262 .iface = SNDRV_CTL_ELEM_IFACE_ 2295 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2263 .name = "Loopback Input", 2296 .name = "Loopback Input",
2264 .info = snd_rme96_info_loopba 2297 .info = snd_rme96_info_loopback_control,
2265 .get = snd_rme96_get_loopbac 2298 .get = snd_rme96_get_loopback_control,
2266 .put = snd_rme96_put_loopbac 2299 .put = snd_rme96_put_loopback_control
2267 }, 2300 },
2268 { 2301 {
2269 .iface = SNDRV_CTL_ELEM_IFACE_ 2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2270 .name = "Sample Clock Source" 2303 .name = "Sample Clock Source",
2271 .info = snd_rme96_info_clockm 2304 .info = snd_rme96_info_clockmode_control,
2272 .get = snd_rme96_get_clockmo 2305 .get = snd_rme96_get_clockmode_control,
2273 .put = snd_rme96_put_clockmo 2306 .put = snd_rme96_put_clockmode_control
2274 }, 2307 },
2275 { 2308 {
2276 .iface = SNDRV_CTL_ELEM_IFACE_ 2309 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2277 .name = "Monitor Tracks", 2310 .name = "Monitor Tracks",
2278 .info = snd_rme96_info_montra 2311 .info = snd_rme96_info_montracks_control,
2279 .get = snd_rme96_get_montrac 2312 .get = snd_rme96_get_montracks_control,
2280 .put = snd_rme96_put_montrac 2313 .put = snd_rme96_put_montracks_control
2281 }, 2314 },
2282 { 2315 {
2283 .iface = SNDRV_CTL_ELEM_IFACE_ 2316 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2284 .name = "Attenuation", 2317 .name = "Attenuation",
2285 .info = snd_rme96_info_attenu 2318 .info = snd_rme96_info_attenuation_control,
2286 .get = snd_rme96_get_attenua 2319 .get = snd_rme96_get_attenuation_control,
2287 .put = snd_rme96_put_attenua 2320 .put = snd_rme96_put_attenuation_control
2288 }, 2321 },
2289 { 2322 {
2290 .iface = SNDRV_CTL_ELEM_IFACE_ 2323 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2291 .name = "DAC Playback Volume" 2324 .name = "DAC Playback Volume",
2292 .info = snd_rme96_dac_volume_ 2325 .info = snd_rme96_dac_volume_info,
2293 .get = snd_rme96_dac_volume_ 2326 .get = snd_rme96_dac_volume_get,
2294 .put = snd_rme96_dac_volume_ 2327 .put = snd_rme96_dac_volume_put
2295 } 2328 }
2296 }; 2329 };
2297 2330
2298 static int 2331 static int
2299 snd_rme96_create_switches(struct snd_card *ca !! 2332 snd_rme96_create_switches(snd_card_t *card,
2300 struct rme96 *rme96 !! 2333 rme96_t *rme96)
2301 { 2334 {
2302 int idx, err; 2335 int idx, err;
2303 struct snd_kcontrol *kctl; !! 2336 snd_kcontrol_t *kctl;
2304 2337
2305 for (idx = 0; idx < 7; idx++) { 2338 for (idx = 0; idx < 7; idx++) {
2306 if ((err = snd_ctl_add(card, 2339 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2307 return err; 2340 return err;
2308 if (idx == 1) /* IEC958 (S/ 2341 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2309 rme96->spdif_ctl = kc 2342 rme96->spdif_ctl = kctl;
2310 } 2343 }
2311 2344
2312 if (RME96_HAS_ANALOG_OUT(rme96)) { 2345 if (RME96_HAS_ANALOG_OUT(rme96)) {
2313 for (idx = 7; idx < 10; idx++ 2346 for (idx = 7; idx < 10; idx++)
2314 if ((err = snd_ctl_ad 2347 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2315 return err; 2348 return err;
2316 } 2349 }
2317 2350
2318 return 0; 2351 return 0;
2319 } 2352 }
2320 2353
2321 /* 2354 /*
2322 * Card initialisation 2355 * Card initialisation
2323 */ 2356 */
2324 2357
2325 static void snd_rme96_card_free(struct snd_ca !! 2358 static void snd_rme96_card_free(snd_card_t *card)
2326 { 2359 {
2327 snd_rme96_free(card->private_data); 2360 snd_rme96_free(card->private_data);
2328 } 2361 }
2329 2362
2330 static int __devinit 2363 static int __devinit
2331 snd_rme96_probe(struct pci_dev *pci, 2364 snd_rme96_probe(struct pci_dev *pci,
2332 const struct pci_device_id *p 2365 const struct pci_device_id *pci_id)
2333 { 2366 {
2334 static int dev; 2367 static int dev;
2335 struct rme96 *rme96; !! 2368 rme96_t *rme96;
2336 struct snd_card *card; !! 2369 snd_card_t *card;
2337 int err; 2370 int err;
2338 u8 val; 2371 u8 val;
2339 2372
2340 if (dev >= SNDRV_CARDS) { 2373 if (dev >= SNDRV_CARDS) {
2341 return -ENODEV; 2374 return -ENODEV;
2342 } 2375 }
2343 if (!enable[dev]) { 2376 if (!enable[dev]) {
2344 dev++; 2377 dev++;
2345 return -ENOENT; 2378 return -ENOENT;
2346 } 2379 }
2347 err = snd_card_create(index[dev], id[ !! 2380 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2348 sizeof(struct r !! 2381 sizeof(rme96_t))) == NULL)
2349 if (err < 0) !! 2382 return -ENOMEM;
2350 return err; <<
2351 card->private_free = snd_rme96_card_f 2383 card->private_free = snd_rme96_card_free;
2352 rme96 = (struct rme96 *)card->private !! 2384 rme96 = (rme96_t *)card->private_data;
2353 rme96->card = card; 2385 rme96->card = card;
2354 rme96->pci = pci; 2386 rme96->pci = pci;
2355 snd_card_set_dev(card, &pci->dev); 2387 snd_card_set_dev(card, &pci->dev);
2356 if ((err = snd_rme96_create(rme96)) < 2388 if ((err = snd_rme96_create(rme96)) < 0) {
2357 snd_card_free(card); 2389 snd_card_free(card);
2358 return err; 2390 return err;
2359 } 2391 }
2360 2392
2361 strcpy(card->driver, "Digi96"); 2393 strcpy(card->driver, "Digi96");
2362 switch (rme96->pci->device) { 2394 switch (rme96->pci->device) {
2363 case PCI_DEVICE_ID_RME_DIGI96: !! 2395 case PCI_DEVICE_ID_DIGI96:
2364 strcpy(card->shortname, "RME 2396 strcpy(card->shortname, "RME Digi96");
2365 break; 2397 break;
2366 case PCI_DEVICE_ID_RME_DIGI96_8: !! 2398 case PCI_DEVICE_ID_DIGI96_8:
2367 strcpy(card->shortname, "RME 2399 strcpy(card->shortname, "RME Digi96/8");
2368 break; 2400 break;
2369 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: !! 2401 case PCI_DEVICE_ID_DIGI96_8_PRO:
2370 strcpy(card->shortname, "RME 2402 strcpy(card->shortname, "RME Digi96/8 PRO");
2371 break; 2403 break;
2372 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_O !! 2404 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2373 pci_read_config_byte(rme96->p 2405 pci_read_config_byte(rme96->pci, 8, &val);
2374 if (val < 5) { 2406 if (val < 5) {
2375 strcpy(card->shortnam 2407 strcpy(card->shortname, "RME Digi96/8 PAD");
2376 } else { 2408 } else {
2377 strcpy(card->shortnam 2409 strcpy(card->shortname, "RME Digi96/8 PST");
2378 } 2410 }
2379 break; 2411 break;
2380 } 2412 }
2381 sprintf(card->longname, "%s at 0x%lx, 2413 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2382 rme96->port, rme96->irq); 2414 rme96->port, rme96->irq);
2383 2415
2384 if ((err = snd_card_register(card)) < 2416 if ((err = snd_card_register(card)) < 0) {
2385 snd_card_free(card); 2417 snd_card_free(card);
2386 return err; 2418 return err;
2387 } 2419 }
2388 pci_set_drvdata(pci, card); 2420 pci_set_drvdata(pci, card);
2389 dev++; 2421 dev++;
2390 return 0; 2422 return 0;
2391 } 2423 }
2392 2424
2393 static void __devexit snd_rme96_remove(struct 2425 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2394 { 2426 {
2395 snd_card_free(pci_get_drvdata(pci)); 2427 snd_card_free(pci_get_drvdata(pci));
2396 pci_set_drvdata(pci, NULL); 2428 pci_set_drvdata(pci, NULL);
2397 } 2429 }
2398 2430
2399 static struct pci_driver driver = { 2431 static struct pci_driver driver = {
2400 .name = "RME Digi96", 2432 .name = "RME Digi96",
2401 .id_table = snd_rme96_ids, 2433 .id_table = snd_rme96_ids,
2402 .probe = snd_rme96_probe, 2434 .probe = snd_rme96_probe,
2403 .remove = __devexit_p(snd_rme96_remov 2435 .remove = __devexit_p(snd_rme96_remove),
2404 }; 2436 };
2405 2437
2406 static int __init alsa_card_rme96_init(void) 2438 static int __init alsa_card_rme96_init(void)
2407 { 2439 {
2408 return pci_register_driver(&driver); !! 2440 return pci_module_init(&driver);
2409 } 2441 }
2410 2442
2411 static void __exit alsa_card_rme96_exit(void) 2443 static void __exit alsa_card_rme96_exit(void)
2412 { 2444 {
2413 pci_unregister_driver(&driver); 2445 pci_unregister_driver(&driver);
2414 } 2446 }
2415 2447
2416 module_init(alsa_card_rme96_init) 2448 module_init(alsa_card_rme96_init)
2417 module_exit(alsa_card_rme96_exit) 2449 module_exit(alsa_card_rme96_exit)
2418 2450
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