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1 /* 1 /*
2 * ALSA driver for RME Digi32, Digi32/8 and 2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 * 3 *
4 * Copyright (c) 2002-2004 Martin Langer 4 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5 * Pilo Chambert 5 * Pilo Chambert <pilo.c@wanadoo.fr>
6 * 6 *
7 * Thanks to : Anders Torger <torg 7 * Thanks to : Anders Torger <torger@ludd.luth.se>,
8 * Henk Hesselink <hen 8 * Henk Hesselink <henk@anda.nl>
9 * for writing the dig 9 * for writing the digi96-driver
10 * and RME for all inf 10 * and RME for all informations.
11 * 11 *
12 * This program is free software; you can re 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Pub 13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either vers 14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version. 15 * (at your option) any later version.
16 * 16 *
17 * This program is distributed in the hope t 17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even th 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICUL 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more detai 20 * GNU General Public License for more details.
21 * 21 *
22 * You should have received a copy of the GN 22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to 23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * 25 *
26 * 26 *
27 * ******************************************* 27 * ****************************************************************************
28 * 28 *
29 * Note #1 "Sek'd models" .................... 29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
30 * 30 *
31 * Identical soundcards by Sek'd were labeled: 31 * Identical soundcards by Sek'd were labeled:
32 * RME Digi 32 = Sek'd Prodif 32 32 * RME Digi 32 = Sek'd Prodif 32
33 * RME Digi 32 Pro = Sek'd Prodif 96 33 * RME Digi 32 Pro = Sek'd Prodif 96
34 * RME Digi 32/8 = Sek'd Prodif Gold 34 * RME Digi 32/8 = Sek'd Prodif Gold
35 * 35 *
36 * ******************************************* 36 * ****************************************************************************
37 * 37 *
38 * Note #2 "full duplex mode" ................ 38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
39 * 39 *
40 * Full duplex doesn't work. All cards (32, 32 40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41 * in this mode. Rec data and play data are us 41 * in this mode. Rec data and play data are using the same buffer therefore. At
42 * first you have got the playing bits in the 42 * first you have got the playing bits in the buffer and then (after playing
43 * them) they were overwitten by the captured 43 * them) they were overwitten by the captured sound of the CS8412/14. Both
44 * modes (play/record) are running harmonicall 44 * modes (play/record) are running harmonically hand in hand in the same buffer
45 * and you have only one start bit plus one in 45 * and you have only one start bit plus one interrupt bit to control this
46 * paired action. 46 * paired action.
47 * This is opposite to the latter rme96 where 47 * This is opposite to the latter rme96 where playing and capturing is totally
48 * separated and so their full duplex mode is 48 * separated and so their full duplex mode is supported by alsa (using two
49 * start bits and two interrupts for two diffe 49 * start bits and two interrupts for two different buffers).
50 * But due to the wrong sequence of playing an 50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
51 * full duplex support for the rme32 at the mo 51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
52 * able to solve it. Are you motivated enough 52 * able to solve it. Are you motivated enough to solve this problem now? Your
53 * patch would be welcome! 53 * patch would be welcome!
54 * 54 *
55 * ******************************************* 55 * ****************************************************************************
56 * 56 *
57 * "The story after the long seeking" -- tiwai 57 * "The story after the long seeking" -- tiwai
58 * 58 *
59 * Ok, the situation regarding the full duplex 59 * Ok, the situation regarding the full duplex is now improved a bit.
60 * In the fullduplex mode (given by the module 60 * In the fullduplex mode (given by the module parameter), the hardware buffer
61 * is split to halves for read and write direc 61 * is split to halves for read and write directions at the DMA pointer.
62 * That is, the half above the current DMA poi 62 * That is, the half above the current DMA pointer is used for write, and
63 * the half below is used for read. To mangle 63 * the half below is used for read. To mangle this strange behavior, an
64 * software intermediate buffer is introduced. 64 * software intermediate buffer is introduced. This is, of course, not good
65 * from the viewpoint of the data transfer eff 65 * from the viewpoint of the data transfer efficiency. However, this allows
66 * you to use arbitrary buffer sizes, instead 66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67 * 67 *
68 * ******************************************* 68 * ****************************************************************************
69 */ 69 */
70 70
71 71
72 #include <linux/delay.h> 72 #include <linux/delay.h>
73 #include <linux/init.h> 73 #include <linux/init.h>
74 #include <linux/interrupt.h> 74 #include <linux/interrupt.h>
75 #include <linux/pci.h> 75 #include <linux/pci.h>
76 #include <linux/slab.h> 76 #include <linux/slab.h>
77 #include <linux/moduleparam.h> 77 #include <linux/moduleparam.h>
78 78
79 #include <sound/core.h> 79 #include <sound/core.h>
80 #include <sound/info.h> 80 #include <sound/info.h>
81 #include <sound/control.h> 81 #include <sound/control.h>
82 #include <sound/pcm.h> 82 #include <sound/pcm.h>
83 #include <sound/pcm_params.h> 83 #include <sound/pcm_params.h>
84 #include <sound/pcm-indirect.h> 84 #include <sound/pcm-indirect.h>
85 #include <sound/asoundef.h> 85 #include <sound/asoundef.h>
86 #include <sound/initval.h> 86 #include <sound/initval.h>
87 87
88 #include <asm/io.h> 88 #include <asm/io.h>
89 89
90 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_ 90 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
91 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_S 91 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
92 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT 92 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
93 static int fullduplex[SNDRV_CARDS]; // = {[0 . 93 static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
94 94
95 module_param_array(index, int, NULL, 0444); 95 module_param_array(index, int, NULL, 0444);
96 MODULE_PARM_DESC(index, "Index value for RME D 96 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
97 module_param_array(id, charp, NULL, 0444); 97 module_param_array(id, charp, NULL, 0444);
98 MODULE_PARM_DESC(id, "ID string for RME Digi32 98 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
99 module_param_array(enable, bool, NULL, 0444); 99 module_param_array(enable, bool, NULL, 0444);
100 MODULE_PARM_DESC(enable, "Enable RME Digi32 so 100 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
101 module_param_array(fullduplex, bool, NULL, 044 101 module_param_array(fullduplex, bool, NULL, 0444);
102 MODULE_PARM_DESC(fullduplex, "Support full-dup 102 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
103 MODULE_AUTHOR("Martin Langer <martin-langer@gm 103 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
104 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi 104 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
105 MODULE_LICENSE("GPL"); 105 MODULE_LICENSE("GPL");
106 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME 106 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
107 107
108 /* Defines for RME Digi32 series */ 108 /* Defines for RME Digi32 series */
109 #define RME32_SPDIF_NCHANNELS 2 109 #define RME32_SPDIF_NCHANNELS 2
110 110
111 /* Playback and capture buffer size */ 111 /* Playback and capture buffer size */
112 #define RME32_BUFFER_SIZE 0x20000 112 #define RME32_BUFFER_SIZE 0x20000
113 113
114 /* IO area size */ 114 /* IO area size */
115 #define RME32_IO_SIZE 0x30000 115 #define RME32_IO_SIZE 0x30000
116 116
117 /* IO area offsets */ 117 /* IO area offsets */
118 #define RME32_IO_DATA_BUFFER 0x0 118 #define RME32_IO_DATA_BUFFER 0x0
119 #define RME32_IO_CONTROL_REGISTER 0x20000 119 #define RME32_IO_CONTROL_REGISTER 0x20000
120 #define RME32_IO_GET_POS 0x20000 120 #define RME32_IO_GET_POS 0x20000
121 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 121 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
122 #define RME32_IO_RESET_POS 0x20100 122 #define RME32_IO_RESET_POS 0x20100
123 123
124 /* Write control register bits */ 124 /* Write control register bits */
125 #define RME32_WCR_START (1 << 0) /* sta 125 #define RME32_WCR_START (1 << 0) /* startbit */
126 #define RME32_WCR_MONO (1 << 1) /* 0=s 126 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
127 Set 127 Setting the whole card to mono
128 doe 128 doesn't seem to be very useful.
129 A s 129 A software-solution can handle
130 ful 130 full-duplex with one direction in
131 ste 131 stereo and the other way in mono.
132 So, 132 So, the hardware should work all
133 the 133 the time in stereo! */
134 #define RME32_WCR_MODE24 (1 << 2) /* 0=1 134 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
135 #define RME32_WCR_SEL (1 << 3) /* 0=i 135 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
136 #define RME32_WCR_FREQ_0 (1 << 4) /* fre 136 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
137 #define RME32_WCR_FREQ_1 (1 << 5) 137 #define RME32_WCR_FREQ_1 (1 << 5)
138 #define RME32_WCR_INP_0 (1 << 6) /* inp 138 #define RME32_WCR_INP_0 (1 << 6) /* input switch */
139 #define RME32_WCR_INP_1 (1 << 7) 139 #define RME32_WCR_INP_1 (1 << 7)
140 #define RME32_WCR_RESET (1 << 8) /* Res 140 #define RME32_WCR_RESET (1 << 8) /* Reset address */
141 #define RME32_WCR_MUTE (1 << 9) /* dig 141 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
142 #define RME32_WCR_PRO (1 << 10) /* 1=p 142 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
143 #define RME32_WCR_DS_BM (1 << 11) /* 1=D 143 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
144 #define RME32_WCR_ADAT (1 << 12) /* Ada 144 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
145 #define RME32_WCR_AUTOSYNC (1 << 13) /* Aut 145 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
146 #define RME32_WCR_PD (1 << 14) /* DAC 146 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
147 #define RME32_WCR_EMP (1 << 15) /* 1=E 147 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
148 148
149 #define RME32_WCR_BITPOS_FREQ_0 4 149 #define RME32_WCR_BITPOS_FREQ_0 4
150 #define RME32_WCR_BITPOS_FREQ_1 5 150 #define RME32_WCR_BITPOS_FREQ_1 5
151 #define RME32_WCR_BITPOS_INP_0 6 151 #define RME32_WCR_BITPOS_INP_0 6
152 #define RME32_WCR_BITPOS_INP_1 7 152 #define RME32_WCR_BITPOS_INP_1 7
153 153
154 /* Read control register bits */ 154 /* Read control register bits */
155 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff 155 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
156 #define RME32_RCR_LOCK (1 << 23) /* 1=l 156 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
157 #define RME32_RCR_ERF (1 << 26) /* 1=E 157 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
158 #define RME32_RCR_FREQ_0 (1 << 27) /* CS8 158 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
159 #define RME32_RCR_FREQ_1 (1 << 28) 159 #define RME32_RCR_FREQ_1 (1 << 28)
160 #define RME32_RCR_FREQ_2 (1 << 29) 160 #define RME32_RCR_FREQ_2 (1 << 29)
161 #define RME32_RCR_KMODE (1 << 30) /* car 161 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
162 #define RME32_RCR_IRQ (1 << 31) /* int 162 #define RME32_RCR_IRQ (1 << 31) /* interrupt */
163 163
164 #define RME32_RCR_BITPOS_F0 27 164 #define RME32_RCR_BITPOS_F0 27
165 #define RME32_RCR_BITPOS_F1 28 165 #define RME32_RCR_BITPOS_F1 28
166 #define RME32_RCR_BITPOS_F2 29 166 #define RME32_RCR_BITPOS_F2 29
167 167
168 /* Input types */ 168 /* Input types */
169 #define RME32_INPUT_OPTICAL 0 169 #define RME32_INPUT_OPTICAL 0
170 #define RME32_INPUT_COAXIAL 1 170 #define RME32_INPUT_COAXIAL 1
171 #define RME32_INPUT_INTERNAL 2 171 #define RME32_INPUT_INTERNAL 2
172 #define RME32_INPUT_XLR 3 172 #define RME32_INPUT_XLR 3
173 173
174 /* Clock modes */ 174 /* Clock modes */
175 #define RME32_CLOCKMODE_SLAVE 0 175 #define RME32_CLOCKMODE_SLAVE 0
176 #define RME32_CLOCKMODE_MASTER_32 1 176 #define RME32_CLOCKMODE_MASTER_32 1
177 #define RME32_CLOCKMODE_MASTER_44 2 177 #define RME32_CLOCKMODE_MASTER_44 2
178 #define RME32_CLOCKMODE_MASTER_48 3 178 #define RME32_CLOCKMODE_MASTER_48 3
179 179
180 /* Block sizes in bytes */ 180 /* Block sizes in bytes */
181 #define RME32_BLOCK_SIZE 8192 181 #define RME32_BLOCK_SIZE 8192
182 182
183 /* Software intermediate buffer (max) size */ 183 /* Software intermediate buffer (max) size */
184 #define RME32_MID_BUFFER_SIZE (1024*1024) 184 #define RME32_MID_BUFFER_SIZE (1024*1024)
185 185
186 /* Hardware revisions */ 186 /* Hardware revisions */
187 #define RME32_32_REVISION 192 187 #define RME32_32_REVISION 192
188 #define RME32_328_REVISION_OLD 100 188 #define RME32_328_REVISION_OLD 100
189 #define RME32_328_REVISION_NEW 101 189 #define RME32_328_REVISION_NEW 101
190 #define RME32_PRO_REVISION_WITH_8412 192 190 #define RME32_PRO_REVISION_WITH_8412 192
191 #define RME32_PRO_REVISION_WITH_8414 150 191 #define RME32_PRO_REVISION_WITH_8414 150
192 192
193 193
194 struct rme32 { 194 struct rme32 {
195 spinlock_t lock; 195 spinlock_t lock;
196 int irq; 196 int irq;
197 unsigned long port; 197 unsigned long port;
198 void __iomem *iobase; 198 void __iomem *iobase;
199 199
200 u32 wcreg; /* cached writ 200 u32 wcreg; /* cached write control register value */
201 u32 wcreg_spdif; /* S/PDIF setu 201 u32 wcreg_spdif; /* S/PDIF setup */
202 u32 wcreg_spdif_stream; /* S/PDIF setu 202 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
203 u32 rcreg; /* cached read 203 u32 rcreg; /* cached read control register value */
204 204
205 u8 rev; /* card revisi 205 u8 rev; /* card revision number */
206 206
207 struct snd_pcm_substream *playback_sub 207 struct snd_pcm_substream *playback_substream;
208 struct snd_pcm_substream *capture_subs 208 struct snd_pcm_substream *capture_substream;
209 209
210 int playback_frlog; /* log2 of fra 210 int playback_frlog; /* log2 of framesize */
211 int capture_frlog; 211 int capture_frlog;
212 212
213 size_t playback_periodsize; /* in 213 size_t playback_periodsize; /* in bytes, zero if not used */
214 size_t capture_periodsize; /* in 214 size_t capture_periodsize; /* in bytes, zero if not used */
215 215
216 unsigned int fullduplex_mode; 216 unsigned int fullduplex_mode;
217 int running; 217 int running;
218 218
219 struct snd_pcm_indirect playback_pcm; 219 struct snd_pcm_indirect playback_pcm;
220 struct snd_pcm_indirect capture_pcm; 220 struct snd_pcm_indirect capture_pcm;
221 221
222 struct snd_card *card; 222 struct snd_card *card;
223 struct snd_pcm *spdif_pcm; 223 struct snd_pcm *spdif_pcm;
224 struct snd_pcm *adat_pcm; 224 struct snd_pcm *adat_pcm;
225 struct pci_dev *pci; 225 struct pci_dev *pci;
226 struct snd_kcontrol *spdif_ctl; 226 struct snd_kcontrol *spdif_ctl;
227 }; 227 };
228 228
229 static struct pci_device_id snd_rme32_ids[] = 229 static struct pci_device_id snd_rme32_ids[] = {
230 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ !! 230 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, !! 231 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
232 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ !! 232 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, <<
234 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ <<
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, <<
236 {0,} 233 {0,}
237 }; 234 };
238 235
239 MODULE_DEVICE_TABLE(pci, snd_rme32_ids); 236 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
240 237
241 #define RME32_ISWORKING(rme32) ((rme32)->wcreg 238 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
242 #define RME32_PRO_WITH_8414(rme32) ((rme32)->p 239 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
243 240
244 static int snd_rme32_playback_prepare(struct s 241 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
245 242
246 static int snd_rme32_capture_prepare(struct sn 243 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
247 244
248 static int snd_rme32_pcm_trigger(struct snd_pc 245 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
249 246
250 static void snd_rme32_proc_init(struct rme32 * 247 static void snd_rme32_proc_init(struct rme32 * rme32);
251 248
252 static int snd_rme32_create_switches(struct sn 249 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
253 250
254 static inline unsigned int snd_rme32_pcm_bytep 251 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
255 { 252 {
256 return (readl(rme32->iobase + RME32_IO 253 return (readl(rme32->iobase + RME32_IO_GET_POS)
257 & RME32_RCR_AUDIO_ADDR_MASK); 254 & RME32_RCR_AUDIO_ADDR_MASK);
258 } 255 }
259 256
260 /* silence callback for halfduplex mode */ 257 /* silence callback for halfduplex mode */
261 static int snd_rme32_playback_silence(struct s 258 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
262 snd_pcm_ 259 snd_pcm_uframes_t pos,
263 snd_pcm_ 260 snd_pcm_uframes_t count)
264 { 261 {
265 struct rme32 *rme32 = snd_pcm_substrea 262 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
266 count <<= rme32->playback_frlog; 263 count <<= rme32->playback_frlog;
267 pos <<= rme32->playback_frlog; 264 pos <<= rme32->playback_frlog;
268 memset_io(rme32->iobase + RME32_IO_DAT 265 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
269 return 0; 266 return 0;
270 } 267 }
271 268
272 /* copy callback for halfduplex mode */ 269 /* copy callback for halfduplex mode */
273 static int snd_rme32_playback_copy(struct snd_ 270 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
274 snd_pcm_ufr 271 snd_pcm_uframes_t pos,
275 void __user 272 void __user *src, snd_pcm_uframes_t count)
276 { 273 {
277 struct rme32 *rme32 = snd_pcm_substrea 274 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
278 count <<= rme32->playback_frlog; 275 count <<= rme32->playback_frlog;
279 pos <<= rme32->playback_frlog; 276 pos <<= rme32->playback_frlog;
280 if (copy_from_user_toio(rme32->iobase 277 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
281 src, count)) 278 src, count))
282 return -EFAULT; 279 return -EFAULT;
283 return 0; 280 return 0;
284 } 281 }
285 282
286 /* copy callback for halfduplex mode */ 283 /* copy callback for halfduplex mode */
287 static int snd_rme32_capture_copy(struct snd_p 284 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
288 snd_pcm_ufra 285 snd_pcm_uframes_t pos,
289 void __user 286 void __user *dst, snd_pcm_uframes_t count)
290 { 287 {
291 struct rme32 *rme32 = snd_pcm_substrea 288 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
292 count <<= rme32->capture_frlog; 289 count <<= rme32->capture_frlog;
293 pos <<= rme32->capture_frlog; 290 pos <<= rme32->capture_frlog;
294 if (copy_to_user_fromio(dst, 291 if (copy_to_user_fromio(dst,
295 rme32->iobase + RM 292 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
296 count)) 293 count))
297 return -EFAULT; 294 return -EFAULT;
298 return 0; 295 return 0;
299 } 296 }
300 297
301 /* 298 /*
302 * SPDIF I/O capabilities (half-duplex mode) 299 * SPDIF I/O capabilities (half-duplex mode)
303 */ 300 */
304 static struct snd_pcm_hardware snd_rme32_spdif 301 static struct snd_pcm_hardware snd_rme32_spdif_info = {
305 .info = (SNDRV_PCM_INFO_MMAP_I 302 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
306 SNDRV_PCM_INFO_MMAP_V 303 SNDRV_PCM_INFO_MMAP_VALID |
307 SNDRV_PCM_INFO_INTERL 304 SNDRV_PCM_INFO_INTERLEAVED |
308 SNDRV_PCM_INFO_PAUSE 305 SNDRV_PCM_INFO_PAUSE |
309 SNDRV_PCM_INFO_SYNC_S 306 SNDRV_PCM_INFO_SYNC_START),
310 .formats = (SNDRV_PCM_FMTBIT_S16_ 307 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
311 SNDRV_PCM_FMTBIT_S32_ 308 SNDRV_PCM_FMTBIT_S32_LE),
312 .rates = (SNDRV_PCM_RATE_32000 309 .rates = (SNDRV_PCM_RATE_32000 |
313 SNDRV_PCM_RATE_44100 310 SNDRV_PCM_RATE_44100 |
314 SNDRV_PCM_RATE_48000) 311 SNDRV_PCM_RATE_48000),
315 .rate_min = 32000, 312 .rate_min = 32000,
316 .rate_max = 48000, 313 .rate_max = 48000,
317 .channels_min = 2, 314 .channels_min = 2,
318 .channels_max = 2, 315 .channels_max = 2,
319 .buffer_bytes_max = RME32_BUFFER_SIZE, 316 .buffer_bytes_max = RME32_BUFFER_SIZE,
320 .period_bytes_min = RME32_BLOCK_SIZE, 317 .period_bytes_min = RME32_BLOCK_SIZE,
321 .period_bytes_max = RME32_BLOCK_SIZE, 318 .period_bytes_max = RME32_BLOCK_SIZE,
322 .periods_min = RME32_BUFFER_SIZE / RM 319 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
323 .periods_max = RME32_BUFFER_SIZE / RM 320 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
324 .fifo_size = 0, 321 .fifo_size = 0,
325 }; 322 };
326 323
327 /* 324 /*
328 * ADAT I/O capabilities (half-duplex mode) 325 * ADAT I/O capabilities (half-duplex mode)
329 */ 326 */
330 static struct snd_pcm_hardware snd_rme32_adat_ 327 static struct snd_pcm_hardware snd_rme32_adat_info =
331 { 328 {
332 .info = (SNDRV_PCM_INFO_M 329 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
333 SNDRV_PCM_INFO_M 330 SNDRV_PCM_INFO_MMAP_VALID |
334 SNDRV_PCM_INFO_I 331 SNDRV_PCM_INFO_INTERLEAVED |
335 SNDRV_PCM_INFO_P 332 SNDRV_PCM_INFO_PAUSE |
336 SNDRV_PCM_INFO_S 333 SNDRV_PCM_INFO_SYNC_START),
337 .formats= SNDRV_PCM_FMTBIT_ 334 .formats= SNDRV_PCM_FMTBIT_S16_LE,
338 .rates = (SNDRV_PCM_RATE_4 335 .rates = (SNDRV_PCM_RATE_44100 |
339 SNDRV_PCM_RATE_4 336 SNDRV_PCM_RATE_48000),
340 .rate_min = 44100, 337 .rate_min = 44100,
341 .rate_max = 48000, 338 .rate_max = 48000,
342 .channels_min = 8, 339 .channels_min = 8,
343 .channels_max = 8, 340 .channels_max = 8,
344 .buffer_bytes_max = RME32_BUFFER_SIZE 341 .buffer_bytes_max = RME32_BUFFER_SIZE,
345 .period_bytes_min = RME32_BLOCK_SIZE, 342 .period_bytes_min = RME32_BLOCK_SIZE,
346 .period_bytes_max = RME32_BLOCK_SIZE, 343 .period_bytes_max = RME32_BLOCK_SIZE,
347 .periods_min = RME32_BUFFER_SIZE 344 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
348 .periods_max = RME32_BUFFER_SIZE 345 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
349 .fifo_size = 0, 346 .fifo_size = 0,
350 }; 347 };
351 348
352 /* 349 /*
353 * SPDIF I/O capabilities (full-duplex mode) 350 * SPDIF I/O capabilities (full-duplex mode)
354 */ 351 */
355 static struct snd_pcm_hardware snd_rme32_spdif 352 static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
356 .info = (SNDRV_PCM_INFO_MMAP | 353 .info = (SNDRV_PCM_INFO_MMAP |
357 SNDRV_PCM_INFO_MMAP_V 354 SNDRV_PCM_INFO_MMAP_VALID |
358 SNDRV_PCM_INFO_INTERL 355 SNDRV_PCM_INFO_INTERLEAVED |
359 SNDRV_PCM_INFO_PAUSE 356 SNDRV_PCM_INFO_PAUSE |
360 SNDRV_PCM_INFO_SYNC_S 357 SNDRV_PCM_INFO_SYNC_START),
361 .formats = (SNDRV_PCM_FMTBIT_S16_ 358 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
362 SNDRV_PCM_FMTBIT_S32_ 359 SNDRV_PCM_FMTBIT_S32_LE),
363 .rates = (SNDRV_PCM_RATE_32000 360 .rates = (SNDRV_PCM_RATE_32000 |
364 SNDRV_PCM_RATE_44100 361 SNDRV_PCM_RATE_44100 |
365 SNDRV_PCM_RATE_48000) 362 SNDRV_PCM_RATE_48000),
366 .rate_min = 32000, 363 .rate_min = 32000,
367 .rate_max = 48000, 364 .rate_max = 48000,
368 .channels_min = 2, 365 .channels_min = 2,
369 .channels_max = 2, 366 .channels_max = 2,
370 .buffer_bytes_max = RME32_MID_BUFFER_S 367 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
371 .period_bytes_min = RME32_BLOCK_SIZE, 368 .period_bytes_min = RME32_BLOCK_SIZE,
372 .period_bytes_max = RME32_BLOCK_SIZE, 369 .period_bytes_max = RME32_BLOCK_SIZE,
373 .periods_min = 2, 370 .periods_min = 2,
374 .periods_max = RME32_MID_BUFFER_SIZE 371 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
375 .fifo_size = 0, 372 .fifo_size = 0,
376 }; 373 };
377 374
378 /* 375 /*
379 * ADAT I/O capabilities (full-duplex mode) 376 * ADAT I/O capabilities (full-duplex mode)
380 */ 377 */
381 static struct snd_pcm_hardware snd_rme32_adat_ 378 static struct snd_pcm_hardware snd_rme32_adat_fd_info =
382 { 379 {
383 .info = (SNDRV_PCM_INFO_M 380 .info = (SNDRV_PCM_INFO_MMAP |
384 SNDRV_PCM_INFO_M 381 SNDRV_PCM_INFO_MMAP_VALID |
385 SNDRV_PCM_INFO_I 382 SNDRV_PCM_INFO_INTERLEAVED |
386 SNDRV_PCM_INFO_P 383 SNDRV_PCM_INFO_PAUSE |
387 SNDRV_PCM_INFO_S 384 SNDRV_PCM_INFO_SYNC_START),
388 .formats= SNDRV_PCM_FMTBIT_ 385 .formats= SNDRV_PCM_FMTBIT_S16_LE,
389 .rates = (SNDRV_PCM_RATE_4 386 .rates = (SNDRV_PCM_RATE_44100 |
390 SNDRV_PCM_RATE_4 387 SNDRV_PCM_RATE_48000),
391 .rate_min = 44100, 388 .rate_min = 44100,
392 .rate_max = 48000, 389 .rate_max = 48000,
393 .channels_min = 8, 390 .channels_min = 8,
394 .channels_max = 8, 391 .channels_max = 8,
395 .buffer_bytes_max = RME32_MID_BUFFER_ 392 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
396 .period_bytes_min = RME32_BLOCK_SIZE, 393 .period_bytes_min = RME32_BLOCK_SIZE,
397 .period_bytes_max = RME32_BLOCK_SIZE, 394 .period_bytes_max = RME32_BLOCK_SIZE,
398 .periods_min = 2, 395 .periods_min = 2,
399 .periods_max = RME32_MID_BUFFER_S 396 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
400 .fifo_size = 0, 397 .fifo_size = 0,
401 }; 398 };
402 399
403 static void snd_rme32_reset_dac(struct rme32 * 400 static void snd_rme32_reset_dac(struct rme32 *rme32)
404 { 401 {
405 writel(rme32->wcreg | RME32_WCR_PD, 402 writel(rme32->wcreg | RME32_WCR_PD,
406 rme32->iobase + RME32_IO_CONTRO 403 rme32->iobase + RME32_IO_CONTROL_REGISTER);
407 writel(rme32->wcreg, rme32->iobase + R 404 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
408 } 405 }
409 406
410 static int snd_rme32_playback_getrate(struct r 407 static int snd_rme32_playback_getrate(struct rme32 * rme32)
411 { 408 {
412 int rate; 409 int rate;
413 410
414 rate = ((rme32->wcreg >> RME32_WCR_BIT 411 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
415 (((rme32->wcreg >> RME32_WCR_BI 412 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
416 switch (rate) { 413 switch (rate) {
417 case 1: 414 case 1:
418 rate = 32000; 415 rate = 32000;
419 break; 416 break;
420 case 2: 417 case 2:
421 rate = 44100; 418 rate = 44100;
422 break; 419 break;
423 case 3: 420 case 3:
424 rate = 48000; 421 rate = 48000;
425 break; 422 break;
426 default: 423 default:
427 return -1; 424 return -1;
428 } 425 }
429 return (rme32->wcreg & RME32_WCR_DS_BM 426 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
430 } 427 }
431 428
432 static int snd_rme32_capture_getrate(struct rm 429 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
433 { 430 {
434 int n; 431 int n;
435 432
436 *is_adat = 0; 433 *is_adat = 0;
437 if (rme32->rcreg & RME32_RCR_LOCK) { 434 if (rme32->rcreg & RME32_RCR_LOCK) {
438 /* ADAT rate */ 435 /* ADAT rate */
439 *is_adat = 1; 436 *is_adat = 1;
440 } 437 }
441 if (rme32->rcreg & RME32_RCR_ERF) { 438 if (rme32->rcreg & RME32_RCR_ERF) {
442 return -1; 439 return -1;
443 } 440 }
444 441
445 /* S/PDIF rate */ 442 /* S/PDIF rate */
446 n = ((rme32->rcreg >> RME32_RCR_BITPOS 443 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
447 (((rme32->rcreg >> RME32_RCR_B 444 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
448 (((rme32->rcreg >> RME32_RCR_B 445 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
449 446
450 if (RME32_PRO_WITH_8414(rme32)) 447 if (RME32_PRO_WITH_8414(rme32))
451 switch (n) { /* supporting 448 switch (n) { /* supporting the CS8414 */
452 case 0: 449 case 0:
453 case 1: 450 case 1:
454 case 2: 451 case 2:
455 return -1; 452 return -1;
456 case 3: 453 case 3:
457 return 96000; 454 return 96000;
458 case 4: 455 case 4:
459 return 88200; 456 return 88200;
460 case 5: 457 case 5:
461 return 48000; 458 return 48000;
462 case 6: 459 case 6:
463 return 44100; 460 return 44100;
464 case 7: 461 case 7:
465 return 32000; 462 return 32000;
466 default: 463 default:
467 return -1; 464 return -1;
468 break; 465 break;
469 } 466 }
470 else 467 else
471 switch (n) { /* supporting 468 switch (n) { /* supporting the CS8412 */
472 case 0: 469 case 0:
473 return -1; 470 return -1;
474 case 1: 471 case 1:
475 return 48000; 472 return 48000;
476 case 2: 473 case 2:
477 return 44100; 474 return 44100;
478 case 3: 475 case 3:
479 return 32000; 476 return 32000;
480 case 4: 477 case 4:
481 return 48000; 478 return 48000;
482 case 5: 479 case 5:
483 return 44100; 480 return 44100;
484 case 6: 481 case 6:
485 return 44056; 482 return 44056;
486 case 7: 483 case 7:
487 return 32000; 484 return 32000;
488 default: 485 default:
489 break; 486 break;
490 } 487 }
491 return -1; 488 return -1;
492 } 489 }
493 490
494 static int snd_rme32_playback_setrate(struct r 491 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
495 { 492 {
496 int ds; 493 int ds;
497 494
498 ds = rme32->wcreg & RME32_WCR_DS_BM; 495 ds = rme32->wcreg & RME32_WCR_DS_BM;
499 switch (rate) { 496 switch (rate) {
500 case 32000: 497 case 32000:
501 rme32->wcreg &= ~RME32_WCR_DS_ 498 rme32->wcreg &= ~RME32_WCR_DS_BM;
502 rme32->wcreg = (rme32->wcreg | 499 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
503 ~RME32_WCR_FREQ_1; 500 ~RME32_WCR_FREQ_1;
504 break; 501 break;
505 case 44100: 502 case 44100:
506 rme32->wcreg &= ~RME32_WCR_DS_ 503 rme32->wcreg &= ~RME32_WCR_DS_BM;
507 rme32->wcreg = (rme32->wcreg | 504 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
508 ~RME32_WCR_FREQ_0; 505 ~RME32_WCR_FREQ_0;
509 break; 506 break;
510 case 48000: 507 case 48000:
511 rme32->wcreg &= ~RME32_WCR_DS_ 508 rme32->wcreg &= ~RME32_WCR_DS_BM;
512 rme32->wcreg = (rme32->wcreg | 509 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
513 RME32_WCR_FREQ_1; 510 RME32_WCR_FREQ_1;
514 break; 511 break;
515 case 64000: 512 case 64000:
516 if (rme32->pci->device != PCI_ 513 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
517 return -EINVAL; 514 return -EINVAL;
518 rme32->wcreg |= RME32_WCR_DS_B 515 rme32->wcreg |= RME32_WCR_DS_BM;
519 rme32->wcreg = (rme32->wcreg | 516 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
520 ~RME32_WCR_FREQ_1; 517 ~RME32_WCR_FREQ_1;
521 break; 518 break;
522 case 88200: 519 case 88200:
523 if (rme32->pci->device != PCI_ 520 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
524 return -EINVAL; 521 return -EINVAL;
525 rme32->wcreg |= RME32_WCR_DS_B 522 rme32->wcreg |= RME32_WCR_DS_BM;
526 rme32->wcreg = (rme32->wcreg | 523 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
527 ~RME32_WCR_FREQ_0; 524 ~RME32_WCR_FREQ_0;
528 break; 525 break;
529 case 96000: 526 case 96000:
530 if (rme32->pci->device != PCI_ 527 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
531 return -EINVAL; 528 return -EINVAL;
532 rme32->wcreg |= RME32_WCR_DS_B 529 rme32->wcreg |= RME32_WCR_DS_BM;
533 rme32->wcreg = (rme32->wcreg | 530 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
534 RME32_WCR_FREQ_1; 531 RME32_WCR_FREQ_1;
535 break; 532 break;
536 default: 533 default:
537 return -EINVAL; 534 return -EINVAL;
538 } 535 }
539 if ((!ds && rme32->wcreg & RME32_WCR_D 536 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
540 (ds && !(rme32->wcreg & RME32_WCR_ 537 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
541 { 538 {
542 /* change to/from double-speed 539 /* change to/from double-speed: reset the DAC (if available) */
543 snd_rme32_reset_dac(rme32); 540 snd_rme32_reset_dac(rme32);
544 } else { 541 } else {
545 writel(rme32->wcreg, rme32->io 542 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
546 } 543 }
547 return 0; 544 return 0;
548 } 545 }
549 546
550 static int snd_rme32_setclockmode(struct rme32 547 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
551 { 548 {
552 switch (mode) { 549 switch (mode) {
553 case RME32_CLOCKMODE_SLAVE: 550 case RME32_CLOCKMODE_SLAVE:
554 /* AutoSync */ 551 /* AutoSync */
555 rme32->wcreg = (rme32->wcreg & 552 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
556 ~RME32_WCR_FREQ_1; 553 ~RME32_WCR_FREQ_1;
557 break; 554 break;
558 case RME32_CLOCKMODE_MASTER_32: 555 case RME32_CLOCKMODE_MASTER_32:
559 /* Internal 32.0kHz */ 556 /* Internal 32.0kHz */
560 rme32->wcreg = (rme32->wcreg | 557 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
561 ~RME32_WCR_FREQ_1; 558 ~RME32_WCR_FREQ_1;
562 break; 559 break;
563 case RME32_CLOCKMODE_MASTER_44: 560 case RME32_CLOCKMODE_MASTER_44:
564 /* Internal 44.1kHz */ 561 /* Internal 44.1kHz */
565 rme32->wcreg = (rme32->wcreg & 562 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
566 RME32_WCR_FREQ_1; 563 RME32_WCR_FREQ_1;
567 break; 564 break;
568 case RME32_CLOCKMODE_MASTER_48: 565 case RME32_CLOCKMODE_MASTER_48:
569 /* Internal 48.0kHz */ 566 /* Internal 48.0kHz */
570 rme32->wcreg = (rme32->wcreg | 567 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
571 RME32_WCR_FREQ_1; 568 RME32_WCR_FREQ_1;
572 break; 569 break;
573 default: 570 default:
574 return -EINVAL; 571 return -EINVAL;
575 } 572 }
576 writel(rme32->wcreg, rme32->iobase + R 573 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
577 return 0; 574 return 0;
578 } 575 }
579 576
580 static int snd_rme32_getclockmode(struct rme32 577 static int snd_rme32_getclockmode(struct rme32 * rme32)
581 { 578 {
582 return ((rme32->wcreg >> RME32_WCR_BIT 579 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
583 (((rme32->wcreg >> RME32_WCR_BITPO 580 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
584 } 581 }
585 582
586 static int snd_rme32_setinputtype(struct rme32 583 static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
587 { 584 {
588 switch (type) { 585 switch (type) {
589 case RME32_INPUT_OPTICAL: 586 case RME32_INPUT_OPTICAL:
590 rme32->wcreg = (rme32->wcreg & 587 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
591 ~RME32_WCR_INP_1; 588 ~RME32_WCR_INP_1;
592 break; 589 break;
593 case RME32_INPUT_COAXIAL: 590 case RME32_INPUT_COAXIAL:
594 rme32->wcreg = (rme32->wcreg | 591 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
595 ~RME32_WCR_INP_1; 592 ~RME32_WCR_INP_1;
596 break; 593 break;
597 case RME32_INPUT_INTERNAL: 594 case RME32_INPUT_INTERNAL:
598 rme32->wcreg = (rme32->wcreg & 595 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
599 RME32_WCR_INP_1; 596 RME32_WCR_INP_1;
600 break; 597 break;
601 case RME32_INPUT_XLR: 598 case RME32_INPUT_XLR:
602 rme32->wcreg = (rme32->wcreg | 599 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
603 RME32_WCR_INP_1; 600 RME32_WCR_INP_1;
604 break; 601 break;
605 default: 602 default:
606 return -EINVAL; 603 return -EINVAL;
607 } 604 }
608 writel(rme32->wcreg, rme32->iobase + R 605 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
609 return 0; 606 return 0;
610 } 607 }
611 608
612 static int snd_rme32_getinputtype(struct rme32 609 static int snd_rme32_getinputtype(struct rme32 * rme32)
613 { 610 {
614 return ((rme32->wcreg >> RME32_WCR_BIT 611 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
615 (((rme32->wcreg >> RME32_WCR_BITPO 612 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
616 } 613 }
617 614
618 static void 615 static void
619 snd_rme32_setframelog(struct rme32 * rme32, in 616 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
620 { 617 {
621 int frlog; 618 int frlog;
622 619
623 if (n_channels == 2) { 620 if (n_channels == 2) {
624 frlog = 1; 621 frlog = 1;
625 } else { 622 } else {
626 /* assume 8 channels */ 623 /* assume 8 channels */
627 frlog = 3; 624 frlog = 3;
628 } 625 }
629 if (is_playback) { 626 if (is_playback) {
630 frlog += (rme32->wcreg & RME32 627 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
631 rme32->playback_frlog = frlog; 628 rme32->playback_frlog = frlog;
632 } else { 629 } else {
633 frlog += (rme32->wcreg & RME32 630 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
634 rme32->capture_frlog = frlog; 631 rme32->capture_frlog = frlog;
635 } 632 }
636 } 633 }
637 634
638 static int snd_rme32_setformat(struct rme32 * 635 static int snd_rme32_setformat(struct rme32 * rme32, int format)
639 { 636 {
640 switch (format) { 637 switch (format) {
641 case SNDRV_PCM_FORMAT_S16_LE: 638 case SNDRV_PCM_FORMAT_S16_LE:
642 rme32->wcreg &= ~RME32_WCR_MOD 639 rme32->wcreg &= ~RME32_WCR_MODE24;
643 break; 640 break;
644 case SNDRV_PCM_FORMAT_S32_LE: 641 case SNDRV_PCM_FORMAT_S32_LE:
645 rme32->wcreg |= RME32_WCR_MODE 642 rme32->wcreg |= RME32_WCR_MODE24;
646 break; 643 break;
647 default: 644 default:
648 return -EINVAL; 645 return -EINVAL;
649 } 646 }
650 writel(rme32->wcreg, rme32->iobase + R 647 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
651 return 0; 648 return 0;
652 } 649 }
653 650
654 static int 651 static int
655 snd_rme32_playback_hw_params(struct snd_pcm_su 652 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
656 struct snd_pcm_hw 653 struct snd_pcm_hw_params *params)
657 { 654 {
658 int err, rate, dummy; 655 int err, rate, dummy;
659 struct rme32 *rme32 = snd_pcm_substrea 656 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
660 struct snd_pcm_runtime *runtime = subs 657 struct snd_pcm_runtime *runtime = substream->runtime;
661 658
662 if (rme32->fullduplex_mode) { 659 if (rme32->fullduplex_mode) {
663 err = snd_pcm_lib_malloc_pages 660 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
664 if (err < 0) 661 if (err < 0)
665 return err; 662 return err;
666 } else { 663 } else {
667 runtime->dma_area = (void __fo 664 runtime->dma_area = (void __force *)(rme32->iobase +
668 665 RME32_IO_DATA_BUFFER);
669 runtime->dma_addr = rme32->por 666 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
670 runtime->dma_bytes = RME32_BUF 667 runtime->dma_bytes = RME32_BUFFER_SIZE;
671 } 668 }
672 669
673 spin_lock_irq(&rme32->lock); 670 spin_lock_irq(&rme32->lock);
674 if ((rme32->rcreg & RME32_RCR_KMODE) & 671 if ((rme32->rcreg & RME32_RCR_KMODE) &&
675 (rate = snd_rme32_capture_getrate( 672 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
676 /* AutoSync */ 673 /* AutoSync */
677 if ((int)params_rate(params) ! 674 if ((int)params_rate(params) != rate) {
678 spin_unlock_irq(&rme32 675 spin_unlock_irq(&rme32->lock);
679 return -EIO; 676 return -EIO;
680 } 677 }
681 } else if ((err = snd_rme32_playback_s 678 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
682 spin_unlock_irq(&rme32->lock); 679 spin_unlock_irq(&rme32->lock);
683 return err; 680 return err;
684 } 681 }
685 if ((err = snd_rme32_setformat(rme32, 682 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
686 spin_unlock_irq(&rme32->lock); 683 spin_unlock_irq(&rme32->lock);
687 return err; 684 return err;
688 } 685 }
689 686
690 snd_rme32_setframelog(rme32, params_ch 687 snd_rme32_setframelog(rme32, params_channels(params), 1);
691 if (rme32->capture_periodsize != 0) { 688 if (rme32->capture_periodsize != 0) {
692 if (params_period_size(params) 689 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
693 spin_unlock_irq(&rme32 690 spin_unlock_irq(&rme32->lock);
694 return -EBUSY; 691 return -EBUSY;
695 } 692 }
696 } 693 }
697 rme32->playback_periodsize = params_pe 694 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
698 /* S/PDIF setup */ 695 /* S/PDIF setup */
699 if ((rme32->wcreg & RME32_WCR_ADAT) == 696 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
700 rme32->wcreg &= ~(RME32_WCR_PR 697 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
701 rme32->wcreg |= rme32->wcreg_s 698 rme32->wcreg |= rme32->wcreg_spdif_stream;
702 writel(rme32->wcreg, rme32->io 699 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
703 } 700 }
704 spin_unlock_irq(&rme32->lock); 701 spin_unlock_irq(&rme32->lock);
705 702
706 return 0; 703 return 0;
707 } 704 }
708 705
709 static int 706 static int
710 snd_rme32_capture_hw_params(struct snd_pcm_sub 707 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
711 struct snd_pcm_hw_ 708 struct snd_pcm_hw_params *params)
712 { 709 {
713 int err, isadat, rate; 710 int err, isadat, rate;
714 struct rme32 *rme32 = snd_pcm_substrea 711 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
715 struct snd_pcm_runtime *runtime = subs 712 struct snd_pcm_runtime *runtime = substream->runtime;
716 713
717 if (rme32->fullduplex_mode) { 714 if (rme32->fullduplex_mode) {
718 err = snd_pcm_lib_malloc_pages 715 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
719 if (err < 0) 716 if (err < 0)
720 return err; 717 return err;
721 } else { 718 } else {
722 runtime->dma_area = (void __fo 719 runtime->dma_area = (void __force *)rme32->iobase +
723 RME32_ 720 RME32_IO_DATA_BUFFER;
724 runtime->dma_addr = rme32->por 721 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
725 runtime->dma_bytes = RME32_BUF 722 runtime->dma_bytes = RME32_BUFFER_SIZE;
726 } 723 }
727 724
728 spin_lock_irq(&rme32->lock); 725 spin_lock_irq(&rme32->lock);
729 /* enable AutoSync for record-preparin 726 /* enable AutoSync for record-preparing */
730 rme32->wcreg |= RME32_WCR_AUTOSYNC; 727 rme32->wcreg |= RME32_WCR_AUTOSYNC;
731 writel(rme32->wcreg, rme32->iobase + R 728 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
732 729
733 if ((err = snd_rme32_setformat(rme32, 730 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
734 spin_unlock_irq(&rme32->lock); 731 spin_unlock_irq(&rme32->lock);
735 return err; 732 return err;
736 } 733 }
737 if ((err = snd_rme32_playback_setrate( 734 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
738 spin_unlock_irq(&rme32->lock); 735 spin_unlock_irq(&rme32->lock);
739 return err; 736 return err;
740 } 737 }
741 if ((rate = snd_rme32_capture_getrate( 738 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
742 if ((int)params_rate(params) ! 739 if ((int)params_rate(params) != rate) {
743 spin_unlock_irq(&rme32 740 spin_unlock_irq(&rme32->lock);
744 return -EIO; 741 return -EIO;
745 } 742 }
746 if ((isadat && runtime->hw.cha 743 if ((isadat && runtime->hw.channels_min == 2) ||
747 (!isadat && runtime->hw.ch 744 (!isadat && runtime->hw.channels_min == 8)) {
748 spin_unlock_irq(&rme32 745 spin_unlock_irq(&rme32->lock);
749 return -EIO; 746 return -EIO;
750 } 747 }
751 } 748 }
752 /* AutoSync off for recording */ 749 /* AutoSync off for recording */
753 rme32->wcreg &= ~RME32_WCR_AUTOSYNC; 750 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
754 writel(rme32->wcreg, rme32->iobase + R 751 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
755 752
756 snd_rme32_setframelog(rme32, params_ch 753 snd_rme32_setframelog(rme32, params_channels(params), 0);
757 if (rme32->playback_periodsize != 0) { 754 if (rme32->playback_periodsize != 0) {
758 if (params_period_size(params) 755 if (params_period_size(params) << rme32->capture_frlog !=
759 rme32->playback_periodsize 756 rme32->playback_periodsize) {
760 spin_unlock_irq(&rme32 757 spin_unlock_irq(&rme32->lock);
761 return -EBUSY; 758 return -EBUSY;
762 } 759 }
763 } 760 }
764 rme32->capture_periodsize = 761 rme32->capture_periodsize =
765 params_period_size(params) << rme3 762 params_period_size(params) << rme32->capture_frlog;
766 spin_unlock_irq(&rme32->lock); 763 spin_unlock_irq(&rme32->lock);
767 764
768 return 0; 765 return 0;
769 } 766 }
770 767
771 static int snd_rme32_pcm_hw_free(struct snd_pc 768 static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
772 { 769 {
773 struct rme32 *rme32 = snd_pcm_substrea 770 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
774 if (! rme32->fullduplex_mode) 771 if (! rme32->fullduplex_mode)
775 return 0; 772 return 0;
776 return snd_pcm_lib_free_pages(substrea 773 return snd_pcm_lib_free_pages(substream);
777 } 774 }
778 775
779 static void snd_rme32_pcm_start(struct rme32 * 776 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
780 { 777 {
781 if (!from_pause) { 778 if (!from_pause) {
782 writel(0, rme32->iobase + RME3 779 writel(0, rme32->iobase + RME32_IO_RESET_POS);
783 } 780 }
784 781
785 rme32->wcreg |= RME32_WCR_START; 782 rme32->wcreg |= RME32_WCR_START;
786 writel(rme32->wcreg, rme32->iobase + R 783 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
787 } 784 }
788 785
789 static void snd_rme32_pcm_stop(struct rme32 * 786 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
790 { 787 {
791 /* 788 /*
792 * Check if there is an unconfirmed IR 789 * Check if there is an unconfirmed IRQ, if so confirm it, or else
793 * the hardware will not stop generati 790 * the hardware will not stop generating interrupts
794 */ 791 */
795 rme32->rcreg = readl(rme32->iobase + R 792 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
796 if (rme32->rcreg & RME32_RCR_IRQ) { 793 if (rme32->rcreg & RME32_RCR_IRQ) {
797 writel(0, rme32->iobase + RME3 794 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
798 } 795 }
799 rme32->wcreg &= ~RME32_WCR_START; 796 rme32->wcreg &= ~RME32_WCR_START;
800 if (rme32->wcreg & RME32_WCR_SEL) 797 if (rme32->wcreg & RME32_WCR_SEL)
801 rme32->wcreg |= RME32_WCR_MUTE 798 rme32->wcreg |= RME32_WCR_MUTE;
802 writel(rme32->wcreg, rme32->iobase + R 799 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
803 if (! to_pause) 800 if (! to_pause)
804 writel(0, rme32->iobase + RME3 801 writel(0, rme32->iobase + RME32_IO_RESET_POS);
805 } 802 }
806 803
807 static irqreturn_t snd_rme32_interrupt(int irq 804 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
808 { 805 {
809 struct rme32 *rme32 = (struct rme32 *) 806 struct rme32 *rme32 = (struct rme32 *) dev_id;
810 807
811 rme32->rcreg = readl(rme32->iobase + R 808 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
812 if (!(rme32->rcreg & RME32_RCR_IRQ)) { 809 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
813 return IRQ_NONE; 810 return IRQ_NONE;
814 } else { 811 } else {
815 if (rme32->capture_substream) 812 if (rme32->capture_substream) {
816 snd_pcm_period_elapsed 813 snd_pcm_period_elapsed(rme32->capture_substream);
817 } 814 }
818 if (rme32->playback_substream) 815 if (rme32->playback_substream) {
819 snd_pcm_period_elapsed 816 snd_pcm_period_elapsed(rme32->playback_substream);
820 } 817 }
821 writel(0, rme32->iobase + RME3 818 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
822 } 819 }
823 return IRQ_HANDLED; 820 return IRQ_HANDLED;
824 } 821 }
825 822
826 static unsigned int period_bytes[] = { RME32_B 823 static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
827 824
828 825
829 static struct snd_pcm_hw_constraint_list hw_co 826 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
830 .count = ARRAY_SIZE(period_bytes), 827 .count = ARRAY_SIZE(period_bytes),
831 .list = period_bytes, 828 .list = period_bytes,
832 .mask = 0 829 .mask = 0
833 }; 830 };
834 831
835 static void snd_rme32_set_buffer_constraint(st 832 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
836 { 833 {
837 if (! rme32->fullduplex_mode) { 834 if (! rme32->fullduplex_mode) {
838 snd_pcm_hw_constraint_minmax(r 835 snd_pcm_hw_constraint_minmax(runtime,
839 S 836 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
840 R 837 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
841 snd_pcm_hw_constraint_list(run 838 snd_pcm_hw_constraint_list(runtime, 0,
842 SND 839 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
843 &hw 840 &hw_constraints_period_bytes);
844 } 841 }
845 } 842 }
846 843
847 static int snd_rme32_playback_spdif_open(struc 844 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
848 { 845 {
849 int rate, dummy; 846 int rate, dummy;
850 struct rme32 *rme32 = snd_pcm_substrea 847 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
851 struct snd_pcm_runtime *runtime = subs 848 struct snd_pcm_runtime *runtime = substream->runtime;
852 849
853 snd_pcm_set_sync(substream); 850 snd_pcm_set_sync(substream);
854 851
855 spin_lock_irq(&rme32->lock); 852 spin_lock_irq(&rme32->lock);
856 if (rme32->playback_substream != NULL) 853 if (rme32->playback_substream != NULL) {
857 spin_unlock_irq(&rme32->lock); 854 spin_unlock_irq(&rme32->lock);
858 return -EBUSY; 855 return -EBUSY;
859 } 856 }
860 rme32->wcreg &= ~RME32_WCR_ADAT; 857 rme32->wcreg &= ~RME32_WCR_ADAT;
861 writel(rme32->wcreg, rme32->iobase + R 858 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
862 rme32->playback_substream = substream; 859 rme32->playback_substream = substream;
863 spin_unlock_irq(&rme32->lock); 860 spin_unlock_irq(&rme32->lock);
864 861
865 if (rme32->fullduplex_mode) 862 if (rme32->fullduplex_mode)
866 runtime->hw = snd_rme32_spdif_ 863 runtime->hw = snd_rme32_spdif_fd_info;
867 else 864 else
868 runtime->hw = snd_rme32_spdif_ 865 runtime->hw = snd_rme32_spdif_info;
869 if (rme32->pci->device == PCI_DEVICE_I 866 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
870 runtime->hw.rates |= SNDRV_PCM 867 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
871 runtime->hw.rate_max = 96000; 868 runtime->hw.rate_max = 96000;
872 } 869 }
873 if ((rme32->rcreg & RME32_RCR_KMODE) & 870 if ((rme32->rcreg & RME32_RCR_KMODE) &&
874 (rate = snd_rme32_capture_getrate( 871 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
875 /* AutoSync */ 872 /* AutoSync */
876 runtime->hw.rates = snd_pcm_ra 873 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
877 runtime->hw.rate_min = rate; 874 runtime->hw.rate_min = rate;
878 runtime->hw.rate_max = rate; 875 runtime->hw.rate_max = rate;
879 } 876 }
880 877
881 snd_rme32_set_buffer_constraint(rme32, 878 snd_rme32_set_buffer_constraint(rme32, runtime);
882 879
883 rme32->wcreg_spdif_stream = rme32->wcr 880 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
884 rme32->spdif_ctl->vd[0].access &= ~SND 881 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
885 snd_ctl_notify(rme32->card, SNDRV_CTL_ 882 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
886 SNDRV_CTL_EVENT_MASK_IN 883 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
887 return 0; 884 return 0;
888 } 885 }
889 886
890 static int snd_rme32_capture_spdif_open(struct 887 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
891 { 888 {
892 int isadat, rate; 889 int isadat, rate;
893 struct rme32 *rme32 = snd_pcm_substrea 890 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
894 struct snd_pcm_runtime *runtime = subs 891 struct snd_pcm_runtime *runtime = substream->runtime;
895 892
896 snd_pcm_set_sync(substream); 893 snd_pcm_set_sync(substream);
897 894
898 spin_lock_irq(&rme32->lock); 895 spin_lock_irq(&rme32->lock);
899 if (rme32->capture_substream != NULL) 896 if (rme32->capture_substream != NULL) {
900 spin_unlock_irq(&rme32->lock); 897 spin_unlock_irq(&rme32->lock);
901 return -EBUSY; 898 return -EBUSY;
902 } 899 }
903 rme32->capture_substream = substream; 900 rme32->capture_substream = substream;
904 spin_unlock_irq(&rme32->lock); 901 spin_unlock_irq(&rme32->lock);
905 902
906 if (rme32->fullduplex_mode) 903 if (rme32->fullduplex_mode)
907 runtime->hw = snd_rme32_spdif_ 904 runtime->hw = snd_rme32_spdif_fd_info;
908 else 905 else
909 runtime->hw = snd_rme32_spdif_ 906 runtime->hw = snd_rme32_spdif_info;
910 if (RME32_PRO_WITH_8414(rme32)) { 907 if (RME32_PRO_WITH_8414(rme32)) {
911 runtime->hw.rates |= SNDRV_PCM 908 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
912 runtime->hw.rate_max = 96000; 909 runtime->hw.rate_max = 96000;
913 } 910 }
914 if ((rate = snd_rme32_capture_getrate( 911 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
915 if (isadat) { 912 if (isadat) {
916 return -EIO; 913 return -EIO;
917 } 914 }
918 runtime->hw.rates = snd_pcm_ra 915 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
919 runtime->hw.rate_min = rate; 916 runtime->hw.rate_min = rate;
920 runtime->hw.rate_max = rate; 917 runtime->hw.rate_max = rate;
921 } 918 }
922 919
923 snd_rme32_set_buffer_constraint(rme32, 920 snd_rme32_set_buffer_constraint(rme32, runtime);
924 921
925 return 0; 922 return 0;
926 } 923 }
927 924
928 static int 925 static int
929 snd_rme32_playback_adat_open(struct snd_pcm_su 926 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
930 { 927 {
931 int rate, dummy; 928 int rate, dummy;
932 struct rme32 *rme32 = snd_pcm_substrea 929 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
933 struct snd_pcm_runtime *runtime = subs 930 struct snd_pcm_runtime *runtime = substream->runtime;
934 931
935 snd_pcm_set_sync(substream); 932 snd_pcm_set_sync(substream);
936 933
937 spin_lock_irq(&rme32->lock); 934 spin_lock_irq(&rme32->lock);
938 if (rme32->playback_substream != NULL) 935 if (rme32->playback_substream != NULL) {
939 spin_unlock_irq(&rme32->lock); 936 spin_unlock_irq(&rme32->lock);
940 return -EBUSY; 937 return -EBUSY;
941 } 938 }
942 rme32->wcreg |= RME32_WCR_ADAT; 939 rme32->wcreg |= RME32_WCR_ADAT;
943 writel(rme32->wcreg, rme32->iobase + R 940 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
944 rme32->playback_substream = substream; 941 rme32->playback_substream = substream;
945 spin_unlock_irq(&rme32->lock); 942 spin_unlock_irq(&rme32->lock);
946 943
947 if (rme32->fullduplex_mode) 944 if (rme32->fullduplex_mode)
948 runtime->hw = snd_rme32_adat_f 945 runtime->hw = snd_rme32_adat_fd_info;
949 else 946 else
950 runtime->hw = snd_rme32_adat_i 947 runtime->hw = snd_rme32_adat_info;
951 if ((rme32->rcreg & RME32_RCR_KMODE) & 948 if ((rme32->rcreg & RME32_RCR_KMODE) &&
952 (rate = snd_rme32_capture_getrate( 949 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
953 /* AutoSync */ 950 /* AutoSync */
954 runtime->hw.rates = snd_pcm_ra 951 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
955 runtime->hw.rate_min = rate; 952 runtime->hw.rate_min = rate;
956 runtime->hw.rate_max = rate; 953 runtime->hw.rate_max = rate;
957 } 954 }
958 955
959 snd_rme32_set_buffer_constraint(rme32, 956 snd_rme32_set_buffer_constraint(rme32, runtime);
960 return 0; 957 return 0;
961 } 958 }
962 959
963 static int 960 static int
964 snd_rme32_capture_adat_open(struct snd_pcm_sub 961 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
965 { 962 {
966 int isadat, rate; 963 int isadat, rate;
967 struct rme32 *rme32 = snd_pcm_substrea 964 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
968 struct snd_pcm_runtime *runtime = subs 965 struct snd_pcm_runtime *runtime = substream->runtime;
969 966
970 if (rme32->fullduplex_mode) 967 if (rme32->fullduplex_mode)
971 runtime->hw = snd_rme32_adat_f 968 runtime->hw = snd_rme32_adat_fd_info;
972 else 969 else
973 runtime->hw = snd_rme32_adat_i 970 runtime->hw = snd_rme32_adat_info;
974 if ((rate = snd_rme32_capture_getrate( 971 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
975 if (!isadat) { 972 if (!isadat) {
976 return -EIO; 973 return -EIO;
977 } 974 }
978 runtime->hw.rates = snd_pcm_ra 975 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
979 runtime->hw.rate_min = rate; 976 runtime->hw.rate_min = rate;
980 runtime->hw.rate_max = rate; 977 runtime->hw.rate_max = rate;
981 } 978 }
982 979
983 snd_pcm_set_sync(substream); 980 snd_pcm_set_sync(substream);
984 981
985 spin_lock_irq(&rme32->lock); 982 spin_lock_irq(&rme32->lock);
986 if (rme32->capture_substream != NULL) 983 if (rme32->capture_substream != NULL) {
987 spin_unlock_irq(&rme32->lock); 984 spin_unlock_irq(&rme32->lock);
988 return -EBUSY; 985 return -EBUSY;
989 } 986 }
990 rme32->capture_substream = substream; 987 rme32->capture_substream = substream;
991 spin_unlock_irq(&rme32->lock); 988 spin_unlock_irq(&rme32->lock);
992 989
993 snd_rme32_set_buffer_constraint(rme32, 990 snd_rme32_set_buffer_constraint(rme32, runtime);
994 return 0; 991 return 0;
995 } 992 }
996 993
997 static int snd_rme32_playback_close(struct snd 994 static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
998 { 995 {
999 struct rme32 *rme32 = snd_pcm_substrea 996 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1000 int spdif = 0; 997 int spdif = 0;
1001 998
1002 spin_lock_irq(&rme32->lock); 999 spin_lock_irq(&rme32->lock);
1003 rme32->playback_substream = NULL; 1000 rme32->playback_substream = NULL;
1004 rme32->playback_periodsize = 0; 1001 rme32->playback_periodsize = 0;
1005 spdif = (rme32->wcreg & RME32_WCR_ADA 1002 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1006 spin_unlock_irq(&rme32->lock); 1003 spin_unlock_irq(&rme32->lock);
1007 if (spdif) { 1004 if (spdif) {
1008 rme32->spdif_ctl->vd[0].acces 1005 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1009 snd_ctl_notify(rme32->card, S 1006 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1010 SNDRV_CTL_EVEN 1007 SNDRV_CTL_EVENT_MASK_INFO,
1011 &rme32->spdif_ 1008 &rme32->spdif_ctl->id);
1012 } 1009 }
1013 return 0; 1010 return 0;
1014 } 1011 }
1015 1012
1016 static int snd_rme32_capture_close(struct snd 1013 static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1017 { 1014 {
1018 struct rme32 *rme32 = snd_pcm_substre 1015 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1019 1016
1020 spin_lock_irq(&rme32->lock); 1017 spin_lock_irq(&rme32->lock);
1021 rme32->capture_substream = NULL; 1018 rme32->capture_substream = NULL;
1022 rme32->capture_periodsize = 0; 1019 rme32->capture_periodsize = 0;
1023 spin_unlock(&rme32->lock); 1020 spin_unlock(&rme32->lock);
1024 return 0; 1021 return 0;
1025 } 1022 }
1026 1023
1027 static int snd_rme32_playback_prepare(struct 1024 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1028 { 1025 {
1029 struct rme32 *rme32 = snd_pcm_substre 1026 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1030 1027
1031 spin_lock_irq(&rme32->lock); 1028 spin_lock_irq(&rme32->lock);
1032 if (rme32->fullduplex_mode) { 1029 if (rme32->fullduplex_mode) {
1033 memset(&rme32->playback_pcm, 1030 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1034 rme32->playback_pcm.hw_buffer 1031 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1035 rme32->playback_pcm.sw_buffer 1032 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1036 } else { 1033 } else {
1037 writel(0, rme32->iobase + RME 1034 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1038 } 1035 }
1039 if (rme32->wcreg & RME32_WCR_SEL) 1036 if (rme32->wcreg & RME32_WCR_SEL)
1040 rme32->wcreg &= ~RME32_WCR_MU 1037 rme32->wcreg &= ~RME32_WCR_MUTE;
1041 writel(rme32->wcreg, rme32->iobase + 1038 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1042 spin_unlock_irq(&rme32->lock); 1039 spin_unlock_irq(&rme32->lock);
1043 return 0; 1040 return 0;
1044 } 1041 }
1045 1042
1046 static int snd_rme32_capture_prepare(struct s 1043 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1047 { 1044 {
1048 struct rme32 *rme32 = snd_pcm_substre 1045 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1049 1046
1050 spin_lock_irq(&rme32->lock); 1047 spin_lock_irq(&rme32->lock);
1051 if (rme32->fullduplex_mode) { 1048 if (rme32->fullduplex_mode) {
1052 memset(&rme32->capture_pcm, 0 1049 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1053 rme32->capture_pcm.hw_buffer_ 1050 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1054 rme32->capture_pcm.hw_queue_s 1051 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1055 rme32->capture_pcm.sw_buffer_ 1052 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1056 } else { 1053 } else {
1057 writel(0, rme32->iobase + RME 1054 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1058 } 1055 }
1059 spin_unlock_irq(&rme32->lock); 1056 spin_unlock_irq(&rme32->lock);
1060 return 0; 1057 return 0;
1061 } 1058 }
1062 1059
1063 static int 1060 static int
1064 snd_rme32_pcm_trigger(struct snd_pcm_substrea 1061 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1065 { 1062 {
1066 struct rme32 *rme32 = snd_pcm_substre 1063 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1067 struct snd_pcm_substream *s; 1064 struct snd_pcm_substream *s;
1068 1065
1069 spin_lock(&rme32->lock); 1066 spin_lock(&rme32->lock);
1070 snd_pcm_group_for_each_entry(s, subst 1067 snd_pcm_group_for_each_entry(s, substream) {
1071 if (s != rme32->playback_subs 1068 if (s != rme32->playback_substream &&
1072 s != rme32->capture_subst 1069 s != rme32->capture_substream)
1073 continue; 1070 continue;
1074 switch (cmd) { 1071 switch (cmd) {
1075 case SNDRV_PCM_TRIGGER_START: 1072 case SNDRV_PCM_TRIGGER_START:
1076 rme32->running |= (1 1073 rme32->running |= (1 << s->stream);
1077 if (rme32->fullduplex 1074 if (rme32->fullduplex_mode) {
1078 /* remember t 1075 /* remember the current DMA position */
1079 if (s == rme3 1076 if (s == rme32->playback_substream) {
1080 rme32 1077 rme32->playback_pcm.hw_io =
1081 rme32 1078 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1082 } else { 1079 } else {
1083 rme32 1080 rme32->capture_pcm.hw_io =
1084 rme32 1081 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1085 } 1082 }
1086 } 1083 }
1087 break; 1084 break;
1088 case SNDRV_PCM_TRIGGER_STOP: 1085 case SNDRV_PCM_TRIGGER_STOP:
1089 rme32->running &= ~(1 1086 rme32->running &= ~(1 << s->stream);
1090 break; 1087 break;
1091 } 1088 }
1092 snd_pcm_trigger_done(s, subst 1089 snd_pcm_trigger_done(s, substream);
1093 } 1090 }
1094 1091
1095 /* prefill playback buffer */ 1092 /* prefill playback buffer */
1096 if (cmd == SNDRV_PCM_TRIGGER_START && 1093 if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1097 snd_pcm_group_for_each_entry( 1094 snd_pcm_group_for_each_entry(s, substream) {
1098 if (s == rme32->playb 1095 if (s == rme32->playback_substream) {
1099 s->ops->ack(s 1096 s->ops->ack(s);
1100 break; 1097 break;
1101 } 1098 }
1102 } 1099 }
1103 } 1100 }
1104 1101
1105 switch (cmd) { 1102 switch (cmd) {
1106 case SNDRV_PCM_TRIGGER_START: 1103 case SNDRV_PCM_TRIGGER_START:
1107 if (rme32->running && ! RME32 1104 if (rme32->running && ! RME32_ISWORKING(rme32))
1108 snd_rme32_pcm_start(r 1105 snd_rme32_pcm_start(rme32, 0);
1109 break; 1106 break;
1110 case SNDRV_PCM_TRIGGER_STOP: 1107 case SNDRV_PCM_TRIGGER_STOP:
1111 if (! rme32->running && RME32 1108 if (! rme32->running && RME32_ISWORKING(rme32))
1112 snd_rme32_pcm_stop(rm 1109 snd_rme32_pcm_stop(rme32, 0);
1113 break; 1110 break;
1114 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1111 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1115 if (rme32->running && RME32_I 1112 if (rme32->running && RME32_ISWORKING(rme32))
1116 snd_rme32_pcm_stop(rm 1113 snd_rme32_pcm_stop(rme32, 1);
1117 break; 1114 break;
1118 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1115 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1119 if (rme32->running && ! RME32 1116 if (rme32->running && ! RME32_ISWORKING(rme32))
1120 snd_rme32_pcm_start(r 1117 snd_rme32_pcm_start(rme32, 1);
1121 break; 1118 break;
1122 } 1119 }
1123 spin_unlock(&rme32->lock); 1120 spin_unlock(&rme32->lock);
1124 return 0; 1121 return 0;
1125 } 1122 }
1126 1123
1127 /* pointer callback for halfduplex mode */ 1124 /* pointer callback for halfduplex mode */
1128 static snd_pcm_uframes_t 1125 static snd_pcm_uframes_t
1129 snd_rme32_playback_pointer(struct snd_pcm_sub 1126 snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1130 { 1127 {
1131 struct rme32 *rme32 = snd_pcm_substre 1128 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1132 return snd_rme32_pcm_byteptr(rme32) > 1129 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1133 } 1130 }
1134 1131
1135 static snd_pcm_uframes_t 1132 static snd_pcm_uframes_t
1136 snd_rme32_capture_pointer(struct snd_pcm_subs 1133 snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1137 { 1134 {
1138 struct rme32 *rme32 = snd_pcm_substre 1135 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1139 return snd_rme32_pcm_byteptr(rme32) > 1136 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1140 } 1137 }
1141 1138
1142 1139
1143 /* ack and pointer callbacks for fullduplex m 1140 /* ack and pointer callbacks for fullduplex mode */
1144 static void snd_rme32_pb_trans_copy(struct sn 1141 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1145 struct sn 1142 struct snd_pcm_indirect *rec, size_t bytes)
1146 { 1143 {
1147 struct rme32 *rme32 = snd_pcm_substre 1144 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1148 memcpy_toio(rme32->iobase + RME32_IO_ 1145 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1149 substream->runtime->dma_a 1146 substream->runtime->dma_area + rec->sw_data, bytes);
1150 } 1147 }
1151 1148
1152 static int snd_rme32_playback_fd_ack(struct s 1149 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1153 { 1150 {
1154 struct rme32 *rme32 = snd_pcm_substre 1151 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1155 struct snd_pcm_indirect *rec, *cprec; 1152 struct snd_pcm_indirect *rec, *cprec;
1156 1153
1157 rec = &rme32->playback_pcm; 1154 rec = &rme32->playback_pcm;
1158 cprec = &rme32->capture_pcm; 1155 cprec = &rme32->capture_pcm;
1159 spin_lock(&rme32->lock); 1156 spin_lock(&rme32->lock);
1160 rec->hw_queue_size = RME32_BUFFER_SIZ 1157 rec->hw_queue_size = RME32_BUFFER_SIZE;
1161 if (rme32->running & (1 << SNDRV_PCM_ 1158 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1162 rec->hw_queue_size -= cprec-> 1159 rec->hw_queue_size -= cprec->hw_ready;
1163 spin_unlock(&rme32->lock); 1160 spin_unlock(&rme32->lock);
1164 snd_pcm_indirect_playback_transfer(su 1161 snd_pcm_indirect_playback_transfer(substream, rec,
1165 sn 1162 snd_rme32_pb_trans_copy);
1166 return 0; 1163 return 0;
1167 } 1164 }
1168 1165
1169 static void snd_rme32_cp_trans_copy(struct sn 1166 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1170 struct sn 1167 struct snd_pcm_indirect *rec, size_t bytes)
1171 { 1168 {
1172 struct rme32 *rme32 = snd_pcm_substre 1169 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1173 memcpy_fromio(substream->runtime->dma 1170 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1174 rme32->iobase + RME32_I 1171 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1175 bytes); 1172 bytes);
1176 } 1173 }
1177 1174
1178 static int snd_rme32_capture_fd_ack(struct sn 1175 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1179 { 1176 {
1180 struct rme32 *rme32 = snd_pcm_substre 1177 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1181 snd_pcm_indirect_capture_transfer(sub 1178 snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1182 snd 1179 snd_rme32_cp_trans_copy);
1183 return 0; 1180 return 0;
1184 } 1181 }
1185 1182
1186 static snd_pcm_uframes_t 1183 static snd_pcm_uframes_t
1187 snd_rme32_playback_fd_pointer(struct snd_pcm_ 1184 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1188 { 1185 {
1189 struct rme32 *rme32 = snd_pcm_substre 1186 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1190 return snd_pcm_indirect_playback_poin 1187 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1191 1188 snd_rme32_pcm_byteptr(rme32));
1192 } 1189 }
1193 1190
1194 static snd_pcm_uframes_t 1191 static snd_pcm_uframes_t
1195 snd_rme32_capture_fd_pointer(struct snd_pcm_s 1192 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1196 { 1193 {
1197 struct rme32 *rme32 = snd_pcm_substre 1194 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1198 return snd_pcm_indirect_capture_point 1195 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1199 1196 snd_rme32_pcm_byteptr(rme32));
1200 } 1197 }
1201 1198
1202 /* for halfduplex mode */ 1199 /* for halfduplex mode */
1203 static struct snd_pcm_ops snd_rme32_playback_ 1200 static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1204 .open = snd_rme32_playback_sp 1201 .open = snd_rme32_playback_spdif_open,
1205 .close = snd_rme32_playback_cl 1202 .close = snd_rme32_playback_close,
1206 .ioctl = snd_pcm_lib_ioctl, 1203 .ioctl = snd_pcm_lib_ioctl,
1207 .hw_params = snd_rme32_playback_hw 1204 .hw_params = snd_rme32_playback_hw_params,
1208 .hw_free = snd_rme32_pcm_hw_free 1205 .hw_free = snd_rme32_pcm_hw_free,
1209 .prepare = snd_rme32_playback_pr 1206 .prepare = snd_rme32_playback_prepare,
1210 .trigger = snd_rme32_pcm_trigger 1207 .trigger = snd_rme32_pcm_trigger,
1211 .pointer = snd_rme32_playback_po 1208 .pointer = snd_rme32_playback_pointer,
1212 .copy = snd_rme32_playback_co 1209 .copy = snd_rme32_playback_copy,
1213 .silence = snd_rme32_playback_si 1210 .silence = snd_rme32_playback_silence,
1214 .mmap = snd_pcm_lib_mmap_iome 1211 .mmap = snd_pcm_lib_mmap_iomem,
1215 }; 1212 };
1216 1213
1217 static struct snd_pcm_ops snd_rme32_capture_s 1214 static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1218 .open = snd_rme32_capture_spd 1215 .open = snd_rme32_capture_spdif_open,
1219 .close = snd_rme32_capture_clo 1216 .close = snd_rme32_capture_close,
1220 .ioctl = snd_pcm_lib_ioctl, 1217 .ioctl = snd_pcm_lib_ioctl,
1221 .hw_params = snd_rme32_capture_hw_ 1218 .hw_params = snd_rme32_capture_hw_params,
1222 .hw_free = snd_rme32_pcm_hw_free 1219 .hw_free = snd_rme32_pcm_hw_free,
1223 .prepare = snd_rme32_capture_pre 1220 .prepare = snd_rme32_capture_prepare,
1224 .trigger = snd_rme32_pcm_trigger 1221 .trigger = snd_rme32_pcm_trigger,
1225 .pointer = snd_rme32_capture_poi 1222 .pointer = snd_rme32_capture_pointer,
1226 .copy = snd_rme32_capture_cop 1223 .copy = snd_rme32_capture_copy,
1227 .mmap = snd_pcm_lib_mmap_iome 1224 .mmap = snd_pcm_lib_mmap_iomem,
1228 }; 1225 };
1229 1226
1230 static struct snd_pcm_ops snd_rme32_playback_ 1227 static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1231 .open = snd_rme32_playback_ad 1228 .open = snd_rme32_playback_adat_open,
1232 .close = snd_rme32_playback_cl 1229 .close = snd_rme32_playback_close,
1233 .ioctl = snd_pcm_lib_ioctl, 1230 .ioctl = snd_pcm_lib_ioctl,
1234 .hw_params = snd_rme32_playback_hw 1231 .hw_params = snd_rme32_playback_hw_params,
1235 .prepare = snd_rme32_playback_pr 1232 .prepare = snd_rme32_playback_prepare,
1236 .trigger = snd_rme32_pcm_trigger 1233 .trigger = snd_rme32_pcm_trigger,
1237 .pointer = snd_rme32_playback_po 1234 .pointer = snd_rme32_playback_pointer,
1238 .copy = snd_rme32_playback_co 1235 .copy = snd_rme32_playback_copy,
1239 .silence = snd_rme32_playback_si 1236 .silence = snd_rme32_playback_silence,
1240 .mmap = snd_pcm_lib_mmap_iome 1237 .mmap = snd_pcm_lib_mmap_iomem,
1241 }; 1238 };
1242 1239
1243 static struct snd_pcm_ops snd_rme32_capture_a 1240 static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1244 .open = snd_rme32_capture_ada 1241 .open = snd_rme32_capture_adat_open,
1245 .close = snd_rme32_capture_clo 1242 .close = snd_rme32_capture_close,
1246 .ioctl = snd_pcm_lib_ioctl, 1243 .ioctl = snd_pcm_lib_ioctl,
1247 .hw_params = snd_rme32_capture_hw_ 1244 .hw_params = snd_rme32_capture_hw_params,
1248 .prepare = snd_rme32_capture_pre 1245 .prepare = snd_rme32_capture_prepare,
1249 .trigger = snd_rme32_pcm_trigger 1246 .trigger = snd_rme32_pcm_trigger,
1250 .pointer = snd_rme32_capture_poi 1247 .pointer = snd_rme32_capture_pointer,
1251 .copy = snd_rme32_capture_cop 1248 .copy = snd_rme32_capture_copy,
1252 .mmap = snd_pcm_lib_mmap_iome 1249 .mmap = snd_pcm_lib_mmap_iomem,
1253 }; 1250 };
1254 1251
1255 /* for fullduplex mode */ 1252 /* for fullduplex mode */
1256 static struct snd_pcm_ops snd_rme32_playback_ 1253 static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1257 .open = snd_rme32_playback_sp 1254 .open = snd_rme32_playback_spdif_open,
1258 .close = snd_rme32_playback_cl 1255 .close = snd_rme32_playback_close,
1259 .ioctl = snd_pcm_lib_ioctl, 1256 .ioctl = snd_pcm_lib_ioctl,
1260 .hw_params = snd_rme32_playback_hw 1257 .hw_params = snd_rme32_playback_hw_params,
1261 .hw_free = snd_rme32_pcm_hw_free 1258 .hw_free = snd_rme32_pcm_hw_free,
1262 .prepare = snd_rme32_playback_pr 1259 .prepare = snd_rme32_playback_prepare,
1263 .trigger = snd_rme32_pcm_trigger 1260 .trigger = snd_rme32_pcm_trigger,
1264 .pointer = snd_rme32_playback_fd 1261 .pointer = snd_rme32_playback_fd_pointer,
1265 .ack = snd_rme32_playback_fd 1262 .ack = snd_rme32_playback_fd_ack,
1266 }; 1263 };
1267 1264
1268 static struct snd_pcm_ops snd_rme32_capture_s 1265 static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1269 .open = snd_rme32_capture_spd 1266 .open = snd_rme32_capture_spdif_open,
1270 .close = snd_rme32_capture_clo 1267 .close = snd_rme32_capture_close,
1271 .ioctl = snd_pcm_lib_ioctl, 1268 .ioctl = snd_pcm_lib_ioctl,
1272 .hw_params = snd_rme32_capture_hw_ 1269 .hw_params = snd_rme32_capture_hw_params,
1273 .hw_free = snd_rme32_pcm_hw_free 1270 .hw_free = snd_rme32_pcm_hw_free,
1274 .prepare = snd_rme32_capture_pre 1271 .prepare = snd_rme32_capture_prepare,
1275 .trigger = snd_rme32_pcm_trigger 1272 .trigger = snd_rme32_pcm_trigger,
1276 .pointer = snd_rme32_capture_fd_ 1273 .pointer = snd_rme32_capture_fd_pointer,
1277 .ack = snd_rme32_capture_fd_ 1274 .ack = snd_rme32_capture_fd_ack,
1278 }; 1275 };
1279 1276
1280 static struct snd_pcm_ops snd_rme32_playback_ 1277 static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1281 .open = snd_rme32_playback_ad 1278 .open = snd_rme32_playback_adat_open,
1282 .close = snd_rme32_playback_cl 1279 .close = snd_rme32_playback_close,
1283 .ioctl = snd_pcm_lib_ioctl, 1280 .ioctl = snd_pcm_lib_ioctl,
1284 .hw_params = snd_rme32_playback_hw 1281 .hw_params = snd_rme32_playback_hw_params,
1285 .prepare = snd_rme32_playback_pr 1282 .prepare = snd_rme32_playback_prepare,
1286 .trigger = snd_rme32_pcm_trigger 1283 .trigger = snd_rme32_pcm_trigger,
1287 .pointer = snd_rme32_playback_fd 1284 .pointer = snd_rme32_playback_fd_pointer,
1288 .ack = snd_rme32_playback_fd 1285 .ack = snd_rme32_playback_fd_ack,
1289 }; 1286 };
1290 1287
1291 static struct snd_pcm_ops snd_rme32_capture_a 1288 static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1292 .open = snd_rme32_capture_ada 1289 .open = snd_rme32_capture_adat_open,
1293 .close = snd_rme32_capture_clo 1290 .close = snd_rme32_capture_close,
1294 .ioctl = snd_pcm_lib_ioctl, 1291 .ioctl = snd_pcm_lib_ioctl,
1295 .hw_params = snd_rme32_capture_hw_ 1292 .hw_params = snd_rme32_capture_hw_params,
1296 .prepare = snd_rme32_capture_pre 1293 .prepare = snd_rme32_capture_prepare,
1297 .trigger = snd_rme32_pcm_trigger 1294 .trigger = snd_rme32_pcm_trigger,
1298 .pointer = snd_rme32_capture_fd_ 1295 .pointer = snd_rme32_capture_fd_pointer,
1299 .ack = snd_rme32_capture_fd_ 1296 .ack = snd_rme32_capture_fd_ack,
1300 }; 1297 };
1301 1298
1302 static void snd_rme32_free(void *private_data 1299 static void snd_rme32_free(void *private_data)
1303 { 1300 {
1304 struct rme32 *rme32 = (struct rme32 * 1301 struct rme32 *rme32 = (struct rme32 *) private_data;
1305 1302
1306 if (rme32 == NULL) { 1303 if (rme32 == NULL) {
1307 return; 1304 return;
1308 } 1305 }
1309 if (rme32->irq >= 0) { 1306 if (rme32->irq >= 0) {
1310 snd_rme32_pcm_stop(rme32, 0); 1307 snd_rme32_pcm_stop(rme32, 0);
1311 free_irq(rme32->irq, (void *) 1308 free_irq(rme32->irq, (void *) rme32);
1312 rme32->irq = -1; 1309 rme32->irq = -1;
1313 } 1310 }
1314 if (rme32->iobase) { 1311 if (rme32->iobase) {
1315 iounmap(rme32->iobase); 1312 iounmap(rme32->iobase);
1316 rme32->iobase = NULL; 1313 rme32->iobase = NULL;
1317 } 1314 }
1318 if (rme32->port) { 1315 if (rme32->port) {
1319 pci_release_regions(rme32->pc 1316 pci_release_regions(rme32->pci);
1320 rme32->port = 0; 1317 rme32->port = 0;
1321 } 1318 }
1322 pci_disable_device(rme32->pci); 1319 pci_disable_device(rme32->pci);
1323 } 1320 }
1324 1321
1325 static void snd_rme32_free_spdif_pcm(struct s 1322 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1326 { 1323 {
1327 struct rme32 *rme32 = (struct rme32 * 1324 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1328 rme32->spdif_pcm = NULL; 1325 rme32->spdif_pcm = NULL;
1329 } 1326 }
1330 1327
1331 static void 1328 static void
1332 snd_rme32_free_adat_pcm(struct snd_pcm *pcm) 1329 snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1333 { 1330 {
1334 struct rme32 *rme32 = (struct rme32 * 1331 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1335 rme32->adat_pcm = NULL; 1332 rme32->adat_pcm = NULL;
1336 } 1333 }
1337 1334
1338 static int __devinit snd_rme32_create(struct 1335 static int __devinit snd_rme32_create(struct rme32 * rme32)
1339 { 1336 {
1340 struct pci_dev *pci = rme32->pci; 1337 struct pci_dev *pci = rme32->pci;
1341 int err; 1338 int err;
1342 1339
1343 rme32->irq = -1; 1340 rme32->irq = -1;
1344 spin_lock_init(&rme32->lock); 1341 spin_lock_init(&rme32->lock);
1345 1342
1346 if ((err = pci_enable_device(pci)) < 1343 if ((err = pci_enable_device(pci)) < 0)
1347 return err; 1344 return err;
1348 1345
1349 if ((err = pci_request_regions(pci, " 1346 if ((err = pci_request_regions(pci, "RME32")) < 0)
1350 return err; 1347 return err;
1351 rme32->port = pci_resource_start(rme3 1348 rme32->port = pci_resource_start(rme32->pci, 0);
1352 1349
1353 if ((rme32->iobase = ioremap_nocache( !! 1350 rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE);
>> 1351 if (!rme32->iobase) {
1354 snd_printk(KERN_ERR "unable t 1352 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n",
1355 rme32->port, rme32 1353 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1356 return -ENOMEM; 1354 return -ENOMEM;
1357 } 1355 }
1358 1356
1359 if (request_irq(pci->irq, snd_rme32_i 1357 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1360 "RME32", rme32)) { 1358 "RME32", rme32)) {
1361 snd_printk(KERN_ERR "unable t 1359 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1362 return -EBUSY; 1360 return -EBUSY;
1363 } 1361 }
1364 rme32->irq = pci->irq; 1362 rme32->irq = pci->irq;
1365 1363
1366 /* read the card's revision number */ 1364 /* read the card's revision number */
1367 pci_read_config_byte(pci, 8, &rme32-> 1365 pci_read_config_byte(pci, 8, &rme32->rev);
1368 1366
1369 /* set up ALSA pcm device for S/PDIF 1367 /* set up ALSA pcm device for S/PDIF */
1370 if ((err = snd_pcm_new(rme32->card, " 1368 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1371 return err; 1369 return err;
1372 } 1370 }
1373 rme32->spdif_pcm->private_data = rme3 1371 rme32->spdif_pcm->private_data = rme32;
1374 rme32->spdif_pcm->private_free = snd_ 1372 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1375 strcpy(rme32->spdif_pcm->name, "Digi3 1373 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1376 if (rme32->fullduplex_mode) { 1374 if (rme32->fullduplex_mode) {
1377 snd_pcm_set_ops(rme32->spdif_ 1375 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1378 &snd_rme32_pl 1376 &snd_rme32_playback_spdif_fd_ops);
1379 snd_pcm_set_ops(rme32->spdif_ 1377 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1380 &snd_rme32_ca 1378 &snd_rme32_capture_spdif_fd_ops);
1381 snd_pcm_lib_preallocate_pages 1379 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1382 1380 snd_dma_continuous_data(GFP_KERNEL),
1383 1381 0, RME32_MID_BUFFER_SIZE);
1384 rme32->spdif_pcm->info_flags 1382 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1385 } else { 1383 } else {
1386 snd_pcm_set_ops(rme32->spdif_ 1384 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1387 &snd_rme32_pl 1385 &snd_rme32_playback_spdif_ops);
1388 snd_pcm_set_ops(rme32->spdif_ 1386 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1389 &snd_rme32_ca 1387 &snd_rme32_capture_spdif_ops);
1390 rme32->spdif_pcm->info_flags 1388 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1391 } 1389 }
1392 1390
1393 /* set up ALSA pcm device for ADAT */ 1391 /* set up ALSA pcm device for ADAT */
1394 if ((pci->device == PCI_DEVICE_ID_RME 1392 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1395 (pci->device == PCI_DEVICE_ID_RME 1393 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1396 /* ADAT is not available on D 1394 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1397 rme32->adat_pcm = NULL; 1395 rme32->adat_pcm = NULL;
1398 } 1396 }
1399 else { 1397 else {
1400 if ((err = snd_pcm_new(rme32- 1398 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1401 1, 1, 1399 1, 1, &rme32->adat_pcm)) < 0)
1402 { 1400 {
1403 return err; 1401 return err;
1404 } 1402 }
1405 rme32->adat_pcm->private_data 1403 rme32->adat_pcm->private_data = rme32;
1406 rme32->adat_pcm->private_free 1404 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1407 strcpy(rme32->adat_pcm->name, 1405 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1408 if (rme32->fullduplex_mode) { 1406 if (rme32->fullduplex_mode) {
1409 snd_pcm_set_ops(rme32 1407 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1410 &snd_ 1408 &snd_rme32_playback_adat_fd_ops);
1411 snd_pcm_set_ops(rme32 1409 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1412 &snd_ 1410 &snd_rme32_capture_adat_fd_ops);
1413 snd_pcm_lib_prealloca 1411 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1414 1412 snd_dma_continuous_data(GFP_KERNEL),
1415 1413 0, RME32_MID_BUFFER_SIZE);
1416 rme32->adat_pcm->info 1414 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1417 } else { 1415 } else {
1418 snd_pcm_set_ops(rme32 1416 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1419 &snd_ 1417 &snd_rme32_playback_adat_ops);
1420 snd_pcm_set_ops(rme32 1418 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1421 &snd_ 1419 &snd_rme32_capture_adat_ops);
1422 rme32->adat_pcm->info 1420 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1423 } 1421 }
1424 } 1422 }
1425 1423
1426 1424
1427 rme32->playback_periodsize = 0; 1425 rme32->playback_periodsize = 0;
1428 rme32->capture_periodsize = 0; 1426 rme32->capture_periodsize = 0;
1429 1427
1430 /* make sure playback/capture is stop 1428 /* make sure playback/capture is stopped, if by some reason active */
1431 snd_rme32_pcm_stop(rme32, 0); 1429 snd_rme32_pcm_stop(rme32, 0);
1432 1430
1433 /* reset DAC */ 1431 /* reset DAC */
1434 snd_rme32_reset_dac(rme32); 1432 snd_rme32_reset_dac(rme32);
1435 1433
1436 /* reset buffer pointer */ 1434 /* reset buffer pointer */
1437 writel(0, rme32->iobase + RME32_IO_RE 1435 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1438 1436
1439 /* set default values in registers */ 1437 /* set default values in registers */
1440 rme32->wcreg = RME32_WCR_SEL | /* n 1438 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1441 RME32_WCR_INP_0 | /* input se 1439 RME32_WCR_INP_0 | /* input select */
1442 RME32_WCR_MUTE; /* muting on 1440 RME32_WCR_MUTE; /* muting on */
1443 writel(rme32->wcreg, rme32->iobase + 1441 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1444 1442
1445 1443
1446 /* init switch interface */ 1444 /* init switch interface */
1447 if ((err = snd_rme32_create_switches( 1445 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1448 return err; 1446 return err;
1449 } 1447 }
1450 1448
1451 /* init proc interface */ 1449 /* init proc interface */
1452 snd_rme32_proc_init(rme32); 1450 snd_rme32_proc_init(rme32);
1453 1451
1454 rme32->capture_substream = NULL; 1452 rme32->capture_substream = NULL;
1455 rme32->playback_substream = NULL; 1453 rme32->playback_substream = NULL;
1456 1454
1457 return 0; 1455 return 0;
1458 } 1456 }
1459 1457
1460 /* 1458 /*
1461 * proc interface 1459 * proc interface
1462 */ 1460 */
1463 1461
1464 static void 1462 static void
1465 snd_rme32_proc_read(struct snd_info_entry * e 1463 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1466 { 1464 {
1467 int n; 1465 int n;
1468 struct rme32 *rme32 = (struct rme32 * 1466 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1469 1467
1470 rme32->rcreg = readl(rme32->iobase + 1468 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1471 1469
1472 snd_iprintf(buffer, rme32->card->long 1470 snd_iprintf(buffer, rme32->card->longname);
1473 snd_iprintf(buffer, " (index #%d)\n", 1471 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1474 1472
1475 snd_iprintf(buffer, "\nGeneral settin 1473 snd_iprintf(buffer, "\nGeneral settings\n");
1476 if (rme32->fullduplex_mode) 1474 if (rme32->fullduplex_mode)
1477 snd_iprintf(buffer, " Full-d 1475 snd_iprintf(buffer, " Full-duplex mode\n");
1478 else 1476 else
1479 snd_iprintf(buffer, " Half-d 1477 snd_iprintf(buffer, " Half-duplex mode\n");
1480 if (RME32_PRO_WITH_8414(rme32)) { 1478 if (RME32_PRO_WITH_8414(rme32)) {
1481 snd_iprintf(buffer, " receiv 1479 snd_iprintf(buffer, " receiver: CS8414\n");
1482 } else { 1480 } else {
1483 snd_iprintf(buffer, " receiv 1481 snd_iprintf(buffer, " receiver: CS8412\n");
1484 } 1482 }
1485 if (rme32->wcreg & RME32_WCR_MODE24) 1483 if (rme32->wcreg & RME32_WCR_MODE24) {
1486 snd_iprintf(buffer, " format 1484 snd_iprintf(buffer, " format: 24 bit");
1487 } else { 1485 } else {
1488 snd_iprintf(buffer, " format 1486 snd_iprintf(buffer, " format: 16 bit");
1489 } 1487 }
1490 if (rme32->wcreg & RME32_WCR_MONO) { 1488 if (rme32->wcreg & RME32_WCR_MONO) {
1491 snd_iprintf(buffer, ", Mono\n 1489 snd_iprintf(buffer, ", Mono\n");
1492 } else { 1490 } else {
1493 snd_iprintf(buffer, ", Stereo 1491 snd_iprintf(buffer, ", Stereo\n");
1494 } 1492 }
1495 1493
1496 snd_iprintf(buffer, "\nInput settings 1494 snd_iprintf(buffer, "\nInput settings\n");
1497 switch (snd_rme32_getinputtype(rme32) 1495 switch (snd_rme32_getinputtype(rme32)) {
1498 case RME32_INPUT_OPTICAL: 1496 case RME32_INPUT_OPTICAL:
1499 snd_iprintf(buffer, " input: 1497 snd_iprintf(buffer, " input: optical");
1500 break; 1498 break;
1501 case RME32_INPUT_COAXIAL: 1499 case RME32_INPUT_COAXIAL:
1502 snd_iprintf(buffer, " input: 1500 snd_iprintf(buffer, " input: coaxial");
1503 break; 1501 break;
1504 case RME32_INPUT_INTERNAL: 1502 case RME32_INPUT_INTERNAL:
1505 snd_iprintf(buffer, " input: 1503 snd_iprintf(buffer, " input: internal");
1506 break; 1504 break;
1507 case RME32_INPUT_XLR: 1505 case RME32_INPUT_XLR:
1508 snd_iprintf(buffer, " input: 1506 snd_iprintf(buffer, " input: XLR");
1509 break; 1507 break;
1510 } 1508 }
1511 if (snd_rme32_capture_getrate(rme32, 1509 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1512 snd_iprintf(buffer, "\n samp 1510 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1513 } else { 1511 } else {
1514 if (n) { 1512 if (n) {
1515 snd_iprintf(buffer, " 1513 snd_iprintf(buffer, " (8 channels)\n");
1516 } else { 1514 } else {
1517 snd_iprintf(buffer, " 1515 snd_iprintf(buffer, " (2 channels)\n");
1518 } 1516 }
1519 snd_iprintf(buffer, " sample 1517 snd_iprintf(buffer, " sample rate: %d Hz\n",
1520 snd_rme32_capture 1518 snd_rme32_capture_getrate(rme32, &n));
1521 } 1519 }
1522 1520
1523 snd_iprintf(buffer, "\nOutput setting 1521 snd_iprintf(buffer, "\nOutput settings\n");
1524 if (rme32->wcreg & RME32_WCR_SEL) { 1522 if (rme32->wcreg & RME32_WCR_SEL) {
1525 snd_iprintf(buffer, " output 1523 snd_iprintf(buffer, " output signal: normal playback");
1526 } else { 1524 } else {
1527 snd_iprintf(buffer, " output 1525 snd_iprintf(buffer, " output signal: same as input");
1528 } 1526 }
1529 if (rme32->wcreg & RME32_WCR_MUTE) { 1527 if (rme32->wcreg & RME32_WCR_MUTE) {
1530 snd_iprintf(buffer, " (muted) 1528 snd_iprintf(buffer, " (muted)\n");
1531 } else { 1529 } else {
1532 snd_iprintf(buffer, "\n"); 1530 snd_iprintf(buffer, "\n");
1533 } 1531 }
1534 1532
1535 /* master output frequency */ 1533 /* master output frequency */
1536 if (! 1534 if (!
1537 ((!(rme32->wcreg & RME32_WCR_FREQ 1535 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1538 && (!(rme32->wcreg & RME32_WCR_F 1536 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1539 snd_iprintf(buffer, " sample 1537 snd_iprintf(buffer, " sample rate: %d Hz\n",
1540 snd_rme32_playbac 1538 snd_rme32_playback_getrate(rme32));
1541 } 1539 }
1542 if (rme32->rcreg & RME32_RCR_KMODE) { 1540 if (rme32->rcreg & RME32_RCR_KMODE) {
1543 snd_iprintf(buffer, " sample 1541 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1544 } else { 1542 } else {
1545 snd_iprintf(buffer, " sample 1543 snd_iprintf(buffer, " sample clock source: Internal\n");
1546 } 1544 }
1547 if (rme32->wcreg & RME32_WCR_PRO) { 1545 if (rme32->wcreg & RME32_WCR_PRO) {
1548 snd_iprintf(buffer, " format 1546 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1549 } else { 1547 } else {
1550 snd_iprintf(buffer, " format 1548 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1551 } 1549 }
1552 if (rme32->wcreg & RME32_WCR_EMP) { 1550 if (rme32->wcreg & RME32_WCR_EMP) {
1553 snd_iprintf(buffer, " emphas 1551 snd_iprintf(buffer, " emphasis: on\n");
1554 } else { 1552 } else {
1555 snd_iprintf(buffer, " emphas 1553 snd_iprintf(buffer, " emphasis: off\n");
1556 } 1554 }
1557 } 1555 }
1558 1556
1559 static void __devinit snd_rme32_proc_init(str 1557 static void __devinit snd_rme32_proc_init(struct rme32 * rme32)
1560 { 1558 {
1561 struct snd_info_entry *entry; 1559 struct snd_info_entry *entry;
1562 1560
1563 if (! snd_card_proc_new(rme32->card, 1561 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1564 snd_info_set_text_ops(entry, 1562 snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1565 } 1563 }
1566 1564
1567 /* 1565 /*
1568 * control interface 1566 * control interface
1569 */ 1567 */
1570 1568
1571 #define snd_rme32_info_loopback_control 1569 #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
1572 1570
1573 static int 1571 static int
1574 snd_rme32_get_loopback_control(struct snd_kco 1572 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1575 struct snd_ctl 1573 struct snd_ctl_elem_value *ucontrol)
1576 { 1574 {
1577 struct rme32 *rme32 = snd_kcontrol_ch 1575 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1578 1576
1579 spin_lock_irq(&rme32->lock); 1577 spin_lock_irq(&rme32->lock);
1580 ucontrol->value.integer.value[0] = 1578 ucontrol->value.integer.value[0] =
1581 rme32->wcreg & RME32_WCR_SEL ? 0 1579 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1582 spin_unlock_irq(&rme32->lock); 1580 spin_unlock_irq(&rme32->lock);
1583 return 0; 1581 return 0;
1584 } 1582 }
1585 static int 1583 static int
1586 snd_rme32_put_loopback_control(struct snd_kco 1584 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1587 struct snd_ctl 1585 struct snd_ctl_elem_value *ucontrol)
1588 { 1586 {
1589 struct rme32 *rme32 = snd_kcontrol_ch 1587 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1590 unsigned int val; 1588 unsigned int val;
1591 int change; 1589 int change;
1592 1590
1593 val = ucontrol->value.integer.value[0 1591 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1594 spin_lock_irq(&rme32->lock); 1592 spin_lock_irq(&rme32->lock);
1595 val = (rme32->wcreg & ~RME32_WCR_SEL) 1593 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1596 change = val != rme32->wcreg; 1594 change = val != rme32->wcreg;
1597 if (ucontrol->value.integer.value[0]) 1595 if (ucontrol->value.integer.value[0])
1598 val &= ~RME32_WCR_MUTE; 1596 val &= ~RME32_WCR_MUTE;
1599 else 1597 else
1600 val |= RME32_WCR_MUTE; 1598 val |= RME32_WCR_MUTE;
1601 rme32->wcreg = val; 1599 rme32->wcreg = val;
1602 writel(val, rme32->iobase + RME32_IO_ 1600 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1603 spin_unlock_irq(&rme32->lock); 1601 spin_unlock_irq(&rme32->lock);
1604 return change; 1602 return change;
1605 } 1603 }
1606 1604
1607 static int 1605 static int
1608 snd_rme32_info_inputtype_control(struct snd_k 1606 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1609 struct snd_c 1607 struct snd_ctl_elem_info *uinfo)
1610 { 1608 {
1611 struct rme32 *rme32 = snd_kcontrol_ch 1609 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1612 static char *texts[4] = { "Optical", 1610 static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1613 1611
1614 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENU 1612 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1615 uinfo->count = 1; 1613 uinfo->count = 1;
1616 switch (rme32->pci->device) { 1614 switch (rme32->pci->device) {
1617 case PCI_DEVICE_ID_RME_DIGI32: 1615 case PCI_DEVICE_ID_RME_DIGI32:
1618 case PCI_DEVICE_ID_RME_DIGI32_8: 1616 case PCI_DEVICE_ID_RME_DIGI32_8:
1619 uinfo->value.enumerated.items 1617 uinfo->value.enumerated.items = 3;
1620 break; 1618 break;
1621 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1619 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1622 uinfo->value.enumerated.items 1620 uinfo->value.enumerated.items = 4;
1623 break; 1621 break;
1624 default: 1622 default:
1625 snd_BUG(); 1623 snd_BUG();
1626 break; 1624 break;
1627 } 1625 }
1628 if (uinfo->value.enumerated.item > 1626 if (uinfo->value.enumerated.item >
1629 uinfo->value.enumerated.items - 1 1627 uinfo->value.enumerated.items - 1) {
1630 uinfo->value.enumerated.item 1628 uinfo->value.enumerated.item =
1631 uinfo->value.enumerated.i 1629 uinfo->value.enumerated.items - 1;
1632 } 1630 }
1633 strcpy(uinfo->value.enumerated.name, 1631 strcpy(uinfo->value.enumerated.name,
1634 texts[uinfo->value.enumerated. 1632 texts[uinfo->value.enumerated.item]);
1635 return 0; 1633 return 0;
1636 } 1634 }
1637 static int 1635 static int
1638 snd_rme32_get_inputtype_control(struct snd_kc 1636 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1639 struct snd_ct 1637 struct snd_ctl_elem_value *ucontrol)
1640 { 1638 {
1641 struct rme32 *rme32 = snd_kcontrol_ch 1639 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1642 unsigned int items = 3; 1640 unsigned int items = 3;
1643 1641
1644 spin_lock_irq(&rme32->lock); 1642 spin_lock_irq(&rme32->lock);
1645 ucontrol->value.enumerated.item[0] = 1643 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1646 1644
1647 switch (rme32->pci->device) { 1645 switch (rme32->pci->device) {
1648 case PCI_DEVICE_ID_RME_DIGI32: 1646 case PCI_DEVICE_ID_RME_DIGI32:
1649 case PCI_DEVICE_ID_RME_DIGI32_8: 1647 case PCI_DEVICE_ID_RME_DIGI32_8:
1650 items = 3; 1648 items = 3;
1651 break; 1649 break;
1652 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1650 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1653 items = 4; 1651 items = 4;
1654 break; 1652 break;
1655 default: 1653 default:
1656 snd_BUG(); 1654 snd_BUG();
1657 break; 1655 break;
1658 } 1656 }
1659 if (ucontrol->value.enumerated.item[0 1657 if (ucontrol->value.enumerated.item[0] >= items) {
1660 ucontrol->value.enumerated.it 1658 ucontrol->value.enumerated.item[0] = items - 1;
1661 } 1659 }
1662 1660
1663 spin_unlock_irq(&rme32->lock); 1661 spin_unlock_irq(&rme32->lock);
1664 return 0; 1662 return 0;
1665 } 1663 }
1666 static int 1664 static int
1667 snd_rme32_put_inputtype_control(struct snd_kc 1665 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1668 struct snd_ct 1666 struct snd_ctl_elem_value *ucontrol)
1669 { 1667 {
1670 struct rme32 *rme32 = snd_kcontrol_ch 1668 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1671 unsigned int val; 1669 unsigned int val;
1672 int change, items = 3; 1670 int change, items = 3;
1673 1671
1674 switch (rme32->pci->device) { 1672 switch (rme32->pci->device) {
1675 case PCI_DEVICE_ID_RME_DIGI32: 1673 case PCI_DEVICE_ID_RME_DIGI32:
1676 case PCI_DEVICE_ID_RME_DIGI32_8: 1674 case PCI_DEVICE_ID_RME_DIGI32_8:
1677 items = 3; 1675 items = 3;
1678 break; 1676 break;
1679 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1677 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1680 items = 4; 1678 items = 4;
1681 break; 1679 break;
1682 default: 1680 default:
1683 snd_BUG(); 1681 snd_BUG();
1684 break; 1682 break;
1685 } 1683 }
1686 val = ucontrol->value.enumerated.item 1684 val = ucontrol->value.enumerated.item[0] % items;
1687 1685
1688 spin_lock_irq(&rme32->lock); 1686 spin_lock_irq(&rme32->lock);
1689 change = val != (unsigned int)snd_rme 1687 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1690 snd_rme32_setinputtype(rme32, val); 1688 snd_rme32_setinputtype(rme32, val);
1691 spin_unlock_irq(&rme32->lock); 1689 spin_unlock_irq(&rme32->lock);
1692 return change; 1690 return change;
1693 } 1691 }
1694 1692
1695 static int 1693 static int
1696 snd_rme32_info_clockmode_control(struct snd_k 1694 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1697 struct snd_c 1695 struct snd_ctl_elem_info *uinfo)
1698 { 1696 {
1699 static char *texts[4] = { "AutoSync", 1697 static char *texts[4] = { "AutoSync",
1700 "Internal 3 1698 "Internal 32.0kHz",
1701 "Internal 4 1699 "Internal 44.1kHz",
1702 "Internal 4 1700 "Internal 48.0kHz" };
1703 1701
1704 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENU 1702 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1705 uinfo->count = 1; 1703 uinfo->count = 1;
1706 uinfo->value.enumerated.items = 4; 1704 uinfo->value.enumerated.items = 4;
1707 if (uinfo->value.enumerated.item > 3) 1705 if (uinfo->value.enumerated.item > 3) {
1708 uinfo->value.enumerated.item 1706 uinfo->value.enumerated.item = 3;
1709 } 1707 }
1710 strcpy(uinfo->value.enumerated.name, 1708 strcpy(uinfo->value.enumerated.name,
1711 texts[uinfo->value.enumerated. 1709 texts[uinfo->value.enumerated.item]);
1712 return 0; 1710 return 0;
1713 } 1711 }
1714 static int 1712 static int
1715 snd_rme32_get_clockmode_control(struct snd_kc 1713 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1716 struct snd_ct 1714 struct snd_ctl_elem_value *ucontrol)
1717 { 1715 {
1718 struct rme32 *rme32 = snd_kcontrol_ch 1716 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1719 1717
1720 spin_lock_irq(&rme32->lock); 1718 spin_lock_irq(&rme32->lock);
1721 ucontrol->value.enumerated.item[0] = 1719 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1722 spin_unlock_irq(&rme32->lock); 1720 spin_unlock_irq(&rme32->lock);
1723 return 0; 1721 return 0;
1724 } 1722 }
1725 static int 1723 static int
1726 snd_rme32_put_clockmode_control(struct snd_kc 1724 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1727 struct snd_ct 1725 struct snd_ctl_elem_value *ucontrol)
1728 { 1726 {
1729 struct rme32 *rme32 = snd_kcontrol_ch 1727 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1730 unsigned int val; 1728 unsigned int val;
1731 int change; 1729 int change;
1732 1730
1733 val = ucontrol->value.enumerated.item 1731 val = ucontrol->value.enumerated.item[0] % 3;
1734 spin_lock_irq(&rme32->lock); 1732 spin_lock_irq(&rme32->lock);
1735 change = val != (unsigned int)snd_rme 1733 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1736 snd_rme32_setclockmode(rme32, val); 1734 snd_rme32_setclockmode(rme32, val);
1737 spin_unlock_irq(&rme32->lock); 1735 spin_unlock_irq(&rme32->lock);
1738 return change; 1736 return change;
1739 } 1737 }
1740 1738
1741 static u32 snd_rme32_convert_from_aes(struct 1739 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1742 { 1740 {
1743 u32 val = 0; 1741 u32 val = 0;
1744 val |= (aes->status[0] & IEC958_AES0_ 1742 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1745 if (val & RME32_WCR_PRO) 1743 if (val & RME32_WCR_PRO)
1746 val |= (aes->status[0] & IEC9 1744 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1747 else 1745 else
1748 val |= (aes->status[0] & IEC9 1746 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1749 return val; 1747 return val;
1750 } 1748 }
1751 1749
1752 static void snd_rme32_convert_to_aes(struct s 1750 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1753 { 1751 {
1754 aes->status[0] = ((val & RME32_WCR_PR 1752 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1755 if (val & RME32_WCR_PRO) 1753 if (val & RME32_WCR_PRO)
1756 aes->status[0] |= (val & RME3 1754 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1757 else 1755 else
1758 aes->status[0] |= (val & RME3 1756 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1759 } 1757 }
1760 1758
1761 static int snd_rme32_control_spdif_info(struc 1759 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1762 struc 1760 struct snd_ctl_elem_info *uinfo)
1763 { 1761 {
1764 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC 1762 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1765 uinfo->count = 1; 1763 uinfo->count = 1;
1766 return 0; 1764 return 0;
1767 } 1765 }
1768 1766
1769 static int snd_rme32_control_spdif_get(struct 1767 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1770 struct 1768 struct snd_ctl_elem_value *ucontrol)
1771 { 1769 {
1772 struct rme32 *rme32 = snd_kcontrol_ch 1770 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1773 1771
1774 snd_rme32_convert_to_aes(&ucontrol->v 1772 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1775 rme32->wcreg 1773 rme32->wcreg_spdif);
1776 return 0; 1774 return 0;
1777 } 1775 }
1778 1776
1779 static int snd_rme32_control_spdif_put(struct 1777 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1780 struct 1778 struct snd_ctl_elem_value *ucontrol)
1781 { 1779 {
1782 struct rme32 *rme32 = snd_kcontrol_ch 1780 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1783 int change; 1781 int change;
1784 u32 val; 1782 u32 val;
1785 1783
1786 val = snd_rme32_convert_from_aes(&uco 1784 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1787 spin_lock_irq(&rme32->lock); 1785 spin_lock_irq(&rme32->lock);
1788 change = val != rme32->wcreg_spdif; 1786 change = val != rme32->wcreg_spdif;
1789 rme32->wcreg_spdif = val; 1787 rme32->wcreg_spdif = val;
1790 spin_unlock_irq(&rme32->lock); 1788 spin_unlock_irq(&rme32->lock);
1791 return change; 1789 return change;
1792 } 1790 }
1793 1791
1794 static int snd_rme32_control_spdif_stream_inf 1792 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1795 1793 struct snd_ctl_elem_info *uinfo)
1796 { 1794 {
1797 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC 1795 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1798 uinfo->count = 1; 1796 uinfo->count = 1;
1799 return 0; 1797 return 0;
1800 } 1798 }
1801 1799
1802 static int snd_rme32_control_spdif_stream_get 1800 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1803 1801 struct snd_ctl_elem_value *
1804 1802 ucontrol)
1805 { 1803 {
1806 struct rme32 *rme32 = snd_kcontrol_ch 1804 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1807 1805
1808 snd_rme32_convert_to_aes(&ucontrol->v 1806 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1809 rme32->wcreg 1807 rme32->wcreg_spdif_stream);
1810 return 0; 1808 return 0;
1811 } 1809 }
1812 1810
1813 static int snd_rme32_control_spdif_stream_put 1811 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1814 1812 struct snd_ctl_elem_value *
1815 1813 ucontrol)
1816 { 1814 {
1817 struct rme32 *rme32 = snd_kcontrol_ch 1815 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1818 int change; 1816 int change;
1819 u32 val; 1817 u32 val;
1820 1818
1821 val = snd_rme32_convert_from_aes(&uco 1819 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1822 spin_lock_irq(&rme32->lock); 1820 spin_lock_irq(&rme32->lock);
1823 change = val != rme32->wcreg_spdif_st 1821 change = val != rme32->wcreg_spdif_stream;
1824 rme32->wcreg_spdif_stream = val; 1822 rme32->wcreg_spdif_stream = val;
1825 rme32->wcreg &= ~(RME32_WCR_PRO | RME 1823 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1826 rme32->wcreg |= val; 1824 rme32->wcreg |= val;
1827 writel(rme32->wcreg, rme32->iobase + 1825 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1828 spin_unlock_irq(&rme32->lock); 1826 spin_unlock_irq(&rme32->lock);
1829 return change; 1827 return change;
1830 } 1828 }
1831 1829
1832 static int snd_rme32_control_spdif_mask_info( 1830 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1833 1831 struct snd_ctl_elem_info *uinfo)
1834 { 1832 {
1835 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC 1833 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1836 uinfo->count = 1; 1834 uinfo->count = 1;
1837 return 0; 1835 return 0;
1838 } 1836 }
1839 1837
1840 static int snd_rme32_control_spdif_mask_get(s 1838 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1841 s 1839 struct snd_ctl_elem_value *
1842 u 1840 ucontrol)
1843 { 1841 {
1844 ucontrol->value.iec958.status[0] = kc 1842 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1845 return 0; 1843 return 0;
1846 } 1844 }
1847 1845
1848 static struct snd_kcontrol_new snd_rme32_cont 1846 static struct snd_kcontrol_new snd_rme32_controls[] = {
1849 { 1847 {
1850 .iface = SNDRV_CTL_ELEM_IFACE 1848 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1851 .name = SNDRV_CTL_NAME_IEC958 1849 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1852 .info = snd_rme32_control_spd 1850 .info = snd_rme32_control_spdif_info,
1853 .get = snd_rme32_control_spd 1851 .get = snd_rme32_control_spdif_get,
1854 .put = snd_rme32_control_spd 1852 .put = snd_rme32_control_spdif_put
1855 }, 1853 },
1856 { 1854 {
1857 .access = SNDRV_CTL_ELEM_ACCE 1855 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1858 .iface = SNDRV_CTL_ELEM_IFACE 1856 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1859 .name = SNDRV_CTL_NAME_IEC958 1857 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1860 .info = snd_rme32_control_spd 1858 .info = snd_rme32_control_spdif_stream_info,
1861 .get = snd_rme32_control_spd 1859 .get = snd_rme32_control_spdif_stream_get,
1862 .put = snd_rme32_control_spd 1860 .put = snd_rme32_control_spdif_stream_put
1863 }, 1861 },
1864 { 1862 {
1865 .access = SNDRV_CTL_ELEM_ACCE 1863 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1866 .iface = SNDRV_CTL_ELEM_IFACE 1864 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1867 .name = SNDRV_CTL_NAME_IEC958 1865 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1868 .info = snd_rme32_control_spd 1866 .info = snd_rme32_control_spdif_mask_info,
1869 .get = snd_rme32_control_spd 1867 .get = snd_rme32_control_spdif_mask_get,
1870 .private_value = IEC958_AES0_ 1868 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1871 }, 1869 },
1872 { 1870 {
1873 .access = SNDRV_CTL_ELEM_ACCE 1871 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1874 .iface = SNDRV_CTL_ELEM_IFACE 1872 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1875 .name = SNDRV_CTL_NAME_IEC958 1873 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1876 .info = snd_rme32_control_spd 1874 .info = snd_rme32_control_spdif_mask_info,
1877 .get = snd_rme32_control_spd 1875 .get = snd_rme32_control_spdif_mask_get,
1878 .private_value = IEC958_AES0_ 1876 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1879 }, 1877 },
1880 { 1878 {
1881 .iface = SNDRV_CTL_ELEM_IFACE 1879 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1882 .name = "Input Connector", 1880 .name = "Input Connector",
1883 .info = snd_rme32_info_inputt 1881 .info = snd_rme32_info_inputtype_control,
1884 .get = snd_rme32_get_inputty 1882 .get = snd_rme32_get_inputtype_control,
1885 .put = snd_rme32_put_inputty 1883 .put = snd_rme32_put_inputtype_control
1886 }, 1884 },
1887 { 1885 {
1888 .iface = SNDRV_CTL_ELEM_IFACE 1886 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1889 .name = "Loopback Input", 1887 .name = "Loopback Input",
1890 .info = snd_rme32_info_loopba 1888 .info = snd_rme32_info_loopback_control,
1891 .get = snd_rme32_get_loopbac 1889 .get = snd_rme32_get_loopback_control,
1892 .put = snd_rme32_put_loopbac 1890 .put = snd_rme32_put_loopback_control
1893 }, 1891 },
1894 { 1892 {
1895 .iface = SNDRV_CTL_ELEM_IFACE 1893 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1896 .name = "Sample Clock Source" 1894 .name = "Sample Clock Source",
1897 .info = snd_rme32_info_clockm 1895 .info = snd_rme32_info_clockmode_control,
1898 .get = snd_rme32_get_clockmo 1896 .get = snd_rme32_get_clockmode_control,
1899 .put = snd_rme32_put_clockmo 1897 .put = snd_rme32_put_clockmode_control
1900 } 1898 }
1901 }; 1899 };
1902 1900
1903 static int snd_rme32_create_switches(struct s 1901 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1904 { 1902 {
1905 int idx, err; 1903 int idx, err;
1906 struct snd_kcontrol *kctl; 1904 struct snd_kcontrol *kctl;
1907 1905
1908 for (idx = 0; idx < (int)ARRAY_SIZE(s 1906 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1909 if ((err = snd_ctl_add(card, 1907 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1910 return err; 1908 return err;
1911 if (idx == 1) /* IEC958 (S/ 1909 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1912 rme32->spdif_ctl = kc 1910 rme32->spdif_ctl = kctl;
1913 } 1911 }
1914 1912
1915 return 0; 1913 return 0;
1916 } 1914 }
1917 1915
1918 /* 1916 /*
1919 * Card initialisation 1917 * Card initialisation
1920 */ 1918 */
1921 1919
1922 static void snd_rme32_card_free(struct snd_ca 1920 static void snd_rme32_card_free(struct snd_card *card)
1923 { 1921 {
1924 snd_rme32_free(card->private_data); 1922 snd_rme32_free(card->private_data);
1925 } 1923 }
1926 1924
1927 static int __devinit 1925 static int __devinit
1928 snd_rme32_probe(struct pci_dev *pci, const st 1926 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1929 { 1927 {
1930 static int dev; 1928 static int dev;
1931 struct rme32 *rme32; 1929 struct rme32 *rme32;
1932 struct snd_card *card; 1930 struct snd_card *card;
1933 int err; 1931 int err;
1934 1932
1935 if (dev >= SNDRV_CARDS) { 1933 if (dev >= SNDRV_CARDS) {
1936 return -ENODEV; 1934 return -ENODEV;
1937 } 1935 }
1938 if (!enable[dev]) { 1936 if (!enable[dev]) {
1939 dev++; 1937 dev++;
1940 return -ENOENT; 1938 return -ENOENT;
1941 } 1939 }
1942 1940
1943 if ((card = snd_card_new(index[dev], !! 1941 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
1944 sizeof(struc !! 1942 sizeof(struct rme32), &card);
1945 return -ENOMEM; !! 1943 if (err < 0)
>> 1944 return err;
1946 card->private_free = snd_rme32_card_f 1945 card->private_free = snd_rme32_card_free;
1947 rme32 = (struct rme32 *) card->privat 1946 rme32 = (struct rme32 *) card->private_data;
1948 rme32->card = card; 1947 rme32->card = card;
1949 rme32->pci = pci; 1948 rme32->pci = pci;
1950 snd_card_set_dev(card, &pci->dev); 1949 snd_card_set_dev(card, &pci->dev);
1951 if (fullduplex[dev]) 1950 if (fullduplex[dev])
1952 rme32->fullduplex_mode = 1; 1951 rme32->fullduplex_mode = 1;
1953 if ((err = snd_rme32_create(rme32)) < 1952 if ((err = snd_rme32_create(rme32)) < 0) {
1954 snd_card_free(card); 1953 snd_card_free(card);
1955 return err; 1954 return err;
1956 } 1955 }
1957 1956
1958 strcpy(card->driver, "Digi32"); 1957 strcpy(card->driver, "Digi32");
1959 switch (rme32->pci->device) { 1958 switch (rme32->pci->device) {
1960 case PCI_DEVICE_ID_RME_DIGI32: 1959 case PCI_DEVICE_ID_RME_DIGI32:
1961 strcpy(card->shortname, "RME 1960 strcpy(card->shortname, "RME Digi32");
1962 break; 1961 break;
1963 case PCI_DEVICE_ID_RME_DIGI32_8: 1962 case PCI_DEVICE_ID_RME_DIGI32_8:
1964 strcpy(card->shortname, "RME 1963 strcpy(card->shortname, "RME Digi32/8");
1965 break; 1964 break;
1966 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1965 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1967 strcpy(card->shortname, "RME 1966 strcpy(card->shortname, "RME Digi32 PRO");
1968 break; 1967 break;
1969 } 1968 }
1970 sprintf(card->longname, "%s (Rev. %d) 1969 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1971 card->shortname, rme32->rev, 1970 card->shortname, rme32->rev, rme32->port, rme32->irq);
1972 1971
1973 if ((err = snd_card_register(card)) < 1972 if ((err = snd_card_register(card)) < 0) {
1974 snd_card_free(card); 1973 snd_card_free(card);
1975 return err; 1974 return err;
1976 } 1975 }
1977 pci_set_drvdata(pci, card); 1976 pci_set_drvdata(pci, card);
1978 dev++; 1977 dev++;
1979 return 0; 1978 return 0;
1980 } 1979 }
1981 1980
1982 static void __devexit snd_rme32_remove(struct 1981 static void __devexit snd_rme32_remove(struct pci_dev *pci)
1983 { 1982 {
1984 snd_card_free(pci_get_drvdata(pci)); 1983 snd_card_free(pci_get_drvdata(pci));
1985 pci_set_drvdata(pci, NULL); 1984 pci_set_drvdata(pci, NULL);
1986 } 1985 }
1987 1986
1988 static struct pci_driver driver = { 1987 static struct pci_driver driver = {
1989 .name = "RME Digi32", 1988 .name = "RME Digi32",
1990 .id_table = snd_rme32_ids, 1989 .id_table = snd_rme32_ids,
1991 .probe = snd_rme32_probe, 1990 .probe = snd_rme32_probe,
1992 .remove = __devexit_p(snd_rme32 1991 .remove = __devexit_p(snd_rme32_remove),
1993 }; 1992 };
1994 1993
1995 static int __init alsa_card_rme32_init(void) 1994 static int __init alsa_card_rme32_init(void)
1996 { 1995 {
1997 return pci_register_driver(&driver); 1996 return pci_register_driver(&driver);
1998 } 1997 }
1999 1998
2000 static void __exit alsa_card_rme32_exit(void) 1999 static void __exit alsa_card_rme32_exit(void)
2001 { 2000 {
2002 pci_unregister_driver(&driver); 2001 pci_unregister_driver(&driver);
2003 } 2002 }
2004 2003
2005 module_init(alsa_card_rme32_init) 2004 module_init(alsa_card_rme32_init)
2006 module_exit(alsa_card_rme32_exit) 2005 module_exit(alsa_card_rme32_exit)
2007 2006
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