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1 /* 1 /*
2 * ALSA driver for ICEnsemble ICE1724 (Envy2 2 * ALSA driver for ICEnsemble ICE1724 (Envy24)
3 * 3 *
4 * Lowlevel functions for Terratec PHASE 22 4 * Lowlevel functions for Terratec PHASE 22
5 * 5 *
6 * Copyright (c) 2005 Misha Zhilin <misha 6 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
7 * 7 *
8 * This program is free software; you can re 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Pub 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either vers 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope t 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even th 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICUL 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more detai 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GN 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * 21 *
22 */ 22 */
23 23
24 /* PHASE 22 overview: 24 /* PHASE 22 overview:
25 * Audio controller: VIA Envy24HT-S (slightl !! 25 * Audio controller: VIA Envy24HT-S (slightly trimmed down version of Envy24HT)
26 * Analog chip: AK4524 (partially via Philip 26 * Analog chip: AK4524 (partially via Philip's 74HCT125)
27 * Digital receiver: CS8414-CS (supported in !! 27 * Digital receiver: CS8414-CS (not supported in this release)
28 * PHASE 22 revision 2.0 and Terr <<
29 * (support status unknown, pleas <<
30 * 28 *
31 * Envy connects to AK4524 29 * Envy connects to AK4524
32 * - CS directly from GPIO 10 30 * - CS directly from GPIO 10
33 * - CCLK via 74HCT125's gate #4 from GPI 31 * - CCLK via 74HCT125's gate #4 from GPIO 4
34 * - CDTI via 74HCT125's gate #2 from GPI 32 * - CDTI via 74HCT125's gate #2 from GPIO 5
35 * CDTI may be completely blocked !! 33 * CDTI may be completely blocked by 74HCT125's gate #1 controlled by GPIO 3
36 * controlled by GPIO 3 <<
37 */ <<
38 <<
39 /* PHASE 28 overview: <<
40 * Audio controller: VIA Envy24HT (full untr <<
41 * Analog chip: WM8770 (8 channel 192k DAC, <<
42 * Digital receiver: CS8414-CS (supported in <<
43 */ 34 */
44 35
45 #include <asm/io.h> 36 #include <asm/io.h>
46 #include <linux/delay.h> 37 #include <linux/delay.h>
47 #include <linux/interrupt.h> 38 #include <linux/interrupt.h>
48 #include <linux/init.h> 39 #include <linux/init.h>
49 #include <linux/slab.h> 40 #include <linux/slab.h>
50 #include <linux/mutex.h> 41 #include <linux/mutex.h>
51 42
52 #include <sound/core.h> 43 #include <sound/core.h>
53 44
54 #include "ice1712.h" 45 #include "ice1712.h"
55 #include "envy24ht.h" 46 #include "envy24ht.h"
56 #include "phase.h" 47 #include "phase.h"
57 #include <sound/tlv.h> 48 #include <sound/tlv.h>
58 49
59 /* AC97 register cache for Phase28 */ 50 /* AC97 register cache for Phase28 */
60 struct phase28_spec { 51 struct phase28_spec {
61 unsigned short master[2]; 52 unsigned short master[2];
62 unsigned short vol[8]; 53 unsigned short vol[8];
63 }; 54 };
64 55
65 /* WM8770 registers */ 56 /* WM8770 registers */
66 #define WM_DAC_ATTEN 0x00 /* DAC 57 #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
67 #define WM_DAC_MASTER_ATTEN 0x08 /* DAC 58 #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
68 #define WM_DAC_DIG_ATTEN 0x09 /* DAC 59 #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
69 #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC 60 #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
70 #define WM_PHASE_SWAP 0x12 /* DAC 61 #define WM_PHASE_SWAP 0x12 /* DAC phase */
71 #define WM_DAC_CTRL1 0x13 /* DAC 62 #define WM_DAC_CTRL1 0x13 /* DAC control bits */
72 #define WM_MUTE 0x14 /* mut 63 #define WM_MUTE 0x14 /* mute controls */
73 #define WM_DAC_CTRL2 0x15 /* de- 64 #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
74 #define WM_INT_CTRL 0x16 /* int 65 #define WM_INT_CTRL 0x16 /* interface control */
75 #define WM_MASTER 0x17 /* mas 66 #define WM_MASTER 0x17 /* master clock and mode */
76 #define WM_POWERDOWN 0x18 /* pow 67 #define WM_POWERDOWN 0x18 /* power-down controls */
77 #define WM_ADC_GAIN 0x19 /* ADC 68 #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
78 #define WM_ADC_MUX 0x1b /* inp 69 #define WM_ADC_MUX 0x1b /* input MUX */
79 #define WM_OUT_MUX1 0x1c /* out 70 #define WM_OUT_MUX1 0x1c /* output MUX */
80 #define WM_OUT_MUX2 0x1e /* out 71 #define WM_OUT_MUX2 0x1e /* output MUX */
81 #define WM_RESET 0x1f /* sof 72 #define WM_RESET 0x1f /* software reset */
82 73
83 74
84 /* 75 /*
85 * Logarithmic volume values for WM8770 76 * Logarithmic volume values for WM8770
86 * Computed as 20 * Log10(255 / x) 77 * Computed as 20 * Log10(255 / x)
87 */ 78 */
88 static const unsigned char wm_vol[256] = { 79 static const unsigned char wm_vol[256] = {
89 127, 48, 42, 39, 36, 34, 33, 31, 30, 2 !! 80 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24, 24, 23,
90 24, 23, 23, 22, 22, 21, 21, 21, 20, 20 !! 81 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17,
91 17, 17, 17, 17, 16, 16, 16, 16, 15, 15 !! 82 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 13, 13, 13,
92 14, 13, 13, 13, 13, 13, 13, 13, 12, 12 !! 83 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11,
93 11, 11, 11, 11, 11, 11, 10, 10, 10, 10 !! 84 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
94 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, !! 85 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
95 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, !! 86 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, !! 87 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3,
97 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, !! 88 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
98 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, !! 89 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
99 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, !! 90 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
100 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, !! 91 0, 0
101 }; 92 };
102 93
103 #define WM_VOL_MAX (sizeof(wm_vol) - 1) 94 #define WM_VOL_MAX (sizeof(wm_vol) - 1)
104 #define WM_VOL_MUTE 0x8000 95 #define WM_VOL_MUTE 0x8000
105 96
106 static struct snd_akm4xxx akm_phase22 __devini 97 static struct snd_akm4xxx akm_phase22 __devinitdata = {
107 .type = SND_AK4524, 98 .type = SND_AK4524,
108 .num_dacs = 2, 99 .num_dacs = 2,
109 .num_adcs = 2, 100 .num_adcs = 2,
110 }; 101 };
111 102
112 static struct snd_ak4xxx_private akm_phase22_p 103 static struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
113 .caddr = 2, 104 .caddr = 2,
114 .cif = 1, 105 .cif = 1,
115 .data_mask = 1 << 4, 106 .data_mask = 1 << 4,
116 .clk_mask = 1 << 5, 107 .clk_mask = 1 << 5,
117 .cs_mask = 1 << 10, 108 .cs_mask = 1 << 10,
118 .cs_addr = 1 << 10, 109 .cs_addr = 1 << 10,
119 .cs_none = 0, 110 .cs_none = 0,
120 .add_flags = 1 << 3, 111 .add_flags = 1 << 3,
121 .mask_flags = 0, 112 .mask_flags = 0,
122 }; 113 };
123 114
124 static int __devinit phase22_init(struct snd_i 115 static int __devinit phase22_init(struct snd_ice1712 *ice)
125 { 116 {
126 struct snd_akm4xxx *ak; 117 struct snd_akm4xxx *ak;
127 int err; 118 int err;
128 119
129 /* Configure DAC/ADC description for g !! 120 // Configure DAC/ADC description for generic part of ice1724
130 switch (ice->eeprom.subvendor) { 121 switch (ice->eeprom.subvendor) {
131 case VT1724_SUBDEVICE_PHASE22: 122 case VT1724_SUBDEVICE_PHASE22:
132 case VT1724_SUBDEVICE_TS22: <<
133 ice->num_total_dacs = 2; 123 ice->num_total_dacs = 2;
134 ice->num_total_adcs = 2; 124 ice->num_total_adcs = 2;
135 ice->vt1720 = 1; /* Envy24HT-S !! 125 ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
136 break; 126 break;
137 default: 127 default:
138 snd_BUG(); 128 snd_BUG();
139 return -EINVAL; 129 return -EINVAL;
140 } 130 }
141 131
142 /* Initialize analog chips */ !! 132 // Initialize analog chips
143 ice->akm = kzalloc(sizeof(struct snd_a !! 133 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
144 ak = ice->akm; !! 134 if (! ak)
145 if (!ak) <<
146 return -ENOMEM; 135 return -ENOMEM;
147 ice->akm_codecs = 1; 136 ice->akm_codecs = 1;
148 switch (ice->eeprom.subvendor) { 137 switch (ice->eeprom.subvendor) {
149 case VT1724_SUBDEVICE_PHASE22: 138 case VT1724_SUBDEVICE_PHASE22:
150 case VT1724_SUBDEVICE_TS22: !! 139 if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
151 err = snd_ice1712_akm4xxx_init <<
152 <<
153 if (err < 0) <<
154 return err; 140 return err;
155 break; 141 break;
156 } 142 }
157 143
158 return 0; 144 return 0;
159 } 145 }
160 146
161 static int __devinit phase22_add_controls(stru 147 static int __devinit phase22_add_controls(struct snd_ice1712 *ice)
162 { 148 {
163 int err = 0; 149 int err = 0;
164 150
165 switch (ice->eeprom.subvendor) { 151 switch (ice->eeprom.subvendor) {
166 case VT1724_SUBDEVICE_PHASE22: 152 case VT1724_SUBDEVICE_PHASE22:
167 case VT1724_SUBDEVICE_TS22: <<
168 err = snd_ice1712_akm4xxx_buil 153 err = snd_ice1712_akm4xxx_build_controls(ice);
169 if (err < 0) 154 if (err < 0)
170 return err; 155 return err;
171 } 156 }
172 return 0; 157 return 0;
173 } 158 }
174 159
175 static unsigned char phase22_eeprom[] __devini 160 static unsigned char phase22_eeprom[] __devinitdata = {
176 [ICE_EEP2_SYSCONF] = 0x28, /* clo !! 161 [ICE_EEP2_SYSCONF] = 0x00, /* 1xADC, 1xDACs */
177 spdif- <<
178 [ICE_EEP2_ACLINK] = 0x80, /* I2S 162 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
179 [ICE_EEP2_I2S] = 0xf0, /* vol !! 163 [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit */
180 [ICE_EEP2_SPDIF] = 0xc3, /* out 164 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
181 [ICE_EEP2_GPIO_DIR] = 0xff, 165 [ICE_EEP2_GPIO_DIR] = 0xff,
182 [ICE_EEP2_GPIO_DIR1] = 0xff, 166 [ICE_EEP2_GPIO_DIR1] = 0xff,
183 [ICE_EEP2_GPIO_DIR2] = 0xff, 167 [ICE_EEP2_GPIO_DIR2] = 0xff,
184 [ICE_EEP2_GPIO_MASK] = 0x00, 168 [ICE_EEP2_GPIO_MASK] = 0x00,
185 [ICE_EEP2_GPIO_MASK1] = 0x00, 169 [ICE_EEP2_GPIO_MASK1] = 0x00,
186 [ICE_EEP2_GPIO_MASK2] = 0x00, 170 [ICE_EEP2_GPIO_MASK2] = 0x00,
187 [ICE_EEP2_GPIO_STATE] = 0x00, 171 [ICE_EEP2_GPIO_STATE] = 0x00,
188 [ICE_EEP2_GPIO_STATE1] = 0x00, 172 [ICE_EEP2_GPIO_STATE1] = 0x00,
189 [ICE_EEP2_GPIO_STATE2] = 0x00, 173 [ICE_EEP2_GPIO_STATE2] = 0x00,
190 }; 174 };
191 175
192 static unsigned char phase28_eeprom[] __devini 176 static unsigned char phase28_eeprom[] __devinitdata = {
193 [ICE_EEP2_SYSCONF] = 0x2b, /* clo !! 177 [ICE_EEP2_SYSCONF] = 0x0b, /* clock 512, spdif-in/ADC, 4DACs */
194 spdif- <<
195 [ICE_EEP2_ACLINK] = 0x80, /* I2S 178 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
196 [ICE_EEP2_I2S] = 0xfc, /* vol 179 [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
197 [ICE_EEP2_SPDIF] = 0xc3, /* out 180 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
198 [ICE_EEP2_GPIO_DIR] = 0xff, 181 [ICE_EEP2_GPIO_DIR] = 0xff,
199 [ICE_EEP2_GPIO_DIR1] = 0xff, 182 [ICE_EEP2_GPIO_DIR1] = 0xff,
200 [ICE_EEP2_GPIO_DIR2] = 0x5f, 183 [ICE_EEP2_GPIO_DIR2] = 0x5f,
201 [ICE_EEP2_GPIO_MASK] = 0x00, 184 [ICE_EEP2_GPIO_MASK] = 0x00,
202 [ICE_EEP2_GPIO_MASK1] = 0x00, 185 [ICE_EEP2_GPIO_MASK1] = 0x00,
203 [ICE_EEP2_GPIO_MASK2] = 0x00, 186 [ICE_EEP2_GPIO_MASK2] = 0x00,
204 [ICE_EEP2_GPIO_STATE] = 0x00, 187 [ICE_EEP2_GPIO_STATE] = 0x00,
205 [ICE_EEP2_GPIO_STATE1] = 0x00, 188 [ICE_EEP2_GPIO_STATE1] = 0x00,
206 [ICE_EEP2_GPIO_STATE2] = 0x00, 189 [ICE_EEP2_GPIO_STATE2] = 0x00,
207 }; 190 };
208 191
209 /* 192 /*
210 * write data in the SPI mode 193 * write data in the SPI mode
211 */ 194 */
212 static void phase28_spi_write(struct snd_ice17 !! 195 static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
213 unsigned int d <<
214 { 196 {
215 unsigned int tmp; 197 unsigned int tmp;
216 int i; 198 int i;
217 199
218 tmp = snd_ice1712_gpio_read(ice); 200 tmp = snd_ice1712_gpio_read(ice);
219 201
220 snd_ice1712_gpio_set_mask(ice, ~(PHASE !! 202 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|PHASE28_SPI_CLK|
221 PHASE2 !! 203 PHASE28_WM_CS));
222 tmp |= PHASE28_WM_RW; 204 tmp |= PHASE28_WM_RW;
223 tmp &= ~cs; 205 tmp &= ~cs;
224 snd_ice1712_gpio_write(ice, tmp); 206 snd_ice1712_gpio_write(ice, tmp);
225 udelay(1); 207 udelay(1);
226 208
227 for (i = bits - 1; i >= 0; i--) { 209 for (i = bits - 1; i >= 0; i--) {
228 tmp &= ~PHASE28_SPI_CLK; 210 tmp &= ~PHASE28_SPI_CLK;
229 snd_ice1712_gpio_write(ice, tm 211 snd_ice1712_gpio_write(ice, tmp);
230 udelay(1); 212 udelay(1);
231 if (data & (1 << i)) 213 if (data & (1 << i))
232 tmp |= PHASE28_SPI_MOS 214 tmp |= PHASE28_SPI_MOSI;
233 else 215 else
234 tmp &= ~PHASE28_SPI_MO 216 tmp &= ~PHASE28_SPI_MOSI;
235 snd_ice1712_gpio_write(ice, tm 217 snd_ice1712_gpio_write(ice, tmp);
236 udelay(1); 218 udelay(1);
237 tmp |= PHASE28_SPI_CLK; 219 tmp |= PHASE28_SPI_CLK;
238 snd_ice1712_gpio_write(ice, tm 220 snd_ice1712_gpio_write(ice, tmp);
239 udelay(1); 221 udelay(1);
240 } 222 }
241 223
242 tmp &= ~PHASE28_SPI_CLK; 224 tmp &= ~PHASE28_SPI_CLK;
243 tmp |= cs; 225 tmp |= cs;
244 snd_ice1712_gpio_write(ice, tmp); 226 snd_ice1712_gpio_write(ice, tmp);
245 udelay(1); 227 udelay(1);
246 tmp |= PHASE28_SPI_CLK; 228 tmp |= PHASE28_SPI_CLK;
247 snd_ice1712_gpio_write(ice, tmp); 229 snd_ice1712_gpio_write(ice, tmp);
248 udelay(1); 230 udelay(1);
249 } 231 }
250 232
251 /* 233 /*
252 * get the current register value of WM codec 234 * get the current register value of WM codec
253 */ 235 */
254 static unsigned short wm_get(struct snd_ice171 236 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
255 { 237 {
256 reg <<= 1; 238 reg <<= 1;
257 return ((unsigned short)ice->akm[0].im 239 return ((unsigned short)ice->akm[0].images[reg] << 8) |
258 ice->akm[0].images[reg + 1]; 240 ice->akm[0].images[reg + 1];
259 } 241 }
260 242
261 /* 243 /*
262 * set the register value of WM codec 244 * set the register value of WM codec
263 */ 245 */
264 static void wm_put_nocache(struct snd_ice1712 246 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
265 { 247 {
266 phase28_spi_write(ice, PHASE28_WM_CS, 248 phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
267 } 249 }
268 250
269 /* 251 /*
270 * set the register value of WM codec and reme 252 * set the register value of WM codec and remember it
271 */ 253 */
272 static void wm_put(struct snd_ice1712 *ice, in 254 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
273 { 255 {
274 wm_put_nocache(ice, reg, val); 256 wm_put_nocache(ice, reg, val);
275 reg <<= 1; 257 reg <<= 1;
276 ice->akm[0].images[reg] = val >> 8; 258 ice->akm[0].images[reg] = val >> 8;
277 ice->akm[0].images[reg + 1] = val; 259 ice->akm[0].images[reg + 1] = val;
278 } 260 }
279 261
280 static void wm_set_vol(struct snd_ice1712 *ice !! 262 static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
281 unsigned short vol, un <<
282 { 263 {
283 unsigned char nvol; 264 unsigned char nvol;
284 265
285 if ((master & WM_VOL_MUTE) || (vol & W 266 if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
286 nvol = 0; 267 nvol = 0;
287 else 268 else
288 nvol = 127 - wm_vol[(((vol & ~ !! 269 nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
289 (master & ~WM_VOL_MUTE <<
290 270
291 wm_put(ice, index, nvol); 271 wm_put(ice, index, nvol);
292 wm_put_nocache(ice, index, 0x180 | nvo 272 wm_put_nocache(ice, index, 0x180 | nvol);
293 } 273 }
294 274
295 /* 275 /*
296 * DAC mute control 276 * DAC mute control
297 */ 277 */
298 #define wm_pcm_mute_info snd_ctl_boolea 278 #define wm_pcm_mute_info snd_ctl_boolean_mono_info
299 279
300 static int wm_pcm_mute_get(struct snd_kcontrol !! 280 static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
301 struct snd_ctl <<
302 { 281 {
303 struct snd_ice1712 *ice = snd_kcontrol 282 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
304 283
305 mutex_lock(&ice->gpio_mutex); 284 mutex_lock(&ice->gpio_mutex);
306 ucontrol->value.integer.value[0] = (wm !! 285 ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
307 <<
308 mutex_unlock(&ice->gpio_mutex); 286 mutex_unlock(&ice->gpio_mutex);
309 return 0; 287 return 0;
310 } 288 }
311 289
312 static int wm_pcm_mute_put(struct snd_kcontrol !! 290 static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
313 struct snd_ctl <<
314 { 291 {
315 struct snd_ice1712 *ice = snd_kcontrol 292 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
316 unsigned short nval, oval; 293 unsigned short nval, oval;
317 int change; 294 int change;
318 295
319 snd_ice1712_save_gpio_status(ice); 296 snd_ice1712_save_gpio_status(ice);
320 oval = wm_get(ice, WM_MUTE); 297 oval = wm_get(ice, WM_MUTE);
321 nval = (oval & ~0x10) | (ucontrol->val 298 nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
322 change = (nval != oval); !! 299 if ((change = (nval != oval)))
323 if (change) <<
324 wm_put(ice, WM_MUTE, nval); 300 wm_put(ice, WM_MUTE, nval);
325 snd_ice1712_restore_gpio_status(ice); 301 snd_ice1712_restore_gpio_status(ice);
326 302
327 return change; 303 return change;
328 } 304 }
329 305
330 /* 306 /*
331 * Master volume attenuation mixer control 307 * Master volume attenuation mixer control
332 */ 308 */
333 static int wm_master_vol_info(struct snd_kcont !! 309 static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
334 struct snd_ctl <<
335 { 310 {
336 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTE 311 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
337 uinfo->count = 2; 312 uinfo->count = 2;
338 uinfo->value.integer.min = 0; 313 uinfo->value.integer.min = 0;
339 uinfo->value.integer.max = WM_VOL_MAX; 314 uinfo->value.integer.max = WM_VOL_MAX;
340 return 0; 315 return 0;
341 } 316 }
342 317
343 static int wm_master_vol_get(struct snd_kcontr !! 318 static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
344 struct snd_ctl <<
345 { 319 {
346 struct snd_ice1712 *ice = snd_kcontrol 320 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
347 struct phase28_spec *spec = ice->spec; 321 struct phase28_spec *spec = ice->spec;
348 int i; 322 int i;
349 for (i = 0; i < 2; i++) !! 323 for (i=0; i<2; i++)
350 ucontrol->value.integer.value[ !! 324 ucontrol->value.integer.value[i] = spec->master[i] & ~WM_VOL_MUTE;
351 <<
352 return 0; 325 return 0;
353 } 326 }
354 327
355 static int wm_master_vol_put(struct snd_kcontr !! 328 static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
356 struct snd_ctl <<
357 { 329 {
358 struct snd_ice1712 *ice = snd_kcontrol 330 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
359 struct phase28_spec *spec = ice->spec; 331 struct phase28_spec *spec = ice->spec;
360 int ch, change = 0; 332 int ch, change = 0;
361 333
362 snd_ice1712_save_gpio_status(ice); 334 snd_ice1712_save_gpio_status(ice);
363 for (ch = 0; ch < 2; ch++) { 335 for (ch = 0; ch < 2; ch++) {
364 unsigned int vol = ucontrol->v 336 unsigned int vol = ucontrol->value.integer.value[ch];
365 if (vol > WM_VOL_MAX) 337 if (vol > WM_VOL_MAX)
366 continue; 338 continue;
367 vol |= spec->master[ch] & WM_V 339 vol |= spec->master[ch] & WM_VOL_MUTE;
368 if (vol != spec->master[ch]) { 340 if (vol != spec->master[ch]) {
369 int dac; 341 int dac;
370 spec->master[ch] = vol 342 spec->master[ch] = vol;
371 for (dac = 0; dac < ic 343 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
372 wm_set_vol(ice 344 wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
373 spe 345 spec->vol[dac + ch],
374 spe 346 spec->master[ch]);
375 change = 1; 347 change = 1;
376 } 348 }
377 } 349 }
378 snd_ice1712_restore_gpio_status(ice); 350 snd_ice1712_restore_gpio_status(ice);
379 return change; 351 return change;
380 } 352 }
381 353
382 static int __devinit phase28_init(struct snd_i 354 static int __devinit phase28_init(struct snd_ice1712 *ice)
383 { 355 {
384 static const unsigned short wm_inits_p 356 static const unsigned short wm_inits_phase28[] = {
385 /* These come first to reduce 357 /* These come first to reduce init pop noise */
386 0x1b, 0x044, /* ADC Mux (AC !! 358 0x1b, 0x044, /* ADC Mux (AC'97 source) */
387 0x1c, 0x00B, /* Out Mux1 (V !! 359 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
388 0x1d, 0x009, /* Out Mux2 (V !! 360 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
389 !! 361
390 0x18, 0x000, /* All power-u !! 362 0x18, 0x000, /* All power-up */
391 !! 363
392 0x16, 0x122, /* I2S, normal !! 364 0x16, 0x122, /* I2S, normal polarity, 24bit */
393 0x17, 0x022, /* 256fs, slav !! 365 0x17, 0x022, /* 256fs, slave mode */
394 0x00, 0, /* DAC1 analog !! 366 0x00, 0, /* DAC1 analog mute */
395 0x01, 0, /* DAC2 analog !! 367 0x01, 0, /* DAC2 analog mute */
396 0x02, 0, /* DAC3 analog !! 368 0x02, 0, /* DAC3 analog mute */
397 0x03, 0, /* DAC4 analog !! 369 0x03, 0, /* DAC4 analog mute */
398 0x04, 0, /* DAC5 analog !! 370 0x04, 0, /* DAC5 analog mute */
399 0x05, 0, /* DAC6 analog !! 371 0x05, 0, /* DAC6 analog mute */
400 0x06, 0, /* DAC7 analog !! 372 0x06, 0, /* DAC7 analog mute */
401 0x07, 0, /* DAC8 analog !! 373 0x07, 0, /* DAC8 analog mute */
402 0x08, 0x100, /* master anal !! 374 0x08, 0x100, /* master analog mute */
403 0x09, 0xff, /* DAC1 digita !! 375 0x09, 0xff, /* DAC1 digital full */
404 0x0a, 0xff, /* DAC2 digita !! 376 0x0a, 0xff, /* DAC2 digital full */
405 0x0b, 0xff, /* DAC3 digita !! 377 0x0b, 0xff, /* DAC3 digital full */
406 0x0c, 0xff, /* DAC4 digita !! 378 0x0c, 0xff, /* DAC4 digital full */
407 0x0d, 0xff, /* DAC5 digita !! 379 0x0d, 0xff, /* DAC5 digital full */
408 0x0e, 0xff, /* DAC6 digita !! 380 0x0e, 0xff, /* DAC6 digital full */
409 0x0f, 0xff, /* DAC7 digita !! 381 0x0f, 0xff, /* DAC7 digital full */
410 0x10, 0xff, /* DAC8 digita !! 382 0x10, 0xff, /* DAC8 digital full */
411 0x11, 0x1ff, /* master digi !! 383 0x11, 0x1ff, /* master digital full */
412 0x12, 0x000, /* phase norma !! 384 0x12, 0x000, /* phase normal */
413 0x13, 0x090, /* unmute DAC !! 385 0x13, 0x090, /* unmute DAC L/R */
414 0x14, 0x000, /* all unmute !! 386 0x14, 0x000, /* all unmute */
415 0x15, 0x000, /* no deemphas !! 387 0x15, 0x000, /* no deemphasis, no ZFLG */
416 0x19, 0x000, /* -12dB ADC/L !! 388 0x19, 0x000, /* -12dB ADC/L */
417 0x1a, 0x000, /* -12dB ADC/R !! 389 0x1a, 0x000, /* -12dB ADC/R */
418 (unsigned short)-1 390 (unsigned short)-1
419 }; 391 };
420 392
421 unsigned int tmp; 393 unsigned int tmp;
422 struct snd_akm4xxx *ak; 394 struct snd_akm4xxx *ak;
423 struct phase28_spec *spec; 395 struct phase28_spec *spec;
424 const unsigned short *p; 396 const unsigned short *p;
425 int i; 397 int i;
426 398
427 ice->num_total_dacs = 8; 399 ice->num_total_dacs = 8;
428 ice->num_total_adcs = 2; 400 ice->num_total_adcs = 2;
429 401
430 spec = kzalloc(sizeof(*spec), GFP_KERN 402 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
431 if (!spec) 403 if (!spec)
432 return -ENOMEM; 404 return -ENOMEM;
433 ice->spec = spec; 405 ice->spec = spec;
434 406
435 /* Initialize analog chips */ !! 407 // Initialize analog chips
436 ice->akm = kzalloc(sizeof(struct snd_a !! 408 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
437 ak = ice->akm; <<
438 if (!ak) 409 if (!ak)
439 return -ENOMEM; 410 return -ENOMEM;
440 ice->akm_codecs = 1; 411 ice->akm_codecs = 1;
441 412
442 snd_ice1712_gpio_set_dir(ice, 0x5fffff !! 413 snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
443 414
444 /* reset the wm codec as the SPI mode 415 /* reset the wm codec as the SPI mode */
445 snd_ice1712_save_gpio_status(ice); 416 snd_ice1712_save_gpio_status(ice);
446 snd_ice1712_gpio_set_mask(ice, ~(PHASE !! 417 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
447 PHASE2 <<
448 418
449 tmp = snd_ice1712_gpio_read(ice); 419 tmp = snd_ice1712_gpio_read(ice);
450 tmp &= ~PHASE28_WM_RESET; 420 tmp &= ~PHASE28_WM_RESET;
451 snd_ice1712_gpio_write(ice, tmp); 421 snd_ice1712_gpio_write(ice, tmp);
452 udelay(1); 422 udelay(1);
453 tmp |= PHASE28_WM_CS; 423 tmp |= PHASE28_WM_CS;
454 snd_ice1712_gpio_write(ice, tmp); 424 snd_ice1712_gpio_write(ice, tmp);
455 udelay(1); 425 udelay(1);
456 tmp |= PHASE28_WM_RESET; 426 tmp |= PHASE28_WM_RESET;
457 snd_ice1712_gpio_write(ice, tmp); 427 snd_ice1712_gpio_write(ice, tmp);
458 udelay(1); 428 udelay(1);
459 429
460 p = wm_inits_phase28; 430 p = wm_inits_phase28;
461 for (; *p != (unsigned short)-1; p += 431 for (; *p != (unsigned short)-1; p += 2)
462 wm_put(ice, p[0], p[1]); 432 wm_put(ice, p[0], p[1]);
463 433
464 snd_ice1712_restore_gpio_status(ice); 434 snd_ice1712_restore_gpio_status(ice);
465 435
466 spec->master[0] = WM_VOL_MUTE; 436 spec->master[0] = WM_VOL_MUTE;
467 spec->master[1] = WM_VOL_MUTE; 437 spec->master[1] = WM_VOL_MUTE;
468 for (i = 0; i < ice->num_total_dacs; i 438 for (i = 0; i < ice->num_total_dacs; i++) {
469 spec->vol[i] = WM_VOL_MUTE; 439 spec->vol[i] = WM_VOL_MUTE;
470 wm_set_vol(ice, i, spec->vol[i 440 wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
471 } 441 }
472 442
473 return 0; 443 return 0;
474 } 444 }
475 445
476 /* 446 /*
477 * DAC volume attenuation mixer control 447 * DAC volume attenuation mixer control
478 */ 448 */
479 static int wm_vol_info(struct snd_kcontrol *kc !! 449 static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
480 struct snd_ctl_elem_in <<
481 { 450 {
482 int voices = kcontrol->private_value > 451 int voices = kcontrol->private_value >> 8;
483 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTE 452 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
484 uinfo->count = voices; 453 uinfo->count = voices;
485 uinfo->value.integer.min = 0; 454 uinfo->value.integer.min = 0; /* mute (-101dB) */
486 uinfo->value.integer.max = 0x7F; 455 uinfo->value.integer.max = 0x7F; /* 0dB */
487 return 0; 456 return 0;
488 } 457 }
489 458
490 static int wm_vol_get(struct snd_kcontrol *kco !! 459 static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
491 struct snd_ctl_elem_va <<
492 { 460 {
493 struct snd_ice1712 *ice = snd_kcontrol 461 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
494 struct phase28_spec *spec = ice->spec; 462 struct phase28_spec *spec = ice->spec;
495 int i, ofs, voices; 463 int i, ofs, voices;
496 464
497 voices = kcontrol->private_value >> 8; 465 voices = kcontrol->private_value >> 8;
498 ofs = kcontrol->private_value & 0xff; 466 ofs = kcontrol->private_value & 0xff;
499 for (i = 0; i < voices; i++) 467 for (i = 0; i < voices; i++)
500 ucontrol->value.integer.value[ 468 ucontrol->value.integer.value[i] =
501 spec->vol[ofs+i] & ~WM 469 spec->vol[ofs+i] & ~WM_VOL_MUTE;
502 return 0; 470 return 0;
503 } 471 }
504 472
505 static int wm_vol_put(struct snd_kcontrol *kco !! 473 static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
506 struct snd_ctl_elem_va <<
507 { 474 {
508 struct snd_ice1712 *ice = snd_kcontrol 475 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
509 struct phase28_spec *spec = ice->spec; 476 struct phase28_spec *spec = ice->spec;
510 int i, idx, ofs, voices; 477 int i, idx, ofs, voices;
511 int change = 0; 478 int change = 0;
512 479
513 voices = kcontrol->private_value >> 8; 480 voices = kcontrol->private_value >> 8;
514 ofs = kcontrol->private_value & 0xff; 481 ofs = kcontrol->private_value & 0xff;
515 snd_ice1712_save_gpio_status(ice); 482 snd_ice1712_save_gpio_status(ice);
516 for (i = 0; i < voices; i++) { 483 for (i = 0; i < voices; i++) {
517 unsigned int vol; 484 unsigned int vol;
518 vol = ucontrol->value.integer. 485 vol = ucontrol->value.integer.value[i];
519 if (vol > 0x7f) 486 if (vol > 0x7f)
520 continue; 487 continue;
521 vol |= spec->vol[ofs+i] & WM_V 488 vol |= spec->vol[ofs+i] & WM_VOL_MUTE;
522 if (vol != spec->vol[ofs+i]) { 489 if (vol != spec->vol[ofs+i]) {
523 spec->vol[ofs+i] = vol 490 spec->vol[ofs+i] = vol;
524 idx = WM_DAC_ATTEN + 491 idx = WM_DAC_ATTEN + ofs + i;
525 wm_set_vol(ice, idx, s 492 wm_set_vol(ice, idx, spec->vol[ofs+i],
526 spec->maste 493 spec->master[i]);
527 change = 1; 494 change = 1;
528 } 495 }
529 } 496 }
530 snd_ice1712_restore_gpio_status(ice); 497 snd_ice1712_restore_gpio_status(ice);
531 return change; 498 return change;
532 } 499 }
533 500
534 /* 501 /*
535 * WM8770 mute control 502 * WM8770 mute control
536 */ 503 */
537 static int wm_mute_info(struct snd_kcontrol *k !! 504 static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
538 struct snd_ctl_elem_in <<
539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOL 505 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
540 uinfo->count = kcontrol->private_value 506 uinfo->count = kcontrol->private_value >> 8;
541 uinfo->value.integer.min = 0; 507 uinfo->value.integer.min = 0;
542 uinfo->value.integer.max = 1; 508 uinfo->value.integer.max = 1;
543 return 0; 509 return 0;
544 } 510 }
545 511
546 static int wm_mute_get(struct snd_kcontrol *kc !! 512 static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
547 struct snd_ctl_elem_va <<
548 { 513 {
549 struct snd_ice1712 *ice = snd_kcontrol 514 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
550 struct phase28_spec *spec = ice->spec; 515 struct phase28_spec *spec = ice->spec;
551 int voices, ofs, i; 516 int voices, ofs, i;
552 517
553 voices = kcontrol->private_value >> 8; 518 voices = kcontrol->private_value >> 8;
554 ofs = kcontrol->private_value & 0xFF; 519 ofs = kcontrol->private_value & 0xFF;
555 520
556 for (i = 0; i < voices; i++) 521 for (i = 0; i < voices; i++)
557 ucontrol->value.integer.value[ 522 ucontrol->value.integer.value[i] =
558 (spec->vol[ofs+i] & WM 523 (spec->vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
559 return 0; 524 return 0;
560 } 525 }
561 526
562 static int wm_mute_put(struct snd_kcontrol *kc !! 527 static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
563 struct snd_ctl_elem_va <<
564 { 528 {
565 struct snd_ice1712 *ice = snd_kcontrol 529 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
566 struct phase28_spec *spec = ice->spec; 530 struct phase28_spec *spec = ice->spec;
567 int change = 0, voices, ofs, i; 531 int change = 0, voices, ofs, i;
568 532
569 voices = kcontrol->private_value >> 8; 533 voices = kcontrol->private_value >> 8;
570 ofs = kcontrol->private_value & 0xFF; 534 ofs = kcontrol->private_value & 0xFF;
571 535
572 snd_ice1712_save_gpio_status(ice); 536 snd_ice1712_save_gpio_status(ice);
573 for (i = 0; i < voices; i++) { 537 for (i = 0; i < voices; i++) {
574 int val = (spec->vol[ofs + i] 538 int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
575 if (ucontrol->value.integer.va 539 if (ucontrol->value.integer.value[i] != val) {
576 spec->vol[ofs + i] &= 540 spec->vol[ofs + i] &= ~WM_VOL_MUTE;
577 spec->vol[ofs + i] |= 541 spec->vol[ofs + i] |=
578 ucontrol->valu !! 542 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
579 WM_VOL_MUTE; <<
580 wm_set_vol(ice, ofs + 543 wm_set_vol(ice, ofs + i, spec->vol[ofs + i],
581 spec-> !! 544 spec->master[i]);
582 change = 1; 545 change = 1;
583 } 546 }
584 } 547 }
585 snd_ice1712_restore_gpio_status(ice); 548 snd_ice1712_restore_gpio_status(ice);
586 549
587 return change; 550 return change;
588 } 551 }
589 552
590 /* 553 /*
591 * WM8770 master mute control 554 * WM8770 master mute control
592 */ 555 */
593 #define wm_master_mute_info snd_ct 556 #define wm_master_mute_info snd_ctl_boolean_stereo_info
594 557
595 static int wm_master_mute_get(struct snd_kcont !! 558 static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
596 struct snd_ctl <<
597 { 559 {
598 struct snd_ice1712 *ice = snd_kcontrol 560 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
599 struct phase28_spec *spec = ice->spec; 561 struct phase28_spec *spec = ice->spec;
600 562
601 ucontrol->value.integer.value[0] = 563 ucontrol->value.integer.value[0] =
602 (spec->master[0] & WM_VOL_MUTE 564 (spec->master[0] & WM_VOL_MUTE) ? 0 : 1;
603 ucontrol->value.integer.value[1] = 565 ucontrol->value.integer.value[1] =
604 (spec->master[1] & WM_VOL_MUTE 566 (spec->master[1] & WM_VOL_MUTE) ? 0 : 1;
605 return 0; 567 return 0;
606 } 568 }
607 569
608 static int wm_master_mute_put(struct snd_kcont !! 570 static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
609 struct snd_ctl <<
610 { 571 {
611 struct snd_ice1712 *ice = snd_kcontrol 572 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
612 struct phase28_spec *spec = ice->spec; 573 struct phase28_spec *spec = ice->spec;
613 int change = 0, i; 574 int change = 0, i;
614 575
615 snd_ice1712_save_gpio_status(ice); 576 snd_ice1712_save_gpio_status(ice);
616 for (i = 0; i < 2; i++) { 577 for (i = 0; i < 2; i++) {
617 int val = (spec->master[i] & W 578 int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1;
618 if (ucontrol->value.integer.va 579 if (ucontrol->value.integer.value[i] != val) {
619 int dac; 580 int dac;
620 spec->master[i] &= ~WM 581 spec->master[i] &= ~WM_VOL_MUTE;
621 spec->master[i] |= 582 spec->master[i] |=
622 ucontrol->valu !! 583 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
623 WM_VOL_MUTE; <<
624 for (dac = 0; dac < ic 584 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
625 wm_set_vol(ice 585 wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
626 !! 586 spec->vol[dac + i],
627 !! 587 spec->master[i]);
628 change = 1; 588 change = 1;
629 } 589 }
630 } 590 }
631 snd_ice1712_restore_gpio_status(ice); 591 snd_ice1712_restore_gpio_status(ice);
632 592
633 return change; 593 return change;
634 } 594 }
635 595
636 /* digital master volume */ 596 /* digital master volume */
637 #define PCM_0dB 0xff 597 #define PCM_0dB 0xff
638 #define PCM_RES 128 /* -64dB */ 598 #define PCM_RES 128 /* -64dB */
639 #define PCM_MIN (PCM_0dB - PCM_RES) 599 #define PCM_MIN (PCM_0dB - PCM_RES)
640 static int wm_pcm_vol_info(struct snd_kcontrol !! 600 static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
641 struct snd_ctl <<
642 { 601 {
643 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTE 602 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
644 uinfo->count = 1; 603 uinfo->count = 1;
645 uinfo->value.integer.min = 0; 604 uinfo->value.integer.min = 0; /* mute (-64dB) */
646 uinfo->value.integer.max = PCM_RES; 605 uinfo->value.integer.max = PCM_RES; /* 0dB */
647 return 0; 606 return 0;
648 } 607 }
649 608
650 static int wm_pcm_vol_get(struct snd_kcontrol !! 609 static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
651 struct snd_ctl <<
652 { 610 {
653 struct snd_ice1712 *ice = snd_kcontrol 611 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
654 unsigned short val; 612 unsigned short val;
655 613
656 mutex_lock(&ice->gpio_mutex); 614 mutex_lock(&ice->gpio_mutex);
657 val = wm_get(ice, WM_DAC_DIG_MASTER_AT 615 val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
658 val = val > PCM_MIN ? (val - PCM_MIN) 616 val = val > PCM_MIN ? (val - PCM_MIN) : 0;
659 ucontrol->value.integer.value[0] = val 617 ucontrol->value.integer.value[0] = val;
660 mutex_unlock(&ice->gpio_mutex); 618 mutex_unlock(&ice->gpio_mutex);
661 return 0; 619 return 0;
662 } 620 }
663 621
664 static int wm_pcm_vol_put(struct snd_kcontrol !! 622 static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
665 struct snd_ctl <<
666 { 623 {
667 struct snd_ice1712 *ice = snd_kcontrol 624 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
668 unsigned short ovol, nvol; 625 unsigned short ovol, nvol;
669 int change = 0; 626 int change = 0;
670 627
671 nvol = ucontrol->value.integer.value[0 628 nvol = ucontrol->value.integer.value[0];
672 if (nvol > PCM_RES) 629 if (nvol > PCM_RES)
673 return -EINVAL; 630 return -EINVAL;
674 snd_ice1712_save_gpio_status(ice); 631 snd_ice1712_save_gpio_status(ice);
675 nvol = (nvol ? (nvol + PCM_MIN) : 0) & 632 nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
676 ovol = wm_get(ice, WM_DAC_DIG_MASTER_A 633 ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
677 if (ovol != nvol) { 634 if (ovol != nvol) {
678 wm_put(ice, WM_DAC_DIG_MASTER_ 635 wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
679 /* update */ !! 636 wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
680 wm_put_nocache(ice, WM_DAC_DIG <<
681 change = 1; 637 change = 1;
682 } 638 }
683 snd_ice1712_restore_gpio_status(ice); 639 snd_ice1712_restore_gpio_status(ice);
684 return change; 640 return change;
685 } 641 }
686 642
687 /* 643 /*
688 * Deemphasis 644 * Deemphasis
689 */ 645 */
690 #define phase28_deemp_info snd_ctl_boolea 646 #define phase28_deemp_info snd_ctl_boolean_mono_info
691 647
692 static int phase28_deemp_get(struct snd_kcontr !! 648 static int phase28_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
693 struct snd_ctl <<
694 { 649 {
695 struct snd_ice1712 *ice = snd_kcontrol 650 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
696 ucontrol->value.integer.value[0] = (wm !! 651 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
697 <<
698 return 0; 652 return 0;
699 } 653 }
700 654
701 static int phase28_deemp_put(struct snd_kcontr !! 655 static int phase28_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
702 struct snd_ctl <<
703 { 656 {
704 struct snd_ice1712 *ice = snd_kcontrol 657 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
705 int temp, temp2; 658 int temp, temp2;
706 temp = wm_get(ice, WM_DAC_CTRL2); !! 659 temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
707 temp2 = temp; <<
708 if (ucontrol->value.integer.value[0]) 660 if (ucontrol->value.integer.value[0])
709 temp |= 0xf; 661 temp |= 0xf;
710 else 662 else
711 temp &= ~0xf; 663 temp &= ~0xf;
712 if (temp != temp2) { 664 if (temp != temp2) {
713 wm_put(ice, WM_DAC_CTRL2, temp 665 wm_put(ice, WM_DAC_CTRL2, temp);
714 return 1; 666 return 1;
715 } 667 }
716 return 0; 668 return 0;
717 } 669 }
718 670
719 /* 671 /*
720 * ADC Oversampling 672 * ADC Oversampling
721 */ 673 */
722 static int phase28_oversampling_info(struct sn !! 674 static int phase28_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
723 struct <<
724 { 675 {
725 static char *texts[2] = { "128x", "64x 676 static char *texts[2] = { "128x", "64x" };
726 677
727 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUM 678 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
728 uinfo->count = 1; 679 uinfo->count = 1;
729 uinfo->value.enumerated.items = 2; 680 uinfo->value.enumerated.items = 2;
730 681
731 if (uinfo->value.enumerated.item >= ui 682 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
732 uinfo->value.enumerated.item = !! 683 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
733 !! 684 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
734 strcpy(uinfo->value.enumerated.name, <<
735 texts[uinfo->value.enumerated. <<
736 685
737 return 0; !! 686 return 0;
738 } 687 }
739 688
740 static int phase28_oversampling_get(struct snd !! 689 static int phase28_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
741 struct <<
742 { 690 {
743 struct snd_ice1712 *ice = snd_kcontrol 691 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
744 ucontrol->value.enumerated.item[0] = ( !! 692 ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
745 <<
746 return 0; 693 return 0;
747 } 694 }
748 695
749 static int phase28_oversampling_put(struct snd !! 696 static int phase28_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
750 struct <<
751 { 697 {
752 int temp, temp2; 698 int temp, temp2;
753 struct snd_ice1712 *ice = snd_kcontrol 699 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
754 700
755 temp = wm_get(ice, WM_MASTER); !! 701 temp2 = temp = wm_get(ice, WM_MASTER);
756 temp2 = temp; <<
757 702
758 if (ucontrol->value.enumerated.item[0] 703 if (ucontrol->value.enumerated.item[0])
759 temp |= 0x8; 704 temp |= 0x8;
760 else 705 else
761 temp &= ~0x8; 706 temp &= ~0x8;
762 707
763 if (temp != temp2) { 708 if (temp != temp2) {
764 wm_put(ice, WM_MASTER, temp); 709 wm_put(ice, WM_MASTER, temp);
765 return 1; 710 return 1;
766 } 711 }
767 return 0; 712 return 0;
768 } 713 }
769 714
770 static const DECLARE_TLV_DB_SCALE(db_scale_wm_ 715 static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
771 static const DECLARE_TLV_DB_SCALE(db_scale_wm_ 716 static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
772 717
773 static struct snd_kcontrol_new phase28_dac_con 718 static struct snd_kcontrol_new phase28_dac_controls[] __devinitdata = {
774 { 719 {
775 .iface = SNDRV_CTL_ELEM_IFACE_ 720 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
776 .name = "Master Playback Switc 721 .name = "Master Playback Switch",
777 .info = wm_master_mute_info, 722 .info = wm_master_mute_info,
778 .get = wm_master_mute_get, 723 .get = wm_master_mute_get,
779 .put = wm_master_mute_put 724 .put = wm_master_mute_put
780 }, 725 },
781 { 726 {
782 .iface = SNDRV_CTL_ELEM_IFACE_ 727 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
783 .access = (SNDRV_CTL_ELEM_ACCE 728 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
784 SNDRV_CTL_ELEM_ACCE 729 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
785 .name = "Master Playback Volum 730 .name = "Master Playback Volume",
786 .info = wm_master_vol_info, 731 .info = wm_master_vol_info,
787 .get = wm_master_vol_get, 732 .get = wm_master_vol_get,
788 .put = wm_master_vol_put, 733 .put = wm_master_vol_put,
789 .tlv = { .p = db_scale_wm_dac 734 .tlv = { .p = db_scale_wm_dac }
790 }, 735 },
791 { 736 {
792 .iface = SNDRV_CTL_ELEM_IFACE_ 737 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
793 .name = "Front Playback Switch 738 .name = "Front Playback Switch",
794 .info = wm_mute_info, 739 .info = wm_mute_info,
795 .get = wm_mute_get, 740 .get = wm_mute_get,
796 .put = wm_mute_put, 741 .put = wm_mute_put,
797 .private_value = (2 << 8) | 0 742 .private_value = (2 << 8) | 0
798 }, 743 },
799 { 744 {
800 .iface = SNDRV_CTL_ELEM_IFACE_ 745 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
801 .access = (SNDRV_CTL_ELEM_ACCE 746 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
802 SNDRV_CTL_ELEM_ACCE 747 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
803 .name = "Front Playback Volume 748 .name = "Front Playback Volume",
804 .info = wm_vol_info, 749 .info = wm_vol_info,
805 .get = wm_vol_get, 750 .get = wm_vol_get,
806 .put = wm_vol_put, 751 .put = wm_vol_put,
807 .private_value = (2 << 8) | 0, 752 .private_value = (2 << 8) | 0,
808 .tlv = { .p = db_scale_wm_dac 753 .tlv = { .p = db_scale_wm_dac }
809 }, 754 },
810 { 755 {
811 .iface = SNDRV_CTL_ELEM_IFACE_ 756 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
812 .name = "Rear Playback Switch" 757 .name = "Rear Playback Switch",
813 .info = wm_mute_info, 758 .info = wm_mute_info,
814 .get = wm_mute_get, 759 .get = wm_mute_get,
815 .put = wm_mute_put, 760 .put = wm_mute_put,
816 .private_value = (2 << 8) | 2 761 .private_value = (2 << 8) | 2
817 }, 762 },
818 { 763 {
819 .iface = SNDRV_CTL_ELEM_IFACE_ 764 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
820 .access = (SNDRV_CTL_ELEM_ACCE 765 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
821 SNDRV_CTL_ELEM_ACCE 766 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
822 .name = "Rear Playback Volume" 767 .name = "Rear Playback Volume",
823 .info = wm_vol_info, 768 .info = wm_vol_info,
824 .get = wm_vol_get, 769 .get = wm_vol_get,
825 .put = wm_vol_put, 770 .put = wm_vol_put,
826 .private_value = (2 << 8) | 2, 771 .private_value = (2 << 8) | 2,
827 .tlv = { .p = db_scale_wm_dac 772 .tlv = { .p = db_scale_wm_dac }
828 }, 773 },
829 { 774 {
830 .iface = SNDRV_CTL_ELEM_IFACE_ 775 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
831 .name = "Center Playback Switc 776 .name = "Center Playback Switch",
832 .info = wm_mute_info, 777 .info = wm_mute_info,
833 .get = wm_mute_get, 778 .get = wm_mute_get,
834 .put = wm_mute_put, 779 .put = wm_mute_put,
835 .private_value = (1 << 8) | 4 780 .private_value = (1 << 8) | 4
836 }, 781 },
837 { 782 {
838 .iface = SNDRV_CTL_ELEM_IFACE_ 783 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
839 .access = (SNDRV_CTL_ELEM_ACCE 784 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
840 SNDRV_CTL_ELEM_ACCE 785 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
841 .name = "Center Playback Volum 786 .name = "Center Playback Volume",
842 .info = wm_vol_info, 787 .info = wm_vol_info,
843 .get = wm_vol_get, 788 .get = wm_vol_get,
844 .put = wm_vol_put, 789 .put = wm_vol_put,
845 .private_value = (1 << 8) | 4, 790 .private_value = (1 << 8) | 4,
846 .tlv = { .p = db_scale_wm_dac 791 .tlv = { .p = db_scale_wm_dac }
847 }, 792 },
848 { 793 {
849 .iface = SNDRV_CTL_ELEM_IFACE_ 794 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
850 .name = "LFE Playback Switch", 795 .name = "LFE Playback Switch",
851 .info = wm_mute_info, 796 .info = wm_mute_info,
852 .get = wm_mute_get, 797 .get = wm_mute_get,
853 .put = wm_mute_put, 798 .put = wm_mute_put,
854 .private_value = (1 << 8) | 5 799 .private_value = (1 << 8) | 5
855 }, 800 },
856 { 801 {
857 .iface = SNDRV_CTL_ELEM_IFACE_ 802 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
858 .access = (SNDRV_CTL_ELEM_ACCE 803 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
859 SNDRV_CTL_ELEM_ACCE 804 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
860 .name = "LFE Playback Volume", 805 .name = "LFE Playback Volume",
861 .info = wm_vol_info, 806 .info = wm_vol_info,
862 .get = wm_vol_get, 807 .get = wm_vol_get,
863 .put = wm_vol_put, 808 .put = wm_vol_put,
864 .private_value = (1 << 8) | 5, 809 .private_value = (1 << 8) | 5,
865 .tlv = { .p = db_scale_wm_dac 810 .tlv = { .p = db_scale_wm_dac }
866 }, 811 },
867 { 812 {
868 .iface = SNDRV_CTL_ELEM_IFACE_ 813 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
869 .name = "Side Playback Switch" 814 .name = "Side Playback Switch",
870 .info = wm_mute_info, 815 .info = wm_mute_info,
871 .get = wm_mute_get, 816 .get = wm_mute_get,
872 .put = wm_mute_put, 817 .put = wm_mute_put,
873 .private_value = (2 << 8) | 6 818 .private_value = (2 << 8) | 6
874 }, 819 },
875 { 820 {
876 .iface = SNDRV_CTL_ELEM_IFACE_ 821 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
877 .access = (SNDRV_CTL_ELEM_ACCE 822 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
878 SNDRV_CTL_ELEM_ACCE 823 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
879 .name = "Side Playback Volume" 824 .name = "Side Playback Volume",
880 .info = wm_vol_info, 825 .info = wm_vol_info,
881 .get = wm_vol_get, 826 .get = wm_vol_get,
882 .put = wm_vol_put, 827 .put = wm_vol_put,
883 .private_value = (2 << 8) | 6, 828 .private_value = (2 << 8) | 6,
884 .tlv = { .p = db_scale_wm_dac 829 .tlv = { .p = db_scale_wm_dac }
885 } 830 }
886 }; 831 };
887 832
888 static struct snd_kcontrol_new wm_controls[] _ 833 static struct snd_kcontrol_new wm_controls[] __devinitdata = {
889 { 834 {
890 .iface = SNDRV_CTL_ELEM_IFACE_ 835 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
891 .name = "PCM Playback Switch", 836 .name = "PCM Playback Switch",
892 .info = wm_pcm_mute_info, 837 .info = wm_pcm_mute_info,
893 .get = wm_pcm_mute_get, 838 .get = wm_pcm_mute_get,
894 .put = wm_pcm_mute_put 839 .put = wm_pcm_mute_put
895 }, 840 },
896 { 841 {
897 .iface = SNDRV_CTL_ELEM_IFACE_ 842 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
898 .access = (SNDRV_CTL_ELEM_ACCE 843 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
899 SNDRV_CTL_ELEM_ACCE 844 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
900 .name = "PCM Playback Volume", 845 .name = "PCM Playback Volume",
901 .info = wm_pcm_vol_info, 846 .info = wm_pcm_vol_info,
902 .get = wm_pcm_vol_get, 847 .get = wm_pcm_vol_get,
903 .put = wm_pcm_vol_put, 848 .put = wm_pcm_vol_put,
904 .tlv = { .p = db_scale_wm_pcm 849 .tlv = { .p = db_scale_wm_pcm }
905 }, 850 },
906 { 851 {
907 .iface = SNDRV_CTL_ELEM_IFACE_ 852 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
908 .name = "DAC Deemphasis Switch 853 .name = "DAC Deemphasis Switch",
909 .info = phase28_deemp_info, 854 .info = phase28_deemp_info,
910 .get = phase28_deemp_get, 855 .get = phase28_deemp_get,
911 .put = phase28_deemp_put 856 .put = phase28_deemp_put
912 }, 857 },
913 { 858 {
914 .iface = SNDRV_CTL_ELEM_IFACE_ 859 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
915 .name = "ADC Oversampling", 860 .name = "ADC Oversampling",
916 .info = phase28_oversampling_i 861 .info = phase28_oversampling_info,
917 .get = phase28_oversampling_ge 862 .get = phase28_oversampling_get,
918 .put = phase28_oversampling_pu 863 .put = phase28_oversampling_put
919 } 864 }
920 }; 865 };
921 866
922 static int __devinit phase28_add_controls(stru 867 static int __devinit phase28_add_controls(struct snd_ice1712 *ice)
923 { 868 {
924 unsigned int i, counts; 869 unsigned int i, counts;
925 int err; 870 int err;
926 871
927 counts = ARRAY_SIZE(phase28_dac_contro 872 counts = ARRAY_SIZE(phase28_dac_controls);
928 for (i = 0; i < counts; i++) { 873 for (i = 0; i < counts; i++) {
929 err = snd_ctl_add(ice->card, !! 874 err = snd_ctl_add(ice->card, snd_ctl_new1(&phase28_dac_controls[i], ice));
930 snd_ct <<
931 <<
932 if (err < 0) 875 if (err < 0)
933 return err; 876 return err;
934 } 877 }
935 878
936 for (i = 0; i < ARRAY_SIZE(wm_controls 879 for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
937 err = snd_ctl_add(ice->card, !! 880 err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
938 snd_ct <<
939 if (err < 0) 881 if (err < 0)
940 return err; 882 return err;
941 } 883 }
942 884
943 return 0; 885 return 0;
944 } 886 }
945 887
946 struct snd_ice1712_card_info snd_vt1724_phase_ 888 struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
947 { 889 {
948 .subvendor = VT1724_SUBDEVICE_ 890 .subvendor = VT1724_SUBDEVICE_PHASE22,
949 .name = "Terratec PHASE 22", 891 .name = "Terratec PHASE 22",
950 .model = "phase22", 892 .model = "phase22",
951 .chip_init = phase22_init, 893 .chip_init = phase22_init,
952 .build_controls = phase22_add_ 894 .build_controls = phase22_add_controls,
953 .eeprom_size = sizeof(phase22_ 895 .eeprom_size = sizeof(phase22_eeprom),
954 .eeprom_data = phase22_eeprom, 896 .eeprom_data = phase22_eeprom,
955 }, 897 },
956 { 898 {
957 .subvendor = VT1724_SUBDEVICE_ 899 .subvendor = VT1724_SUBDEVICE_PHASE28,
958 .name = "Terratec PHASE 28", 900 .name = "Terratec PHASE 28",
959 .model = "phase28", 901 .model = "phase28",
960 .chip_init = phase28_init, 902 .chip_init = phase28_init,
961 .build_controls = phase28_add_ 903 .build_controls = phase28_add_controls,
962 .eeprom_size = sizeof(phase28_ 904 .eeprom_size = sizeof(phase28_eeprom),
963 .eeprom_data = phase28_eeprom, 905 .eeprom_data = phase28_eeprom,
964 }, 906 },
965 { <<
966 .subvendor = VT1724_SUBDEVICE_ <<
967 .name = "Terrasoniq TS22 PCI", <<
968 .model = "TS22", <<
969 .chip_init = phase22_init, <<
970 .build_controls = phase22_add_ <<
971 .eeprom_size = sizeof(phase22_ <<
972 .eeprom_data = phase22_eeprom, <<
973 }, <<
974 { } /* terminator */ 907 { } /* terminator */
975 }; 908 };
976 909
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