Diff markup
1 #ifndef __SOUND_YMFPCI_H 1 #ifndef __SOUND_YMFPCI_H
2 #define __SOUND_YMFPCI_H 2 #define __SOUND_YMFPCI_H
3 3
4 /* 4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@pe !! 5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for Yahama YMF724/740/744/754 6 * Definitions for Yahama YMF724/740/744/754 chips
7 * 7 *
8 * 8 *
9 * This program is free software; you can re 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Pub 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either vers 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope t 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even th 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICUL 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more detai 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GN 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22 *
23 */ 23 */
24 24
25 #include "pcm.h" 25 #include "pcm.h"
26 #include "rawmidi.h" 26 #include "rawmidi.h"
27 #include "ac97_codec.h" 27 #include "ac97_codec.h"
28 #include "timer.h" 28 #include "timer.h"
29 #include <linux/gameport.h> 29 #include <linux/gameport.h>
30 30
>> 31 #ifndef PCI_VENDOR_ID_YAMAHA
>> 32 #define PCI_VENDOR_ID_YAMAHA 0x1073
>> 33 #endif
>> 34 #ifndef PCI_DEVICE_ID_YAMAHA_724
>> 35 #define PCI_DEVICE_ID_YAMAHA_724 0x0004
>> 36 #endif
>> 37 #ifndef PCI_DEVICE_ID_YAMAHA_724F
>> 38 #define PCI_DEVICE_ID_YAMAHA_724F 0x000d
>> 39 #endif
>> 40 #ifndef PCI_DEVICE_ID_YAMAHA_740
>> 41 #define PCI_DEVICE_ID_YAMAHA_740 0x000a
>> 42 #endif
>> 43 #ifndef PCI_DEVICE_ID_YAMAHA_740C
>> 44 #define PCI_DEVICE_ID_YAMAHA_740C 0x000c
>> 45 #endif
>> 46 #ifndef PCI_DEVICE_ID_YAMAHA_744
>> 47 #define PCI_DEVICE_ID_YAMAHA_744 0x0010
>> 48 #endif
>> 49 #ifndef PCI_DEVICE_ID_YAMAHA_754
>> 50 #define PCI_DEVICE_ID_YAMAHA_754 0x0012
>> 51 #endif
>> 52
31 /* 53 /*
32 * Direct registers 54 * Direct registers
33 */ 55 */
34 56
35 #define YMFREG(chip, reg) (chip- 57 #define YMFREG(chip, reg) (chip->port + YDSXGR_##reg)
36 58
37 #define YDSXGR_INTFLAG 0x0004 59 #define YDSXGR_INTFLAG 0x0004
38 #define YDSXGR_ACTIVITY 0x0006 60 #define YDSXGR_ACTIVITY 0x0006
39 #define YDSXGR_GLOBALCTRL 0x0008 61 #define YDSXGR_GLOBALCTRL 0x0008
40 #define YDSXGR_ZVCTRL 0x000A 62 #define YDSXGR_ZVCTRL 0x000A
41 #define YDSXGR_TIMERCTRL 0x0010 63 #define YDSXGR_TIMERCTRL 0x0010
42 #define YDSXGR_TIMERCOUNT 0x0012 64 #define YDSXGR_TIMERCOUNT 0x0012
43 #define YDSXGR_SPDIFOUTCTRL 0x0018 65 #define YDSXGR_SPDIFOUTCTRL 0x0018
44 #define YDSXGR_SPDIFOUTSTATUS 0x001C 66 #define YDSXGR_SPDIFOUTSTATUS 0x001C
45 #define YDSXGR_EEPROMCTRL 0x0020 67 #define YDSXGR_EEPROMCTRL 0x0020
46 #define YDSXGR_SPDIFINCTRL 0x0034 68 #define YDSXGR_SPDIFINCTRL 0x0034
47 #define YDSXGR_SPDIFINSTATUS 0x0038 69 #define YDSXGR_SPDIFINSTATUS 0x0038
48 #define YDSXGR_DSPPROGRAMDL 0x0048 70 #define YDSXGR_DSPPROGRAMDL 0x0048
49 #define YDSXGR_DLCNTRL 0x004C 71 #define YDSXGR_DLCNTRL 0x004C
50 #define YDSXGR_GPIOININTFLAG 0x0050 72 #define YDSXGR_GPIOININTFLAG 0x0050
51 #define YDSXGR_GPIOININTENABLE 0x0052 73 #define YDSXGR_GPIOININTENABLE 0x0052
52 #define YDSXGR_GPIOINSTATUS 0x0054 74 #define YDSXGR_GPIOINSTATUS 0x0054
53 #define YDSXGR_GPIOOUTCTRL 0x0056 75 #define YDSXGR_GPIOOUTCTRL 0x0056
54 #define YDSXGR_GPIOFUNCENABLE 0x0058 76 #define YDSXGR_GPIOFUNCENABLE 0x0058
55 #define YDSXGR_GPIOTYPECONFIG 0x005A 77 #define YDSXGR_GPIOTYPECONFIG 0x005A
56 #define YDSXGR_AC97CMDDATA 0x0060 78 #define YDSXGR_AC97CMDDATA 0x0060
57 #define YDSXGR_AC97CMDADR 0x0062 79 #define YDSXGR_AC97CMDADR 0x0062
58 #define YDSXGR_PRISTATUSDATA 0x0064 80 #define YDSXGR_PRISTATUSDATA 0x0064
59 #define YDSXGR_PRISTATUSADR 0x0066 81 #define YDSXGR_PRISTATUSADR 0x0066
60 #define YDSXGR_SECSTATUSDATA 0x0068 82 #define YDSXGR_SECSTATUSDATA 0x0068
61 #define YDSXGR_SECSTATUSADR 0x006A 83 #define YDSXGR_SECSTATUSADR 0x006A
62 #define YDSXGR_SECCONFIG 0x0070 84 #define YDSXGR_SECCONFIG 0x0070
63 #define YDSXGR_LEGACYOUTVOL 0x0080 85 #define YDSXGR_LEGACYOUTVOL 0x0080
64 #define YDSXGR_LEGACYOUTVOLL 0x0080 86 #define YDSXGR_LEGACYOUTVOLL 0x0080
65 #define YDSXGR_LEGACYOUTVOLR 0x0082 87 #define YDSXGR_LEGACYOUTVOLR 0x0082
66 #define YDSXGR_NATIVEDACOUTVOL 0x0084 88 #define YDSXGR_NATIVEDACOUTVOL 0x0084
67 #define YDSXGR_NATIVEDACOUTVOLL 0x0084 89 #define YDSXGR_NATIVEDACOUTVOLL 0x0084
68 #define YDSXGR_NATIVEDACOUTVOLR 0x0086 90 #define YDSXGR_NATIVEDACOUTVOLR 0x0086
69 #define YDSXGR_ZVOUTVOL 0x0088 91 #define YDSXGR_ZVOUTVOL 0x0088
70 #define YDSXGR_ZVOUTVOLL 0x0088 92 #define YDSXGR_ZVOUTVOLL 0x0088
71 #define YDSXGR_ZVOUTVOLR 0x008A 93 #define YDSXGR_ZVOUTVOLR 0x008A
72 #define YDSXGR_SECADCOUTVOL 0x008C 94 #define YDSXGR_SECADCOUTVOL 0x008C
73 #define YDSXGR_SECADCOUTVOLL 0x008C 95 #define YDSXGR_SECADCOUTVOLL 0x008C
74 #define YDSXGR_SECADCOUTVOLR 0x008E 96 #define YDSXGR_SECADCOUTVOLR 0x008E
75 #define YDSXGR_PRIADCOUTVOL 0x0090 97 #define YDSXGR_PRIADCOUTVOL 0x0090
76 #define YDSXGR_PRIADCOUTVOLL 0x0090 98 #define YDSXGR_PRIADCOUTVOLL 0x0090
77 #define YDSXGR_PRIADCOUTVOLR 0x0092 99 #define YDSXGR_PRIADCOUTVOLR 0x0092
78 #define YDSXGR_LEGACYLOOPVOL 0x0094 100 #define YDSXGR_LEGACYLOOPVOL 0x0094
79 #define YDSXGR_LEGACYLOOPVOLL 0x0094 101 #define YDSXGR_LEGACYLOOPVOLL 0x0094
80 #define YDSXGR_LEGACYLOOPVOLR 0x0096 102 #define YDSXGR_LEGACYLOOPVOLR 0x0096
81 #define YDSXGR_NATIVEDACLOOPVOL 0x0098 103 #define YDSXGR_NATIVEDACLOOPVOL 0x0098
82 #define YDSXGR_NATIVEDACLOOPVOLL 0x0098 104 #define YDSXGR_NATIVEDACLOOPVOLL 0x0098
83 #define YDSXGR_NATIVEDACLOOPVOLR 0x009A 105 #define YDSXGR_NATIVEDACLOOPVOLR 0x009A
84 #define YDSXGR_ZVLOOPVOL 0x009C 106 #define YDSXGR_ZVLOOPVOL 0x009C
85 #define YDSXGR_ZVLOOPVOLL 0x009E 107 #define YDSXGR_ZVLOOPVOLL 0x009E
86 #define YDSXGR_ZVLOOPVOLR 0x009E 108 #define YDSXGR_ZVLOOPVOLR 0x009E
87 #define YDSXGR_SECADCLOOPVOL 0x00A0 109 #define YDSXGR_SECADCLOOPVOL 0x00A0
88 #define YDSXGR_SECADCLOOPVOLL 0x00A0 110 #define YDSXGR_SECADCLOOPVOLL 0x00A0
89 #define YDSXGR_SECADCLOOPVOLR 0x00A2 111 #define YDSXGR_SECADCLOOPVOLR 0x00A2
90 #define YDSXGR_PRIADCLOOPVOL 0x00A4 112 #define YDSXGR_PRIADCLOOPVOL 0x00A4
91 #define YDSXGR_PRIADCLOOPVOLL 0x00A4 113 #define YDSXGR_PRIADCLOOPVOLL 0x00A4
92 #define YDSXGR_PRIADCLOOPVOLR 0x00A6 114 #define YDSXGR_PRIADCLOOPVOLR 0x00A6
93 #define YDSXGR_NATIVEADCINVOL 0x00A8 115 #define YDSXGR_NATIVEADCINVOL 0x00A8
94 #define YDSXGR_NATIVEADCINVOLL 0x00A8 116 #define YDSXGR_NATIVEADCINVOLL 0x00A8
95 #define YDSXGR_NATIVEADCINVOLR 0x00AA 117 #define YDSXGR_NATIVEADCINVOLR 0x00AA
96 #define YDSXGR_NATIVEDACINVOL 0x00AC 118 #define YDSXGR_NATIVEDACINVOL 0x00AC
97 #define YDSXGR_NATIVEDACINVOLL 0x00AC 119 #define YDSXGR_NATIVEDACINVOLL 0x00AC
98 #define YDSXGR_NATIVEDACINVOLR 0x00AE 120 #define YDSXGR_NATIVEDACINVOLR 0x00AE
99 #define YDSXGR_BUF441OUTVOL 0x00B0 121 #define YDSXGR_BUF441OUTVOL 0x00B0
100 #define YDSXGR_BUF441OUTVOLL 0x00B0 122 #define YDSXGR_BUF441OUTVOLL 0x00B0
101 #define YDSXGR_BUF441OUTVOLR 0x00B2 123 #define YDSXGR_BUF441OUTVOLR 0x00B2
102 #define YDSXGR_BUF441LOOPVOL 0x00B4 124 #define YDSXGR_BUF441LOOPVOL 0x00B4
103 #define YDSXGR_BUF441LOOPVOLL 0x00B4 125 #define YDSXGR_BUF441LOOPVOLL 0x00B4
104 #define YDSXGR_BUF441LOOPVOLR 0x00B6 126 #define YDSXGR_BUF441LOOPVOLR 0x00B6
105 #define YDSXGR_SPDIFOUTVOL 0x00B8 127 #define YDSXGR_SPDIFOUTVOL 0x00B8
106 #define YDSXGR_SPDIFOUTVOLL 0x00B8 128 #define YDSXGR_SPDIFOUTVOLL 0x00B8
107 #define YDSXGR_SPDIFOUTVOLR 0x00BA 129 #define YDSXGR_SPDIFOUTVOLR 0x00BA
108 #define YDSXGR_SPDIFLOOPVOL 0x00BC 130 #define YDSXGR_SPDIFLOOPVOL 0x00BC
109 #define YDSXGR_SPDIFLOOPVOLL 0x00BC 131 #define YDSXGR_SPDIFLOOPVOLL 0x00BC
110 #define YDSXGR_SPDIFLOOPVOLR 0x00BE 132 #define YDSXGR_SPDIFLOOPVOLR 0x00BE
111 #define YDSXGR_ADCSLOTSR 0x00C0 133 #define YDSXGR_ADCSLOTSR 0x00C0
112 #define YDSXGR_RECSLOTSR 0x00C4 134 #define YDSXGR_RECSLOTSR 0x00C4
113 #define YDSXGR_ADCFORMAT 0x00C8 135 #define YDSXGR_ADCFORMAT 0x00C8
114 #define YDSXGR_RECFORMAT 0x00CC 136 #define YDSXGR_RECFORMAT 0x00CC
115 #define YDSXGR_P44SLOTSR 0x00D0 137 #define YDSXGR_P44SLOTSR 0x00D0
116 #define YDSXGR_STATUS 0x0100 138 #define YDSXGR_STATUS 0x0100
117 #define YDSXGR_CTRLSELECT 0x0104 139 #define YDSXGR_CTRLSELECT 0x0104
118 #define YDSXGR_MODE 0x0108 140 #define YDSXGR_MODE 0x0108
119 #define YDSXGR_SAMPLECOUNT 0x010C 141 #define YDSXGR_SAMPLECOUNT 0x010C
120 #define YDSXGR_NUMOFSAMPLES 0x0110 142 #define YDSXGR_NUMOFSAMPLES 0x0110
121 #define YDSXGR_CONFIG 0x0114 143 #define YDSXGR_CONFIG 0x0114
122 #define YDSXGR_PLAYCTRLSIZE 0x0140 144 #define YDSXGR_PLAYCTRLSIZE 0x0140
123 #define YDSXGR_RECCTRLSIZE 0x0144 145 #define YDSXGR_RECCTRLSIZE 0x0144
124 #define YDSXGR_EFFCTRLSIZE 0x0148 146 #define YDSXGR_EFFCTRLSIZE 0x0148
125 #define YDSXGR_WORKSIZE 0x014C 147 #define YDSXGR_WORKSIZE 0x014C
126 #define YDSXGR_MAPOFREC 0x0150 148 #define YDSXGR_MAPOFREC 0x0150
127 #define YDSXGR_MAPOFEFFECT 0x0154 149 #define YDSXGR_MAPOFEFFECT 0x0154
128 #define YDSXGR_PLAYCTRLBASE 0x0158 150 #define YDSXGR_PLAYCTRLBASE 0x0158
129 #define YDSXGR_RECCTRLBASE 0x015C 151 #define YDSXGR_RECCTRLBASE 0x015C
130 #define YDSXGR_EFFCTRLBASE 0x0160 152 #define YDSXGR_EFFCTRLBASE 0x0160
131 #define YDSXGR_WORKBASE 0x0164 153 #define YDSXGR_WORKBASE 0x0164
132 #define YDSXGR_DSPINSTRAM 0x1000 154 #define YDSXGR_DSPINSTRAM 0x1000
133 #define YDSXGR_CTRLINSTRAM 0x4000 155 #define YDSXGR_CTRLINSTRAM 0x4000
134 156
135 #define YDSXG_AC97READCMD 0x8000 157 #define YDSXG_AC97READCMD 0x8000
136 #define YDSXG_AC97WRITECMD 0x0000 158 #define YDSXG_AC97WRITECMD 0x0000
137 159
138 #define PCIR_DSXG_LEGACY 0x40 160 #define PCIR_DSXG_LEGACY 0x40
139 #define PCIR_DSXG_ELEGACY 0x42 161 #define PCIR_DSXG_ELEGACY 0x42
140 #define PCIR_DSXG_CTRL 0x48 162 #define PCIR_DSXG_CTRL 0x48
141 #define PCIR_DSXG_PWRCTRL1 0x4a 163 #define PCIR_DSXG_PWRCTRL1 0x4a
142 #define PCIR_DSXG_PWRCTRL2 0x4e 164 #define PCIR_DSXG_PWRCTRL2 0x4e
143 #define PCIR_DSXG_FMBASE 0x60 165 #define PCIR_DSXG_FMBASE 0x60
144 #define PCIR_DSXG_SBBASE 0x62 166 #define PCIR_DSXG_SBBASE 0x62
145 #define PCIR_DSXG_MPU401BASE 0x64 167 #define PCIR_DSXG_MPU401BASE 0x64
146 #define PCIR_DSXG_JOYBASE 0x66 168 #define PCIR_DSXG_JOYBASE 0x66
147 169
148 #define YDSXG_DSPLENGTH 0x0080 170 #define YDSXG_DSPLENGTH 0x0080
149 #define YDSXG_CTRLLENGTH 0x3000 171 #define YDSXG_CTRLLENGTH 0x3000
150 172
151 #define YDSXG_DEFAULT_WORK_SIZE 0x0400 173 #define YDSXG_DEFAULT_WORK_SIZE 0x0400
152 174
153 #define YDSXG_PLAYBACK_VOICES 64 175 #define YDSXG_PLAYBACK_VOICES 64
154 #define YDSXG_CAPTURE_VOICES 2 176 #define YDSXG_CAPTURE_VOICES 2
155 #define YDSXG_EFFECT_VOICES 5 177 #define YDSXG_EFFECT_VOICES 5
156 178
157 #define YMFPCI_LEGACY_SBEN (1 << 0) 179 #define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */
158 #define YMFPCI_LEGACY_FMEN (1 << 1) 180 #define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */
159 #define YMFPCI_LEGACY_JPEN (1 << 2) 181 #define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */
160 #define YMFPCI_LEGACY_MEN (1 << 3) 182 #define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */
161 #define YMFPCI_LEGACY_MIEN (1 << 4) 183 #define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */
162 #define YMFPCI_LEGACY_IOBITS (1 << 5) 184 #define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */
163 #define YMFPCI_LEGACY_SDMA (3 << 6) 185 #define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */
164 #define YMFPCI_LEGACY_SBIRQ (7 << 8) 186 #define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */
165 #define YMFPCI_LEGACY_MPUIRQ (7 << 11) 187 #define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */
166 #define YMFPCI_LEGACY_SIEN (1 << 14) 188 #define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */
167 #define YMFPCI_LEGACY_LAD (1 << 15) 189 #define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */
168 190
169 #define YMFPCI_LEGACY2_FMIO (3 << 0) 191 #define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */
170 #define YMFPCI_LEGACY2_SBIO (3 << 2) 192 #define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */
171 #define YMFPCI_LEGACY2_MPUIO (3 << 4) 193 #define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */
172 #define YMFPCI_LEGACY2_JSIO (3 << 6) 194 #define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */
173 #define YMFPCI_LEGACY2_MAIM (1 << 8) 195 #define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */
174 #define YMFPCI_LEGACY2_SMOD (3 << 11) 196 #define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */
175 #define YMFPCI_LEGACY2_SBVER (3 << 13) 197 #define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */
176 #define YMFPCI_LEGACY2_IMOD (1 << 15) 198 #define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */
177 /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 199 /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
178 200
179 #if defined(CONFIG_GAMEPORT) || (defined(MODUL <<
180 #define SUPPORT_JOYSTICK <<
181 #endif <<
182 <<
183 /* 201 /*
184 * 202 *
185 */ 203 */
186 204
187 struct snd_ymfpci_playback_bank { !! 205 typedef struct _snd_ymfpci_playback_bank {
188 u32 format; 206 u32 format;
189 u32 loop_default; 207 u32 loop_default;
190 u32 base; /* 32- 208 u32 base; /* 32-bit address */
191 u32 loop_start; /* 32- 209 u32 loop_start; /* 32-bit offset */
192 u32 loop_end; /* 32- 210 u32 loop_end; /* 32-bit offset */
193 u32 loop_frac; /* 8-b 211 u32 loop_frac; /* 8-bit fraction - loop_start */
194 u32 delta_end; /* pit 212 u32 delta_end; /* pitch delta end */
195 u32 lpfK_end; 213 u32 lpfK_end;
196 u32 eg_gain_end; 214 u32 eg_gain_end;
197 u32 left_gain_end; 215 u32 left_gain_end;
198 u32 right_gain_end; 216 u32 right_gain_end;
199 u32 eff1_gain_end; 217 u32 eff1_gain_end;
200 u32 eff2_gain_end; 218 u32 eff2_gain_end;
201 u32 eff3_gain_end; 219 u32 eff3_gain_end;
202 u32 lpfQ; 220 u32 lpfQ;
203 u32 status; 221 u32 status;
204 u32 num_of_frames; 222 u32 num_of_frames;
205 u32 loop_count; 223 u32 loop_count;
206 u32 start; 224 u32 start;
207 u32 start_frac; 225 u32 start_frac;
208 u32 delta; 226 u32 delta;
209 u32 lpfK; 227 u32 lpfK;
210 u32 eg_gain; 228 u32 eg_gain;
211 u32 left_gain; 229 u32 left_gain;
212 u32 right_gain; 230 u32 right_gain;
213 u32 eff1_gain; 231 u32 eff1_gain;
214 u32 eff2_gain; 232 u32 eff2_gain;
215 u32 eff3_gain; 233 u32 eff3_gain;
216 u32 lpfD1; 234 u32 lpfD1;
217 u32 lpfD2; 235 u32 lpfD2;
218 }; !! 236 } snd_ymfpci_playback_bank_t;
219 237
220 struct snd_ymfpci_capture_bank { !! 238 typedef struct _snd_ymfpci_capture_bank {
221 u32 base; /* 32- 239 u32 base; /* 32-bit address */
222 u32 loop_end; /* 32- 240 u32 loop_end; /* 32-bit offset */
223 u32 start; /* 32- 241 u32 start; /* 32-bit offset */
224 u32 num_of_loops; /* cou 242 u32 num_of_loops; /* counter */
225 }; !! 243 } snd_ymfpci_capture_bank_t;
226 244
227 struct snd_ymfpci_effect_bank { !! 245 typedef struct _snd_ymfpci_effect_bank {
228 u32 base; /* 32- 246 u32 base; /* 32-bit address */
229 u32 loop_end; /* 32- 247 u32 loop_end; /* 32-bit offset */
230 u32 start; /* 32- 248 u32 start; /* 32-bit offset */
231 u32 temp; 249 u32 temp;
232 }; !! 250 } snd_ymfpci_effect_bank_t;
233 251
234 struct snd_ymfpci_pcm; !! 252 typedef struct _snd_ymfpci_voice ymfpci_voice_t;
235 struct snd_ymfpci; !! 253 typedef struct _snd_ymfpci_pcm ymfpci_pcm_t;
>> 254 typedef struct _snd_ymfpci ymfpci_t;
236 255
237 enum snd_ymfpci_voice_type { !! 256 typedef enum {
238 YMFPCI_PCM, 257 YMFPCI_PCM,
239 YMFPCI_SYNTH, 258 YMFPCI_SYNTH,
240 YMFPCI_MIDI 259 YMFPCI_MIDI
241 }; !! 260 } ymfpci_voice_type_t;
242 261
243 struct snd_ymfpci_voice { !! 262 struct _snd_ymfpci_voice {
244 struct snd_ymfpci *chip; !! 263 ymfpci_t *chip;
245 int number; 264 int number;
246 unsigned int use: 1, !! 265 int use: 1,
247 pcm: 1, 266 pcm: 1,
248 synth: 1, 267 synth: 1,
249 midi: 1; 268 midi: 1;
250 struct snd_ymfpci_playback_bank *bank; !! 269 snd_ymfpci_playback_bank_t *bank;
251 dma_addr_t bank_addr; 270 dma_addr_t bank_addr;
252 void (*interrupt)(struct snd_ymfpci *c !! 271 void (*interrupt)(ymfpci_t *chip, ymfpci_voice_t *voice);
253 struct snd_ymfpci_pcm *ypcm; !! 272 ymfpci_pcm_t *ypcm;
254 }; 273 };
255 274
256 enum snd_ymfpci_pcm_type { !! 275 typedef enum {
257 PLAYBACK_VOICE, 276 PLAYBACK_VOICE,
258 CAPTURE_REC, 277 CAPTURE_REC,
259 CAPTURE_AC97, 278 CAPTURE_AC97,
260 EFFECT_DRY_LEFT, 279 EFFECT_DRY_LEFT,
261 EFFECT_DRY_RIGHT, 280 EFFECT_DRY_RIGHT,
262 EFFECT_EFF1, 281 EFFECT_EFF1,
263 EFFECT_EFF2, 282 EFFECT_EFF2,
264 EFFECT_EFF3 283 EFFECT_EFF3
265 }; !! 284 } snd_ymfpci_pcm_type_t;
266 285
267 struct snd_ymfpci_pcm { !! 286 struct _snd_ymfpci_pcm {
268 struct snd_ymfpci *chip; !! 287 ymfpci_t *chip;
269 enum snd_ymfpci_pcm_type type; !! 288 snd_ymfpci_pcm_type_t type;
270 struct snd_pcm_substream *substream; !! 289 snd_pcm_substream_t *substream;
271 struct snd_ymfpci_voice *voices[2]; !! 290 ymfpci_voice_t *voices[2]; /* playback only */
272 unsigned int running: 1, !! 291 int running: 1;
273 use_441_slot: 1, !! 292 int output_front: 1;
274 output_front: 1, !! 293 int output_rear: 1;
275 output_rear: 1, <<
276 swap_rear: 1; <<
277 unsigned int update_pcm_vol; <<
278 u32 period_size; /* cac 294 u32 period_size; /* cached from runtime->period_size */
279 u32 buffer_size; /* cac 295 u32 buffer_size; /* cached from runtime->buffer_size */
280 u32 period_pos; 296 u32 period_pos;
281 u32 last_pos; 297 u32 last_pos;
282 u32 capture_bank_number; 298 u32 capture_bank_number;
283 u32 shift; 299 u32 shift;
284 }; 300 };
285 301
286 struct snd_ymfpci { !! 302 struct _snd_ymfpci {
287 int irq; 303 int irq;
288 304
289 unsigned int device_id; /* PCI device 305 unsigned int device_id; /* PCI device ID */
290 unsigned char rev; /* PCI revisio !! 306 unsigned int rev; /* PCI revision */
291 unsigned long reg_area_phys; 307 unsigned long reg_area_phys;
292 void __iomem *reg_area_virt; 308 void __iomem *reg_area_virt;
293 struct resource *res_reg_area; 309 struct resource *res_reg_area;
294 struct resource *fm_res; 310 struct resource *fm_res;
295 struct resource *mpu_res; 311 struct resource *mpu_res;
296 312
297 unsigned short old_legacy_ctrl; 313 unsigned short old_legacy_ctrl;
298 #ifdef SUPPORT_JOYSTICK !! 314 #if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE)
299 struct gameport *gameport; !! 315 struct resource *joystick_res;
>> 316 struct gameport gameport;
300 #endif 317 #endif
301 318
302 struct snd_dma_buffer work_ptr; 319 struct snd_dma_buffer work_ptr;
303 320
304 unsigned int bank_size_playback; 321 unsigned int bank_size_playback;
305 unsigned int bank_size_capture; 322 unsigned int bank_size_capture;
306 unsigned int bank_size_effect; 323 unsigned int bank_size_effect;
307 unsigned int work_size; 324 unsigned int work_size;
308 325
309 void *bank_base_playback; 326 void *bank_base_playback;
310 void *bank_base_capture; 327 void *bank_base_capture;
311 void *bank_base_effect; 328 void *bank_base_effect;
312 void *work_base; 329 void *work_base;
313 dma_addr_t bank_base_playback_addr; 330 dma_addr_t bank_base_playback_addr;
314 dma_addr_t bank_base_capture_addr; 331 dma_addr_t bank_base_capture_addr;
315 dma_addr_t bank_base_effect_addr; 332 dma_addr_t bank_base_effect_addr;
316 dma_addr_t work_base_addr; 333 dma_addr_t work_base_addr;
317 struct snd_dma_buffer ac3_tmp_base; 334 struct snd_dma_buffer ac3_tmp_base;
318 335
319 u32 *ctrl_playback; 336 u32 *ctrl_playback;
320 struct snd_ymfpci_playback_bank *bank_ !! 337 snd_ymfpci_playback_bank_t *bank_playback[YDSXG_PLAYBACK_VOICES][2];
321 struct snd_ymfpci_capture_bank *bank_c !! 338 snd_ymfpci_capture_bank_t *bank_capture[YDSXG_CAPTURE_VOICES][2];
322 struct snd_ymfpci_effect_bank *bank_ef !! 339 snd_ymfpci_effect_bank_t *bank_effect[YDSXG_EFFECT_VOICES][2];
323 340
324 int start_count; 341 int start_count;
325 342
326 u32 active_bank; 343 u32 active_bank;
327 struct snd_ymfpci_voice voices[64]; !! 344 ymfpci_voice_t voices[64];
328 int src441_used; <<
329 345
330 struct snd_ac97_bus *ac97_bus; !! 346 ac97_bus_t *ac97_bus;
331 struct snd_ac97 *ac97; !! 347 ac97_t *ac97;
332 struct snd_rawmidi *rawmidi; !! 348 snd_rawmidi_t *rawmidi;
333 struct snd_timer *timer; !! 349 snd_timer_t *timer;
334 350
335 struct pci_dev *pci; 351 struct pci_dev *pci;
336 struct snd_card *card; !! 352 snd_card_t *card;
337 struct snd_pcm *pcm; !! 353 snd_pcm_t *pcm;
338 struct snd_pcm *pcm2; !! 354 snd_pcm_t *pcm2;
339 struct snd_pcm *pcm_spdif; !! 355 snd_pcm_t *pcm_spdif;
340 struct snd_pcm *pcm_4ch; !! 356 snd_pcm_t *pcm_4ch;
341 struct snd_pcm_substream *capture_subs !! 357 snd_pcm_substream_t *capture_substream[YDSXG_CAPTURE_VOICES];
342 struct snd_pcm_substream *effect_subst !! 358 snd_pcm_substream_t *effect_substream[YDSXG_EFFECT_VOICES];
343 struct snd_kcontrol *ctl_vol_recsrc; !! 359 snd_kcontrol_t *ctl_vol_recsrc;
344 struct snd_kcontrol *ctl_vol_adcrec; !! 360 snd_kcontrol_t *ctl_vol_adcrec;
345 struct snd_kcontrol *ctl_vol_spdifrec; !! 361 snd_kcontrol_t *ctl_vol_spdifrec;
346 unsigned short spdif_bits, spdif_pcm_b 362 unsigned short spdif_bits, spdif_pcm_bits;
347 struct snd_kcontrol *spdif_pcm_ctl; !! 363 snd_kcontrol_t *spdif_pcm_ctl;
348 int mode_dup4ch; 364 int mode_dup4ch;
349 int rear_opened; 365 int rear_opened;
350 int spdif_opened; 366 int spdif_opened;
351 struct snd_ymfpci_pcm_mixer { <<
352 u16 left; <<
353 u16 right; <<
354 struct snd_kcontrol *ctl; <<
355 } pcm_mixer[32]; <<
356 367
357 spinlock_t reg_lock; 368 spinlock_t reg_lock;
358 spinlock_t voice_lock; 369 spinlock_t voice_lock;
359 wait_queue_head_t interrupt_sleep; 370 wait_queue_head_t interrupt_sleep;
360 atomic_t interrupt_sleep_count; 371 atomic_t interrupt_sleep_count;
361 struct snd_info_entry *proc_entry; !! 372 snd_info_entry_t *proc_entry;
362 const struct firmware *dsp_microcode; <<
363 const struct firmware *controller_micr <<
364 373
365 #ifdef CONFIG_PM 374 #ifdef CONFIG_PM
366 u32 *saved_regs; 375 u32 *saved_regs;
367 u32 saved_ydsxgr_mode; 376 u32 saved_ydsxgr_mode;
368 #endif 377 #endif
369 }; 378 };
370 379
371 int snd_ymfpci_create(struct snd_card *card, !! 380 int snd_ymfpci_create(snd_card_t * card,
372 struct pci_dev *pci, 381 struct pci_dev *pci,
373 unsigned short old_legac 382 unsigned short old_legacy_ctrl,
374 struct snd_ymfpci ** rco !! 383 ymfpci_t ** rcodec);
375 void snd_ymfpci_free_gameport(struct snd_ymfpc <<
376 384
377 int snd_ymfpci_suspend(struct pci_dev *pci, pm !! 385 int snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
378 int snd_ymfpci_resume(struct pci_dev *pci); !! 386 int snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
>> 387 int snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
>> 388 int snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
>> 389 int snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch);
>> 390 int snd_ymfpci_timer(ymfpci_t *chip, int device);
379 391
380 int snd_ymfpci_pcm(struct snd_ymfpci *chip, in !! 392 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
381 int snd_ymfpci_pcm2(struct snd_ymfpci *chip, i !! 393 #define SUPPORT_JOYSTICK
382 int snd_ymfpci_pcm_spdif(struct snd_ymfpci *ch !! 394 #endif
383 int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip <<
384 int snd_ymfpci_mixer(struct snd_ymfpci *chip, <<
385 int snd_ymfpci_timer(struct snd_ymfpci *chip, <<
386 395
387 #endif /* __SOUND_YMFPCI_H */ 396 #endif /* __SOUND_YMFPCI_H */
388 397
|
This page was automatically generated by the
LXR engine.
|