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1 #ifndef __SOUND_EMU10K1_H 1 #ifndef __SOUND_EMU10K1_H
2 #define __SOUND_EMU10K1_H 2 #define __SOUND_EMU10K1_H
3 3
4 /* 4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@pe !! 5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Creative Labs, Inc. 6 * Creative Labs, Inc.
7 * Definitions for EMU10K1 (SB Live!) chips 7 * Definitions for EMU10K1 (SB Live!) chips
8 * 8 *
9 * 9 *
10 * This program is free software; you can re 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Pub 11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either vers 12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version. 13 * (at your option) any later version.
14 * 14 *
15 * This program is distributed in the hope t 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even th 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICUL 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more detai 18 * GNU General Public License for more details.
19 * 19 *
20 * You should have received a copy of the GN 20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * 23 *
24 */ 24 */
25 25
26 #ifdef __KERNEL__ 26 #ifdef __KERNEL__
27 27
28 #include <sound/pcm.h> 28 #include <sound/pcm.h>
29 #include <sound/rawmidi.h> 29 #include <sound/rawmidi.h>
30 #include <sound/hwdep.h> 30 #include <sound/hwdep.h>
31 #include <sound/ac97_codec.h> 31 #include <sound/ac97_codec.h>
32 #include <sound/util_mem.h> 32 #include <sound/util_mem.h>
33 #include <sound/pcm-indirect.h> 33 #include <sound/pcm-indirect.h>
34 #include <sound/timer.h> 34 #include <sound/timer.h>
35 #include <linux/interrupt.h> 35 #include <linux/interrupt.h>
36 #include <linux/mutex.h> <<
37 #include <asm/io.h> 36 #include <asm/io.h>
38 37
>> 38 #ifndef PCI_VENDOR_ID_CREATIVE
>> 39 #define PCI_VENDOR_ID_CREATIVE 0x1102
>> 40 #endif
>> 41 #ifndef PCI_DEVICE_ID_CREATIVE_EMU10K1
>> 42 #define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
>> 43 #endif
>> 44
39 /* ------------------- DEFINES --------------- 45 /* ------------------- DEFINES -------------------- */
40 46
41 #define EMUPAGESIZE 4096 47 #define EMUPAGESIZE 4096
42 #define MAXREQVOICES 8 48 #define MAXREQVOICES 8
43 #define MAXPAGES 8192 49 #define MAXPAGES 8192
44 #define RESERVED 0 50 #define RESERVED 0
45 #define NUM_MIDI 16 51 #define NUM_MIDI 16
46 #define NUM_G 64 /* use 52 #define NUM_G 64 /* use all channels */
47 #define NUM_FXSENDS 4 53 #define NUM_FXSENDS 4
48 #define NUM_EFX_PLAYBACK 16 <<
49 54
50 /* FIXME? - according to the OSS driver the EM <<
51 #define EMU10K1_DMA_MASK 0x7fffffffUL 55 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
52 #define AUDIGY_DMA_MASK 0x7fffffffUL !! 56 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit */
53 <<
54 57
55 #define TMEMSIZE 256*1024 58 #define TMEMSIZE 256*1024
56 #define TMEMSIZEREG 4 59 #define TMEMSIZEREG 4
57 60
58 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x000 61 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
59 62
60 // Audigy specify registers are prefixed with 63 // Audigy specify registers are prefixed with 'A_'
61 64
62 /********************************************* 65 /************************************************************************************************/
63 /* PCI function 0 registers, address = <val> + 66 /* PCI function 0 registers, address = <val> + PCIBASE0 */
64 /********************************************* 67 /************************************************************************************************/
65 68
66 #define PTR 0x00 69 #define PTR 0x00 /* Indexed register set pointer register */
67 70 /* NOTE: The CHANNELNUM and ADDRESS words can */
68 71 /* be modified independently of each other. */
69 #define PTR_CHANNELNUM_MASK 0x0000003f 72 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
70 73 /* channel number of the register to be */
71 74 /* accessed. For non per-channel registers the */
72 75 /* value should be set to zero. */
73 #define PTR_ADDRESS_MASK 0x07ff0000 76 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
74 #define A_PTR_ADDRESS_MASK 0x0fff0000 77 #define A_PTR_ADDRESS_MASK 0x0fff0000
75 78
76 #define DATA 0x04 79 #define DATA 0x04 /* Indexed register set data register */
77 80
78 #define IPR 0x08 81 #define IPR 0x08 /* Global interrupt pending register */
79 82 /* Clear pending interrupts by writing a 1 to */
80 83 /* the relevant bits and zero to the other bits */
81 #define IPR_P16V 0x80000000 <<
82 <<
83 #define IPR_GPIOMSG 0x20000000 <<
84 <<
85 84
86 /* The next two interrupts are for the midi po 85 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
87 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 86 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
88 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 87 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
89 88
90 #define IPR_SPDIFBUFFULL 0x04000000 <<
91 #define IPR_SPDIFBUFHALFFULL 0x02000000 <<
92 <<
93 #define IPR_SAMPLERATETRACKER 0x01000000 89 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
94 #define IPR_FXDSP 0x00800000 90 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
95 #define IPR_FORCEINT 0x00400000 91 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
96 #define IPR_PCIERROR 0x00200000 92 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
97 #define IPR_VOLINCR 0x00100000 93 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
98 #define IPR_VOLDECR 0x00080000 94 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
99 #define IPR_MUTE 0x00040000 95 #define IPR_MUTE 0x00040000 /* Mute button pressed */
100 #define IPR_MICBUFFULL 0x00020000 96 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
101 #define IPR_MICBUFHALFFULL 0x00010000 97 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
102 #define IPR_ADCBUFFULL 0x00008000 98 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
103 #define IPR_ADCBUFHALFFULL 0x00004000 99 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
104 #define IPR_EFXBUFFULL 0x00002000 100 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
105 #define IPR_EFXBUFHALFFULL 0x00001000 101 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
106 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 102 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
107 #define IPR_CDROMSTATUSCHANGE 0x00000400 103 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
108 #define IPR_INTERVALTIMER 0x00000200 104 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
109 #define IPR_MIDITRANSBUFEMPTY 0x00000100 105 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
110 #define IPR_MIDIRECVBUFEMPTY 0x00000080 106 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
111 #define IPR_CHANNELLOOP 0x00000040 !! 107 #define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */
112 #define IPR_CHANNELNUMBERMASK 0x0000003f 108 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
113 !! 109 /* Highest set channel in CLIPL or CLIPH. When */
114 !! 110 /* IP is written with CL set, the bit in CLIPL */
115 !! 111 /* or CLIPH corresponding to the CIN value */
116 !! 112 /* written will be cleared. */
117 113
118 #define INTE 0x0c 114 #define INTE 0x0c /* Interrupt enable register */
119 #define INTE_VIRTUALSB_MASK 0xc0000000 115 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
120 #define INTE_VIRTUALSB_220 0x00000000 116 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
121 #define INTE_VIRTUALSB_240 0x40000000 117 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
122 #define INTE_VIRTUALSB_260 0x80000000 118 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
123 #define INTE_VIRTUALSB_280 0xc0000000 119 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
124 #define INTE_VIRTUALMPU_MASK 0x30000000 120 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
125 #define INTE_VIRTUALMPU_300 0x00000000 121 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
126 #define INTE_VIRTUALMPU_310 0x10000000 122 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
127 #define INTE_VIRTUALMPU_320 0x20000000 123 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
128 #define INTE_VIRTUALMPU_330 0x30000000 124 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
129 #define INTE_MASTERDMAENABLE 0x08000000 125 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
130 #define INTE_SLAVEDMAENABLE 0x04000000 126 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
131 #define INTE_MASTERPICENABLE 0x02000000 127 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
132 #define INTE_SLAVEPICENABLE 0x01000000 128 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
133 #define INTE_VSBENABLE 0x00800000 129 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
134 #define INTE_ADLIBENABLE 0x00400000 130 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
135 #define INTE_MPUENABLE 0x00200000 131 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
136 #define INTE_FORCEINT 0x00100000 132 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
137 133
138 #define INTE_MRHANDENABLE 0x00080000 134 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
139 135 /* NOTE: There is no reason to use this under */
140 136 /* Linux, and it will cause odd hardware */
141 137 /* behavior and possibly random segfaults and */
142 138 /* lockups if enabled. */
143 139
144 /* The next two interrupts are for the midi po 140 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
145 #define INTE_A_MIDITXENABLE2 0x00020000 141 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
146 #define INTE_A_MIDIRXENABLE2 0x00010000 142 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
147 143
148 144
149 #define INTE_SAMPLERATETRACKER 0x00002000 145 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
150 146 /* NOTE: This bit must always be enabled */
151 #define INTE_FXDSPENABLE 0x00001000 147 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
152 #define INTE_PCIERRORENABLE 0x00000800 148 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
153 #define INTE_VOLINCRENABLE 0x00000400 149 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
154 #define INTE_VOLDECRENABLE 0x00000200 150 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
155 #define INTE_MUTEENABLE 0x00000100 151 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
156 #define INTE_MICBUFENABLE 0x00000080 152 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
157 #define INTE_ADCBUFENABLE 0x00000040 153 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
158 #define INTE_EFXBUFENABLE 0x00000020 154 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
159 #define INTE_GPSPDIFENABLE 0x00000010 155 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
160 #define INTE_CDSPDIFENABLE 0x00000008 156 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
161 #define INTE_INTERVALTIMERENB 0x00000004 157 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
162 #define INTE_MIDITXENABLE 0x00000002 158 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
163 #define INTE_MIDIRXENABLE 0x00000001 159 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
164 160
165 #define WC 0x10 161 #define WC 0x10 /* Wall Clock register */
166 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 162 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
167 #define WC_SAMPLECOUNTER 0x14060010 163 #define WC_SAMPLECOUNTER 0x14060010
168 #define WC_CURRENTCHANNEL 0x0000003F 164 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
169 165 /* NOTE: Each channel takes 1/64th of a sample */
170 166 /* period to be serviced. */
171 167
172 #define HCFG 0x14 168 #define HCFG 0x14 /* Hardware config register */
173 169 /* NOTE: There is no reason to use the legacy */
174 170 /* SoundBlaster emulation stuff described below */
175 171 /* under Linux, and all kinds of weird hardware */
176 172 /* behavior can result if you try. Don't. */
177 #define HCFG_LEGACYFUNC_MASK 0xe0000000 173 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
178 #define HCFG_LEGACYFUNC_MPU 0x00000000 174 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
179 #define HCFG_LEGACYFUNC_SB 0x40000000 175 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
180 #define HCFG_LEGACYFUNC_AD 0x60000000 176 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
181 #define HCFG_LEGACYFUNC_MPIC 0x80000000 177 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
182 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 178 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
183 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 179 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
184 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 180 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
185 #define HCFG_IOCAPTUREADDR 0x1f000000 181 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
186 #define HCFG_LEGACYWRITE 0x00800000 182 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
187 #define HCFG_LEGACYWORD 0x00400000 183 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
188 #define HCFG_LEGACYINT 0x00200000 184 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
189 185 /* NOTE: The rest of the bits in this register */
190 186 /* _are_ relevant under Linux. */
191 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 !! 187 #define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
192 #define HCFG_BAUD_RATE 0x00080000 <<
193 #define HCFG_EXPANDED_MEM 0x00040000 <<
194 #define HCFG_CODECFORMAT_MASK 0x00030000 <<
195 <<
196 /* Specific to Alice2, CA0102 */ <<
197 #define HCFG_CODECFORMAT_AC97_1 0x00000000 <<
198 #define HCFG_CODECFORMAT_AC97_2 0x00010000 <<
199 #define HCFG_AUTOMUTE_ASYNC 0x00008000 <<
200 <<
201 <<
202 <<
203 #define HCFG_AUTOMUTE_SPDIF 0x00004000 <<
204 <<
205 <<
206 #define HCFG_EMU32_SLAVE 0x00002000 <<
207 #define HCFG_SLOW_RAMP 0x00001000 <<
208 /* 0x00000800 not used on Alice2 */ <<
209 #define HCFG_PHASE_TRACK_MASK 0x00000700 <<
210 <<
211 <<
212 #define HCFG_I2S_ASRC_ENABLE 0x00000070 <<
213 <<
214 <<
215 /* Rest of HCFG 0x0000000f same as below. LOCK <<
216 <<
217 <<
218 <<
219 /* Older chips */ <<
220 #define HCFG_CODECFORMAT_AC97 0x00000000 188 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
221 #define HCFG_CODECFORMAT_I2S 0x00010000 189 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
222 #define HCFG_GPINPUT0 0x00004000 190 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
223 #define HCFG_GPINPUT1 0x00002000 191 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
224 #define HCFG_GPOUTPUT_MASK 0x00001c00 192 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
225 #define HCFG_GPOUT0 0x00001000 193 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
226 #define HCFG_GPOUT1 0x00000800 194 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
227 #define HCFG_GPOUT2 0x00000400 195 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
228 #define HCFG_JOYENABLE 0x00000200 196 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
229 #define HCFG_PHASETRACKENABLE 0x00000100 197 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
230 198 /* 1 = Force all 3 async digital inputs to use */
231 199 /* the same async sample rate tracker (ZVIDEO) */
232 #define HCFG_AC3ENABLE_MASK 0x000000e0 200 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
233 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 201 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
234 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 202 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
235 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 203 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
236 #define HCFG_AUTOMUTE 0x00000010 204 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
237 205 /* will automatically mute their output when */
238 206 /* they are not rate-locked to the external */
239 207 /* async audio source */
240 #define HCFG_LOCKSOUNDCACHE 0x00000008 208 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
241 209 /* NOTE: This should generally never be used. */
242 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 210 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
243 211 /* NOTE: This should generally never be used. */
244 #define HCFG_LOCKTANKCACHE 0x01020014 212 #define HCFG_LOCKTANKCACHE 0x01020014
245 #define HCFG_MUTEBUTTONENABLE 0x00000002 213 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
246 214 /* NOTE: This is a 'cheap' way to implement a */
247 215 /* master mute function on the mute button, and */
248 216 /* in general should not be used unless a more */
249 217 /* sophisticated master mute function has not */
250 218 /* been written. */
251 #define HCFG_AUDIOENABLE 0x00000001 219 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
252 220 /* Should be set to 1 when the EMU10K1 is */
253 221 /* completely initialized. */
254 222
255 //For Audigy, MPU port move to 0x70-0x74 ptr r 223 //For Audigy, MPU port move to 0x70-0x74 ptr register
256 224
257 #define MUDATA 0x18 225 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
258 226
259 #define MUCMD 0x19 227 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
260 #define MUCMD_RESET 0xff 228 #define MUCMD_RESET 0xff /* RESET command */
261 #define MUCMD_ENTERUARTMODE 0x3f 229 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
262 230 /* NOTE: All other commands are ignored */
263 231
264 #define MUSTAT MUCMD 232 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
265 #define MUSTAT_IRDYN 0x80 233 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
266 #define MUSTAT_ORDYN 0x40 234 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
267 235
268 #define A_IOCFG 0x18 236 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
269 #define A_GPINPUT_MASK 0xff00 237 #define A_GPINPUT_MASK 0xff00
270 #define A_GPOUTPUT_MASK 0x00ff 238 #define A_GPOUTPUT_MASK 0x00ff
271 !! 239 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital? */
272 // Audigy output/GPIO stuff taken from the kX !! 240 #define A_IOCFG_GPOUT1 0x0002 /* IR */
273 #define A_IOCFG_GPOUT0 0x0044 <<
274 #define A_IOCFG_DISABLE_ANALOG 0x0040 <<
275 #define A_IOCFG_ENABLE_DIGITAL 0x0004 <<
276 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080 <<
277 #define A_IOCFG_UNKNOWN_20 0x0020 <<
278 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 <<
279 #define A_IOCFG_GPOUT1 0x0002 <<
280 #define A_IOCFG_GPOUT2 0x0001 241 #define A_IOCFG_GPOUT2 0x0001 /* IR */
281 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 <<
282 <<
283 #define A_IOCFG_DIGITAL_JACK 0x1000 <<
284 #define A_IOCFG_FRONT_JACK 0x4000 <<
285 #define A_IOCFG_REAR_JACK 0x8000 <<
286 #define A_IOCFG_PHONES_JACK 0x0100 <<
287 <<
288 /* outputs: <<
289 * for audigy2 platinum: 0xa00 <<
290 * for a2 platinum ex: 0x1c00 <<
291 * for a1 platinum: 0x0 <<
292 */ <<
293 242
294 #define TIMER 0x1a 243 #define TIMER 0x1a /* Timer terminal count register */
295 244 /* NOTE: After the rate is changed, a maximum */
296 245 /* of 1024 sample periods should be allowed */
297 246 /* before the new rate is guaranteed accurate. */
298 #define TIMER_RATE_MASK 0x000003ff 247 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
299 248 /* 0 == 1024 periods, [1..4] are not useful */
300 #define TIMER_RATE 0x0a00001a 249 #define TIMER_RATE 0x0a00001a
301 250
302 #define AC97DATA 0x1c 251 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
303 252
304 #define AC97ADDRESS 0x1e 253 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
305 #define AC97ADDRESS_READY 0x80 254 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
306 #define AC97ADDRESS_ADDRESS 0x7f 255 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
307 256
308 /* Available on the Audigy 2 and Audigy 4 only <<
309 #define PTR2 0x20 <<
310 #define DATA2 0x24 <<
311 #define IPR2 0x28 <<
312 #define IPR2_PLAYBACK_CH_0_LOOP 0x0000100 <<
313 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x0000010 <<
314 #define IPR2_CAPTURE_CH_0_LOOP 0x0010000 <<
315 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x0001000 <<
316 <<
317 <<
318 <<
319 #define INTE2 0x2c <<
320 #define INTE2_PLAYBACK_CH_0_LOOP 0x000010 <<
321 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x000001 <<
322 #define INTE2_PLAYBACK_CH_1_LOOP 0x000020 <<
323 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x000002 <<
324 #define INTE2_PLAYBACK_CH_2_LOOP 0x000040 <<
325 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x000004 <<
326 #define INTE2_PLAYBACK_CH_3_LOOP 0x000080 <<
327 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x000008 <<
328 #define INTE2_CAPTURE_CH_0_LOOP 0x001000 <<
329 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x000100 <<
330 #define HCFG2 0x34 <<
331 <<
332 <<
333 <<
334 <<
335 <<
336 <<
337 <<
338 <<
339 <<
340 <<
341 <<
342 <<
343 <<
344 <<
345 <<
346 #define IPR3 0x38 <<
347 #define INTE3 0x3c <<
348 /********************************************* 257 /************************************************************************************************/
349 /* PCI function 1 registers, address = <val> + 258 /* PCI function 1 registers, address = <val> + PCIBASE1 */
350 /********************************************* 259 /************************************************************************************************/
351 260
352 #define JOYSTICK1 0x00 261 #define JOYSTICK1 0x00 /* Analog joystick port register */
353 #define JOYSTICK2 0x01 262 #define JOYSTICK2 0x01 /* Analog joystick port register */
354 #define JOYSTICK3 0x02 263 #define JOYSTICK3 0x02 /* Analog joystick port register */
355 #define JOYSTICK4 0x03 264 #define JOYSTICK4 0x03 /* Analog joystick port register */
356 #define JOYSTICK5 0x04 265 #define JOYSTICK5 0x04 /* Analog joystick port register */
357 #define JOYSTICK6 0x05 266 #define JOYSTICK6 0x05 /* Analog joystick port register */
358 #define JOYSTICK7 0x06 267 #define JOYSTICK7 0x06 /* Analog joystick port register */
359 #define JOYSTICK8 0x07 268 #define JOYSTICK8 0x07 /* Analog joystick port register */
360 269
361 /* When writing, any write causes JOYSTICK_COM 270 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
362 /* When reading, use these bitfields: */ 271 /* When reading, use these bitfields: */
363 #define JOYSTICK_BUTTONS 0x0f 272 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
364 #define JOYSTICK_COMPARATOR 0xf0 273 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
365 274
366 275
367 /********************************************* 276 /********************************************************************************************************/
368 /* Emu10k1 pointer-offset register set, access 277 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
369 /********************************************* 278 /********************************************************************************************************/
370 279
371 #define CPF 0x00 280 #define CPF 0x00 /* Current pitch and fraction register */
372 #define CPF_CURRENTPITCH_MASK 0xffff0000 281 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
373 #define CPF_CURRENTPITCH 0x10100000 282 #define CPF_CURRENTPITCH 0x10100000
374 #define CPF_STEREO_MASK 0x00008000 283 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
375 #define CPF_STOP_MASK 0x00004000 284 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
376 #define CPF_FRACADDRESS_MASK 0x00003fff 285 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
377 286
378 #define PTRX 0x01 287 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
379 #define PTRX_PITCHTARGET_MASK 0xffff0000 288 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
380 #define PTRX_PITCHTARGET 0x10100001 289 #define PTRX_PITCHTARGET 0x10100001
381 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 290 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
382 #define PTRX_FXSENDAMOUNT_A 0x08080001 291 #define PTRX_FXSENDAMOUNT_A 0x08080001
383 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff 292 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
384 #define PTRX_FXSENDAMOUNT_B 0x08000001 293 #define PTRX_FXSENDAMOUNT_B 0x08000001
385 294
386 #define CVCF 0x02 295 #define CVCF 0x02 /* Current volume and filter cutoff register */
387 #define CVCF_CURRENTVOL_MASK 0xffff0000 296 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
388 #define CVCF_CURRENTVOL 0x10100002 297 #define CVCF_CURRENTVOL 0x10100002
389 #define CVCF_CURRENTFILTER_MASK 0x0000ffff 298 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
390 #define CVCF_CURRENTFILTER 0x10000002 299 #define CVCF_CURRENTFILTER 0x10000002
391 300
392 #define VTFT 0x03 301 #define VTFT 0x03 /* Volume target and filter cutoff target register */
393 #define VTFT_VOLUMETARGET_MASK 0xffff0000 302 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
394 #define VTFT_VOLUMETARGET 0x10100003 303 #define VTFT_VOLUMETARGET 0x10100003
395 #define VTFT_FILTERTARGET_MASK 0x0000ffff 304 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
396 #define VTFT_FILTERTARGET 0x10000003 305 #define VTFT_FILTERTARGET 0x10000003
397 306
398 #define Z1 0x05 307 #define Z1 0x05 /* Filter delay memory 1 register */
399 308
400 #define Z2 0x04 309 #define Z2 0x04 /* Filter delay memory 2 register */
401 310
402 #define PSST 0x06 311 #define PSST 0x06 /* Send C amount and loop start address register */
403 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 312 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
404 313
405 #define PSST_FXSENDAMOUNT_C 0x08180006 314 #define PSST_FXSENDAMOUNT_C 0x08180006
406 315
407 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff 316 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
408 #define PSST_LOOPSTARTADDR 0x18000006 317 #define PSST_LOOPSTARTADDR 0x18000006
409 318
410 #define DSL 0x07 319 #define DSL 0x07 /* Send D amount and loop start address register */
411 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 320 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
412 321
413 #define DSL_FXSENDAMOUNT_D 0x08180007 322 #define DSL_FXSENDAMOUNT_D 0x08180007
414 323
415 #define DSL_LOOPENDADDR_MASK 0x00ffffff 324 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
416 #define DSL_LOOPENDADDR 0x18000007 325 #define DSL_LOOPENDADDR 0x18000007
417 326
418 #define CCCA 0x08 327 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
419 #define CCCA_RESONANCE 0xf0000000 328 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
420 #define CCCA_INTERPROMMASK 0x0e000000 329 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
421 330 /* 1 == full band, 7 == lowpass */
422 331 /* ROM 0 is used when pitch shifting downward or less */
423 332 /* then 3 semitones upward. Increasingly higher ROM */
424 333 /* numbers are used, typically in steps of 3 semitones, */
425 334 /* as upward pitch shifting is performed. */
426 #define CCCA_INTERPROM_0 0x00000000 335 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
427 #define CCCA_INTERPROM_1 0x02000000 336 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
428 #define CCCA_INTERPROM_2 0x04000000 337 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
429 #define CCCA_INTERPROM_3 0x06000000 338 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
430 #define CCCA_INTERPROM_4 0x08000000 339 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
431 #define CCCA_INTERPROM_5 0x0a000000 340 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
432 #define CCCA_INTERPROM_6 0x0c000000 341 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
433 #define CCCA_INTERPROM_7 0x0e000000 342 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
434 #define CCCA_8BITSELECT 0x01000000 343 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
435 #define CCCA_CURRADDR_MASK 0x00ffffff 344 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
436 #define CCCA_CURRADDR 0x18000008 345 #define CCCA_CURRADDR 0x18000008
437 346
438 #define CCR 0x09 347 #define CCR 0x09 /* Cache control register */
439 #define CCR_CACHEINVALIDSIZE 0x07190009 348 #define CCR_CACHEINVALIDSIZE 0x07190009
440 #define CCR_CACHEINVALIDSIZE_MASK 0xfe00 349 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
441 #define CCR_CACHELOOPFLAG 0x01000000 350 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
442 #define CCR_INTERLEAVEDSAMPLES 0x00800000 351 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
443 #define CCR_WORDSIZEDSAMPLES 0x00400000 352 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
444 #define CCR_READADDRESS 0x06100009 353 #define CCR_READADDRESS 0x06100009
445 #define CCR_READADDRESS_MASK 0x003f0000 354 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
446 #define CCR_LOOPINVALSIZE 0x0000fe00 355 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
447 356 /* NOTE: This is valid only if CACHELOOPFLAG is set */
448 #define CCR_LOOPFLAG 0x00000100 357 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
449 #define CCR_CACHELOOPADDRHI 0x000000ff 358 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
450 359
451 #define CLP 0x0a 360 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
452 361 /* NOTE: This register is normally not used */
453 #define CLP_CACHELOOPADDR 0x0000ffff 362 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
454 363
455 #define FXRT 0x0b 364 #define FXRT 0x0b /* Effects send routing register */
456 365 /* NOTE: It is illegal to assign the same routing to */
457 366 /* two effects sends. */
458 #define FXRT_CHANNELA 0x000f0000 367 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
459 #define FXRT_CHANNELB 0x00f00000 368 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
460 #define FXRT_CHANNELC 0x0f000000 369 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
461 #define FXRT_CHANNELD 0xf0000000 370 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
462 371
463 #define A_HR 0x0b /* Hig <<
464 #define MAPA 0x0c 372 #define MAPA 0x0c /* Cache map A */
465 373
466 #define MAPB 0x0d 374 #define MAPB 0x0d /* Cache map B */
467 375
468 #define MAP_PTE_MASK 0xffffe000 376 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
469 #define MAP_PTI_MASK 0x00001fff 377 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
470 378
471 /* 0x0e, 0x0f: Not used */ <<
472 <<
473 #define ENVVOL 0x10 379 #define ENVVOL 0x10 /* Volume envelope register */
474 #define ENVVOL_MASK 0x0000ffff 380 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
475 381 /* 0x8000-n == 666*n usec delay */
476 382
477 #define ATKHLDV 0x11 383 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
478 #define ATKHLDV_PHASE0 0x00008000 384 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
479 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 385 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
480 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f 386 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
481 387 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
482 388
483 #define DCYSUSV 0x12 389 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
484 #define DCYSUSV_PHASE1_MASK 0x00008000 390 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
485 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 391 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
486 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 392 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
487 393 /* this channel and from writing to pitch, filter and */
488 394 /* volume targets. */
489 #define DCYSUSV_DECAYTIME_MASK 0x0000007f 395 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
490 396 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
491 397
492 #define LFOVAL1 0x13 398 #define LFOVAL1 0x13 /* Modulation LFO value */
493 #define LFOVAL_MASK 0x0000ffff 399 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
494 400 /* 0x8000-n == 666*n usec delay */
495 401
496 #define ENVVAL 0x14 402 #define ENVVAL 0x14 /* Modulation envelope register */
497 #define ENVVAL_MASK 0x0000ffff 403 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
498 404 /* 0x8000-n == 666*n usec delay */
499 405
500 #define ATKHLDM 0x15 406 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
501 #define ATKHLDM_PHASE0 0x00008000 407 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
502 #define ATKHLDM_HOLDTIME 0x00007f00 408 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
503 #define ATKHLDM_ATTACKTIME 0x0000007f 409 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
504 410 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
505 411
506 #define DCYSUSM 0x16 412 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
507 #define DCYSUSM_PHASE1_MASK 0x00008000 413 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
508 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 414 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
509 #define DCYSUSM_DECAYTIME_MASK 0x0000007f 415 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
510 416 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
511 417
512 #define LFOVAL2 0x17 418 #define LFOVAL2 0x17 /* Vibrato LFO register */
513 #define LFOVAL2_MASK 0x0000ffff 419 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
514 420 /* 0x8000-n == 666*n usec delay */
515 421
516 #define IP 0x18 422 #define IP 0x18 /* Initial pitch register */
517 #define IP_MASK 0x0000ffff 423 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
518 424 /* 4 bits of octave, 12 bits of fractional octave */
519 #define IP_UNITY 0x0000e000 425 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
520 426
521 #define IFATN 0x19 427 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
522 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 428 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
523 429 /* 6 most significant bits are semitones */
524 430 /* 2 least significant bits are fractions */
525 #define IFATN_FILTERCUTOFF 0x08080019 431 #define IFATN_FILTERCUTOFF 0x08080019
526 #define IFATN_ATTENUATION_MASK 0x000000ff 432 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
527 #define IFATN_ATTENUATION 0x08000019 433 #define IFATN_ATTENUATION 0x08000019
528 434
529 435
530 #define PEFE 0x1a 436 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
531 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 437 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
532 438 /* Signed 2's complement, +/- one octave peak extremes */
533 #define PEFE_PITCHAMOUNT 0x0808001a 439 #define PEFE_PITCHAMOUNT 0x0808001a
534 #define PEFE_FILTERAMOUNT_MASK 0x000000ff 440 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
535 441 /* Signed 2's complement, +/- six octaves peak extremes */
536 #define PEFE_FILTERAMOUNT 0x0800001a 442 #define PEFE_FILTERAMOUNT 0x0800001a
537 #define FMMOD 0x1b 443 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
538 #define FMMOD_MODVIBRATO 0x0000ff00 444 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
539 445 /* Signed 2's complement, +/- one octave extremes */
540 #define FMMOD_MOFILTER 0x000000ff 446 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
541 447 /* Signed 2's complement, +/- three octave extremes */
542 448
543 449
544 #define TREMFRQ 0x1c 450 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
545 #define TREMFRQ_DEPTH 0x0000ff00 451 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
546 452 /* Signed 2's complement, with +/- 12dB extremes */
547 453
548 #define TREMFRQ_FREQUENCY 0x000000ff 454 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
549 455 /* ??Hz steps, maximum of ?? Hz. */
550 #define FM2FRQ2 0x1d 456 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
551 #define FM2FRQ2_DEPTH 0x0000ff00 457 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
552 458 /* Signed 2's complement, +/- one octave extremes */
553 #define FM2FRQ2_FREQUENCY 0x000000ff 459 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
554 460 /* 0.039Hz steps, maximum of 9.85 Hz. */
555 461
556 #define TEMPENV 0x1e 462 #define TEMPENV 0x1e /* Tempory envelope register */
557 #define TEMPENV_MASK 0x0000ffff 463 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
558 464 /* NOTE: All channels contain internal variables; do */
559 465 /* not write to these locations. */
560 466
561 /* 0x1f: not used */ <<
562 <<
563 #define CD0 0x20 467 #define CD0 0x20 /* Cache data 0 register */
564 #define CD1 0x21 468 #define CD1 0x21 /* Cache data 1 register */
565 #define CD2 0x22 469 #define CD2 0x22 /* Cache data 2 register */
566 #define CD3 0x23 470 #define CD3 0x23 /* Cache data 3 register */
567 #define CD4 0x24 471 #define CD4 0x24 /* Cache data 4 register */
568 #define CD5 0x25 472 #define CD5 0x25 /* Cache data 5 register */
569 #define CD6 0x26 473 #define CD6 0x26 /* Cache data 6 register */
570 #define CD7 0x27 474 #define CD7 0x27 /* Cache data 7 register */
571 #define CD8 0x28 475 #define CD8 0x28 /* Cache data 8 register */
572 #define CD9 0x29 476 #define CD9 0x29 /* Cache data 9 register */
573 #define CDA 0x2a 477 #define CDA 0x2a /* Cache data A register */
574 #define CDB 0x2b 478 #define CDB 0x2b /* Cache data B register */
575 #define CDC 0x2c 479 #define CDC 0x2c /* Cache data C register */
576 #define CDD 0x2d 480 #define CDD 0x2d /* Cache data D register */
577 #define CDE 0x2e 481 #define CDE 0x2e /* Cache data E register */
578 #define CDF 0x2f 482 #define CDF 0x2f /* Cache data F register */
579 483
580 /* 0x30-3f seem to be the same as 0x20-2f */ <<
581 <<
582 #define PTB 0x40 484 #define PTB 0x40 /* Page table base register */
583 #define PTB_MASK 0xfffff000 485 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
584 486
585 #define TCB 0x41 487 #define TCB 0x41 /* Tank cache base register */
586 #define TCB_MASK 0xfffff000 488 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
587 489
588 #define ADCCR 0x42 490 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
589 #define ADCCR_RCHANENABLE 0x00000010 491 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
590 #define ADCCR_LCHANENABLE 0x00000008 492 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
591 493 /* NOTE: To guarantee phase coherency, both channels */
592 494 /* must be disabled prior to enabling both channels. */
593 #define A_ADCCR_RCHANENABLE 0x00000020 495 #define A_ADCCR_RCHANENABLE 0x00000020
594 #define A_ADCCR_LCHANENABLE 0x00000010 496 #define A_ADCCR_LCHANENABLE 0x00000010
595 497
596 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F 498 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
597 #define ADCCR_SAMPLERATE_MASK 0x00000007 499 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
598 #define ADCCR_SAMPLERATE_48 0x00000000 500 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
599 #define ADCCR_SAMPLERATE_44 0x00000001 501 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
600 #define ADCCR_SAMPLERATE_32 0x00000002 502 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
601 #define ADCCR_SAMPLERATE_24 0x00000003 503 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
602 #define ADCCR_SAMPLERATE_22 0x00000004 504 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
603 #define ADCCR_SAMPLERATE_16 0x00000005 505 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
604 #define ADCCR_SAMPLERATE_11 0x00000006 506 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
605 #define ADCCR_SAMPLERATE_8 0x00000007 507 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
606 #define A_ADCCR_SAMPLERATE_12 0x00000006 508 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
607 #define A_ADCCR_SAMPLERATE_11 0x00000007 509 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
608 #define A_ADCCR_SAMPLERATE_8 0x00000008 510 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
609 511
610 #define FXWC 0x43 512 #define FXWC 0x43 /* FX output write channels register */
611 513 /* When set, each bit enables the writing of the */
612 !! 514 /* corresponding FX output channel into host memory */
613 <<
614 <<
615 <<
616 <<
617 #define FXWC_DEFAULTROUTE_C (1<<0) 515 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
618 #define FXWC_DEFAULTROUTE_B (1<<1) 516 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
619 #define FXWC_DEFAULTROUTE_A (1<<12) 517 #define FXWC_DEFAULTROUTE_A (1<<12)
620 #define FXWC_DEFAULTROUTE_D (1<<13) 518 #define FXWC_DEFAULTROUTE_D (1<<13)
621 #define FXWC_ADCLEFT (1<<18) 519 #define FXWC_ADCLEFT (1<<18)
622 #define FXWC_CDROMSPDIFLEFT (1<<18) 520 #define FXWC_CDROMSPDIFLEFT (1<<18)
623 #define FXWC_ADCRIGHT (1<<19) 521 #define FXWC_ADCRIGHT (1<<19)
624 #define FXWC_CDROMSPDIFRIGHT (1<<19) 522 #define FXWC_CDROMSPDIFRIGHT (1<<19)
625 #define FXWC_MIC (1<<20) 523 #define FXWC_MIC (1<<20)
626 #define FXWC_ZOOMLEFT (1<<20) 524 #define FXWC_ZOOMLEFT (1<<20)
627 #define FXWC_ZOOMRIGHT (1<<21) 525 #define FXWC_ZOOMRIGHT (1<<21)
628 #define FXWC_SPDIFLEFT (1<<22) 526 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
629 #define FXWC_SPDIFRIGHT (1<<23) 527 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
630 528
631 #define A_TBLSZ 0x43 /* Eff <<
632 <<
633 #define TCBS 0x44 529 #define TCBS 0x44 /* Tank cache buffer size register */
634 #define TCBS_MASK 0x00000007 530 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
635 #define TCBS_BUFFSIZE_16K 0x00000000 531 #define TCBS_BUFFSIZE_16K 0x00000000
636 #define TCBS_BUFFSIZE_32K 0x00000001 532 #define TCBS_BUFFSIZE_32K 0x00000001
637 #define TCBS_BUFFSIZE_64K 0x00000002 533 #define TCBS_BUFFSIZE_64K 0x00000002
638 #define TCBS_BUFFSIZE_128K 0x00000003 534 #define TCBS_BUFFSIZE_128K 0x00000003
639 #define TCBS_BUFFSIZE_256K 0x00000004 535 #define TCBS_BUFFSIZE_256K 0x00000004
640 #define TCBS_BUFFSIZE_512K 0x00000005 536 #define TCBS_BUFFSIZE_512K 0x00000005
641 #define TCBS_BUFFSIZE_1024K 0x00000006 537 #define TCBS_BUFFSIZE_1024K 0x00000006
642 #define TCBS_BUFFSIZE_2048K 0x00000007 538 #define TCBS_BUFFSIZE_2048K 0x00000007
643 539
644 #define MICBA 0x45 540 #define MICBA 0x45 /* AC97 microphone buffer address register */
645 #define MICBA_MASK 0xfffff000 541 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
646 542
647 #define ADCBA 0x46 543 #define ADCBA 0x46 /* ADC buffer address register */
648 #define ADCBA_MASK 0xfffff000 544 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
649 545
650 #define FXBA 0x47 546 #define FXBA 0x47 /* FX Buffer Address */
651 #define FXBA_MASK 0xfffff000 547 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
652 548
653 #define A_HWM 0x48 /* Hig <<
654 <<
655 #define MICBS 0x49 549 #define MICBS 0x49 /* Microphone buffer size register */
656 550
657 #define ADCBS 0x4a 551 #define ADCBS 0x4a /* ADC buffer size register */
658 552
659 #define FXBS 0x4b 553 #define FXBS 0x4b /* FX buffer size register */
660 554
661 /* register: 0x4c..4f: ffff-ffff current amoun <<
662 <<
663 /* The following mask values define the size o 555 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
664 #define ADCBS_BUFSIZE_NONE 0x00000000 556 #define ADCBS_BUFSIZE_NONE 0x00000000
665 #define ADCBS_BUFSIZE_384 0x00000001 557 #define ADCBS_BUFSIZE_384 0x00000001
666 #define ADCBS_BUFSIZE_448 0x00000002 558 #define ADCBS_BUFSIZE_448 0x00000002
667 #define ADCBS_BUFSIZE_512 0x00000003 559 #define ADCBS_BUFSIZE_512 0x00000003
668 #define ADCBS_BUFSIZE_640 0x00000004 560 #define ADCBS_BUFSIZE_640 0x00000004
669 #define ADCBS_BUFSIZE_768 0x00000005 561 #define ADCBS_BUFSIZE_768 0x00000005
670 #define ADCBS_BUFSIZE_896 0x00000006 562 #define ADCBS_BUFSIZE_896 0x00000006
671 #define ADCBS_BUFSIZE_1024 0x00000007 563 #define ADCBS_BUFSIZE_1024 0x00000007
672 #define ADCBS_BUFSIZE_1280 0x00000008 564 #define ADCBS_BUFSIZE_1280 0x00000008
673 #define ADCBS_BUFSIZE_1536 0x00000009 565 #define ADCBS_BUFSIZE_1536 0x00000009
674 #define ADCBS_BUFSIZE_1792 0x0000000a 566 #define ADCBS_BUFSIZE_1792 0x0000000a
675 #define ADCBS_BUFSIZE_2048 0x0000000b 567 #define ADCBS_BUFSIZE_2048 0x0000000b
676 #define ADCBS_BUFSIZE_2560 0x0000000c 568 #define ADCBS_BUFSIZE_2560 0x0000000c
677 #define ADCBS_BUFSIZE_3072 0x0000000d 569 #define ADCBS_BUFSIZE_3072 0x0000000d
678 #define ADCBS_BUFSIZE_3584 0x0000000e 570 #define ADCBS_BUFSIZE_3584 0x0000000e
679 #define ADCBS_BUFSIZE_4096 0x0000000f 571 #define ADCBS_BUFSIZE_4096 0x0000000f
680 #define ADCBS_BUFSIZE_5120 0x00000010 572 #define ADCBS_BUFSIZE_5120 0x00000010
681 #define ADCBS_BUFSIZE_6144 0x00000011 573 #define ADCBS_BUFSIZE_6144 0x00000011
682 #define ADCBS_BUFSIZE_7168 0x00000012 574 #define ADCBS_BUFSIZE_7168 0x00000012
683 #define ADCBS_BUFSIZE_8192 0x00000013 575 #define ADCBS_BUFSIZE_8192 0x00000013
684 #define ADCBS_BUFSIZE_10240 0x00000014 576 #define ADCBS_BUFSIZE_10240 0x00000014
685 #define ADCBS_BUFSIZE_12288 0x00000015 577 #define ADCBS_BUFSIZE_12288 0x00000015
686 #define ADCBS_BUFSIZE_14366 0x00000016 578 #define ADCBS_BUFSIZE_14366 0x00000016
687 #define ADCBS_BUFSIZE_16384 0x00000017 579 #define ADCBS_BUFSIZE_16384 0x00000017
688 #define ADCBS_BUFSIZE_20480 0x00000018 580 #define ADCBS_BUFSIZE_20480 0x00000018
689 #define ADCBS_BUFSIZE_24576 0x00000019 581 #define ADCBS_BUFSIZE_24576 0x00000019
690 #define ADCBS_BUFSIZE_28672 0x0000001a 582 #define ADCBS_BUFSIZE_28672 0x0000001a
691 #define ADCBS_BUFSIZE_32768 0x0000001b 583 #define ADCBS_BUFSIZE_32768 0x0000001b
692 #define ADCBS_BUFSIZE_40960 0x0000001c 584 #define ADCBS_BUFSIZE_40960 0x0000001c
693 #define ADCBS_BUFSIZE_49152 0x0000001d 585 #define ADCBS_BUFSIZE_49152 0x0000001d
694 #define ADCBS_BUFSIZE_57344 0x0000001e 586 #define ADCBS_BUFSIZE_57344 0x0000001e
695 #define ADCBS_BUFSIZE_65536 0x0000001f 587 #define ADCBS_BUFSIZE_65536 0x0000001f
696 588
697 /* Current Send B, A Amounts */ <<
698 #define A_CSBA 0x4c <<
699 <<
700 /* Current Send D, C Amounts */ <<
701 #define A_CSDC 0x4d <<
702 <<
703 /* Current Send F, E Amounts */ <<
704 #define A_CSFE 0x4e <<
705 <<
706 /* Current Send H, G Amounts */ <<
707 #define A_CSHG 0x4f <<
708 <<
709 589
710 #define CDCS 0x50 590 #define CDCS 0x50 /* CD-ROM digital channel status register */
711 591
712 #define GPSCS 0x51 592 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
713 593
714 #define DBG 0x52 594 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
715 595
716 /* S/PDIF Input C Channel Status */ <<
717 #define A_SPSC 0x52 <<
718 <<
719 #define REG53 0x53 596 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
720 597
721 #define A_DBG 0x53 598 #define A_DBG 0x53
722 #define A_DBG_SINGLE_STEP 0x00020000 599 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
723 #define A_DBG_ZC 0x40000000 600 #define A_DBG_ZC 0x40000000 /* zero tram counter */
724 #define A_DBG_STEP_ADDR 0x000003ff 601 #define A_DBG_STEP_ADDR 0x000003ff
725 #define A_DBG_SATURATION_OCCURED 0x20000000 602 #define A_DBG_SATURATION_OCCURED 0x20000000
726 #define A_DBG_SATURATION_ADDR 0x0ffc0000 603 #define A_DBG_SATURATION_ADDR 0x0ffc0000
727 604
728 // NOTE: 0x54,55,56: 64-bit <<
729 #define SPCS0 0x54 605 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
730 606
731 #define SPCS1 0x55 607 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
732 608
733 #define SPCS2 0x56 609 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
734 610
735 #define SPCS_CLKACCYMASK 0x30000000 611 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
736 #define SPCS_CLKACCY_1000PPM 0x00000000 612 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
737 #define SPCS_CLKACCY_50PPM 0x10000000 613 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
738 #define SPCS_CLKACCY_VARIABLE 0x20000000 614 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
739 #define SPCS_SAMPLERATEMASK 0x0f000000 615 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
740 #define SPCS_SAMPLERATE_44 0x00000000 616 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
741 #define SPCS_SAMPLERATE_48 0x02000000 617 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
742 #define SPCS_SAMPLERATE_32 0x03000000 618 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
743 #define SPCS_CHANNELNUMMASK 0x00f00000 619 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
744 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 620 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
745 #define SPCS_CHANNELNUM_LEFT 0x00100000 621 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
746 #define SPCS_CHANNELNUM_RIGHT 0x00200000 622 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
747 #define SPCS_SOURCENUMMASK 0x000f0000 623 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
748 #define SPCS_SOURCENUM_UNSPEC 0x00000000 624 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
749 #define SPCS_GENERATIONSTATUS 0x00008000 625 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
750 #define SPCS_CATEGORYCODEMASK 0x00007f00 626 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
751 #define SPCS_MODEMASK 0x000000c0 627 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
752 #define SPCS_EMPHASISMASK 0x00000038 628 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
753 #define SPCS_EMPHASIS_NONE 0x00000000 629 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
754 #define SPCS_EMPHASIS_50_15 0x00000008 630 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
755 #define SPCS_COPYRIGHT 0x00000004 631 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
756 #define SPCS_NOTAUDIODATA 0x00000002 632 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
757 #define SPCS_PROFESSIONAL 0x00000001 633 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
758 634
759 /* 0x57: Not used */ <<
760 <<
761 /* The 32-bit CLIx and SOLx registers all have 635 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
762 #define CLIEL 0x58 636 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
763 637
764 #define CLIEH 0x59 638 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
765 639
766 #define CLIPL 0x5a 640 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
767 641
768 #define CLIPH 0x5b 642 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
769 643
770 #define SOLEL 0x5c 644 #define SOLEL 0x5c /* Stop on loop enable low register */
771 645
772 #define SOLEH 0x5d 646 #define SOLEH 0x5d /* Stop on loop enable high register */
773 647
774 #define SPBYPASS 0x5e 648 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
775 #define SPBYPASS_SPDIF0_MASK 0x00000003 649 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
776 #define SPBYPASS_SPDIF1_MASK 0x0000000c 650 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
777 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDI 651 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
778 #define SPBYPASS_FORMAT 0x00000f00 652 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
779 653
780 #define AC97SLOT 0x5f 654 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
781 #define AC97SLOT_REAR_RIGHT 0x01 655 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
782 #define AC97SLOT_REAR_LEFT 0x02 656 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
783 #define AC97SLOT_CNTR 0x10 657 #define AC97SLOT_CNTR 0x10 /* Center enable */
784 #define AC97SLOT_LFE 0x20 658 #define AC97SLOT_LFE 0x20 /* LFE enable */
785 659
786 /* PCB Revision */ <<
787 #define A_PCB 0x5f <<
788 <<
789 // NOTE: 0x60,61,62: 64-bit <<
790 #define CDSRCS 0x60 660 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
791 661
792 #define GPSRCS 0x61 662 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
793 663
794 #define ZVSRCS 0x62 664 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
795 665 /* NOTE: This one has no SPDIFLOCKED field */
796 666 /* Assumes sample lock */
797 667
798 /* These three bitfields apply to CDSRCS, GPSR 668 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
799 #define SRCS_SPDIFVALID 0x04000000 <<
800 #define SRCS_SPDIFLOCKED 0x02000000 669 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
801 #define SRCS_RATELOCKED 0x01000000 670 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
802 #define SRCS_ESTSAMPLERATE 0x0007ffff 671 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
803 672
804 /* Note that these values can vary +/- by a sm 673 /* Note that these values can vary +/- by a small amount */
805 #define SRCS_SPDIFRATE_44 0x0003acd9 674 #define SRCS_SPDIFRATE_44 0x0003acd9
806 #define SRCS_SPDIFRATE_48 0x00040000 675 #define SRCS_SPDIFRATE_48 0x00040000
807 #define SRCS_SPDIFRATE_96 0x00080000 676 #define SRCS_SPDIFRATE_96 0x00080000
808 677
809 #define MICIDX 0x63 678 #define MICIDX 0x63 /* Microphone recording buffer index register */
810 #define MICIDX_MASK 0x0000ffff 679 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
811 #define MICIDX_IDX 0x10000063 680 #define MICIDX_IDX 0x10000063
812 681
813 #define ADCIDX 0x64 682 #define ADCIDX 0x64 /* ADC recording buffer index register */
814 #define ADCIDX_MASK 0x0000ffff 683 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
815 #define ADCIDX_IDX 0x10000064 684 #define ADCIDX_IDX 0x10000064
816 685
817 #define A_ADCIDX 0x63 686 #define A_ADCIDX 0x63
818 #define A_ADCIDX_IDX 0x10000063 687 #define A_ADCIDX_IDX 0x10000063
819 688
820 #define A_MICIDX 0x64 689 #define A_MICIDX 0x64
821 #define A_MICIDX_IDX 0x10000064 690 #define A_MICIDX_IDX 0x10000064
822 691
823 #define FXIDX 0x65 692 #define FXIDX 0x65 /* FX recording buffer index register */
824 #define FXIDX_MASK 0x0000ffff 693 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
825 #define FXIDX_IDX 0x10000065 694 #define FXIDX_IDX 0x10000065
826 695
827 /* The 32-bit HLIx and HLIPx registers all hav <<
828 #define HLIEL 0x66 <<
829 <<
830 #define HLIEH 0x67 <<
831 <<
832 #define HLIPL 0x68 <<
833 <<
834 #define HLIPH 0x69 <<
835 <<
836 /* S/PDIF Host Record Index (bypasses SRC) */ <<
837 #define A_SPRI 0x6a <<
838 /* S/PDIF Host Record Address */ <<
839 #define A_SPRA 0x6b <<
840 /* S/PDIF Host Record Control */ <<
841 #define A_SPRC 0x6c <<
842 /* Delayed Interrupt Counter & Enable */ <<
843 #define A_DICE 0x6d <<
844 /* Tank Table Base */ <<
845 #define A_TTB 0x6e <<
846 /* Tank Delay Offset */ <<
847 #define A_TDOF 0x6f <<
848 <<
849 /* This is the MPU port on the card (via the g 696 /* This is the MPU port on the card (via the game port) */
850 #define A_MUDATA1 0x70 697 #define A_MUDATA1 0x70
851 #define A_MUCMD1 0x71 698 #define A_MUCMD1 0x71
852 #define A_MUSTAT1 A_MUCMD1 699 #define A_MUSTAT1 A_MUCMD1
853 700
854 /* This is the MPU port on the Audigy Drive 701 /* This is the MPU port on the Audigy Drive */
855 #define A_MUDATA2 0x72 702 #define A_MUDATA2 0x72
856 #define A_MUCMD2 0x73 703 #define A_MUCMD2 0x73
857 #define A_MUSTAT2 A_MUCMD2 704 #define A_MUSTAT2 A_MUCMD2
858 705
859 /* The next two are the Audigy equivalent of F 706 /* The next two are the Audigy equivalent of FXWC */
860 /* the Audigy can record any output (16bit, 48 707 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
861 /* Each bit selects a channel for recording */ 708 /* Each bit selects a channel for recording */
862 #define A_FXWC1 0x74 709 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
863 #define A_FXWC2 0x75 710 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
864 711
865 /* Extended Hardware Control */ <<
866 #define A_SPDIF_SAMPLERATE 0x76 712 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
867 #define A_SAMPLE_RATE 0x76 !! 713 #define A_SPDIF_48000 0x00000080
868 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e !! 714 #define A_SPDIF_44100 0x00000000
869 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 <<
870 #define A_SPDIF_RATE_MASK 0x000000e0 <<
871 #define A_SPDIF_48000 0x00000000 <<
872 #define A_SPDIF_192000 0x00000020 <<
873 #define A_SPDIF_96000 0x00000040 715 #define A_SPDIF_96000 0x00000040
874 #define A_SPDIF_44100 0x00000080 <<
875 <<
876 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 <<
877 #define A_I2S_CAPTURE_48000 0x00000000 <<
878 #define A_I2S_CAPTURE_192000 0x00000200 <<
879 #define A_I2S_CAPTURE_96000 0x00000400 <<
880 #define A_I2S_CAPTURE_44100 0x00000800 <<
881 <<
882 #define A_PCM_RATE_MASK 0x0000e000 <<
883 #define A_PCM_48000 0x00000000 <<
884 #define A_PCM_192000 0x00002000 <<
885 #define A_PCM_96000 0x00004000 <<
886 #define A_PCM_44100 0x00008000 <<
887 <<
888 /* I2S0 Sample Rate Tracker Status */ <<
889 #define A_SRT3 0x77 <<
890 <<
891 /* I2S1 Sample Rate Tracker Status */ <<
892 #define A_SRT4 0x78 <<
893 <<
894 /* I2S2 Sample Rate Tracker Status */ <<
895 #define A_SRT5 0x79 <<
896 /* - default to 0x01080000 on my audigy 2 ZS - <<
897 <<
898 /* Tank Table DMA Address */ <<
899 #define A_TTDA 0x7a <<
900 /* Tank Table DMA Data */ <<
901 #define A_TTDD 0x7b <<
902 716
903 #define A_FXRT2 0x7c 717 #define A_FXRT2 0x7c
904 #define A_FXRT_CHANNELE 0x0000003f 718 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
905 #define A_FXRT_CHANNELF 0x00003f00 719 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
906 #define A_FXRT_CHANNELG 0x003f0000 720 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
907 #define A_FXRT_CHANNELH 0x3f000000 721 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
908 722
909 #define A_SENDAMOUNTS 0x7d 723 #define A_SENDAMOUNTS 0x7d
910 #define A_FXSENDAMOUNT_E_MASK 0xFF000000 724 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
911 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000 725 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
912 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00 726 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
913 #define A_FXSENDAMOUNT_H_MASK 0x000000FF 727 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
914 /* 0x7c, 0x7e "high bit is used for filtering" !! 728
915 <<
916 /* The send amounts for this one are the same 729 /* The send amounts for this one are the same as used with the emu10k1 */
917 #define A_FXRT1 0x7e 730 #define A_FXRT1 0x7e
918 #define A_FXRT_CHANNELA 0x0000003f 731 #define A_FXRT_CHANNELA 0x0000003f
919 #define A_FXRT_CHANNELB 0x00003f00 732 #define A_FXRT_CHANNELB 0x00003f00
920 #define A_FXRT_CHANNELC 0x003f0000 733 #define A_FXRT_CHANNELC 0x003f0000
921 #define A_FXRT_CHANNELD 0x3f000000 734 #define A_FXRT_CHANNELD 0x3f000000
922 735
923 /* 0x7f: Not used */ !! 736
924 /* Each FX general purpose register is 32 bits 737 /* Each FX general purpose register is 32 bits in length, all bits are used */
925 #define FXGPREGBASE 0x100 738 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
926 #define A_FXGPREGBASE 0x400 739 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
927 740
928 #define A_TANKMEMCTLREGBASE 0x100 741 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
929 #define A_TANKMEMCTLREG_MASK 0x1f 742 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
930 743
931 /* Tank audio data is logarithmically compress 744 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
932 /* decompressed back to 20 bits on a read. Th 745 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
933 /* locations are for external TRAM. 746 /* locations are for external TRAM. */
934 #define TANKMEMDATAREGBASE 0x200 747 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
935 #define TANKMEMDATAREG_MASK 0x000fffff 748 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
936 749
937 /* Combined address field and memory opcode or 750 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
938 #define TANKMEMADDRREGBASE 0x300 751 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
939 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff 752 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
940 #define TANKMEMADDRREG_CLEAR 0x00800000 753 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
941 #define TANKMEMADDRREG_ALIGN 0x00400000 754 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
942 #define TANKMEMADDRREG_WRITE 0x00200000 755 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
943 #define TANKMEMADDRREG_READ 0x00100000 756 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
944 757
945 #define MICROCODEBASE 0x400 758 #define MICROCODEBASE 0x400 /* Microcode data base address */
946 759
947 /* Each DSP microcode instruction is mapped in 760 /* Each DSP microcode instruction is mapped into 2 doublewords */
948 /* NOTE: When writing, always write the LO dou 761 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
949 #define LOWORD_OPX_MASK 0x000ffc00 762 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
950 #define LOWORD_OPY_MASK 0x000003ff 763 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
951 #define HIWORD_OPCODE_MASK 0x00f00000 764 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
952 #define HIWORD_RESULT_MASK 0x000ffc00 765 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
953 #define HIWORD_OPA_MASK 0x000003ff 766 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
954 767
955 768
956 /* Audigy Soundcard have a different instructi 769 /* Audigy Soundcard have a different instruction format */
957 #define A_MICROCODEBASE 0x600 770 #define A_MICROCODEBASE 0x600
958 #define A_LOWORD_OPY_MASK 0x000007ff 771 #define A_LOWORD_OPY_MASK 0x000007ff
959 #define A_LOWORD_OPX_MASK 0x007ff000 772 #define A_LOWORD_OPX_MASK 0x007ff000
960 #define A_HIWORD_OPCODE_MASK 0x0f000000 773 #define A_HIWORD_OPCODE_MASK 0x0f000000
961 #define A_HIWORD_RESULT_MASK 0x007ff000 774 #define A_HIWORD_RESULT_MASK 0x007ff000
962 #define A_HIWORD_OPA_MASK 0x000007ff 775 #define A_HIWORD_OPA_MASK 0x000007ff
963 776
964 /********************************************* <<
965 /* EMU1010m HANA FPGA registers <<
966 /********************************************* <<
967 #define EMU_HANA_DESTHI 0x00 /* 000 <<
968 #define EMU_HANA_DESTLO 0x01 /* 00x <<
969 #define EMU_HANA_SRCHI 0x02 /* 000 <<
970 #define EMU_HANA_SRCLO 0x03 /* 00x <<
971 #define EMU_HANA_DOCK_PWR 0x04 /* 000 <<
972 #define EMU_HANA_DOCK_PWR_ON 0x01 / <<
973 #define EMU_HANA_WCLOCK 0x05 /* 000 <<
974 /* Mus <<
975 /* One <<
976 #define EMU_HANA_WCLOCK_SRC_MASK 0x07 <<
977 #define EMU_HANA_WCLOCK_INT_48K 0x00 <<
978 #define EMU_HANA_WCLOCK_INT_44_1K 0x01 <<
979 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 <<
980 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 <<
981 #define EMU_HANA_WCLOCK_SYNC_BNCN 0x04 <<
982 #define EMU_HANA_WCLOCK_2ND_HANA 0x05 <<
983 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 <<
984 #define EMU_HANA_WCLOCK_OFF 0x07 / <<
985 #define EMU_HANA_WCLOCK_MULT_MASK 0x18 <<
986 #define EMU_HANA_WCLOCK_1X 0x00 <<
987 #define EMU_HANA_WCLOCK_2X 0x08 <<
988 #define EMU_HANA_WCLOCK_4X 0x10 <<
989 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 <<
990 <<
991 #define EMU_HANA_DEFCLOCK 0x06 /* 000 <<
992 #define EMU_HANA_DEFCLOCK_48K 0x00 <<
993 #define EMU_HANA_DEFCLOCK_44_1K 0x01 <<
994 <<
995 #define EMU_HANA_UNMUTE 0x07 /* 000 <<
996 #define EMU_MUTE 0x00 <<
997 #define EMU_UNMUTE 0x01 <<
998 <<
999 #define EMU_HANA_FPGA_CONFIG 0x08 /* 000 <<
1000 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 <<
1001 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 <<
1002 <<
1003 #define EMU_HANA_IRQ_ENABLE 0x09 /* 00 <<
1004 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01 <<
1005 #define EMU_HANA_IRQ_ADAT 0x02 <<
1006 #define EMU_HANA_IRQ_DOCK 0x04 <<
1007 #define EMU_HANA_IRQ_DOCK_LOST 0x08 <<
1008 <<
1009 #define EMU_HANA_SPDIF_MODE 0x0a /* 00 <<
1010 #define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00 <<
1011 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 <<
1012 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 <<
1013 #define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00 <<
1014 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 <<
1015 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 <<
1016 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10 <<
1017 <<
1018 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00 <<
1019 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00 <<
1020 #define EMU_HANA_OPTICAL_IN_ADAT 0x01 <<
1021 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00 <<
1022 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02 <<
1023 <<
1024 #define EMU_HANA_MIDI_IN 0x0c <<
1025 #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 <<
1026 #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 <<
1027 <<
1028 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 00 <<
1029 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 <<
1030 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 <<
1031 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 <<
1032 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 <<
1033 <<
1034 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0x <<
1035 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 <<
1036 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 <<
1037 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 <<
1038 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 <<
1039 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 <<
1040 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 <<
1041 <<
1042 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0x <<
1043 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 <<
1044 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 <<
1045 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 <<
1046 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 <<
1047 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP <<
1048 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL <<
1049 <<
1050 #define EMU_HANA_ADC_PADS 0x10 /* 00 <<
1051 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14 <<
1052 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14 <<
1053 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14 <<
1054 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14 <<
1055 <<
1056 #define EMU_HANA_DOCK_MISC 0x11 /* 0x <<
1057 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DA <<
1058 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DA <<
1059 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DA <<
1060 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DA <<
1061 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 <<
1062 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 <<
1063 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 <<
1064 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 <<
1065 <<
1066 #define EMU_HANA_MIDI_OUT 0x12 /* 00 <<
1067 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 <<
1068 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio <<
1069 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio <<
1070 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync <<
1071 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = b <<
1072 <<
1073 #define EMU_HANA_DAC_PADS 0x13 /* 00 <<
1074 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14 <<
1075 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14 <<
1076 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14 <<
1077 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14 <<
1078 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14 <<
1079 <<
1080 /* 0x14 - 0x1f Unused R/W registers */ <<
1081 #define EMU_HANA_IRQ_STATUS 0x20 /* 00 <<
1082 #if 0 /* Already defined for reg 0x09 IRQ_EN <<
1083 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01 <<
1084 #define EMU_HANA_IRQ_ADAT 0x02 <<
1085 #define EMU_HANA_IRQ_DOCK 0x04 <<
1086 #define EMU_HANA_IRQ_DOCK_LOST 0x08 <<
1087 #endif <<
1088 <<
1089 #define EMU_HANA_OPTION_CARDS 0x21 /* 00 <<
1090 #define EMU_HANA_OPTION_HAMOA 0x01 /* HA <<
1091 #define EMU_HANA_OPTION_SYNC 0x02 /* Sy <<
1092 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 <<
1093 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 <<
1094 <<
1095 #define EMU_HANA_ID 0x22 /* 10 <<
1096 <<
1097 #define EMU_HANA_MAJOR_REV 0x23 /* 00 <<
1098 #define EMU_HANA_MINOR_REV 0x24 /* 00 <<
1099 <<
1100 #define EMU_DOCK_MAJOR_REV 0x25 /* 00 <<
1101 #define EMU_DOCK_MINOR_REV 0x26 /* 00 <<
1102 <<
1103 #define EMU_DOCK_BOARD_ID 0x27 /* 00 <<
1104 #define EMU_DOCK_BOARD_ID0 0x00 /* ID <<
1105 #define EMU_DOCK_BOARD_ID1 0x03 /* ID <<
1106 <<
1107 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0x <<
1108 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0x <<
1109 <<
1110 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0x <<
1111 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0x <<
1112 <<
1113 #define EMU_HANA_WC_BNC_LO 0x2c /* 0x <<
1114 #define EMU_HANA_WC_BNC_HI 0x2d /* 0x <<
1115 <<
1116 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0x <<
1117 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0x <<
1118 /* 0x30 - 0x3f Unused Read only registers */ <<
1119 <<
1120 /******************************************** <<
1121 /* EMU1010m HANA Destinations <<
1122 /******************************************** <<
1123 /* Hana, original 1010,1212,1820 using Alice2 <<
1124 * Destiniations for SRATEX = 1X rates: 44.1 <<
1125 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alic <<
1126 * 0x01, 0x10-0x1f: 32 Elink channels to Audi <<
1127 * 0x01, 0x00: Dock DAC 1 Left <<
1128 * 0x01, 0x04: Dock DAC 1 Right <<
1129 * 0x01, 0x08: Dock DAC 2 Left <<
1130 * 0x01, 0x0c: Dock DAC 2 Right <<
1131 * 0x01, 0x10: Dock DAC 3 Left <<
1132 * 0x01, 0x12: PHONES Left <<
1133 * 0x01, 0x14: Dock DAC 3 Right <<
1134 * 0x01, 0x16: PHONES Right <<
1135 * 0x01, 0x18: Dock DAC 4 Left <<
1136 * 0x01, 0x1a: S/PDIF Left <<
1137 * 0x01, 0x1c: Dock DAC 4 Right <<
1138 * 0x01, 0x1e: S/PDIF Right <<
1139 * 0x02, 0x00: Hana S/PDIF Left <<
1140 * 0x02, 0x01: Hana S/PDIF Right <<
1141 * 0x03, 0x00: Hanoa DAC Left <<
1142 * 0x03, 0x01: Hanoa DAC Right <<
1143 * 0x04, 0x00-0x07: Hana ADAT <<
1144 * 0x05, 0x00: I2S0 Left to Alice2 <<
1145 * 0x05, 0x01: I2S0 Right to Alice2 <<
1146 * 0x06, 0x00: I2S0 Left to Alice2 <<
1147 * 0x06, 0x01: I2S0 Right to Alice2 <<
1148 * 0x07, 0x00: I2S0 Left to Alice2 <<
1149 * 0x07, 0x01: I2S0 Right to Alice2 <<
1150 * <<
1151 * Hana2 never released, but used Tina <<
1152 * Not needed. <<
1153 * <<
1154 * Hana3, rev2 1010,1212,1616 using Tina <<
1155 * Destinations for SRATEX = 1X rates: 44.1 k <<
1156 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tin <<
1157 * 0x01, 0x10-0x1f: 32 EDI channels to Micro <<
1158 * 0x01, 0x00: Dock DAC 1 Left <<
1159 * 0x01, 0x04: Dock DAC 1 Right <<
1160 * 0x01, 0x08: Dock DAC 2 Left <<
1161 * 0x01, 0x0c: Dock DAC 2 Right <<
1162 * 0x01, 0x10: Dock DAC 3 Left <<
1163 * 0x01, 0x12: Dock S/PDIF Left <<
1164 * 0x01, 0x14: Dock DAC 3 Right <<
1165 * 0x01, 0x16: Dock S/PDIF Right <<
1166 * 0x01, 0x18-0x1f: Dock ADAT 0-7 <<
1167 * 0x02, 0x00: Hana3 S/PDIF Left <<
1168 * 0x02, 0x01: Hana3 S/PDIF Right <<
1169 * 0x03, 0x00: Hanoa DAC Left <<
1170 * 0x03, 0x01: Hanoa DAC Right <<
1171 * 0x04, 0x00-0x07: Hana3 ADAT 0-7 <<
1172 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tin <<
1173 * 0x06-0x07: Not used <<
1174 * <<
1175 * HanaLite, rev1 0404 using Alice2 <<
1176 * Destiniations for SRATEX = 1X rates: 44.1 <<
1177 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alic <<
1178 * 0x01: Not used <<
1179 * 0x02, 0x00: S/PDIF Left <<
1180 * 0x02, 0x01: S/PDIF Right <<
1181 * 0x03, 0x00: DAC Left <<
1182 * 0x03, 0x01: DAC Right <<
1183 * 0x04-0x07: Not used <<
1184 * <<
1185 * HanaLiteLite, rev2 0404 using Alice2 <<
1186 * Destiniations for SRATEX = 1X rates: 44.1 <<
1187 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alic <<
1188 * 0x01: Not used <<
1189 * 0x02, 0x00: S/PDIF Left <<
1190 * 0x02, 0x01: S/PDIF Right <<
1191 * 0x03, 0x00: DAC Left <<
1192 * 0x03, 0x01: DAC Right <<
1193 * 0x04-0x07: Not used <<
1194 * <<
1195 * Mana, Cardbus 1616 using Tina2 <<
1196 * Destinations for SRATEX = 1X rates: 44.1 k <<
1197 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tin <<
1198 * 0x01, 0x10-0x1f: 32 EDI channels to Micro <<
1199 * 0x01, 0x00: Dock DAC 1 Left <<
1200 * 0x01, 0x04: Dock DAC 1 Right <<
1201 * 0x01, 0x08: Dock DAC 2 Left <<
1202 * 0x01, 0x0c: Dock DAC 2 Right <<
1203 * 0x01, 0x10: Dock DAC 3 Left <<
1204 * 0x01, 0x12: Dock S/PDIF Left <<
1205 * 0x01, 0x14: Dock DAC 3 Right <<
1206 * 0x01, 0x16: Dock S/PDIF Right <<
1207 * 0x01, 0x18-0x1f: Dock ADAT 0-7 <<
1208 * 0x02: Not used <<
1209 * 0x03, 0x00: Mana DAC Left <<
1210 * 0x03, 0x01: Mana DAC Right <<
1211 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tin <<
1212 * 0x05-0x07: Not used <<
1213 * <<
1214 * <<
1215 */ <<
1216 /* 32-bit destinations of signal in the Hana <<
1217 * physical outputs of Hana, or outputs going <<
1218 * - 16 x EMU_DST_ALICE2_EMU32_X. <<
1219 */ <<
1220 /* EMU32 = 32-bit serial channel between Alic <<
1221 /* EMU_DST_ALICE2_EMU32_X - data channels fro <<
1222 * Which data is fed into a EMU_DST_ALICE2_EM <<
1223 * setup of mixer control for each destinatio <<
1224 * snd_emu1010_output_enum_ctls[], snd_emu101 <<
1225 */ <<
1226 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 <<
1227 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 <<
1228 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 <<
1229 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 <<
1230 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 <<
1231 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 <<
1232 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 <<
1233 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 <<
1234 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 <<
1235 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 <<
1236 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 <<
1237 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 <<
1238 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 <<
1239 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 <<
1240 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 <<
1241 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 <<
1242 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Au <<
1243 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Au <<
1244 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Au <<
1245 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Au <<
1246 #define EMU_DST_DOCK_DAC1_RIGHT1 0x010 <<
1247 #define EMU_DST_DOCK_DAC1_RIGHT2 0x010 <<
1248 #define EMU_DST_DOCK_DAC1_RIGHT3 0x010 <<
1249 #define EMU_DST_DOCK_DAC1_RIGHT4 0x010 <<
1250 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Au <<
1251 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Au <<
1252 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Au <<
1253 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Au <<
1254 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010 <<
1255 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010 <<
1256 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010 <<
1257 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010 <<
1258 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Au <<
1259 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Au <<
1260 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Au <<
1261 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Au <<
1262 #define EMU_DST_DOCK_PHONES_LEFT1 0x011 <<
1263 #define EMU_DST_DOCK_PHONES_LEFT2 0x011 <<
1264 #define EMU_DST_DOCK_DAC3_RIGHT1 0x011 <<
1265 #define EMU_DST_DOCK_DAC3_RIGHT2 0x011 <<
1266 #define EMU_DST_DOCK_DAC3_RIGHT3 0x011 <<
1267 #define EMU_DST_DOCK_DAC3_RIGHT4 0x011 <<
1268 #define EMU_DST_DOCK_PHONES_RIGHT1 0x011 <<
1269 #define EMU_DST_DOCK_PHONES_RIGHT2 0x011 <<
1270 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Au <<
1271 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Au <<
1272 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Au <<
1273 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Au <<
1274 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011 <<
1275 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011 <<
1276 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011 <<
1277 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011 <<
1278 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011 <<
1279 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011 <<
1280 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011 <<
1281 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011 <<
1282 #define EMU_DST_HANA_SPDIF_LEFT1 0x020 <<
1283 #define EMU_DST_HANA_SPDIF_LEFT2 0x020 <<
1284 #define EMU_DST_HANA_SPDIF_RIGHT1 0x020 <<
1285 #define EMU_DST_HANA_SPDIF_RIGHT2 0x020 <<
1286 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Ha <<
1287 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Ha <<
1288 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Ha <<
1289 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Ha <<
1290 #define EMU_DST_HAMOA_DAC_RIGHT1 0x030 <<
1291 #define EMU_DST_HAMOA_DAC_RIGHT2 0x030 <<
1292 #define EMU_DST_HAMOA_DAC_RIGHT3 0x030 <<
1293 #define EMU_DST_HAMOA_DAC_RIGHT4 0x030 <<
1294 #define EMU_DST_HANA_ADAT 0x0400 /* Ha <<
1295 #define EMU_DST_ALICE_I2S0_LEFT 0x050 <<
1296 #define EMU_DST_ALICE_I2S0_RIGHT 0x050 <<
1297 #define EMU_DST_ALICE_I2S1_LEFT 0x060 <<
1298 #define EMU_DST_ALICE_I2S1_RIGHT 0x060 <<
1299 #define EMU_DST_ALICE_I2S2_LEFT 0x070 <<
1300 #define EMU_DST_ALICE_I2S2_RIGHT 0x070 <<
1301 <<
1302 /* Additional destinations for 1616(M)/Microd <<
1303 /* Microdock S/PDIF OUT Left, 1st or 48kHz on <<
1304 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x011 <<
1305 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ <<
1306 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x011 <<
1307 /* Microdock S/PDIF OUT Right, 1st or 48kHz o <<
1308 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x011 <<
1309 /* Microdock S/PDIF OUT Right, 2nd or 96kHz <<
1310 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x011 <<
1311 /* Microdock S/PDIF ADAT 8 channel out +8 to <<
1312 #define EMU_DST_MDOCK_ADAT 0x011 <<
1313 <<
1314 /* Headphone jack on 1010 cardbus? 44.1/48kHz <<
1315 #define EMU_DST_MANA_DAC_LEFT 0x030 <<
1316 /* Headphone jack on 1010 cardbus? 44.1/48kHz <<
1317 #define EMU_DST_MANA_DAC_RIGHT 0x030 <<
1318 <<
1319 /******************************************** <<
1320 /* EMU1010m HANA Sources <<
1321 /******************************************** <<
1322 /* Hana, original 1010,1212,1820 using Alice2 <<
1323 * Sources SRATEX = 1X rates: 44.1 kHz or 48 <<
1324 * 0x00,0x00-0x1f: Silence <<
1325 * 0x01, 0x10-0x1f: 32 Elink channels from Au <<
1326 * 0x01, 0x00: Dock Mic A <<
1327 * 0x01, 0x04: Dock Mic B <<
1328 * 0x01, 0x08: Dock ADC 1 Left <<
1329 * 0x01, 0x0c: Dock ADC 1 Right <<
1330 * 0x01, 0x10: Dock ADC 2 Left <<
1331 * 0x01, 0x14: Dock ADC 2 Right <<
1332 * 0x01, 0x18: Dock ADC 3 Left <<
1333 * 0x01, 0x1c: Dock ADC 3 Right <<
1334 * 0x02, 0x00: Hana ADC Left <<
1335 * 0x02, 0x01: Hana ADC Right <<
1336 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu <<
1337 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu <<
1338 * 0x04, 0x00-0x07: Hana ADAT <<
1339 * 0x05, 0x00: Hana S/PDIF Left <<
1340 * 0x05, 0x01: Hana S/PDIF Right <<
1341 * 0x06-0x07: Not used <<
1342 * <<
1343 * Hana2 never released, but used Tina <<
1344 * Not needed. <<
1345 * <<
1346 * Hana3, rev2 1010,1212,1616 using Tina <<
1347 * Sources SRATEX = 1X rates: 44.1 kHz or 48 <<
1348 * 0x00,0x00-0x1f: Silence <<
1349 * 0x01, 0x10-0x1f: 32 Elink channels from Au <<
1350 * 0x01, 0x00: Dock Mic A <<
1351 * 0x01, 0x04: Dock Mic B <<
1352 * 0x01, 0x08: Dock ADC 1 Left <<
1353 * 0x01, 0x0c: Dock ADC 1 Right <<
1354 * 0x01, 0x10: Dock ADC 2 Left <<
1355 * 0x01, 0x12: Dock S/PDIF Left <<
1356 * 0x01, 0x14: Dock ADC 2 Right <<
1357 * 0x01, 0x16: Dock S/PDIF Right <<
1358 * 0x01, 0x18-0x1f: Dock ADAT 0-7 <<
1359 * 0x01, 0x18: Dock ADC 3 Left <<
1360 * 0x01, 0x1c: Dock ADC 3 Right <<
1361 * 0x02, 0x00: Hanoa ADC Left <<
1362 * 0x02, 0x01: Hanoa ADC Right <<
1363 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32 <<
1364 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32 <<
1365 * 0x04, 0x00-0x07: Hana3 ADAT <<
1366 * 0x05, 0x00: Hana3 S/PDIF Left <<
1367 * 0x05, 0x01: Hana3 S/PDIF Right <<
1368 * 0x06-0x07: Not used <<
1369 * <<
1370 * HanaLite, rev1 0404 using Alice2 <<
1371 * Sources SRATEX = 1X rates: 44.1 kHz or 48 <<
1372 * 0x00,0x00-0x1f: Silence <<
1373 * 0x01: Not used <<
1374 * 0x02, 0x00: ADC Left <<
1375 * 0x02, 0x01: ADC Right <<
1376 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu <<
1377 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu <<
1378 * 0x04: Not used <<
1379 * 0x05, 0x00: S/PDIF Left <<
1380 * 0x05, 0x01: S/PDIF Right <<
1381 * 0x06-0x07: Not used <<
1382 * <<
1383 * HanaLiteLite, rev2 0404 using Alice2 <<
1384 * Sources SRATEX = 1X rates: 44.1 kHz or 48 <<
1385 * 0x00,0x00-0x1f: Silence <<
1386 * 0x01: Not used <<
1387 * 0x02, 0x00: ADC Left <<
1388 * 0x02, 0x01: ADC Right <<
1389 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu <<
1390 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu <<
1391 * 0x04: Not used <<
1392 * 0x05, 0x00: S/PDIF Left <<
1393 * 0x05, 0x01: S/PDIF Right <<
1394 * 0x06-0x07: Not used <<
1395 * <<
1396 * Mana, Cardbus 1616 using Tina2 <<
1397 * Sources SRATEX = 1X rates: 44.1 kHz or 48 <<
1398 * 0x00,0x00-0x1f: Silence <<
1399 * 0x01, 0x10-0x1f: 32 Elink channels from Au <<
1400 * 0x01, 0x00: Dock Mic A <<
1401 * 0x01, 0x04: Dock Mic B <<
1402 * 0x01, 0x08: Dock ADC 1 Left <<
1403 * 0x01, 0x0c: Dock ADC 1 Right <<
1404 * 0x01, 0x10: Dock ADC 2 Left <<
1405 * 0x01, 0x12: Dock S/PDIF Left <<
1406 * 0x01, 0x14: Dock ADC 2 Right <<
1407 * 0x01, 0x16: Dock S/PDIF Right <<
1408 * 0x01, 0x18-0x1f: Dock ADAT 0-7 <<
1409 * 0x01, 0x18: Dock ADC 3 Left <<
1410 * 0x01, 0x1c: Dock ADC 3 Right <<
1411 * 0x02: Not used <<
1412 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32 <<
1413 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32 <<
1414 * 0x04-0x07: Not used <<
1415 * <<
1416 */ <<
1417 <<
1418 /* 32-bit sources of signal in the Hana FPGA. <<
1419 * destinations using mixer control for each <<
1420 * Sources are either physical inputs of FPGA <<
1421 * or outputs from Alice (audigy) - 16 x EMU_ <<
1422 * 16 x EMU_SRC_ALICE_EMU32B <<
1423 */ <<
1424 #define EMU_SRC_SILENCE 0x0000 /* Si <<
1425 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Au <<
1426 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Au <<
1427 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Au <<
1428 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Au <<
1429 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Au <<
1430 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Au <<
1431 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Au <<
1432 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Au <<
1433 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Au <<
1434 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Au <<
1435 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Au <<
1436 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Au <<
1437 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010 <<
1438 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010 <<
1439 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010 <<
1440 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010 <<
1441 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Au <<
1442 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Au <<
1443 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Au <<
1444 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Au <<
1445 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x011 <<
1446 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x011 <<
1447 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x011 <<
1448 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x011 <<
1449 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Au <<
1450 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Au <<
1451 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Au <<
1452 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Au <<
1453 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011 <<
1454 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011 <<
1455 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011 <<
1456 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011 <<
1457 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Ha <<
1458 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Ha <<
1459 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Ha <<
1460 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Ha <<
1461 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x020 <<
1462 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x020 <<
1463 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x020 <<
1464 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x020 <<
1465 #define EMU_SRC_ALICE_EMU32A 0x030 <<
1466 #define EMU_SRC_ALICE_EMU32B 0x031 <<
1467 #define EMU_SRC_HANA_ADAT 0x0400 /* Ha <<
1468 #define EMU_SRC_HANA_SPDIF_LEFT1 0x050 <<
1469 #define EMU_SRC_HANA_SPDIF_LEFT2 0x050 <<
1470 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x050 <<
1471 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x050 <<
1472 <<
1473 /* Additional inputs for 1616(M)/Microdock */ <<
1474 /* Microdock S/PDIF Left, 1st or 48kHz only * <<
1475 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x011 <<
1476 /* Microdock S/PDIF Left, 2nd or 96kHz */ <<
1477 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x011 <<
1478 /* Microdock S/PDIF Right, 1st or 48kHz only <<
1479 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x011 <<
1480 /* Microdock S/PDIF Right, 2nd or 96kHz */ <<
1481 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x011 <<
1482 /* Microdock ADAT 8 channel in +8 to +f */ <<
1483 #define EMU_SRC_MDOCK_ADAT 0x011 <<
1484 <<
1485 /* 0x600 and 0x700 no used */ <<
1486 777
1487 /* ------------------- STRUCTURES ----------- 778 /* ------------------- STRUCTURES -------------------- */
1488 779
1489 enum { !! 780 typedef struct _snd_emu10k1 emu10k1_t;
1490 EMU10K1_EFX, !! 781 typedef struct _snd_emu10k1_voice emu10k1_voice_t;
>> 782 typedef struct _snd_emu10k1_pcm emu10k1_pcm_t;
>> 783
>> 784 typedef enum {
1491 EMU10K1_PCM, 785 EMU10K1_PCM,
1492 EMU10K1_SYNTH, 786 EMU10K1_SYNTH,
1493 EMU10K1_MIDI 787 EMU10K1_MIDI
1494 }; !! 788 } emu10k1_voice_type_t;
1495 <<
1496 struct snd_emu10k1; <<
1497 789
1498 struct snd_emu10k1_voice { !! 790 struct _snd_emu10k1_voice {
1499 struct snd_emu10k1 *emu; !! 791 emu10k1_t *emu;
1500 int number; 792 int number;
1501 unsigned int use: 1, !! 793 int use: 1,
1502 pcm: 1, 794 pcm: 1,
1503 efx: 1, <<
1504 synth: 1, 795 synth: 1,
1505 midi: 1; 796 midi: 1;
1506 void (*interrupt)(struct snd_emu10k1 !! 797 void (*interrupt)(emu10k1_t *emu, emu10k1_voice_t *pvoice);
1507 798
1508 struct snd_emu10k1_pcm *epcm; !! 799 emu10k1_pcm_t *epcm;
1509 }; 800 };
1510 801
1511 enum { !! 802 typedef enum {
1512 PLAYBACK_EMUVOICE, 803 PLAYBACK_EMUVOICE,
1513 PLAYBACK_EFX, <<
1514 CAPTURE_AC97ADC, 804 CAPTURE_AC97ADC,
1515 CAPTURE_AC97MIC, 805 CAPTURE_AC97MIC,
1516 CAPTURE_EFX 806 CAPTURE_EFX
1517 }; !! 807 } snd_emu10k1_pcm_type_t;
1518 808
1519 struct snd_emu10k1_pcm { !! 809 struct _snd_emu10k1_pcm {
1520 struct snd_emu10k1 *emu; !! 810 emu10k1_t *emu;
1521 int type; !! 811 snd_emu10k1_pcm_type_t type;
1522 struct snd_pcm_substream *substream; !! 812 snd_pcm_substream_t *substream;
1523 struct snd_emu10k1_voice *voices[NUM_ !! 813 emu10k1_voice_t *voices[2];
1524 struct snd_emu10k1_voice *extra; !! 814 emu10k1_voice_t *extra;
1525 unsigned short running; 815 unsigned short running;
1526 unsigned short first_ptr; 816 unsigned short first_ptr;
1527 struct snd_util_memblk *memblk; !! 817 snd_util_memblk_t *memblk;
1528 unsigned int start_addr; 818 unsigned int start_addr;
1529 unsigned int ccca_start_addr; 819 unsigned int ccca_start_addr;
1530 unsigned int capture_ipr; /* in 820 unsigned int capture_ipr; /* interrupt acknowledge mask */
1531 unsigned int capture_inte; /* in 821 unsigned int capture_inte; /* interrupt enable mask */
1532 unsigned int capture_ba_reg; /* bu 822 unsigned int capture_ba_reg; /* buffer address register */
1533 unsigned int capture_bs_reg; /* bu 823 unsigned int capture_bs_reg; /* buffer size register */
1534 unsigned int capture_idx_reg; /* bu 824 unsigned int capture_idx_reg; /* buffer index register */
1535 unsigned int capture_cr_val; /* co 825 unsigned int capture_cr_val; /* control value */
1536 unsigned int capture_cr_val2; /* co 826 unsigned int capture_cr_val2; /* control value2 (for audigy) */
1537 unsigned int capture_bs_val; /* bu 827 unsigned int capture_bs_val; /* buffer size value */
1538 unsigned int capture_bufsize; /* bu 828 unsigned int capture_bufsize; /* buffer size in bytes */
1539 }; 829 };
1540 830
1541 struct snd_emu10k1_pcm_mixer { !! 831 typedef struct {
1542 /* mono, left, right x 8 sends (4 on 832 /* mono, left, right x 8 sends (4 on emu10k1) */
1543 unsigned char send_routing[3][8]; 833 unsigned char send_routing[3][8];
1544 unsigned char send_volume[3][8]; 834 unsigned char send_volume[3][8];
1545 unsigned short attn[3]; 835 unsigned short attn[3];
1546 struct snd_emu10k1_pcm *epcm; !! 836 emu10k1_pcm_t *epcm;
1547 }; !! 837 } emu10k1_pcm_mixer_t;
1548 838
1549 #define snd_emu10k1_compose_send_routing(rout 839 #define snd_emu10k1_compose_send_routing(route) \
1550 ((route[0] | (route[1] << 4) | (route[2] << 8 840 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1551 841
1552 #define snd_emu10k1_compose_audigy_fxrt1(rout 842 #define snd_emu10k1_compose_audigy_fxrt1(route) \
1553 ((unsigned int)route[0] | ((unsigned int)rout 843 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1554 844
1555 #define snd_emu10k1_compose_audigy_fxrt2(rout 845 #define snd_emu10k1_compose_audigy_fxrt2(route) \
1556 ((unsigned int)route[4] | ((unsigned int)rout 846 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1557 847
1558 struct snd_emu10k1_memblk { !! 848 typedef struct snd_emu10k1_memblk {
1559 struct snd_util_memblk mem; !! 849 snd_util_memblk_t mem;
1560 /* private part */ 850 /* private part */
1561 int first_page, last_page, pages, map 851 int first_page, last_page, pages, mapped_page;
1562 unsigned int map_locked; 852 unsigned int map_locked;
1563 struct list_head mapped_link; 853 struct list_head mapped_link;
1564 struct list_head mapped_order_link; 854 struct list_head mapped_order_link;
1565 }; !! 855 } emu10k1_memblk_t;
1566 856
1567 #define snd_emu10k1_memblk_offset(blk) (((bl 857 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1568 858
1569 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 859 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1570 860
1571 struct snd_emu10k1_fx8010_ctl { !! 861 typedef struct {
1572 struct list_head list; /* li 862 struct list_head list; /* list link container */
1573 unsigned int vcount; 863 unsigned int vcount;
1574 unsigned int count; /* co 864 unsigned int count; /* count of GPR (1..16) */
1575 unsigned short gpr[32]; /* GP 865 unsigned short gpr[32]; /* GPR number(s) */
1576 unsigned int value[32]; 866 unsigned int value[32];
1577 unsigned int min; /* mi 867 unsigned int min; /* minimum range */
1578 unsigned int max; /* ma 868 unsigned int max; /* maximum range */
1579 unsigned int translation; /* tr 869 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1580 struct snd_kcontrol *kcontrol; !! 870 snd_kcontrol_t *kcontrol;
1581 }; !! 871 } snd_emu10k1_fx8010_ctl_t;
1582 872
1583 typedef void (snd_fx8010_irq_handler_t)(struc !! 873 typedef void (snd_fx8010_irq_handler_t)(emu10k1_t *emu, void *private_data);
1584 874
1585 struct snd_emu10k1_fx8010_irq { !! 875 typedef struct _snd_emu10k1_fx8010_irq {
1586 struct snd_emu10k1_fx8010_irq *next; !! 876 struct _snd_emu10k1_fx8010_irq *next;
1587 snd_fx8010_irq_handler_t *handler; 877 snd_fx8010_irq_handler_t *handler;
1588 unsigned short gpr_running; 878 unsigned short gpr_running;
1589 void *private_data; 879 void *private_data;
1590 }; !! 880 } snd_emu10k1_fx8010_irq_t;
1591 881
1592 struct snd_emu10k1_fx8010_pcm { !! 882 typedef struct {
1593 unsigned int valid: 1, 883 unsigned int valid: 1,
1594 opened: 1, 884 opened: 1,
1595 active: 1; 885 active: 1;
1596 unsigned int channels; /* 16 886 unsigned int channels; /* 16-bit channels count */
1597 unsigned int tram_start; /* in 887 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1598 unsigned int buffer_size; /* co 888 unsigned int buffer_size; /* count of buffered samples */
1599 unsigned short gpr_size; 889 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1600 unsigned short gpr_ptr; /* GP 890 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1601 unsigned short gpr_count; /* GP 891 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1602 unsigned short gpr_tmpcount; /* GP 892 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1603 unsigned short gpr_trigger; /* GP 893 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1604 unsigned short gpr_running; /* GP 894 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1605 unsigned char etram[32]; /* ex 895 unsigned char etram[32]; /* external TRAM address & data */
1606 struct snd_pcm_indirect pcm_rec; !! 896 snd_pcm_indirect_t pcm_rec;
1607 unsigned int tram_pos; 897 unsigned int tram_pos;
1608 unsigned int tram_shift; 898 unsigned int tram_shift;
1609 struct snd_emu10k1_fx8010_irq *irq; !! 899 snd_emu10k1_fx8010_irq_t *irq;
1610 }; !! 900 } snd_emu10k1_fx8010_pcm_t;
1611 901
1612 struct snd_emu10k1_fx8010 { !! 902 typedef struct {
1613 unsigned short fxbus_mask; /* us 903 unsigned short fxbus_mask; /* used FX buses (bitmask) */
1614 unsigned short extin_mask; /* us 904 unsigned short extin_mask; /* used external inputs (bitmask) */
1615 unsigned short extout_mask; /* us 905 unsigned short extout_mask; /* used external outputs (bitmask) */
1616 unsigned short pad1; 906 unsigned short pad1;
1617 unsigned int itram_size; /* in 907 unsigned int itram_size; /* internal TRAM size in samples */
1618 struct snd_dma_buffer etram_pages; /* 908 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1619 unsigned int dbg; /* FX 909 unsigned int dbg; /* FX debugger register */
1620 unsigned char name[128]; 910 unsigned char name[128];
1621 int gpr_size; /* si 911 int gpr_size; /* size of allocated GPR controls */
1622 int gpr_count; /* co 912 int gpr_count; /* count of used kcontrols */
1623 struct list_head gpr_ctl; /* GP 913 struct list_head gpr_ctl; /* GPR controls */
1624 struct mutex lock; !! 914 struct semaphore lock;
1625 struct snd_emu10k1_fx8010_pcm pcm[8]; !! 915 snd_emu10k1_fx8010_pcm_t pcm[8];
1626 spinlock_t irq_lock; 916 spinlock_t irq_lock;
1627 struct snd_emu10k1_fx8010_irq *irq_ha !! 917 snd_emu10k1_fx8010_irq_t *irq_handlers;
1628 }; !! 918 } snd_emu10k1_fx8010_t;
>> 919
>> 920 #define emu10k1_gpr_ctl(n) list_entry(n, snd_emu10k1_fx8010_ctl_t, list)
1629 921
1630 struct snd_emu10k1_midi { !! 922 typedef struct {
1631 struct snd_emu10k1 *emu; !! 923 struct _snd_emu10k1 *emu;
1632 struct snd_rawmidi *rmidi; !! 924 snd_rawmidi_t *rmidi;
1633 struct snd_rawmidi_substream *substre !! 925 snd_rawmidi_substream_t *substream_input;
1634 struct snd_rawmidi_substream *substre !! 926 snd_rawmidi_substream_t *substream_output;
1635 unsigned int midi_mode; 927 unsigned int midi_mode;
1636 spinlock_t input_lock; 928 spinlock_t input_lock;
1637 spinlock_t output_lock; 929 spinlock_t output_lock;
1638 spinlock_t open_lock; 930 spinlock_t open_lock;
1639 int tx_enable, rx_enable; 931 int tx_enable, rx_enable;
1640 int port; 932 int port;
1641 int ipr_tx, ipr_rx; 933 int ipr_tx, ipr_rx;
1642 void (*interrupt)(struct snd_emu10k1 !! 934 void (*interrupt)(emu10k1_t *emu, unsigned int status);
1643 }; !! 935 } emu10k1_midi_t;
1644 <<
1645 enum { <<
1646 EMU_MODEL_SB, <<
1647 EMU_MODEL_EMU1010, <<
1648 EMU_MODEL_EMU1010B, <<
1649 EMU_MODEL_EMU1616, <<
1650 EMU_MODEL_EMU0404, <<
1651 }; <<
1652 <<
1653 struct snd_emu_chip_details { <<
1654 u32 vendor; <<
1655 u32 device; <<
1656 u32 subsystem; <<
1657 unsigned char revision; <<
1658 unsigned char emu10k1_chip; /* Origin <<
1659 unsigned char emu10k2_chip; /* Audigy <<
1660 unsigned char ca0102_chip; /* Audigy <<
1661 unsigned char ca0108_chip; /* Audigy <<
1662 unsigned char ca_cardbus_chip; /* Aud <<
1663 unsigned char ca0151_chip; /* P16V * <<
1664 unsigned char spk71; /* Has 7. <<
1665 unsigned char sblive51; /* SBLive <<
1666 unsigned char spdif_bug; /* Has Sp <<
1667 unsigned char ac97_chip; /* Has an <<
1668 unsigned char ecard; /* APS EE <<
1669 unsigned char emu_model; /* EMU m <<
1670 unsigned char spi_dac; /* SPI in <<
1671 unsigned char i2c_adc; /* I2C in <<
1672 unsigned char adc_1361t; /* Use Ph <<
1673 const char *driver; <<
1674 const char *name; <<
1675 const char *id; /* for backwa <<
1676 }; <<
1677 936
1678 struct snd_emu1010 { !! 937 struct _snd_emu10k1 {
1679 unsigned int output_source[64]; <<
1680 unsigned int input_source[64]; <<
1681 unsigned int adc_pads; /* bit mask */ <<
1682 unsigned int dac_pads; /* bit mask */ <<
1683 unsigned int internal_clock; /* 44100 <<
1684 unsigned int optical_in; /* 0:SPDIF, <<
1685 unsigned int optical_out; /* 0:SPDIF, <<
1686 struct task_struct *firmware_thread; <<
1687 }; <<
1688 <<
1689 struct snd_emu10k1 { <<
1690 int irq; 938 int irq;
1691 939
1692 unsigned long port; 940 unsigned long port; /* I/O port number */
1693 unsigned int tos_link: 1, !! 941 int APS: 1, /* APS flag */
1694 rear_ac97: 1, !! 942 no_ac97: 1, /* no AC'97 */
1695 enable_ir: 1; !! 943 tos_link: 1, /* tos link detected */
1696 unsigned int support_tlv :1; !! 944 rear_ac97: 1, /* rear channels are on AC'97 */
1697 /* Contains profile of card capabilit !! 945 spk71:1; /* 7.1 configuration (Audigy 2 ZS) */
1698 const struct snd_emu_chip_details *ca <<
1699 unsigned int audigy; 946 unsigned int audigy; /* is Audigy? */
1700 unsigned int revision; 947 unsigned int revision; /* chip revision */
1701 unsigned int serial; 948 unsigned int serial; /* serial number */
1702 unsigned short model; 949 unsigned short model; /* subsystem id */
1703 unsigned int card_type; 950 unsigned int card_type; /* EMU10K1_CARD_* */
1704 unsigned int ecard_ctrl; 951 unsigned int ecard_ctrl; /* ecard control bits */
1705 unsigned long dma_mask; 952 unsigned long dma_mask; /* PCI DMA mask */
1706 int max_cache_pages; 953 int max_cache_pages; /* max memory size / PAGE_SIZE */
1707 struct snd_dma_buffer silent_page; 954 struct snd_dma_buffer silent_page; /* silent page */
1708 struct snd_dma_buffer ptb_pages; 955 struct snd_dma_buffer ptb_pages; /* page table pages */
1709 struct snd_dma_device p16v_dma_dev; !! 956 snd_util_memhdr_t *memhdr; /* page allocation list */
1710 struct snd_dma_buffer p16v_buffer; !! 957 emu10k1_memblk_t *reserved_page; /* reserved page */
1711 <<
1712 struct snd_util_memhdr *memhdr; <<
1713 struct snd_emu10k1_memblk *reserved_p <<
1714 958
1715 struct list_head mapped_link_head; 959 struct list_head mapped_link_head;
1716 struct list_head mapped_order_link_he 960 struct list_head mapped_order_link_head;
1717 void **page_ptr_table; 961 void **page_ptr_table;
1718 unsigned long *page_addr_table; 962 unsigned long *page_addr_table;
1719 spinlock_t memblk_lock; 963 spinlock_t memblk_lock;
1720 964
1721 unsigned int spdif_bits[3]; 965 unsigned int spdif_bits[3]; /* s/pdif out setup */
1722 unsigned int i2c_capture_source; <<
1723 u8 i2c_capture_volume[4][2]; <<
1724 966
1725 struct snd_emu10k1_fx8010 fx8010; !! 967 snd_emu10k1_fx8010_t fx8010; /* FX8010 info */
1726 int gpr_base; 968 int gpr_base;
1727 969
1728 struct snd_ac97 *ac97; !! 970 ac97_t *ac97;
1729 971
1730 struct pci_dev *pci; 972 struct pci_dev *pci;
1731 struct snd_card *card; !! 973 snd_card_t *card;
1732 struct snd_pcm *pcm; !! 974 snd_pcm_t *pcm;
1733 struct snd_pcm *pcm_mic; !! 975 snd_pcm_t *pcm_mic;
1734 struct snd_pcm *pcm_efx; !! 976 snd_pcm_t *pcm_efx;
1735 struct snd_pcm *pcm_multi; <<
1736 struct snd_pcm *pcm_p16v; <<
1737 977
1738 spinlock_t synth_lock; 978 spinlock_t synth_lock;
1739 void *synth; 979 void *synth;
1740 int (*get_synth_voice)(struct snd_emu !! 980 int (*get_synth_voice)(emu10k1_t *emu);
1741 981
1742 spinlock_t reg_lock; 982 spinlock_t reg_lock;
1743 spinlock_t emu_lock; 983 spinlock_t emu_lock;
1744 spinlock_t voice_lock; 984 spinlock_t voice_lock;
1745 spinlock_t spi_lock; /* serialises ac !! 985 struct semaphore ptb_lock;
1746 spinlock_t i2c_lock; /* serialises ac <<
1747 986
1748 struct snd_emu10k1_voice voices[NUM_G !! 987 emu10k1_voice_t voices[64];
1749 struct snd_emu10k1_voice p16v_voices[ !! 988 emu10k1_pcm_mixer_t pcm_mixer[32];
1750 struct snd_emu10k1_voice p16v_capture !! 989 snd_kcontrol_t *ctl_send_routing;
1751 int p16v_device_offset; !! 990 snd_kcontrol_t *ctl_send_volume;
1752 u32 p16v_capture_source; !! 991 snd_kcontrol_t *ctl_attn;
1753 u32 p16v_capture_channel; !! 992
1754 struct snd_emu1010 emu1010; !! 993 void (*hwvol_interrupt)(emu10k1_t *emu, unsigned int status);
1755 struct snd_emu10k1_pcm_mixer pcm_mixe !! 994 void (*capture_interrupt)(emu10k1_t *emu, unsigned int status);
1756 struct snd_emu10k1_pcm_mixer efx_pcm_ !! 995 void (*capture_mic_interrupt)(emu10k1_t *emu, unsigned int status);
1757 struct snd_kcontrol *ctl_send_routing !! 996 void (*capture_efx_interrupt)(emu10k1_t *emu, unsigned int status);
1758 struct snd_kcontrol *ctl_send_volume; !! 997 void (*timer_interrupt)(emu10k1_t *emu);
1759 struct snd_kcontrol *ctl_attn; !! 998 void (*spdif_interrupt)(emu10k1_t *emu, unsigned int status);
1760 struct snd_kcontrol *ctl_efx_send_rou !! 999 void (*dsp_interrupt)(emu10k1_t *emu);
1761 struct snd_kcontrol *ctl_efx_send_vol !! 1000
1762 struct snd_kcontrol *ctl_efx_attn; !! 1001 snd_pcm_substream_t *pcm_capture_substream;
1763 !! 1002 snd_pcm_substream_t *pcm_capture_mic_substream;
1764 void (*hwvol_interrupt)(struct snd_em !! 1003 snd_pcm_substream_t *pcm_capture_efx_substream;
1765 void (*capture_interrupt)(struct snd_ <<
1766 void (*capture_mic_interrupt)(struct <<
1767 void (*capture_efx_interrupt)(struct <<
1768 void (*spdif_interrupt)(struct snd_em <<
1769 void (*dsp_interrupt)(struct snd_emu1 <<
1770 <<
1771 struct snd_pcm_substream *pcm_capture <<
1772 struct snd_pcm_substream *pcm_capture <<
1773 struct snd_pcm_substream *pcm_capture <<
1774 struct snd_pcm_substream *pcm_playbac <<
1775 1004
1776 struct snd_timer *timer; !! 1005 snd_timer_t *timer;
1777 1006
1778 struct snd_emu10k1_midi midi; !! 1007 emu10k1_midi_t midi;
1779 struct snd_emu10k1_midi midi2; /* for !! 1008 emu10k1_midi_t midi2; /* for audigy */
1780 1009
1781 unsigned int efx_voices_mask[2]; 1010 unsigned int efx_voices_mask[2];
1782 unsigned int next_free_voice; <<
1783 <<
1784 #ifdef CONFIG_PM <<
1785 unsigned int *saved_ptr; <<
1786 unsigned int *saved_gpr; <<
1787 unsigned int *tram_val_saved; <<
1788 unsigned int *tram_addr_saved; <<
1789 unsigned int *saved_icode; <<
1790 unsigned int *p16v_saved; <<
1791 unsigned int saved_a_iocfg, saved_hcf <<
1792 #endif <<
1793 <<
1794 }; 1011 };
1795 1012
1796 int snd_emu10k1_create(struct snd_card *card, !! 1013 int snd_emu10k1_create(snd_card_t * card,
1797 struct pci_dev *pci, 1014 struct pci_dev *pci,
1798 unsigned short extin_m 1015 unsigned short extin_mask,
1799 unsigned short extout_ 1016 unsigned short extout_mask,
1800 long max_cache_bytes, 1017 long max_cache_bytes,
1801 int enable_ir, 1018 int enable_ir,
1802 uint subsystem, !! 1019 emu10k1_t ** remu);
1803 struct snd_emu10k1 ** <<
1804 1020
1805 int snd_emu10k1_pcm(struct snd_emu10k1 * emu, !! 1021 int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1806 int snd_emu10k1_pcm_mic(struct snd_emu10k1 * !! 1022 int snd_emu10k1_pcm_mic(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1807 int snd_emu10k1_pcm_efx(struct snd_emu10k1 * !! 1023 int snd_emu10k1_pcm_efx(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1808 int snd_p16v_pcm(struct snd_emu10k1 * emu, in !! 1024 int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1809 int snd_p16v_free(struct snd_emu10k1 * emu); !! 1025 int snd_emu10k1_mixer(emu10k1_t * emu);
1810 int snd_p16v_mixer(struct snd_emu10k1 * emu); !! 1026 int snd_emu10k1_timer(emu10k1_t * emu, int device);
1811 int snd_emu10k1_pcm_multi(struct snd_emu10k1 !! 1027 int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep);
1812 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 !! 1028
1813 int snd_emu10k1_mixer(struct snd_emu10k1 * em !! 1029 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1814 int snd_emu10k1_timer(struct snd_emu10k1 * em !! 1030
1815 int snd_emu10k1_fx8010_new(struct snd_emu10k1 !! 1031 /* initialization */
1816 !! 1032 void snd_emu10k1_voice_init(emu10k1_t * emu, int voice);
1817 irqreturn_t snd_emu10k1_interrupt(int irq, vo !! 1033 int snd_emu10k1_init_efx(emu10k1_t *emu);
1818 !! 1034 void snd_emu10k1_free_efx(emu10k1_t *emu);
1819 void snd_emu10k1_voice_init(struct snd_emu10k !! 1035 int snd_emu10k1_fx8010_tram_setup(emu10k1_t *emu, u32 size);
1820 int snd_emu10k1_init_efx(struct snd_emu10k1 * <<
1821 void snd_emu10k1_free_efx(struct snd_emu10k1 <<
1822 int snd_emu10k1_fx8010_tram_setup(struct snd_ <<
1823 int snd_emu10k1_done(struct snd_emu10k1 * emu <<
1824 1036
1825 /* I/O functions */ 1037 /* I/O functions */
1826 unsigned int snd_emu10k1_ptr_read(struct snd_ !! 1038 unsigned int snd_emu10k1_ptr_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1827 void snd_emu10k1_ptr_write(struct snd_emu10k1 !! 1039 void snd_emu10k1_ptr_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1828 unsigned int snd_emu10k1_ptr20_read(struct sn !! 1040 unsigned int snd_emu10k1_efx_read(emu10k1_t *emu, unsigned int pc);
1829 void snd_emu10k1_ptr20_write(struct snd_emu10 !! 1041 void snd_emu10k1_intr_enable(emu10k1_t *emu, unsigned int intrenb);
1830 int snd_emu10k1_spi_write(struct snd_emu10k1 !! 1042 void snd_emu10k1_intr_disable(emu10k1_t *emu, unsigned int intrenb);
1831 int snd_emu10k1_i2c_write(struct snd_emu10k1 !! 1043 void snd_emu10k1_voice_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1832 int snd_emu1010_fpga_write(struct snd_emu10k1 !! 1044 void snd_emu10k1_voice_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1833 int snd_emu1010_fpga_read(struct snd_emu10k1 !! 1045 void snd_emu10k1_voice_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1834 int snd_emu1010_fpga_link_dst_src_write(struc !! 1046 void snd_emu10k1_voice_set_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1835 unsigned int snd_emu10k1_efx_read(struct snd_ !! 1047 void snd_emu10k1_voice_clear_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1836 void snd_emu10k1_intr_enable(struct snd_emu10 !! 1048 void snd_emu10k1_wait(emu10k1_t *emu, unsigned int wait);
1837 void snd_emu10k1_intr_disable(struct snd_emu1 !! 1049 static inline unsigned int snd_emu10k1_wc(emu10k1_t *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1838 void snd_emu10k1_voice_intr_enable(struct snd !! 1050 unsigned short snd_emu10k1_ac97_read(ac97_t *ac97, unsigned short reg);
1839 void snd_emu10k1_voice_intr_disable(struct sn !! 1051 void snd_emu10k1_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short data);
1840 void snd_emu10k1_voice_intr_ack(struct snd_em <<
1841 void snd_emu10k1_voice_half_loop_intr_enable( <<
1842 void snd_emu10k1_voice_half_loop_intr_disable <<
1843 void snd_emu10k1_voice_half_loop_intr_ack(str <<
1844 void snd_emu10k1_voice_set_loop_stop(struct s <<
1845 void snd_emu10k1_voice_clear_loop_stop(struct <<
1846 void snd_emu10k1_wait(struct snd_emu10k1 *emu <<
1847 static inline unsigned int snd_emu10k1_wc(str <<
1848 unsigned short snd_emu10k1_ac97_read(struct s <<
1849 void snd_emu10k1_ac97_write(struct snd_ac97 * <<
1850 unsigned int snd_emu10k1_rate_to_pitch(unsign 1052 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1851 1053
1852 #ifdef CONFIG_PM <<
1853 void snd_emu10k1_suspend_regs(struct snd_emu1 <<
1854 void snd_emu10k1_resume_init(struct snd_emu10 <<
1855 void snd_emu10k1_resume_regs(struct snd_emu10 <<
1856 int snd_emu10k1_efx_alloc_pm_buffer(struct sn <<
1857 void snd_emu10k1_efx_free_pm_buffer(struct sn <<
1858 void snd_emu10k1_efx_suspend(struct snd_emu10 <<
1859 void snd_emu10k1_efx_resume(struct snd_emu10k <<
1860 int snd_p16v_alloc_pm_buffer(struct snd_emu10 <<
1861 void snd_p16v_free_pm_buffer(struct snd_emu10 <<
1862 void snd_p16v_suspend(struct snd_emu10k1 *emu <<
1863 void snd_p16v_resume(struct snd_emu10k1 *emu) <<
1864 #endif <<
1865 <<
1866 /* memory allocation */ 1054 /* memory allocation */
1867 struct snd_util_memblk *snd_emu10k1_alloc_pag !! 1055 snd_util_memblk_t *snd_emu10k1_alloc_pages(emu10k1_t *emu, snd_pcm_substream_t *substream);
1868 int snd_emu10k1_free_pages(struct snd_emu10k1 !! 1056 int snd_emu10k1_free_pages(emu10k1_t *emu, snd_util_memblk_t *blk);
1869 struct snd_util_memblk *snd_emu10k1_synth_all !! 1057 snd_util_memblk_t *snd_emu10k1_synth_alloc(emu10k1_t *emu, unsigned int size);
1870 int snd_emu10k1_synth_free(struct snd_emu10k1 !! 1058 int snd_emu10k1_synth_free(emu10k1_t *emu, snd_util_memblk_t *blk);
1871 int snd_emu10k1_synth_bzero(struct snd_emu10k !! 1059 int snd_emu10k1_synth_bzero(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, int size);
1872 int snd_emu10k1_synth_copy_from_user(struct s !! 1060 int snd_emu10k1_synth_copy_from_user(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, const char __user *data, int size);
1873 int snd_emu10k1_memblk_map(struct snd_emu10k1 !! 1061 int snd_emu10k1_memblk_map(emu10k1_t *emu, emu10k1_memblk_t *blk);
1874 1062
1875 /* voice allocation */ 1063 /* voice allocation */
1876 int snd_emu10k1_voice_alloc(struct snd_emu10k !! 1064 int snd_emu10k1_voice_alloc(emu10k1_t *emu, emu10k1_voice_type_t type, int pair, emu10k1_voice_t **rvoice);
1877 int snd_emu10k1_voice_free(struct snd_emu10k1 !! 1065 int snd_emu10k1_voice_free(emu10k1_t *emu, emu10k1_voice_t *pvoice);
1878 1066
1879 /* MIDI uart */ 1067 /* MIDI uart */
1880 int snd_emu10k1_midi(struct snd_emu10k1 * emu !! 1068 int snd_emu10k1_midi(emu10k1_t * emu);
1881 int snd_emu10k1_audigy_midi(struct snd_emu10k !! 1069 int snd_emu10k1_audigy_midi(emu10k1_t * emu);
1882 1070
1883 /* proc interface */ 1071 /* proc interface */
1884 int snd_emu10k1_proc_init(struct snd_emu10k1 !! 1072 int snd_emu10k1_proc_init(emu10k1_t * emu);
1885 1073
1886 /* fx8010 irq handler */ 1074 /* fx8010 irq handler */
1887 int snd_emu10k1_fx8010_register_irq_handler(s !! 1075 int snd_emu10k1_fx8010_register_irq_handler(emu10k1_t *emu,
1888 s 1076 snd_fx8010_irq_handler_t *handler,
1889 u 1077 unsigned char gpr_running,
1890 v 1078 void *private_data,
1891 s !! 1079 snd_emu10k1_fx8010_irq_t **r_irq);
1892 int snd_emu10k1_fx8010_unregister_irq_handler !! 1080 int snd_emu10k1_fx8010_unregister_irq_handler(emu10k1_t *emu,
1893 !! 1081 snd_emu10k1_fx8010_irq_t *irq);
1894 1082
1895 #endif /* __KERNEL__ */ 1083 #endif /* __KERNEL__ */
1896 1084
1897 /* 1085 /*
1898 * ---- FX8010 ---- 1086 * ---- FX8010 ----
1899 */ 1087 */
1900 1088
1901 #define EMU10K1_CARD_CREATIVE 1089 #define EMU10K1_CARD_CREATIVE 0x00000000
1902 #define EMU10K1_CARD_EMUAPS 1090 #define EMU10K1_CARD_EMUAPS 0x00000001
1903 1091
1904 #define EMU10K1_FX8010_PCM_COUNT 1092 #define EMU10K1_FX8010_PCM_COUNT 8
1905 1093
1906 /* instruction set */ 1094 /* instruction set */
1907 #define iMAC0 0x00 /* R = A + (X * Y >> 1095 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1908 #define iMAC1 0x01 /* R = A + (-X * Y >> 1096 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1909 #define iMAC2 0x02 /* R = A + (X * Y >> 1097 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1910 #define iMAC3 0x03 /* R = A + (-X * Y >> 1098 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1911 #define iMACINT0 0x04 /* R = A + X * Y 1099 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1912 #define iMACINT1 0x05 /* R = A + X * Y 1100 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1913 #define iACC3 0x06 /* R = A + X + Y 1101 #define iACC3 0x06 /* R = A + X + Y ; saturation */
1914 #define iMACMV 0x07 /* R = A, acc += X * 1102 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1915 #define iANDXOR 0x08 /* R = (A & X) ^ Y */ 1103 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
1916 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : 1104 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1917 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : 1105 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1918 #define iLIMITLT 0x0b /* R = (A < Y) ? X : 1106 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1919 #define iLOG 0x0c /* R = linear_data, A 1107 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1920 #define iEXP 0x0d /* R = log_data, A (l 1108 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1921 #define iINTERP 0x0e /* R = A + (X * (Y - 1109 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1922 #define iSKIP 0x0f /* R = A (cc_reg), X 1110 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1923 1111
1924 /* GPRs */ 1112 /* GPRs */
1925 #define FXBUS(x) (0x00 + (x)) /* x 1113 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1926 #define EXTIN(x) (0x10 + (x)) /* x 1114 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1927 #define EXTOUT(x) (0x20 + (x)) /* x !! 1115 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f */
1928 #define FXBUS2(x) (0x30 + (x)) /* x <<
1929 /* NB <<
1930 <<
1931 #define C_00000000 0x40 1116 #define C_00000000 0x40
1932 #define C_00000001 0x41 1117 #define C_00000001 0x41
1933 #define C_00000002 0x42 1118 #define C_00000002 0x42
1934 #define C_00000003 0x43 1119 #define C_00000003 0x43
1935 #define C_00000004 0x44 1120 #define C_00000004 0x44
1936 #define C_00000008 0x45 1121 #define C_00000008 0x45
1937 #define C_00000010 0x46 1122 #define C_00000010 0x46
1938 #define C_00000020 0x47 1123 #define C_00000020 0x47
1939 #define C_00000100 0x48 1124 #define C_00000100 0x48
1940 #define C_00010000 0x49 1125 #define C_00010000 0x49
1941 #define C_00080000 0x4a 1126 #define C_00080000 0x4a
1942 #define C_10000000 0x4b 1127 #define C_10000000 0x4b
1943 #define C_20000000 0x4c 1128 #define C_20000000 0x4c
1944 #define C_40000000 0x4d 1129 #define C_40000000 0x4d
1945 #define C_80000000 0x4e 1130 #define C_80000000 0x4e
1946 #define C_7fffffff 0x4f 1131 #define C_7fffffff 0x4f
1947 #define C_ffffffff 0x50 1132 #define C_ffffffff 0x50
1948 #define C_fffffffe 0x51 1133 #define C_fffffffe 0x51
1949 #define C_c0000000 0x52 1134 #define C_c0000000 0x52
1950 #define C_4f1bbcdc 0x53 1135 #define C_4f1bbcdc 0x53
1951 #define C_5a7ef9db 0x54 1136 #define C_5a7ef9db 0x54
1952 #define C_00100000 0x55 /* ?? 1137 #define C_00100000 0x55 /* ?? */
1953 #define GPR_ACCU 0x56 /* AC 1138 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
1954 #define GPR_COND 0x57 /* CC 1139 #define GPR_COND 0x57 /* CCR, condition register */
1955 #define GPR_NOISE0 0x58 /* no 1140 #define GPR_NOISE0 0x58 /* noise source */
1956 #define GPR_NOISE1 0x59 /* no 1141 #define GPR_NOISE1 0x59 /* noise source */
1957 #define GPR_IRQ 0x5a /* IR 1142 #define GPR_IRQ 0x5a /* IRQ register */
1958 #define GPR_DBAC 0x5b /* TR 1143 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1959 #define GPR(x) (FXGPREGBASE + (x)) / 1144 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1960 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 1145 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1961 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 1146 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1962 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 1147 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1963 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 1148 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1964 1149
1965 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 1150 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1966 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 1151 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1967 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 1152 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1968 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 1153 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1969 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE 1154 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1970 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE 1155 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1971 1156
1972 #define A_FXBUS(x) (0x00 + (x)) /* x !! 1157 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f? */
1973 #define A_EXTIN(x) (0x40 + (x)) /* x !! 1158 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x1f? */
1974 #define A_P16VIN(x) (0x50 + (x)) /* x !! 1159 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f? */
1975 #define A_EXTOUT(x) (0x60 + (x)) /* x <<
1976 #define A_FXBUS2(x) (0x80 + (x)) /* x <<
1977 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x <<
1978 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x <<
1979 #define A3_EMU32IN(x) (0x160 + (x)) /* x <<
1980 #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x <<
1981 #define A_GPR(x) (A_FXGPREGBASE + (x)) 1160 #define A_GPR(x) (A_FXGPREGBASE + (x))
1982 1161
1983 /* cc_reg constants */ 1162 /* cc_reg constants */
1984 #define CC_REG_NORMALIZED C_00000001 1163 #define CC_REG_NORMALIZED C_00000001
1985 #define CC_REG_BORROW C_00000002 1164 #define CC_REG_BORROW C_00000002
1986 #define CC_REG_MINUS C_00000004 1165 #define CC_REG_MINUS C_00000004
1987 #define CC_REG_ZERO C_00000008 1166 #define CC_REG_ZERO C_00000008
1988 #define CC_REG_SATURATE C_00000010 1167 #define CC_REG_SATURATE C_00000010
1989 #define CC_REG_NONZERO C_00000100 1168 #define CC_REG_NONZERO C_00000100
1990 1169
1991 /* FX buses */ 1170 /* FX buses */
1992 #define FXBUS_PCM_LEFT 0x00 1171 #define FXBUS_PCM_LEFT 0x00
1993 #define FXBUS_PCM_RIGHT 0x01 1172 #define FXBUS_PCM_RIGHT 0x01
1994 #define FXBUS_PCM_LEFT_REAR 0x02 1173 #define FXBUS_PCM_LEFT_REAR 0x02
1995 #define FXBUS_PCM_RIGHT_REAR 0x03 1174 #define FXBUS_PCM_RIGHT_REAR 0x03
1996 #define FXBUS_MIDI_LEFT 0x04 1175 #define FXBUS_MIDI_LEFT 0x04
1997 #define FXBUS_MIDI_RIGHT 0x05 1176 #define FXBUS_MIDI_RIGHT 0x05
1998 #define FXBUS_PCM_CENTER 0x06 1177 #define FXBUS_PCM_CENTER 0x06
1999 #define FXBUS_PCM_LFE 0x07 1178 #define FXBUS_PCM_LFE 0x07
2000 #define FXBUS_PCM_LEFT_FRONT 0x08 1179 #define FXBUS_PCM_LEFT_FRONT 0x08
2001 #define FXBUS_PCM_RIGHT_FRONT 0x09 1180 #define FXBUS_PCM_RIGHT_FRONT 0x09
2002 #define FXBUS_MIDI_REVERB 0x0c 1181 #define FXBUS_MIDI_REVERB 0x0c
2003 #define FXBUS_MIDI_CHORUS 0x0d 1182 #define FXBUS_MIDI_CHORUS 0x0d
2004 #define FXBUS_PCM_LEFT_SIDE 0x0e 1183 #define FXBUS_PCM_LEFT_SIDE 0x0e
2005 #define FXBUS_PCM_RIGHT_SIDE 0x0f 1184 #define FXBUS_PCM_RIGHT_SIDE 0x0f
2006 #define FXBUS_PT_LEFT 0x14 1185 #define FXBUS_PT_LEFT 0x14
2007 #define FXBUS_PT_RIGHT 0x15 1186 #define FXBUS_PT_RIGHT 0x15
2008 1187
2009 /* Inputs */ 1188 /* Inputs */
2010 #define EXTIN_AC97_L 0x00 /* AC'97 capt 1189 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
2011 #define EXTIN_AC97_R 0x01 /* AC'97 capt 1190 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
2012 #define EXTIN_SPDIF_CD_L 0x02 /* internal S 1191 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
2013 #define EXTIN_SPDIF_CD_R 0x03 /* internal S 1192 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
2014 #define EXTIN_ZOOM_L 0x04 /* Zoom Video 1193 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
2015 #define EXTIN_ZOOM_R 0x05 /* Zoom Video 1194 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
2016 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive 1195 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
2017 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive 1196 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
2018 #define EXTIN_LINE1_L 0x08 /* LiveDrive 1197 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
2019 #define EXTIN_LINE1_R 0x09 /* LiveDrive 1198 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
2020 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive 1199 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
2021 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive 1200 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
2022 #define EXTIN_LINE2_L 0x0c /* LiveDrive 1201 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
2023 #define EXTIN_LINE2_R 0x0d /* LiveDrive 1202 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
2024 1203
2025 /* Outputs */ 1204 /* Outputs */
2026 #define EXTOUT_AC97_L 0x00 /* AC'97 play 1205 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
2027 #define EXTOUT_AC97_R 0x01 /* AC'97 play 1206 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
2028 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive 1207 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
2029 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive 1208 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
2030 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5. 1209 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
2031 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5. 1210 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
2032 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive 1211 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
2033 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive 1212 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
2034 #define EXTOUT_REAR_L 0x08 /* Rear chann 1213 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
2035 #define EXTOUT_REAR_R 0x09 /* Rear chann 1214 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
2036 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Captur 1215 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
2037 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Captur 1216 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
2038 #define EXTOUT_MIC_CAP 0x0c /* MIC Captur 1217 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
2039 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5. 1218 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
2040 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5. 1219 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
2041 #define EXTOUT_ACENTER 0x11 /* Analog Cen 1220 #define EXTOUT_ACENTER 0x11 /* Analog Center */
2042 #define EXTOUT_ALFE 0x12 /* Analog LFE 1221 #define EXTOUT_ALFE 0x12 /* Analog LFE */
2043 1222
2044 /* Audigy Inputs */ 1223 /* Audigy Inputs */
2045 #define A_EXTIN_AC97_L 0x00 /* AC 1224 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
2046 #define A_EXTIN_AC97_R 0x01 /* AC 1225 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
2047 #define A_EXTIN_SPDIF_CD_L 0x02 /* di 1226 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
2048 #define A_EXTIN_SPDIF_CD_R 0x03 /* di 1227 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
2049 #define A_EXTIN_OPT_SPDIF_L 0x04 /* au 1228 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
2050 #define A_EXTIN_OPT_SPDIF_R 0x05 /* 1229 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
2051 #define A_EXTIN_LINE2_L 0x08 /* au 1230 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
2052 #define A_EXTIN_LINE2_R 0x09 /* 1231 #define A_EXTIN_LINE2_R 0x09 /* right */
2053 #define A_EXTIN_ADC_L 0x0a /* Ph 1232 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
2054 #define A_EXTIN_ADC_R 0x0b /* 1233 #define A_EXTIN_ADC_R 0x0b /* right */
2055 #define A_EXTIN_AUX2_L 0x0c /* au 1234 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
2056 #define A_EXTIN_AUX2_R 0x0d /* 1235 #define A_EXTIN_AUX2_R 0x0d /* - right */
2057 1236
2058 /* Audigiy Outputs */ 1237 /* Audigiy Outputs */
2059 #define A_EXTOUT_FRONT_L 0x00 /* di 1238 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
2060 #define A_EXTOUT_FRONT_R 0x01 /* 1239 #define A_EXTOUT_FRONT_R 0x01 /* right */
2061 #define A_EXTOUT_CENTER 0x02 /* di 1240 #define A_EXTOUT_CENTER 0x02 /* digital front center */
2062 #define A_EXTOUT_LFE 0x03 /* di 1241 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
2063 #define A_EXTOUT_HEADPHONE_L 0x04 /* he 1242 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
2064 #define A_EXTOUT_HEADPHONE_R 0x05 /* 1243 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
2065 #define A_EXTOUT_REAR_L 0x06 /* di 1244 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
2066 #define A_EXTOUT_REAR_R 0x07 /* 1245 #define A_EXTOUT_REAR_R 0x07 /* right */
2067 #define A_EXTOUT_AFRONT_L 0x08 /* an 1246 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
2068 #define A_EXTOUT_AFRONT_R 0x09 /* 1247 #define A_EXTOUT_AFRONT_R 0x09 /* right */
2069 #define A_EXTOUT_ACENTER 0x0a /* an 1248 #define A_EXTOUT_ACENTER 0x0a /* analog center */
2070 #define A_EXTOUT_ALFE 0x0b /* an 1249 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
2071 #define A_EXTOUT_ASIDE_L 0x0c /* an 1250 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
2072 #define A_EXTOUT_ASIDE_R 0x0d /* 1251 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
2073 #define A_EXTOUT_AREAR_L 0x0e /* an 1252 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
2074 #define A_EXTOUT_AREAR_R 0x0f /* 1253 #define A_EXTOUT_AREAR_R 0x0f /* right */
2075 #define A_EXTOUT_AC97_L 0x10 /* AC 1254 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
2076 #define A_EXTOUT_AC97_R 0x11 /* 1255 #define A_EXTOUT_AC97_R 0x11 /* right */
2077 #define A_EXTOUT_ADC_CAP_L 0x16 /* AD 1256 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
2078 #define A_EXTOUT_ADC_CAP_R 0x17 /* 1257 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
2079 #define A_EXTOUT_MIC_CAP 0x18 /* Mi 1258 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
2080 1259
2081 /* Audigy constants */ 1260 /* Audigy constants */
2082 #define A_C_00000000 0xc0 1261 #define A_C_00000000 0xc0
2083 #define A_C_00000001 0xc1 1262 #define A_C_00000001 0xc1
2084 #define A_C_00000002 0xc2 1263 #define A_C_00000002 0xc2
2085 #define A_C_00000003 0xc3 1264 #define A_C_00000003 0xc3
2086 #define A_C_00000004 0xc4 1265 #define A_C_00000004 0xc4
2087 #define A_C_00000008 0xc5 1266 #define A_C_00000008 0xc5
2088 #define A_C_00000010 0xc6 1267 #define A_C_00000010 0xc6
2089 #define A_C_00000020 0xc7 1268 #define A_C_00000020 0xc7
2090 #define A_C_00000100 0xc8 1269 #define A_C_00000100 0xc8
2091 #define A_C_00010000 0xc9 1270 #define A_C_00010000 0xc9
2092 #define A_C_00000800 0xca 1271 #define A_C_00000800 0xca
2093 #define A_C_10000000 0xcb 1272 #define A_C_10000000 0xcb
2094 #define A_C_20000000 0xcc 1273 #define A_C_20000000 0xcc
2095 #define A_C_40000000 0xcd 1274 #define A_C_40000000 0xcd
2096 #define A_C_80000000 0xce 1275 #define A_C_80000000 0xce
2097 #define A_C_7fffffff 0xcf 1276 #define A_C_7fffffff 0xcf
2098 #define A_C_ffffffff 0xd0 1277 #define A_C_ffffffff 0xd0
2099 #define A_C_fffffffe 0xd1 1278 #define A_C_fffffffe 0xd1
2100 #define A_C_c0000000 0xd2 1279 #define A_C_c0000000 0xd2
2101 #define A_C_4f1bbcdc 0xd3 1280 #define A_C_4f1bbcdc 0xd3
2102 #define A_C_5a7ef9db 0xd4 1281 #define A_C_5a7ef9db 0xd4
2103 #define A_C_00100000 0xd5 1282 #define A_C_00100000 0xd5
2104 #define A_GPR_ACCU 0xd6 /* AC 1283 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
2105 #define A_GPR_COND 0xd7 /* CC 1284 #define A_GPR_COND 0xd7 /* CCR, condition register */
2106 #define A_GPR_NOISE0 0xd8 /* no 1285 #define A_GPR_NOISE0 0xd8 /* noise source */
2107 #define A_GPR_NOISE1 0xd9 /* no 1286 #define A_GPR_NOISE1 0xd9 /* noise source */
2108 #define A_GPR_IRQ 0xda /* IR 1287 #define A_GPR_IRQ 0xda /* IRQ register */
2109 #define A_GPR_DBAC 0xdb /* TR 1288 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
2110 #define A_GPR_DBACE 0xde /* TR 1289 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
2111 1290
2112 /* definitions for debug register */ 1291 /* definitions for debug register */
2113 #define EMU10K1_DBG_ZC 0x800 1292 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
2114 #define EMU10K1_DBG_SATURATION_OCCURED 0x020 1293 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
2115 #define EMU10K1_DBG_SATURATION_ADDR 0x01f 1294 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
2116 #define EMU10K1_DBG_SINGLE_STEP 0x000 1295 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
2117 #define EMU10K1_DBG_STEP 0x000 1296 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
2118 #define EMU10K1_DBG_CONDITION_CODE 0x000 1297 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
2119 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000 1298 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
2120 1299
2121 /* tank memory address line */ 1300 /* tank memory address line */
2122 #ifndef __KERNEL__ 1301 #ifndef __KERNEL__
2123 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff 1302 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
2124 #define TANKMEMADDRREG_CLEAR 0x00800000 1303 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
2125 #define TANKMEMADDRREG_ALIGN 0x00400000 1304 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
2126 #define TANKMEMADDRREG_WRITE 0x00200000 1305 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
2127 #define TANKMEMADDRREG_READ 0x00100000 1306 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
2128 #endif 1307 #endif
2129 1308
2130 struct snd_emu10k1_fx8010_info { !! 1309 typedef struct {
>> 1310 unsigned int card; /* card type */
2131 unsigned int internal_tram_size; 1311 unsigned int internal_tram_size; /* in samples */
2132 unsigned int external_tram_size; 1312 unsigned int external_tram_size; /* in samples */
2133 char fxbus_names[16][32]; 1313 char fxbus_names[16][32]; /* names of FXBUSes */
2134 char extin_names[16][32]; 1314 char extin_names[16][32]; /* names of external inputs */
2135 char extout_names[32][32]; 1315 char extout_names[32][32]; /* names of external outputs */
2136 unsigned int gpr_controls; 1316 unsigned int gpr_controls; /* count of GPR controls */
2137 }; !! 1317 } emu10k1_fx8010_info_t;
2138 1318
2139 #define EMU10K1_GPR_TRANSLATION_NONE 1319 #define EMU10K1_GPR_TRANSLATION_NONE 0
2140 #define EMU10K1_GPR_TRANSLATION_TABLE100 1320 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
2141 #define EMU10K1_GPR_TRANSLATION_BASS 1321 #define EMU10K1_GPR_TRANSLATION_BASS 2
2142 #define EMU10K1_GPR_TRANSLATION_TREBLE 1322 #define EMU10K1_GPR_TRANSLATION_TREBLE 3
2143 #define EMU10K1_GPR_TRANSLATION_ONOFF 1323 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
2144 1324
2145 struct snd_emu10k1_fx8010_control_gpr { !! 1325 typedef struct {
2146 struct snd_ctl_elem_id id; !! 1326 snd_ctl_elem_id_t id; /* full control ID definition */
2147 unsigned int vcount; /* vi 1327 unsigned int vcount; /* visible count */
2148 unsigned int count; /* co 1328 unsigned int count; /* count of GPR (1..16) */
2149 unsigned short gpr[32]; /* GP 1329 unsigned short gpr[32]; /* GPR number(s) */
2150 unsigned int value[32]; /* in 1330 unsigned int value[32]; /* initial values */
2151 unsigned int min; /* mi 1331 unsigned int min; /* minimum range */
2152 unsigned int max; /* ma 1332 unsigned int max; /* maximum range */
2153 unsigned int translation; /* tr 1333 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
2154 const unsigned int *tlv; !! 1334 } emu10k1_fx8010_control_gpr_t;
2155 }; <<
2156 1335
2157 /* old ABI without TLV support */ !! 1336 typedef struct {
2158 struct snd_emu10k1_fx8010_control_old_gpr { <<
2159 struct snd_ctl_elem_id id; <<
2160 unsigned int vcount; <<
2161 unsigned int count; <<
2162 unsigned short gpr[32]; <<
2163 unsigned int value[32]; <<
2164 unsigned int min; <<
2165 unsigned int max; <<
2166 unsigned int translation; <<
2167 }; <<
2168 <<
2169 struct snd_emu10k1_fx8010_code { <<
2170 char name[128]; 1337 char name[128];
2171 1338
2172 DECLARE_BITMAP(gpr_valid, 0x200); /* 1339 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
2173 u_int32_t __user *gpr_map; /* 1340 u_int32_t __user *gpr_map; /* initializers */
2174 1341
2175 unsigned int gpr_add_control_count; / 1342 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
2176 struct snd_emu10k1_fx8010_control_gpr !! 1343 emu10k1_fx8010_control_gpr_t __user *gpr_add_controls; /* GPR controls to add/replace */
2177 1344
2178 unsigned int gpr_del_control_count; / 1345 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
2179 struct snd_ctl_elem_id __user *gpr_de !! 1346 snd_ctl_elem_id_t __user *gpr_del_controls; /* IDs of GPR controls to remove */
2180 1347
2181 unsigned int gpr_list_control_count; 1348 unsigned int gpr_list_control_count; /* count of GPR controls to list */
2182 unsigned int gpr_list_control_total; 1349 unsigned int gpr_list_control_total; /* total count of GPR controls */
2183 struct snd_emu10k1_fx8010_control_gpr !! 1350 emu10k1_fx8010_control_gpr_t __user *gpr_list_controls; /* listed GPR controls */
2184 1351
2185 DECLARE_BITMAP(tram_valid, 0x100); /* 1352 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
2186 u_int32_t __user *tram_data_map; /* 1353 u_int32_t __user *tram_data_map; /* data initializers */
2187 u_int32_t __user *tram_addr_map; /* 1354 u_int32_t __user *tram_addr_map; /* map initializers */
2188 1355
2189 DECLARE_BITMAP(code_valid, 1024); /* 1356 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
2190 u_int32_t __user *code; /* 1357 u_int32_t __user *code; /* one instruction - 64 bits */
2191 }; !! 1358 } emu10k1_fx8010_code_t;
2192 1359
2193 struct snd_emu10k1_fx8010_tram { !! 1360 typedef struct {
2194 unsigned int address; /* 31 1361 unsigned int address; /* 31.bit == 1 -> external TRAM */
2195 unsigned int size; /* si 1362 unsigned int size; /* size in samples (4 bytes) */
2196 unsigned int *samples; /* po 1363 unsigned int *samples; /* pointer to samples (20-bit) */
2197 /* NU 1364 /* NULL->clear memory */
2198 }; !! 1365 } emu10k1_fx8010_tram_t;
2199 1366
2200 struct snd_emu10k1_fx8010_pcm_rec { !! 1367 typedef struct {
2201 unsigned int substream; /* su 1368 unsigned int substream; /* substream number */
2202 unsigned int res1; /* re 1369 unsigned int res1; /* reserved */
2203 unsigned int channels; /* 16 1370 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
2204 unsigned int tram_start; /* ri 1371 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
2205 unsigned int buffer_size; /* co 1372 unsigned int buffer_size; /* count of buffered samples */
2206 unsigned short gpr_size; 1373 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
2207 unsigned short gpr_ptr; /* GP 1374 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
2208 unsigned short gpr_count; /* GP 1375 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
2209 unsigned short gpr_tmpcount; /* GP 1376 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
2210 unsigned short gpr_trigger; /* GP 1377 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
2211 unsigned short gpr_running; /* GP 1378 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
2212 unsigned char pad; /* re 1379 unsigned char pad; /* reserved */
2213 unsigned char etram[32]; /* ex 1380 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
2214 unsigned int res2; /* re 1381 unsigned int res2; /* reserved */
2215 }; !! 1382 } emu10k1_fx8010_pcm_t;
2216 <<
2217 #define SNDRV_EMU10K1_VERSION SNDRV <<
2218 1383
2219 #define SNDRV_EMU10K1_IOCTL_INFO _IOR !! 1384 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t)
2220 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW !! 1385 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t)
2221 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR !! 1386 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, emu10k1_fx8010_code_t)
2222 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW 1387 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
2223 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW !! 1388 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t)
2224 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR !! 1389 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, emu10k1_fx8010_tram_t)
2225 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW !! 1390 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t)
2226 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR !! 1391 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t)
2227 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR <<
2228 #define SNDRV_EMU10K1_IOCTL_STOP _IO 1392 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
2229 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO 1393 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
2230 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER 1394 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
2231 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW 1395 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
2232 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR 1396 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
2233 1397
2234 /* typedefs for compatibility to user-space * <<
2235 typedef struct snd_emu10k1_fx8010_info emu10k <<
2236 typedef struct snd_emu10k1_fx8010_control_gpr <<
2237 typedef struct snd_emu10k1_fx8010_code emu10k <<
2238 typedef struct snd_emu10k1_fx8010_tram emu10k <<
2239 typedef struct snd_emu10k1_fx8010_pcm_rec emu <<
2240 <<
2241 #endif /* __SOUND_EMU10K1_H */ 1398 #endif /* __SOUND_EMU10K1_H */
2242 1399
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