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1 /* 1 /*
2 * pci.h 2 * pci.h
3 * 3 *
4 * PCI defines and function prototypes 4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt 5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ 6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 * 7 *
8 * For more information, please consult t 8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get 9 * http://www.pcisig.com/ for how to get them):
10 * 10 *
11 * PCI BIOS Specification 11 * PCI BIOS Specification
12 * PCI Local Bus Specification 12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification 13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide 14 * PCI System Design Guide
15 */ 15 */
16 16
17 #ifndef LINUX_PCI_H 17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H 18 #define LINUX_PCI_H
19 19
20 #include <linux/mod_devicetable.h> !! 20 /* Include the pci register defines */
21 !! 21 #include <linux/pci_regs.h>
22 /* <<
23 * Under PCI, each device has 256 bytes of con <<
24 * of which the first 64 bytes are standardize <<
25 */ <<
26 #define PCI_VENDOR_ID 0x00 /* 16 <<
27 #define PCI_DEVICE_ID 0x02 /* 16 <<
28 #define PCI_COMMAND 0x04 /* 16 <<
29 #define PCI_COMMAND_IO 0x1 /* Ena <<
30 #define PCI_COMMAND_MEMORY 0x2 /* Ena <<
31 #define PCI_COMMAND_MASTER 0x4 /* Ena <<
32 #define PCI_COMMAND_SPECIAL 0x8 /* Ena <<
33 #define PCI_COMMAND_INVALIDATE 0x10 /* Use <<
34 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Ena <<
35 #define PCI_COMMAND_PARITY 0x40 /* Ena <<
36 #define PCI_COMMAND_WAIT 0x80 /* Ena <<
37 #define PCI_COMMAND_SERR 0x100 /* Ena <<
38 #define PCI_COMMAND_FAST_BACK 0x200 /* Ena <<
39 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INT <<
40 <<
41 #define PCI_STATUS 0x06 /* 16 <<
42 #define PCI_STATUS_CAP_LIST 0x10 /* Sup <<
43 #define PCI_STATUS_66MHZ 0x20 /* Sup <<
44 #define PCI_STATUS_UDF 0x40 /* Sup <<
45 #define PCI_STATUS_FAST_BACK 0x80 /* Acc <<
46 #define PCI_STATUS_PARITY 0x100 /* Det <<
47 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEV <<
48 #define PCI_STATUS_DEVSEL_FAST 0x000 <<
49 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 <<
50 #define PCI_STATUS_DEVSEL_SLOW 0x400 <<
51 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* <<
52 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* <<
53 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* <<
54 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* <<
55 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* <<
56 <<
57 #define PCI_CLASS_REVISION 0x08 /* Hig <<
58 rev <<
59 #define PCI_REVISION_ID 0x08 /* Rev <<
60 #define PCI_CLASS_PROG 0x09 /* Reg <<
61 #define PCI_CLASS_DEVICE 0x0a /* Dev <<
62 <<
63 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 b <<
64 #define PCI_LATENCY_TIMER 0x0d /* 8 b <<
65 #define PCI_HEADER_TYPE 0x0e /* 8 b <<
66 #define PCI_HEADER_TYPE_NORMAL 0 <<
67 #define PCI_HEADER_TYPE_BRIDGE 1 <<
68 #define PCI_HEADER_TYPE_CARDBUS 2 <<
69 <<
70 #define PCI_BIST 0x0f /* 8 b <<
71 #define PCI_BIST_CODE_MASK 0x0f /* Ret <<
72 #define PCI_BIST_START 0x40 /* 1 t <<
73 #define PCI_BIST_CAPABLE 0x80 /* 1 i <<
74 <<
75 /* <<
76 * Base addresses specify locations in memory <<
77 * Decoded size can be determined by writing a <<
78 * 0xffffffff to the register, and reading it <<
79 * 1 bits are decoded. <<
80 */ <<
81 #define PCI_BASE_ADDRESS_0 0x10 /* 32 <<
82 #define PCI_BASE_ADDRESS_1 0x14 /* 32 <<
83 #define PCI_BASE_ADDRESS_2 0x18 /* 32 <<
84 #define PCI_BASE_ADDRESS_3 0x1c /* 32 <<
85 #define PCI_BASE_ADDRESS_4 0x20 /* 32 <<
86 #define PCI_BASE_ADDRESS_5 0x24 /* 32 <<
87 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = <<
88 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 <<
89 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 <<
90 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 <<
91 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 <<
92 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 <<
93 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 <<
94 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 <<
95 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f <<
96 #define PCI_BASE_ADDRESS_IO_MASK (~0x03 <<
97 /* bit 1 is reserved if address_space = 1 */ <<
98 <<
99 /* Header type 0 (normal devices) */ <<
100 #define PCI_CARDBUS_CIS 0x28 <<
101 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c <<
102 #define PCI_SUBSYSTEM_ID 0x2e <<
103 #define PCI_ROM_ADDRESS 0x30 /* Bit <<
104 #define PCI_ROM_ADDRESS_ENABLE 0x01 <<
105 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) <<
106 <<
107 #define PCI_CAPABILITY_LIST 0x34 /* Off <<
108 <<
109 /* 0x35-0x3b are reserved */ <<
110 #define PCI_INTERRUPT_LINE 0x3c /* 8 b <<
111 #define PCI_INTERRUPT_PIN 0x3d /* 8 b <<
112 #define PCI_MIN_GNT 0x3e /* 8 b <<
113 #define PCI_MAX_LAT 0x3f /* 8 b <<
114 <<
115 /* Header type 1 (PCI-to-PCI bridges) */ <<
116 #define PCI_PRIMARY_BUS 0x18 /* Pri <<
117 #define PCI_SECONDARY_BUS 0x19 /* Sec <<
118 #define PCI_SUBORDINATE_BUS 0x1a /* Hig <<
119 #define PCI_SEC_LATENCY_TIMER 0x1b /* Lat <<
120 #define PCI_IO_BASE 0x1c /* I/O <<
121 #define PCI_IO_LIMIT 0x1d <<
122 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O <<
123 #define PCI_IO_RANGE_TYPE_16 0x00 <<
124 #define PCI_IO_RANGE_TYPE_32 0x01 <<
125 #define PCI_IO_RANGE_MASK (~0x0fUL) <<
126 #define PCI_SEC_STATUS 0x1e /* Sec <<
127 #define PCI_MEMORY_BASE 0x20 /* Mem <<
128 #define PCI_MEMORY_LIMIT 0x22 <<
129 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL <<
130 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) <<
131 #define PCI_PREF_MEMORY_BASE 0x24 /* Pre <<
132 #define PCI_PREF_MEMORY_LIMIT 0x26 <<
133 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL <<
134 #define PCI_PREF_RANGE_TYPE_32 0x00 <<
135 #define PCI_PREF_RANGE_TYPE_64 0x01 <<
136 #define PCI_PREF_RANGE_MASK (~0x0fUL) <<
137 #define PCI_PREF_BASE_UPPER32 0x28 /* Upp <<
138 #define PCI_PREF_LIMIT_UPPER32 0x2c <<
139 #define PCI_IO_BASE_UPPER16 0x30 /* Upp <<
140 #define PCI_IO_LIMIT_UPPER16 0x32 <<
141 /* 0x34 same as for htype 0 */ <<
142 /* 0x35-0x3b is reserved */ <<
143 #define PCI_ROM_ADDRESS1 0x38 /* Sam <<
144 /* 0x3c-0x3d are same as for htype 0 */ <<
145 #define PCI_BRIDGE_CONTROL 0x3e <<
146 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Ena <<
147 #define PCI_BRIDGE_CTL_SERR 0x02 /* The <<
148 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Dis <<
149 #define PCI_BRIDGE_CTL_VGA 0x08 /* For <<
150 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* <<
151 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Sec <<
152 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fas <<
153 <<
154 /* Header type 2 (CardBus bridges) */ <<
155 #define PCI_CB_CAPABILITY_LIST 0x14 <<
156 /* 0x15 reserved */ <<
157 #define PCI_CB_SEC_STATUS 0x16 /* Sec <<
158 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI <<
159 #define PCI_CB_CARD_BUS 0x19 /* Car <<
160 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Sub <<
161 #define PCI_CB_LATENCY_TIMER 0x1b /* Car <<
162 #define PCI_CB_MEMORY_BASE_0 0x1c <<
163 #define PCI_CB_MEMORY_LIMIT_0 0x20 <<
164 #define PCI_CB_MEMORY_BASE_1 0x24 <<
165 #define PCI_CB_MEMORY_LIMIT_1 0x28 <<
166 #define PCI_CB_IO_BASE_0 0x2c <<
167 #define PCI_CB_IO_BASE_0_HI 0x2e <<
168 #define PCI_CB_IO_LIMIT_0 0x30 <<
169 #define PCI_CB_IO_LIMIT_0_HI 0x32 <<
170 #define PCI_CB_IO_BASE_1 0x34 <<
171 #define PCI_CB_IO_BASE_1_HI 0x36 <<
172 #define PCI_CB_IO_LIMIT_1 0x38 <<
173 #define PCI_CB_IO_LIMIT_1_HI 0x3a <<
174 #define PCI_CB_IO_RANGE_MASK (~0x03UL) <<
175 /* 0x3c-0x3d are same as for htype 0 */ <<
176 #define PCI_CB_BRIDGE_CONTROL 0x3e <<
177 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 <<
178 #define PCI_CB_BRIDGE_CTL_SERR 0x02 <<
179 #define PCI_CB_BRIDGE_CTL_ISA 0x04 <<
180 #define PCI_CB_BRIDGE_CTL_VGA 0x08 <<
181 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 <<
182 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 <<
183 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 <<
184 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 <<
185 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 <<
186 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 <<
187 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 <<
188 #define PCI_CB_SUBSYSTEM_ID 0x42 <<
189 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16- <<
190 /* 0x48-0x7f reserved */ <<
191 <<
192 /* Capability lists */ <<
193 <<
194 #define PCI_CAP_LIST_ID 0 /* Cap <<
195 #define PCI_CAP_ID_PM 0x01 /* Pow <<
196 #define PCI_CAP_ID_AGP 0x02 /* Acc <<
197 #define PCI_CAP_ID_VPD 0x03 /* Vit <<
198 #define PCI_CAP_ID_SLOTID 0x04 /* Slo <<
199 #define PCI_CAP_ID_MSI 0x05 /* Mes <<
200 #define PCI_CAP_ID_CHSWP 0x06 /* Com <<
201 #define PCI_CAP_ID_PCIX 0x07 /* PCI <<
202 #define PCI_CAP_ID_SHPC 0x0C /* PCI <<
203 #define PCI_CAP_ID_EXP 0x10 /* PCI <<
204 #define PCI_CAP_ID_MSIX 0x11 /* MSI <<
205 #define PCI_CAP_LIST_NEXT 1 /* Nex <<
206 #define PCI_CAP_FLAGS 2 /* Cap <<
207 #define PCI_CAP_SIZEOF 4 <<
208 <<
209 /* Power Management Registers */ <<
210 <<
211 #define PCI_PM_PMC 2 /* PM <<
212 #define PCI_PM_CAP_VER_MASK 0x0007 /* Ver <<
213 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME <<
214 #define PCI_PM_CAP_RESERVED 0x0010 /* Res <<
215 #define PCI_PM_CAP_DSI 0x0020 /* Dev <<
216 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Aux <<
217 #define PCI_PM_CAP_D1 0x0200 /* D1 <<
218 #define PCI_PM_CAP_D2 0x0400 /* D2 <<
219 #define PCI_PM_CAP_PME 0x0800 /* PME <<
220 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME <<
221 #define PCI_PM_CAP_PME_D0 0x0800 /* PME <<
222 #define PCI_PM_CAP_PME_D1 0x1000 /* PME <<
223 #define PCI_PM_CAP_PME_D2 0x2000 /* PME <<
224 #define PCI_PM_CAP_PME_D3 0x4000 /* PME <<
225 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME <<
226 #define PCI_PM_CTRL 4 /* PM <<
227 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Cur <<
228 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME <<
229 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 <<
230 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 <<
231 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME <<
232 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB <<
233 #define PCI_PM_PPB_B2_B3 0x40 /* Sto <<
234 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus <<
235 #define PCI_PM_DATA_REGISTER 7 /* (?? <<
236 #define PCI_PM_SIZEOF 8 <<
237 <<
238 /* AGP registers */ <<
239 <<
240 #define PCI_AGP_VERSION 2 /* BCD <<
241 #define PCI_AGP_RFU 3 /* Res <<
242 #define PCI_AGP_STATUS 4 /* Sta <<
243 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 <<
244 #define PCI_AGP_STATUS_SBA 0x0200 /* Sid <<
245 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64- <<
246 #define PCI_AGP_STATUS_FW 0x0010 /* FW <<
247 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x <<
248 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x <<
249 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x <<
250 #define PCI_AGP_COMMAND 8 /* Con <<
251 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 / <<
252 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sid <<
253 #define PCI_AGP_COMMAND_AGP 0x0100 /* All <<
254 #define PCI_AGP_COMMAND_64BIT 0x0020 /* All <<
255 #define PCI_AGP_COMMAND_FW 0x0010 /* For <<
256 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use <<
257 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use <<
258 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use <<
259 #define PCI_AGP_SIZEOF 12 <<
260 <<
261 /* Vital Product Data */ <<
262 <<
263 #define PCI_VPD_ADDR 2 /* Add <<
264 #define PCI_VPD_ADDR_MASK 0x7fff /* Add <<
265 #define PCI_VPD_ADDR_F 0x8000 /* Wri <<
266 #define PCI_VPD_DATA 4 /* 32- <<
267 <<
268 /* Slot Identification */ <<
269 <<
270 #define PCI_SID_ESR 2 /* Exp <<
271 #define PCI_SID_ESR_NSLOTS 0x1f /* Num <<
272 #define PCI_SID_ESR_FIC 0x20 /* Fir <<
273 #define PCI_SID_CHASSIS_NR 3 /* Cha <<
274 <<
275 /* Message Signalled Interrupts registers */ <<
276 <<
277 #define PCI_MSI_FLAGS 2 /* Var <<
278 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64- <<
279 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Mes <<
280 #define PCI_MSI_FLAGS_QMASK 0x0e /* Max <<
281 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI <<
282 #define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64- <<
283 #define PCI_MSI_RFU 3 /* Res <<
284 #define PCI_MSI_ADDRESS_LO 4 /* Low <<
285 #define PCI_MSI_ADDRESS_HI 8 /* Upp <<
286 #define PCI_MSI_DATA_32 8 /* 16 <<
287 #define PCI_MSI_DATA_64 12 /* 16 <<
288 #define PCI_MSI_MASK_BIT 16 /* Mas <<
289 <<
290 /* CompactPCI Hotswap Register */ <<
291 <<
292 #define PCI_CHSWP_CSR 2 /* Con <<
293 #define PCI_CHSWP_DHA 0x01 /* Dev <<
294 #define PCI_CHSWP_EIM 0x02 /* ENU <<
295 #define PCI_CHSWP_PIE 0x04 /* Pen <<
296 #define PCI_CHSWP_LOO 0x08 /* LED <<
297 #define PCI_CHSWP_PI 0x30 /* Pro <<
298 #define PCI_CHSWP_EXT 0x40 /* ENU <<
299 #define PCI_CHSWP_INS 0x80 /* ENU <<
300 <<
301 /* PCI-X registers */ <<
302 <<
303 #define PCI_X_CMD 2 /* Mod <<
304 #define PCI_X_CMD_DPERR_E 0x0001 /* Dat <<
305 #define PCI_X_CMD_ERO 0x0002 /* Ena <<
306 #define PCI_X_CMD_MAX_READ 0x000c /* Max <<
307 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max <<
308 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & <<
309 #define PCI_X_STATUS 4 /* PCI <<
310 #define PCI_X_STATUS_DEVFN 0x000000ff <<
311 #define PCI_X_STATUS_BUS 0x0000ff00 <<
312 #define PCI_X_STATUS_64BIT 0x00010000 <<
313 #define PCI_X_STATUS_133MHZ 0x00020000 <<
314 #define PCI_X_STATUS_SPL_DISC 0x00040000 <<
315 #define PCI_X_STATUS_UNX_SPL 0x00080000 <<
316 #define PCI_X_STATUS_COMPLEX 0x00100000 <<
317 #define PCI_X_STATUS_MAX_READ 0x00600000 <<
318 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 <<
319 #define PCI_X_STATUS_MAX_CUM 0x1c000000 <<
320 #define PCI_X_STATUS_SPL_ERR 0x20000000 <<
321 #define PCI_X_STATUS_266MHZ 0x40000000 <<
322 #define PCI_X_STATUS_533MHZ 0x80000000 <<
323 <<
324 /* PCI Express capability registers */ <<
325 <<
326 #define PCI_EXP_FLAGS 2 /* Cap <<
327 #define PCI_EXP_FLAGS_VERS 0x000f /* Cap <<
328 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Dev <<
329 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Exp <<
330 #define PCI_EXP_TYPE_LEG_END 0x1 /* Leg <<
331 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Roo <<
332 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Ups <<
333 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Dow <<
334 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI <<
335 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slo <<
336 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Int <<
337 #define PCI_EXP_DEVCAP 4 /* Dev <<
338 #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max <<
339 #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Pha <<
340 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Ext <<
341 #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s <<
342 #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 <<
343 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Att <<
344 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Att <<
345 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Pow <<
346 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* S <<
347 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* S <<
348 #define PCI_EXP_DEVCTL 8 /* Dev <<
349 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Cor <<
350 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non <<
351 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fat <<
352 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Uns <<
353 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Ena <<
354 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max <<
355 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Ext <<
356 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Pha <<
357 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Aux <<
358 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* <<
359 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max <<
360 #define PCI_EXP_DEVSTA 10 /* Dev <<
361 #define PCI_EXP_DEVSTA_CED 0x01 /* Cor <<
362 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non <<
363 #define PCI_EXP_DEVSTA_FED 0x04 /* Fat <<
364 #define PCI_EXP_DEVSTA_URD 0x08 /* Uns <<
365 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX <<
366 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Tra <<
367 #define PCI_EXP_LNKCAP 12 /* Lin <<
368 #define PCI_EXP_LNKCTL 16 /* Lin <<
369 #define PCI_EXP_LNKSTA 18 /* Lin <<
370 #define PCI_EXP_SLTCAP 20 /* Slo <<
371 #define PCI_EXP_SLTCTL 24 /* Slo <<
372 #define PCI_EXP_SLTSTA 26 /* Slo <<
373 #define PCI_EXP_RTCTL 28 /* Roo <<
374 #define PCI_EXP_RTCTL_SECEE 0x01 /* Sys <<
375 #define PCI_EXP_RTCTL_SENFEE 0x02 /* Sys <<
376 #define PCI_EXP_RTCTL_SEFEE 0x04 /* Sys <<
377 #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME <<
378 #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS <<
379 #define PCI_EXP_RTCAP 30 /* Roo <<
380 #define PCI_EXP_RTSTA 32 /* Roo <<
381 <<
382 /* Extended Capabilities (PCI-X 2.0 and Expres <<
383 #define PCI_EXT_CAP_ID(header) (heade <<
384 #define PCI_EXT_CAP_VER(header) ((head <<
385 #define PCI_EXT_CAP_NEXT(header) ((head <<
386 <<
387 #define PCI_EXT_CAP_ID_ERR 1 <<
388 #define PCI_EXT_CAP_ID_VC 2 <<
389 #define PCI_EXT_CAP_ID_DSN 3 <<
390 #define PCI_EXT_CAP_ID_PWR 4 <<
391 <<
392 /* Advanced Error Reporting */ <<
393 #define PCI_ERR_UNCOR_STATUS 4 /* Unc <<
394 #define PCI_ERR_UNC_TRAIN 0x00000001 <<
395 #define PCI_ERR_UNC_DLP 0x00000010 <<
396 #define PCI_ERR_UNC_POISON_TLP 0x00001000 <<
397 #define PCI_ERR_UNC_FCP 0x00002000 <<
398 #define PCI_ERR_UNC_COMP_TIME 0x00004000 <<
399 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 <<
400 #define PCI_ERR_UNC_UNX_COMP 0x00010000 <<
401 #define PCI_ERR_UNC_RX_OVER 0x00020000 <<
402 #define PCI_ERR_UNC_MALF_TLP 0x00040000 <<
403 #define PCI_ERR_UNC_ECRC 0x00080000 <<
404 #define PCI_ERR_UNC_UNSUP 0x00100000 <<
405 #define PCI_ERR_UNCOR_MASK 8 /* Unc <<
406 /* Same bits as above */ <<
407 #define PCI_ERR_UNCOR_SEVER 12 /* Unc <<
408 /* Same bits as above */ <<
409 #define PCI_ERR_COR_STATUS 16 /* Cor <<
410 #define PCI_ERR_COR_RCVR 0x00000001 <<
411 #define PCI_ERR_COR_BAD_TLP 0x00000040 <<
412 #define PCI_ERR_COR_BAD_DLLP 0x00000080 <<
413 #define PCI_ERR_COR_REP_ROLL 0x00000100 <<
414 #define PCI_ERR_COR_REP_TIMER 0x00001000 <<
415 #define PCI_ERR_COR_MASK 20 /* Cor <<
416 /* Same bits as above */ <<
417 #define PCI_ERR_CAP 24 /* Adv <<
418 #define PCI_ERR_CAP_FEP(x) ((x) & 31) <<
419 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 <<
420 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 <<
421 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 <<
422 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 <<
423 #define PCI_ERR_HEADER_LOG 28 /* Hea <<
424 #define PCI_ERR_ROOT_COMMAND 44 /* Roo <<
425 #define PCI_ERR_ROOT_STATUS 48 <<
426 #define PCI_ERR_ROOT_COR_SRC 52 <<
427 #define PCI_ERR_ROOT_SRC 54 <<
428 <<
429 /* Virtual Channel */ <<
430 #define PCI_VC_PORT_REG1 4 <<
431 #define PCI_VC_PORT_REG2 8 <<
432 #define PCI_VC_PORT_CTRL 12 <<
433 #define PCI_VC_PORT_STATUS 14 <<
434 #define PCI_VC_RES_CAP 16 <<
435 #define PCI_VC_RES_CTRL 20 <<
436 #define PCI_VC_RES_STATUS 26 <<
437 <<
438 /* Power Budgeting */ <<
439 #define PCI_PWR_DSR 4 /* Dat <<
440 #define PCI_PWR_DATA 8 /* Dat <<
441 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) <<
442 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & <<
443 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & <<
444 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) <<
445 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & <<
446 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & <<
447 #define PCI_PWR_CAP 12 /* Cap <<
448 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) <<
449 <<
450 /* Include the ID list */ <<
451 <<
452 #include <linux/pci_ids.h> <<
453 22
454 /* 23 /*
455 * The PCI interface treats multi-function dev 24 * The PCI interface treats multi-function devices as independent
456 * devices. The slot/function address of each 25 * devices. The slot/function address of each device is encoded
457 * in a single byte as follows: 26 * in a single byte as follows:
458 * 27 *
459 * 7:3 = slot 28 * 7:3 = slot
460 * 2:0 = function 29 * 2:0 = function
461 */ 30 */
462 #define PCI_DEVFN(slot,func) ((((slot) & 0x !! 31 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
463 #define PCI_SLOT(devfn) (((devfn) >> 3 32 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
464 #define PCI_FUNC(devfn) ((devfn) & 0x0 33 #define PCI_FUNC(devfn) ((devfn) & 0x07)
465 34
466 /* Ioctls for /proc/bus/pci/X/Y nodes. */ 35 /* Ioctls for /proc/bus/pci/X/Y nodes. */
467 #define PCIIOC_BASE ('P' << 24 | ' 36 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
468 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 37 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
469 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 38 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
470 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 39 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
471 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 40 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
472 41
473 #ifdef __KERNEL__ 42 #ifdef __KERNEL__
474 43
>> 44 #include <linux/mod_devicetable.h>
>> 45
475 #include <linux/types.h> 46 #include <linux/types.h>
476 #include <linux/config.h> <<
477 #include <linux/ioport.h> 47 #include <linux/ioport.h>
478 #include <linux/list.h> 48 #include <linux/list.h>
>> 49 #include <linux/compiler.h>
479 #include <linux/errno.h> 50 #include <linux/errno.h>
>> 51 #include <asm/atomic.h>
480 #include <linux/device.h> 52 #include <linux/device.h>
481 53
>> 54 /* Include the ID list */
>> 55 #include <linux/pci_ids.h>
>> 56
482 /* File state for mmap()s on /proc/bus/pci/X/Y 57 /* File state for mmap()s on /proc/bus/pci/X/Y */
483 enum pci_mmap_state { 58 enum pci_mmap_state {
484 pci_mmap_io, 59 pci_mmap_io,
485 pci_mmap_mem 60 pci_mmap_mem
486 }; 61 };
487 62
488 /* This defines the direction arg to the DMA m 63 /* This defines the direction arg to the DMA mapping routines. */
489 #define PCI_DMA_BIDIRECTIONAL 0 64 #define PCI_DMA_BIDIRECTIONAL 0
490 #define PCI_DMA_TODEVICE 1 65 #define PCI_DMA_TODEVICE 1
491 #define PCI_DMA_FROMDEVICE 2 66 #define PCI_DMA_FROMDEVICE 2
492 #define PCI_DMA_NONE 3 67 #define PCI_DMA_NONE 3
493 68
494 #define DEVICE_COUNT_COMPATIBLE 4 <<
495 #define DEVICE_COUNT_RESOURCE 12 69 #define DEVICE_COUNT_RESOURCE 12
496 70
497 typedef int __bitwise pci_power_t; 71 typedef int __bitwise pci_power_t;
498 72
499 #define PCI_D0 ((pci_power_t __force) 0) !! 73 #define PCI_D0 ((pci_power_t __force) 0)
500 #define PCI_D1 ((pci_power_t __force) 1) !! 74 #define PCI_D1 ((pci_power_t __force) 1)
501 #define PCI_D2 ((pci_power_t __force) 2) !! 75 #define PCI_D2 ((pci_power_t __force) 2)
502 #define PCI_D3hot ((pci_power_t __force) 76 #define PCI_D3hot ((pci_power_t __force) 3)
503 #define PCI_D3cold ((pci_power_t __force) 77 #define PCI_D3cold ((pci_power_t __force) 4)
>> 78 #define PCI_UNKNOWN ((pci_power_t __force) 5)
>> 79 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
>> 80
>> 81 /** The pci_channel state describes connectivity between the CPU and
>> 82 * the pci device. If some PCI bus between here and the pci device
>> 83 * has crashed or locked up, this info is reflected here.
>> 84 */
>> 85 typedef unsigned int __bitwise pci_channel_state_t;
>> 86
>> 87 enum pci_channel_state {
>> 88 /* I/O channel is in normal state */
>> 89 pci_channel_io_normal = (__force pci_channel_state_t) 1,
>> 90
>> 91 /* I/O to channel is blocked */
>> 92 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
>> 93
>> 94 /* PCI card is dead */
>> 95 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
>> 96 };
>> 97
>> 98 typedef unsigned int __bitwise pcie_reset_state_t;
>> 99
>> 100 enum pcie_reset_state {
>> 101 /* Reset is NOT asserted (Use to deassert reset) */
>> 102 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
>> 103
>> 104 /* Use #PERST to reset PCI-E device */
>> 105 pcie_warm_reset = (__force pcie_reset_state_t) 2,
>> 106
>> 107 /* Use PCI-E Hot Reset to reset device */
>> 108 pcie_hot_reset = (__force pcie_reset_state_t) 3
>> 109 };
>> 110
>> 111 typedef unsigned short __bitwise pci_dev_flags_t;
>> 112 enum pci_dev_flags {
>> 113 /* INTX_DISABLE in PCI_COMMAND register disables MSI
>> 114 * generation too.
>> 115 */
>> 116 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
>> 117 };
>> 118
>> 119 typedef unsigned short __bitwise pci_bus_flags_t;
>> 120 enum pci_bus_flags {
>> 121 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
>> 122 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>> 123 };
>> 124
>> 125 struct pci_cap_saved_state {
>> 126 struct hlist_node next;
>> 127 char cap_nr;
>> 128 u32 data[0];
>> 129 };
504 130
505 /* 131 /*
506 * The pci_dev structure is used to describe P 132 * The pci_dev structure is used to describe PCI devices.
507 */ 133 */
508 struct pci_dev { 134 struct pci_dev {
509 struct list_head global_list; /* nod 135 struct list_head global_list; /* node in list of all PCI devices */
510 struct list_head bus_list; /* nod 136 struct list_head bus_list; /* node in per-bus list */
511 struct pci_bus *bus; /* bus 137 struct pci_bus *bus; /* bus this device is on */
512 struct pci_bus *subordinate; /* bus 138 struct pci_bus *subordinate; /* bus this device bridges to */
513 139
514 void *sysdata; /* hoo 140 void *sysdata; /* hook for sys-specific extension */
515 struct proc_dir_entry *procent; /* dev 141 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
516 142
517 unsigned int devfn; /* enc 143 unsigned int devfn; /* encoded device & function index */
518 unsigned short vendor; 144 unsigned short vendor;
519 unsigned short device; 145 unsigned short device;
520 unsigned short subsystem_vendor; 146 unsigned short subsystem_vendor;
521 unsigned short subsystem_device; 147 unsigned short subsystem_device;
522 unsigned int class; /* 3 b 148 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
>> 149 u8 revision; /* PCI revision, low byte of class word */
523 u8 hdr_type; /* PCI 150 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
>> 151 u8 pcie_type; /* PCI-E device/port type */
524 u8 rom_base_reg; /* whi 152 u8 rom_base_reg; /* which config register controls the ROM */
>> 153 u8 pin; /* which interrupt pin this device uses */
525 154
526 struct pci_driver *driver; /* whi 155 struct pci_driver *driver; /* which driver has allocated this device */
527 u64 dma_mask; /* Mas 156 u64 dma_mask; /* Mask of the bits of bus address this
528 dev 157 device implements. Normally this is
529 0xf 158 0xffffffff. You only need to change
530 thi 159 this if your device has broken DMA
531 or 160 or supports 64-bit transfers. */
532 161
>> 162 struct device_dma_parameters dma_parms;
>> 163
533 pci_power_t current_state; /* Cur 164 pci_power_t current_state; /* Current operating state. In ACPI-speak,
534 thi 165 this is D0-D3, D0 being fully functional,
535 and 166 and D3 being off. */
536 167
>> 168 pci_channel_state_t error_state; /* current connectivity state */
537 struct device dev; /* Gen 169 struct device dev; /* Generic device interface */
538 170
539 /* device is compatible with these IDs <<
540 unsigned short vendor_compatible[DEVIC <<
541 unsigned short device_compatible[DEVIC <<
542 <<
543 int cfg_size; /* Siz 171 int cfg_size; /* Size of configuration space */
544 172
545 /* 173 /*
546 * Instead of touching interrupt line 174 * Instead of touching interrupt line and base address registers
547 * directly, use the values stored her 175 * directly, use the values stored here. They might be different!
548 */ 176 */
549 unsigned int irq; 177 unsigned int irq;
550 struct resource resource[DEVICE_COUNT_ 178 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
551 179
552 char * slot_name; /* poi <<
553 <<
554 /* These fields are used by common fix 180 /* These fields are used by common fixups */
555 unsigned int transparent:1; /* Tra 181 unsigned int transparent:1; /* Transparent PCI bridge */
556 unsigned int multifunction:1;/* Par 182 unsigned int multifunction:1;/* Part of multi-function device */
557 /* keep track of device state */ 183 /* keep track of device state */
558 unsigned int is_enabled:1; /* pci <<
559 unsigned int is_busmaster:1; /* dev 184 unsigned int is_busmaster:1; /* device is busmaster */
560 !! 185 unsigned int no_msi:1; /* device may not use msi */
>> 186 unsigned int no_d1d2:1; /* only allow d0 or d3 */
>> 187 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
>> 188 unsigned int broken_parity_status:1; /* Device generates false positive parity */
>> 189 unsigned int msi_enabled:1;
>> 190 unsigned int msix_enabled:1;
>> 191 unsigned int is_managed:1;
>> 192 unsigned int is_pcie:1;
>> 193 pci_dev_flags_t dev_flags;
>> 194 atomic_t enable_cnt; /* pci_enable_device has been called */
>> 195
561 u32 saved_config_space[16] 196 u32 saved_config_space[16]; /* config space saved at suspend time */
>> 197 struct hlist_head saved_cap_space;
562 struct bin_attribute *rom_attr; /* att 198 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
563 int rom_attr_enabled; /* has 199 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
564 struct bin_attribute *res_attr[DEVICE_ 200 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
565 #ifdef CONFIG_PCI_NAMES !! 201 #ifdef CONFIG_PCI_MSI
566 #define PCI_NAME_SIZE 96 !! 202 struct list_head msi_list;
567 #define PCI_NAME_HALF __stringify(43) /* les <<
568 char pretty_name[PCI_NAME_S <<
569 #endif 203 #endif
570 }; 204 };
571 205
>> 206 extern struct pci_dev *alloc_pci_dev(void);
>> 207
572 #define pci_dev_g(n) list_entry(n, struct pci_ 208 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
573 #define pci_dev_b(n) list_entry(n, struct pci_ 209 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
574 #define to_pci_dev(n) container_of(n, struct p 210 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
575 #define for_each_pci_dev(d) while ((d = pci_ge 211 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
576 212
>> 213 static inline int pci_channel_offline(struct pci_dev *pdev)
>> 214 {
>> 215 return (pdev->error_state != pci_channel_io_normal);
>> 216 }
>> 217
>> 218 static inline struct pci_cap_saved_state *pci_find_saved_cap(
>> 219 struct pci_dev *pci_dev, char cap)
>> 220 {
>> 221 struct pci_cap_saved_state *tmp;
>> 222 struct hlist_node *pos;
>> 223
>> 224 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
>> 225 if (tmp->cap_nr == cap)
>> 226 return tmp;
>> 227 }
>> 228 return NULL;
>> 229 }
>> 230
>> 231 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
>> 232 struct pci_cap_saved_state *new_cap)
>> 233 {
>> 234 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
>> 235 }
>> 236
577 /* 237 /*
578 * For PCI devices, the region numbers are as 238 * For PCI devices, the region numbers are assigned this way:
579 * 239 *
580 * 0-5 standard PCI regions 240 * 0-5 standard PCI regions
581 * 6 expansion ROM 241 * 6 expansion ROM
582 * 7-10 bridges: address space assigne 242 * 7-10 bridges: address space assigned to buses behind the bridge
583 */ 243 */
584 244
585 #define PCI_ROM_RESOURCE 6 !! 245 #define PCI_ROM_RESOURCE 6
586 #define PCI_BRIDGE_RESOURCES 7 !! 246 #define PCI_BRIDGE_RESOURCES 7
587 #define PCI_NUM_RESOURCES 11 !! 247 #define PCI_NUM_RESOURCES 11
588 248
589 #ifndef PCI_BUS_NUM_RESOURCES 249 #ifndef PCI_BUS_NUM_RESOURCES
590 #define PCI_BUS_NUM_RESOURCES 4 !! 250 #define PCI_BUS_NUM_RESOURCES 8
591 #endif 251 #endif
592 !! 252
593 #define PCI_REGION_FLAG_MASK 0x0fU /* The !! 253 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
594 254
595 struct pci_bus { 255 struct pci_bus {
596 struct list_head node; /* nod 256 struct list_head node; /* node in list of buses */
597 struct pci_bus *parent; /* par 257 struct pci_bus *parent; /* parent bus this bridge is on */
598 struct list_head children; /* lis 258 struct list_head children; /* list of child buses */
599 struct list_head devices; /* lis 259 struct list_head devices; /* list of devices on this bus */
600 struct pci_dev *self; /* bri 260 struct pci_dev *self; /* bridge device as seen by parent */
601 struct resource *resource[PCI_BUS_NUM_ 261 struct resource *resource[PCI_BUS_NUM_RESOURCES];
602 /* add 262 /* address space routed to this bus */
603 263
604 struct pci_ops *ops; /* con 264 struct pci_ops *ops; /* configuration access functions */
605 void *sysdata; /* hoo 265 void *sysdata; /* hook for sys-specific extension */
606 struct proc_dir_entry *procdir; /* dir 266 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
607 267
608 unsigned char number; /* bus 268 unsigned char number; /* bus number */
609 unsigned char primary; /* num 269 unsigned char primary; /* number of primary bridge */
610 unsigned char secondary; /* num 270 unsigned char secondary; /* number of secondary bridge */
611 unsigned char subordinate; /* max 271 unsigned char subordinate; /* max number of subordinate buses */
612 272
613 char name[48]; 273 char name[48];
614 274
615 unsigned short bridge_ctl; /* man 275 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
616 unsigned short pad2; !! 276 pci_bus_flags_t bus_flags; /* Inherited by child busses */
617 struct device *bridge; 277 struct device *bridge;
618 struct class_device class_dev; !! 278 struct device dev;
619 struct bin_attribute *legacy_io; /* 279 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
620 struct bin_attribute *legacy_mem; / 280 struct bin_attribute *legacy_mem; /* legacy mem */
>> 281 unsigned int is_added:1;
621 }; 282 };
622 283
623 #define pci_bus_b(n) list_entry(n, struct p 284 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
624 #define to_pci_bus(n) container_of(n, struct !! 285 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
625 286
626 /* 287 /*
627 * Error values that may be returned by PCI fu 288 * Error values that may be returned by PCI functions.
628 */ 289 */
629 #define PCIBIOS_SUCCESSFUL 0x00 290 #define PCIBIOS_SUCCESSFUL 0x00
630 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 291 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
631 #define PCIBIOS_BAD_VENDOR_ID 0x83 292 #define PCIBIOS_BAD_VENDOR_ID 0x83
632 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 293 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
633 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 294 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
634 #define PCIBIOS_SET_FAILED 0x88 295 #define PCIBIOS_SET_FAILED 0x88
635 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 296 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
636 297
637 /* Low-level architecture-dependent routines * 298 /* Low-level architecture-dependent routines */
638 299
639 struct pci_ops { 300 struct pci_ops {
640 int (*read)(struct pci_bus *bus, unsig 301 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
641 int (*write)(struct pci_bus *bus, unsi 302 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
642 }; 303 };
643 304
644 struct pci_raw_ops { !! 305 /*
645 int (*read)(int dom, int bus, int devf !! 306 * ACPI needs to be able to access PCI config space before we've done a
646 int (*write)(int dom, int bus, int dev !! 307 * PCI bus scan and created pci_bus structures.
647 }; !! 308 */
648 !! 309 extern int raw_pci_read(unsigned int domain, unsigned int bus,
649 extern struct pci_raw_ops *raw_pci_ops; !! 310 unsigned int devfn, int reg, int len, u32 *val);
>> 311 extern int raw_pci_write(unsigned int domain, unsigned int bus,
>> 312 unsigned int devfn, int reg, int len, u32 val);
650 313
651 struct pci_bus_region { 314 struct pci_bus_region {
652 unsigned long start; !! 315 resource_size_t start;
653 unsigned long end; !! 316 resource_size_t end;
654 }; 317 };
655 318
656 struct pci_dynids { 319 struct pci_dynids {
657 spinlock_t lock; /* protect 320 spinlock_t lock; /* protects list, index */
658 struct list_head list; /* for IDs 321 struct list_head list; /* for IDs added at runtime */
659 unsigned int use_driver_data:1; /* pci 322 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
660 }; 323 };
661 324
>> 325 /* ---------------------------------------------------------------- */
>> 326 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
>> 327 * a set of callbacks in struct pci_error_handlers, then that device driver
>> 328 * will be notified of PCI bus errors, and will be driven to recovery
>> 329 * when an error occurs.
>> 330 */
>> 331
>> 332 typedef unsigned int __bitwise pci_ers_result_t;
>> 333
>> 334 enum pci_ers_result {
>> 335 /* no result/none/not supported in device driver */
>> 336 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
>> 337
>> 338 /* Device driver can recover without slot reset */
>> 339 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
>> 340
>> 341 /* Device driver wants slot to be reset. */
>> 342 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
>> 343
>> 344 /* Device has completely failed, is unrecoverable */
>> 345 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
>> 346
>> 347 /* Device driver is fully recovered and operational */
>> 348 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
>> 349 };
>> 350
>> 351 /* PCI bus error event callbacks */
>> 352 struct pci_error_handlers {
>> 353 /* PCI bus error detected on this device */
>> 354 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
>> 355 enum pci_channel_state error);
>> 356
>> 357 /* MMIO has been re-enabled, but not DMA */
>> 358 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
>> 359
>> 360 /* PCI Express link has been reset */
>> 361 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
>> 362
>> 363 /* PCI slot has been reset */
>> 364 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
>> 365
>> 366 /* Device driver may resume normal operations */
>> 367 void (*resume)(struct pci_dev *dev);
>> 368 };
>> 369
>> 370 /* ---------------------------------------------------------------- */
>> 371
662 struct module; 372 struct module;
663 struct pci_driver { 373 struct pci_driver {
664 struct list_head node; 374 struct list_head node;
665 char *name; 375 char *name;
666 struct module *owner; <<
667 const struct pci_device_id *id_table; 376 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
668 int (*probe) (struct pci_dev *dev, c 377 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
669 void (*remove) (struct pci_dev *dev); 378 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
670 int (*suspend) (struct pci_dev *dev, 379 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
>> 380 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
>> 381 int (*resume_early) (struct pci_dev *dev);
671 int (*resume) (struct pci_dev *dev); 382 int (*resume) (struct pci_dev *dev); /* Device woken up */
672 int (*enable_wake) (struct pci_dev *d !! 383 void (*shutdown) (struct pci_dev *dev);
673 384
>> 385 struct pci_error_handlers *err_handler;
674 struct device_driver driver; 386 struct device_driver driver;
675 struct pci_dynids dynids; 387 struct pci_dynids dynids;
676 }; 388 };
677 389
678 #define to_pci_driver(drv) container_of(drv,st !! 390 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
>> 391
>> 392 /**
>> 393 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
>> 394 * @_table: device table name
>> 395 *
>> 396 * This macro is used to create a struct pci_device_id array (a device table)
>> 397 * in a generic manner.
>> 398 */
>> 399 #define DEFINE_PCI_DEVICE_TABLE(_table) \
>> 400 const struct pci_device_id _table[] __devinitconst
679 401
680 /** 402 /**
681 * PCI_DEVICE - macro used to describe a speci 403 * PCI_DEVICE - macro used to describe a specific pci device
682 * @vend: the 16 bit PCI Vendor ID 404 * @vend: the 16 bit PCI Vendor ID
683 * @dev: the 16 bit PCI Device ID 405 * @dev: the 16 bit PCI Device ID
684 * 406 *
685 * This macro is used to create a struct pci_d 407 * This macro is used to create a struct pci_device_id that matches a
686 * specific device. The subvendor and subdevi 408 * specific device. The subvendor and subdevice fields will be set to
687 * PCI_ANY_ID. 409 * PCI_ANY_ID.
688 */ 410 */
689 #define PCI_DEVICE(vend,dev) \ 411 #define PCI_DEVICE(vend,dev) \
690 .vendor = (vend), .device = (dev), \ 412 .vendor = (vend), .device = (dev), \
691 .subvendor = PCI_ANY_ID, .subdevice = 413 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
692 414
693 /** 415 /**
694 * PCI_DEVICE_CLASS - macro used to describe a 416 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
695 * @dev_class: the class, subclass, prog-if tr 417 * @dev_class: the class, subclass, prog-if triple for this device
696 * @dev_class_mask: the class mask for this de 418 * @dev_class_mask: the class mask for this device
697 * 419 *
698 * This macro is used to create a struct pci_d 420 * This macro is used to create a struct pci_device_id that matches a
699 * specific PCI class. The vendor, device, su !! 421 * specific PCI class. The vendor, device, subvendor, and subdevice
700 * fields will be set to PCI_ANY_ID. 422 * fields will be set to PCI_ANY_ID.
701 */ 423 */
702 #define PCI_DEVICE_CLASS(dev_class,dev_class_m 424 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
703 .class = (dev_class), .class_mask = (d 425 .class = (dev_class), .class_mask = (dev_class_mask), \
704 .vendor = PCI_ANY_ID, .device = PCI_AN 426 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
705 .subvendor = PCI_ANY_ID, .subdevice = 427 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
706 428
707 /* !! 429 /**
708 * pci_module_init is obsolete, this stays her !! 430 * PCI_VDEVICE - macro used to describe a specific pci device in short form
709 * in the tree. !! 431 * @vend: the vendor name
>> 432 * @dev: the 16 bit PCI Device ID
>> 433 *
>> 434 * This macro is used to create a struct pci_device_id that matches a
>> 435 * specific PCI device. The subvendor, and subdevice fields will be set
>> 436 * to PCI_ANY_ID. The macro allows the next field to follow as the device
>> 437 * private data.
710 */ 438 */
711 #define pci_module_init pci_register_driver !! 439
>> 440 #define PCI_VDEVICE(vendor, device) \
>> 441 PCI_VENDOR_ID_##vendor, (device), \
>> 442 PCI_ANY_ID, PCI_ANY_ID, 0, 0
712 443
713 /* these external functions are only available 444 /* these external functions are only available when PCI support is enabled */
714 #ifdef CONFIG_PCI 445 #ifdef CONFIG_PCI
715 446
716 extern struct bus_type pci_bus_type; 447 extern struct bus_type pci_bus_type;
717 448
718 /* Do NOT directly access these two variables, 449 /* Do NOT directly access these two variables, unless you are arch specific pci
719 * code, or pci core code. */ 450 * code, or pci core code. */
720 extern struct list_head pci_root_buses; /* lis 451 extern struct list_head pci_root_buses; /* list of all known PCI buses */
721 extern struct list_head pci_devices; /* lis 452 extern struct list_head pci_devices; /* list of all devices */
>> 453 /* Some device drivers need know if pci is initiated */
>> 454 extern int no_pci_devices(void);
722 455
723 void pcibios_fixup_bus(struct pci_bus *); 456 void pcibios_fixup_bus(struct pci_bus *);
724 int pcibios_enable_device(struct pci_dev *, in !! 457 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
725 char *pcibios_setup (char *str); !! 458 char *pcibios_setup(char *str);
726 459
727 /* Used only when drivers/pci/setup.c is used 460 /* Used only when drivers/pci/setup.c is used */
728 void pcibios_align_resource(void *, struct res !! 461 void pcibios_align_resource(void *, struct resource *, resource_size_t,
729 unsigned long, uns !! 462 resource_size_t);
730 void pcibios_update_irq(struct pci_dev *, int 463 void pcibios_update_irq(struct pci_dev *, int irq);
731 464
732 /* Generic PCI functions used internally */ 465 /* Generic PCI functions used internally */
733 466
734 extern struct pci_bus *pci_find_bus(int domain 467 extern struct pci_bus *pci_find_bus(int domain, int busnr);
735 struct pci_bus *pci_scan_bus_parented(struct d !! 468 void pci_bus_add_devices(struct pci_bus *bus);
736 static inline struct pci_bus *pci_scan_bus(int !! 469 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
>> 470 struct pci_ops *ops, void *sysdata);
>> 471 static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
>> 472 void *sysdata)
737 { 473 {
738 return pci_scan_bus_parented(NULL, bus !! 474 struct pci_bus *root_bus;
>> 475 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
>> 476 if (root_bus)
>> 477 pci_bus_add_devices(root_bus);
>> 478 return root_bus;
739 } 479 }
>> 480 struct pci_bus *pci_create_bus(struct device *parent, int bus,
>> 481 struct pci_ops *ops, void *sysdata);
>> 482 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
>> 483 int busnr);
740 int pci_scan_slot(struct pci_bus *bus, int dev 484 int pci_scan_slot(struct pci_bus *bus, int devfn);
741 struct pci_dev * pci_scan_single_device(struct !! 485 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
>> 486 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
742 unsigned int pci_scan_child_bus(struct pci_bus 487 unsigned int pci_scan_child_bus(struct pci_bus *bus);
743 void pci_bus_add_device(struct pci_dev *dev); !! 488 int __must_check pci_bus_add_device(struct pci_dev *dev);
744 void pci_bus_add_devices(struct pci_bus *bus); <<
745 void pci_name_device(struct pci_dev *dev); <<
746 char *pci_class_name(u32 class); <<
747 void pci_read_bridge_bases(struct pci_bus *chi 489 void pci_read_bridge_bases(struct pci_bus *child);
748 struct resource *pci_find_parent_resource(cons !! 490 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
>> 491 struct resource *res);
749 int pci_get_interrupt_pin(struct pci_dev *dev, 492 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
750 extern struct pci_dev *pci_dev_get(struct pci_ 493 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
751 extern void pci_dev_put(struct pci_dev *dev); 494 extern void pci_dev_put(struct pci_dev *dev);
752 extern void pci_remove_bus(struct pci_bus *b); 495 extern void pci_remove_bus(struct pci_bus *b);
753 extern void pci_remove_bus_device(struct pci_d 496 extern void pci_remove_bus_device(struct pci_dev *dev);
>> 497 extern void pci_stop_bus_device(struct pci_dev *dev);
>> 498 void pci_setup_cardbus(struct pci_bus *bus);
>> 499 extern void pci_sort_breadthfirst(void);
754 500
755 /* Generic PCI functions exported to card driv 501 /* Generic PCI functions exported to card drivers */
756 502
757 struct pci_dev *pci_find_device (unsigned int !! 503 #ifdef CONFIG_PCI_LEGACY
758 struct pci_dev *pci_find_device_reverse (unsig !! 504 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
759 struct pci_dev *pci_find_slot (unsigned int bu !! 505 unsigned int device,
760 int pci_find_capability (struct pci_dev *dev, !! 506 const struct pci_dev *from);
761 int pci_find_ext_capability (struct pci_dev *d !! 507 struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
762 struct pci_bus * pci_find_next_bus(const struc !! 508 unsigned int devfn);
>> 509 #endif /* CONFIG_PCI_LEGACY */
>> 510
>> 511 int pci_find_capability(struct pci_dev *dev, int cap);
>> 512 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
>> 513 int pci_find_ext_capability(struct pci_dev *dev, int cap);
>> 514 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
>> 515 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
>> 516 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
763 517
764 struct pci_dev *pci_get_device (unsigned int v !! 518 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
765 struct pci_dev *pci_get_subsys (unsigned int v !! 519 struct pci_dev *from);
>> 520 struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
>> 521 struct pci_dev *from);
>> 522
>> 523 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
766 unsigned int s 524 unsigned int ss_vendor, unsigned int ss_device,
767 struct pci_dev 525 struct pci_dev *from);
768 struct pci_dev *pci_get_slot (struct pci_bus * !! 526 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
769 struct pci_dev *pci_get_class (unsigned int cl !! 527 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
>> 528 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
770 int pci_dev_present(const struct pci_device_id 529 int pci_dev_present(const struct pci_device_id *ids);
>> 530 const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
771 531
772 int pci_bus_read_config_byte (struct pci_bus * !! 532 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
773 int pci_bus_read_config_word (struct pci_bus * !! 533 int where, u8 *val);
774 int pci_bus_read_config_dword (struct pci_bus !! 534 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
775 int pci_bus_write_config_byte (struct pci_bus !! 535 int where, u16 *val);
776 int pci_bus_write_config_word (struct pci_bus !! 536 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
777 int pci_bus_write_config_dword (struct pci_bus !! 537 int where, u32 *val);
>> 538 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
>> 539 int where, u8 val);
>> 540 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
>> 541 int where, u16 val);
>> 542 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
>> 543 int where, u32 val);
778 544
779 static inline int pci_read_config_byte(struct 545 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
780 { 546 {
781 return pci_bus_read_config_byte (dev-> !! 547 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
782 } 548 }
783 static inline int pci_read_config_word(struct 549 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
784 { 550 {
785 return pci_bus_read_config_word (dev-> !! 551 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
786 } 552 }
787 static inline int pci_read_config_dword(struct !! 553 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
>> 554 u32 *val)
788 { 555 {
789 return pci_bus_read_config_dword (dev- !! 556 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
790 } 557 }
791 static inline int pci_write_config_byte(struct 558 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
792 { 559 {
793 return pci_bus_write_config_byte (dev- !! 560 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
794 } 561 }
795 static inline int pci_write_config_word(struct 562 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
796 { 563 {
797 return pci_bus_write_config_word (dev- !! 564 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
>> 565 }
>> 566 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
>> 567 u32 val)
>> 568 {
>> 569 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
798 } 570 }
799 static inline int pci_write_config_dword(struc !! 571
>> 572 int __must_check pci_enable_device(struct pci_dev *dev);
>> 573 int __must_check pci_enable_device_io(struct pci_dev *dev);
>> 574 int __must_check pci_enable_device_mem(struct pci_dev *dev);
>> 575 int __must_check pci_reenable_device(struct pci_dev *);
>> 576 int __must_check pcim_enable_device(struct pci_dev *pdev);
>> 577 void pcim_pin_device(struct pci_dev *pdev);
>> 578
>> 579 static inline int pci_is_managed(struct pci_dev *pdev)
800 { 580 {
801 return pci_bus_write_config_dword (dev !! 581 return pdev->is_managed;
802 } 582 }
803 583
804 int pci_enable_device(struct pci_dev *dev); <<
805 int pci_enable_device_bars(struct pci_dev *dev <<
806 void pci_disable_device(struct pci_dev *dev); 584 void pci_disable_device(struct pci_dev *dev);
807 void pci_set_master(struct pci_dev *dev); 585 void pci_set_master(struct pci_dev *dev);
>> 586 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
808 #define HAVE_PCI_SET_MWI 587 #define HAVE_PCI_SET_MWI
809 int pci_set_mwi(struct pci_dev *dev); !! 588 int __must_check pci_set_mwi(struct pci_dev *dev);
>> 589 int pci_try_set_mwi(struct pci_dev *dev);
810 void pci_clear_mwi(struct pci_dev *dev); 590 void pci_clear_mwi(struct pci_dev *dev);
>> 591 void pci_intx(struct pci_dev *dev, int enable);
>> 592 void pci_msi_off(struct pci_dev *dev);
811 int pci_set_dma_mask(struct pci_dev *dev, u64 593 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
812 int pci_dac_set_dma_mask(struct pci_dev *dev, <<
813 int pci_set_consistent_dma_mask(struct pci_dev 594 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
814 int pci_assign_resource(struct pci_dev *dev, i !! 595 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
>> 596 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
>> 597 int pcix_get_max_mmrbc(struct pci_dev *dev);
>> 598 int pcix_get_mmrbc(struct pci_dev *dev);
>> 599 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
>> 600 int pcie_get_readrq(struct pci_dev *dev);
>> 601 int pcie_set_readrq(struct pci_dev *dev, int rq);
>> 602 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
>> 603 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
>> 604 int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
>> 605 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
815 606
816 /* ROM control related routines */ 607 /* ROM control related routines */
817 void __iomem *pci_map_rom(struct pci_dev *pdev !! 608 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
818 void __iomem *pci_map_rom_copy(struct pci_dev <<
819 void pci_unmap_rom(struct pci_dev *pdev, void 609 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
820 void pci_remove_rom(struct pci_dev *pdev); !! 610 size_t pci_get_rom_size(void __iomem *rom, size_t size);
821 611
822 /* Power management related routines */ 612 /* Power management related routines */
823 int pci_save_state(struct pci_dev *dev); 613 int pci_save_state(struct pci_dev *dev);
824 int pci_restore_state(struct pci_dev *dev); 614 int pci_restore_state(struct pci_dev *dev);
825 int pci_set_power_state(struct pci_dev *dev, p 615 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
826 pci_power_t pci_choose_state(struct pci_dev *d 616 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
827 int pci_enable_wake(struct pci_dev *dev, pci_p 617 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
828 618
>> 619 /* Functions for PCI Hotplug drivers to use */
>> 620 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
>> 621
829 /* Helper functions for low-level code (driver 622 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
830 void pci_bus_assign_resources(struct pci_bus * 623 void pci_bus_assign_resources(struct pci_bus *bus);
831 void pci_bus_size_bridges(struct pci_bus *bus) 624 void pci_bus_size_bridges(struct pci_bus *bus);
832 int pci_claim_resource(struct pci_dev *, int); 625 int pci_claim_resource(struct pci_dev *, int);
833 void pci_assign_unassigned_resources(void); 626 void pci_assign_unassigned_resources(void);
834 void pdev_enable_device(struct pci_dev *); 627 void pdev_enable_device(struct pci_dev *);
835 void pdev_sort_resources(struct pci_dev *, str 628 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
836 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u 629 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
837 int (*)(struct pci_dev *, 630 int (*)(struct pci_dev *, u8, u8));
838 #define HAVE_PCI_REQ_REGIONS 2 631 #define HAVE_PCI_REQ_REGIONS 2
839 int pci_request_regions(struct pci_dev *, char !! 632 int __must_check pci_request_regions(struct pci_dev *, const char *);
840 void pci_release_regions(struct pci_dev *); 633 void pci_release_regions(struct pci_dev *);
841 int pci_request_region(struct pci_dev *, int, !! 634 int __must_check pci_request_region(struct pci_dev *, int, const char *);
842 void pci_release_region(struct pci_dev *, int) 635 void pci_release_region(struct pci_dev *, int);
>> 636 int pci_request_selected_regions(struct pci_dev *, int, const char *);
>> 637 void pci_release_selected_regions(struct pci_dev *, int);
843 638
844 /* drivers/pci/bus.c */ 639 /* drivers/pci/bus.c */
845 int pci_bus_alloc_resource(struct pci_bus *bus !! 640 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
846 unsigned long size, !! 641 struct resource *res, resource_size_t size,
847 unsigned long min, !! 642 resource_size_t align, resource_size_t min,
848 void (*alignf)(void !! 643 unsigned int type_mask,
849 unsi !! 644 void (*alignf)(void *, struct resource *,
850 void *alignf_data); !! 645 resource_size_t, resource_size_t),
>> 646 void *alignf_data);
851 void pci_enable_bridges(struct pci_bus *bus); 647 void pci_enable_bridges(struct pci_bus *bus);
852 648
853 /* New-style probing supporting hot-pluggable !! 649 /* Proper probing supporting hot-pluggable devices */
854 int pci_register_driver(struct pci_driver *); !! 650 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
855 void pci_unregister_driver(struct pci_driver * !! 651 const char *mod_name);
856 void pci_remove_behind_bridge(struct pci_dev * !! 652 static inline int __must_check pci_register_driver(struct pci_driver *driver)
857 struct pci_driver *pci_dev_driver(const struct !! 653 {
858 const struct pci_device_id *pci_match_device(c !! 654 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
859 int pci_scan_bridge(struct pci_bus *bus, struc !! 655 }
>> 656
>> 657 void pci_unregister_driver(struct pci_driver *dev);
>> 658 void pci_remove_behind_bridge(struct pci_dev *dev);
>> 659 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
>> 660 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
>> 661 struct pci_dev *dev);
>> 662 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
>> 663 int pass);
>> 664
>> 665 void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
>> 666 void *userdata);
>> 667 int pci_cfg_space_size(struct pci_dev *dev);
>> 668 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
860 669
861 /* kmem_cache style wrapper around pci_alloc_c 670 /* kmem_cache style wrapper around pci_alloc_consistent() */
862 671
863 #include <linux/dmapool.h> 672 #include <linux/dmapool.h>
864 673
865 #define pci_pool dma_pool 674 #define pci_pool dma_pool
866 #define pci_pool_create(name, pdev, size, alig 675 #define pci_pool_create(name, pdev, size, align, allocation) \
867 dma_pool_create(name, &pdev->d 676 dma_pool_create(name, &pdev->dev, size, align, allocation)
868 #define pci_pool_destroy(pool) dma_pool_destro 677 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
869 #define pci_pool_alloc(pool, flags, handle) dm 678 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
870 #define pci_pool_free(pool, vaddr, addr) dma_p 679 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
871 680
872 #if defined(CONFIG_ISA) || defined(CONFIG_EISA !! 681 enum pci_dma_burst_strategy {
873 extern struct pci_dev *isa_bridge; !! 682 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
874 #endif !! 683 strategy_parameter is N/A */
>> 684 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
>> 685 byte boundaries */
>> 686 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
>> 687 strategy_parameter byte boundaries */
>> 688 };
875 689
876 struct msix_entry { 690 struct msix_entry {
877 u16 vector; /* kernel uses to writ 691 u16 vector; /* kernel uses to write allocated vector */
878 u16 entry; /* driver uses to spec 692 u16 entry; /* driver uses to specify entry, OS writes */
879 }; 693 };
880 694
>> 695
881 #ifndef CONFIG_PCI_MSI 696 #ifndef CONFIG_PCI_MSI
882 static inline void pci_scan_msi_device(struct !! 697 static inline int pci_enable_msi(struct pci_dev *dev)
883 static inline int pci_enable_msi(struct pci_de !! 698 {
884 static inline void pci_disable_msi(struct pci_ !! 699 return -1;
885 static inline int pci_enable_msix(struct pci_d !! 700 }
886 struct msix_entry *entries, int nvec) !! 701
887 static inline void pci_disable_msix(struct pci !! 702 static inline void pci_disable_msi(struct pci_dev *dev)
888 static inline void msi_remove_pci_irq_vectors( !! 703 { }
>> 704
>> 705 static inline int pci_enable_msix(struct pci_dev *dev,
>> 706 struct msix_entry *entries, int nvec)
>> 707 {
>> 708 return -1;
>> 709 }
>> 710
>> 711 static inline void pci_disable_msix(struct pci_dev *dev)
>> 712 { }
>> 713
>> 714 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
>> 715 { }
>> 716
>> 717 static inline void pci_restore_msi_state(struct pci_dev *dev)
>> 718 { }
889 #else 719 #else
890 extern void pci_scan_msi_device(struct pci_dev <<
891 extern int pci_enable_msi(struct pci_dev *dev) 720 extern int pci_enable_msi(struct pci_dev *dev);
892 extern void pci_disable_msi(struct pci_dev *de 721 extern void pci_disable_msi(struct pci_dev *dev);
893 extern int pci_enable_msix(struct pci_dev* dev !! 722 extern int pci_enable_msix(struct pci_dev *dev,
894 struct msix_entry *entries, int nvec); 723 struct msix_entry *entries, int nvec);
895 extern void pci_disable_msix(struct pci_dev *d 724 extern void pci_disable_msix(struct pci_dev *dev);
896 extern void msi_remove_pci_irq_vectors(struct 725 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
>> 726 extern void pci_restore_msi_state(struct pci_dev *dev);
897 #endif 727 #endif
898 728
899 #endif /* CONFIG_PCI */ !! 729 #ifdef CONFIG_HT_IRQ
>> 730 /* The functions a driver should call */
>> 731 int ht_create_irq(struct pci_dev *dev, int idx);
>> 732 void ht_destroy_irq(unsigned int irq);
>> 733 #endif /* CONFIG_HT_IRQ */
900 734
901 /* Include architecture-dependent settings and !! 735 extern void pci_block_user_cfg_access(struct pci_dev *dev);
>> 736 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
902 737
903 #include <asm/pci.h> !! 738 /*
>> 739 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
>> 740 * a PCI domain is defined to be a set of PCI busses which share
>> 741 * configuration space.
>> 742 */
>> 743 #ifdef CONFIG_PCI_DOMAINS
>> 744 extern int pci_domains_supported;
>> 745 #else
>> 746 enum { pci_domains_supported = 0 };
>> 747 static inline int pci_domain_nr(struct pci_bus *bus)
>> 748 {
>> 749 return 0;
>> 750 }
>> 751
>> 752 static inline int pci_proc_domain(struct pci_bus *bus)
>> 753 {
>> 754 return 0;
>> 755 }
>> 756 #endif /* CONFIG_PCI_DOMAINS */
>> 757
>> 758 #else /* CONFIG_PCI is not enabled */
904 759
905 /* 760 /*
906 * If the system does not have PCI, clearly t 761 * If the system does not have PCI, clearly these return errors. Define
907 * these as simple inline functions to avoid 762 * these as simple inline functions to avoid hair in drivers.
908 */ 763 */
909 764
910 #ifndef CONFIG_PCI !! 765 #define _PCI_NOP(o, s, t) \
911 #define _PCI_NOP(o,s,t) \ !! 766 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
912 static inline int pci_##o##_config_##s !! 767 int where, t val) \
913 { return PCIBIOS_FUNC_NOT_SUPP 768 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
914 #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byt !! 769
915 _PCI_NOP(o,wor !! 770 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
916 _PCI_NOP(o,dwo !! 771 _PCI_NOP(o, word, u16 x) \
>> 772 _PCI_NOP(o, dword, u32 x)
917 _PCI_NOP_ALL(read, *) 773 _PCI_NOP_ALL(read, *)
918 _PCI_NOP_ALL(write,) 774 _PCI_NOP_ALL(write,)
919 775
920 static inline struct pci_dev *pci_find_device( !! 776 static inline struct pci_dev *pci_find_device(unsigned int vendor,
921 { return NULL; } !! 777 unsigned int device,
>> 778 const struct pci_dev *from)
>> 779 {
>> 780 return NULL;
>> 781 }
922 782
923 static inline struct pci_dev *pci_find_slot(un !! 783 static inline struct pci_dev *pci_find_slot(unsigned int bus,
924 { return NULL; } !! 784 unsigned int devfn)
>> 785 {
>> 786 return NULL;
>> 787 }
925 788
926 static inline struct pci_dev *pci_get_device ( !! 789 static inline struct pci_dev *pci_get_device(unsigned int vendor,
927 { return NULL; } !! 790 unsigned int device,
>> 791 struct pci_dev *from)
>> 792 {
>> 793 return NULL;
>> 794 }
928 795
929 static inline struct pci_dev *pci_get_subsys ( !! 796 static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
930 unsigned int ss_vendor, unsigned int ss_device !! 797 unsigned int device,
931 { return NULL; } !! 798 struct pci_dev *from)
>> 799 {
>> 800 return NULL;
>> 801 }
932 802
933 static inline struct pci_dev *pci_get_class(un !! 803 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
934 { return NULL; } !! 804 unsigned int device,
>> 805 unsigned int ss_vendor,
>> 806 unsigned int ss_device,
>> 807 struct pci_dev *from)
>> 808 {
>> 809 return NULL;
>> 810 }
>> 811
>> 812 static inline struct pci_dev *pci_get_class(unsigned int class,
>> 813 struct pci_dev *from)
>> 814 {
>> 815 return NULL;
>> 816 }
935 817
936 #define pci_dev_present(ids) (0) 818 #define pci_dev_present(ids) (0)
>> 819 #define no_pci_devices() (1)
>> 820 #define pci_find_present(ids) (NULL)
937 #define pci_dev_put(dev) do { } while ( 821 #define pci_dev_put(dev) do { } while (0)
938 822
939 static inline void pci_set_master(struct pci_d !! 823 static inline void pci_set_master(struct pci_dev *dev)
940 static inline int pci_enable_device(struct pci !! 824 { }
941 static inline void pci_disable_device(struct p !! 825
942 static inline int pci_set_dma_mask(struct pci_ !! 826 static inline int pci_enable_device(struct pci_dev *dev)
943 static inline int pci_dac_set_dma_mask(struct !! 827 {
944 static inline int pci_assign_resource(struct p !! 828 return -EIO;
945 static inline int pci_register_driver(struct p !! 829 }
946 static inline void pci_unregister_driver(struc !! 830
947 static inline int pci_find_capability (struct !! 831 static inline void pci_disable_device(struct pci_dev *dev)
948 static inline int pci_find_ext_capability (str !! 832 { }
949 static inline const struct pci_device_id *pci_ !! 833
>> 834 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
>> 835 {
>> 836 return -EIO;
>> 837 }
>> 838
>> 839 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
>> 840 unsigned int size)
>> 841 {
>> 842 return -EIO;
>> 843 }
>> 844
>> 845 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
>> 846 unsigned long mask)
>> 847 {
>> 848 return -EIO;
>> 849 }
>> 850
>> 851 static inline int pci_assign_resource(struct pci_dev *dev, int i)
>> 852 {
>> 853 return -EBUSY;
>> 854 }
>> 855
>> 856 static inline int __pci_register_driver(struct pci_driver *drv,
>> 857 struct module *owner)
>> 858 {
>> 859 return 0;
>> 860 }
>> 861
>> 862 static inline int pci_register_driver(struct pci_driver *drv)
>> 863 {
>> 864 return 0;
>> 865 }
>> 866
>> 867 static inline void pci_unregister_driver(struct pci_driver *drv)
>> 868 { }
>> 869
>> 870 static inline int pci_find_capability(struct pci_dev *dev, int cap)
>> 871 {
>> 872 return 0;
>> 873 }
>> 874
>> 875 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
>> 876 int cap)
>> 877 {
>> 878 return 0;
>> 879 }
>> 880
>> 881 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
>> 882 {
>> 883 return 0;
>> 884 }
950 885
951 /* Power management related routines */ 886 /* Power management related routines */
952 static inline int pci_save_state(struct pci_de !! 887 static inline int pci_save_state(struct pci_dev *dev)
953 static inline int pci_restore_state(struct pci !! 888 {
954 static inline int pci_set_power_state(struct p !! 889 return 0;
955 static inline pci_power_t pci_choose_state(str !! 890 }
956 static inline int pci_enable_wake(struct pci_d !! 891
>> 892 static inline int pci_restore_state(struct pci_dev *dev)
>> 893 {
>> 894 return 0;
>> 895 }
957 896
958 #define isa_bridge ((struct pci_dev *)NUL !! 897 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
>> 898 {
>> 899 return 0;
>> 900 }
959 901
960 #else !! 902 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
>> 903 pm_message_t state)
>> 904 {
>> 905 return PCI_D0;
>> 906 }
961 907
962 /* !! 908 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
963 * PCI domain support. Sometimes called PCI s !! 909 int enable)
964 * a PCI domain is defined to be a set of PCI <<
965 * configuration space. <<
966 */ <<
967 #ifndef CONFIG_PCI_DOMAINS <<
968 static inline int pci_domain_nr(struct pci_bus <<
969 static inline int pci_name_bus(char *name, str <<
970 { 910 {
971 sprintf(name, "%02x", bus->number); <<
972 return 0; 911 return 0;
973 } 912 }
974 #endif <<
975 913
976 #endif /* !CONFIG_PCI */ !! 914 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
>> 915 {
>> 916 return -EIO;
>> 917 }
>> 918
>> 919 static inline void pci_release_regions(struct pci_dev *dev)
>> 920 { }
>> 921
>> 922 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
>> 923
>> 924 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
>> 925 { }
>> 926
>> 927 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
>> 928 { }
>> 929
>> 930 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
>> 931 { return NULL; }
>> 932
>> 933 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
>> 934 unsigned int devfn)
>> 935 { return NULL; }
>> 936
>> 937 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
>> 938 unsigned int devfn)
>> 939 { return NULL; }
>> 940
>> 941 #endif /* CONFIG_PCI */
>> 942
>> 943 /* Include architecture-dependent settings and functions */
>> 944
>> 945 #include <asm/pci.h>
977 946
978 /* these helpers provide future and backwards 947 /* these helpers provide future and backwards compatibility
979 * for accessing popular PCI BAR info */ 948 * for accessing popular PCI BAR info */
980 #define pci_resource_start(dev,bar) ((dev)-> !! 949 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
981 #define pci_resource_end(dev,bar) ((dev)-> !! 950 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
982 #define pci_resource_flags(dev,bar) ((dev)-> !! 951 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
983 #define pci_resource_len(dev,bar) \ 952 #define pci_resource_len(dev,bar) \
984 ((pci_resource_start((dev),(bar)) == 0 !! 953 ((pci_resource_start((dev), (bar)) == 0 && \
985 pci_resource_end((dev),(bar)) == !! 954 pci_resource_end((dev), (bar)) == \
986 pci_resource_start((dev),(bar))) ? 0 !! 955 pci_resource_start((dev), (bar))) ? 0 : \
987 !! 956 \
988 (pci_resource_end((dev),(bar)) - !! 957 (pci_resource_end((dev), (bar)) - \
989 pci_resource_start((dev),(bar)) + 1) !! 958 pci_resource_start((dev), (bar)) + 1))
990 959
991 /* Similar to the helpers above, these manipul 960 /* Similar to the helpers above, these manipulate per-pci_dev
992 * driver-specific data. They are really just 961 * driver-specific data. They are really just a wrapper around
993 * the generic device structure functions of t 962 * the generic device structure functions of these calls.
994 */ 963 */
995 static inline void *pci_get_drvdata (struct pc !! 964 static inline void *pci_get_drvdata(struct pci_dev *pdev)
996 { 965 {
997 return dev_get_drvdata(&pdev->dev); 966 return dev_get_drvdata(&pdev->dev);
998 } 967 }
999 968
1000 static inline void pci_set_drvdata (struct pc !! 969 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1001 { 970 {
1002 dev_set_drvdata(&pdev->dev, data); 971 dev_set_drvdata(&pdev->dev, data);
1003 } 972 }
1004 973
1005 /* If you want to know what to call your pci_ 974 /* If you want to know what to call your pci_dev, ask this function.
1006 * Again, it's a wrapper around the generic d 975 * Again, it's a wrapper around the generic device.
1007 */ 976 */
1008 static inline char *pci_name(struct pci_dev * 977 static inline char *pci_name(struct pci_dev *pdev)
1009 { 978 {
1010 return pdev->dev.bus_id; 979 return pdev->dev.bus_id;
1011 } 980 }
1012 981
1013 /* Some archs want to see the pretty pci name !! 982
1014 #ifdef CONFIG_PCI_NAMES !! 983 /* Some archs don't want to expose struct resource to userland as-is
1015 #define pci_pretty_name(dev) ((dev)->pretty_n !! 984 * in sysfs and /proc
1016 #else !! 985 */
1017 #define pci_pretty_name(dev) "" !! 986 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1018 #endif !! 987 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
>> 988 const struct resource *rsrc, resource_size_t *start,
>> 989 resource_size_t *end)
>> 990 {
>> 991 *start = rsrc->start;
>> 992 *end = rsrc->end;
>> 993 }
>> 994 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
>> 995
1019 996
1020 /* 997 /*
1021 * The world is not perfect and supplies us 998 * The world is not perfect and supplies us with broken PCI devices.
1022 * For at least a part of these bugs we need 999 * For at least a part of these bugs we need a work-around, so both
1023 * generic (drivers/pci/quirks.c) and per-ar 1000 * generic (drivers/pci/quirks.c) and per-architecture code can define
1024 * fixup hooks to be called for particular b 1001 * fixup hooks to be called for particular buggy devices.
1025 */ 1002 */
1026 1003
1027 struct pci_fixup { 1004 struct pci_fixup {
1028 u16 vendor, device; /* You can us 1005 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1029 void (*hook)(struct pci_dev *dev); 1006 void (*hook)(struct pci_dev *dev);
1030 }; 1007 };
1031 1008
1032 enum pci_fixup_pass { 1009 enum pci_fixup_pass {
1033 pci_fixup_early, /* Before pro 1010 pci_fixup_early, /* Before probing BARs */
1034 pci_fixup_header, /* After read 1011 pci_fixup_header, /* After reading configuration header */
1035 pci_fixup_final, /* Final phas 1012 pci_fixup_final, /* Final phase of device fixups */
1036 pci_fixup_enable, /* pci_enable 1013 pci_fixup_enable, /* pci_enable_device() time */
>> 1014 pci_fixup_resume, /* pci_enable_device() time */
1037 }; 1015 };
1038 1016
1039 /* Anonymous variables would be nice... */ 1017 /* Anonymous variables would be nice... */
1040 #define DECLARE_PCI_FIXUP_SECTION(section, na 1018 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1041 static struct pci_fixup __pci_fixup_# !! 1019 static const struct pci_fixup __pci_fixup_##name __used \
1042 __attribute__((__section__(#section)) 1020 __attribute__((__section__(#section))) = { vendor, device, hook };
1043 #define DECLARE_PCI_FIXUP_EARLY(vendor, devic 1021 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1044 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_ 1022 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1045 vendor##device##hook, 1023 vendor##device##hook, vendor, device, hook)
1046 #define DECLARE_PCI_FIXUP_HEADER(vendor, devi 1024 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1047 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_ 1025 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1048 vendor##device##hook, 1026 vendor##device##hook, vendor, device, hook)
1049 #define DECLARE_PCI_FIXUP_FINAL(vendor, devic 1027 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1050 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_ 1028 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1051 vendor##device##hook, 1029 vendor##device##hook, vendor, device, hook)
1052 #define DECLARE_PCI_FIXUP_ENABLE(vendor, devi 1030 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_ 1031 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1054 vendor##device##hook, 1032 vendor##device##hook, vendor, device, hook)
>> 1033 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
>> 1034 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
>> 1035 resume##vendor##device##hook, vendor, device, hook)
1055 1036
1056 1037
1057 void pci_fixup_device(enum pci_fixup_pass pas 1038 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1058 1039
>> 1040 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
>> 1041 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
>> 1042 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
>> 1043 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
>> 1044 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
>> 1045 const char *name);
>> 1046 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
>> 1047
1059 extern int pci_pci_problems; 1048 extern int pci_pci_problems;
1060 #define PCIPCI_FAIL 1 !! 1049 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1061 #define PCIPCI_TRITON 2 1050 #define PCIPCI_TRITON 2
1062 #define PCIPCI_NATOMA 4 1051 #define PCIPCI_NATOMA 4
1063 #define PCIPCI_VIAETBF 8 1052 #define PCIPCI_VIAETBF 8
1064 #define PCIPCI_VSFX 16 1053 #define PCIPCI_VSFX 16
1065 #define PCIPCI_ALIMAGIK 32 !! 1054 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
>> 1055 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
>> 1056
>> 1057 extern unsigned long pci_cardbus_io_size;
>> 1058 extern unsigned long pci_cardbus_mem_size;
>> 1059
>> 1060 extern int pcibios_add_platform_entries(struct pci_dev *dev);
1066 1061
1067 #endif /* __KERNEL__ */ 1062 #endif /* __KERNEL__ */
1068 #endif /* LINUX_PCI_H */ 1063 #endif /* LINUX_PCI_H */
1069 1064
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