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1 /* 1 /*
2 * 2 *
3 * Hardware accelerated Matrox Millennium I, I 3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
4 * 4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.c 5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 * 6 *
7 */ 7 */
8 #ifndef __MATROXFB_H__ 8 #ifndef __MATROXFB_H__
9 #define __MATROXFB_H__ 9 #define __MATROXFB_H__
10 10
11 /* general, but fairly heavy, debugging */ 11 /* general, but fairly heavy, debugging */
12 #undef MATROXFB_DEBUG 12 #undef MATROXFB_DEBUG
13 13
14 /* heavy debugging: */ 14 /* heavy debugging: */
15 /* -- logs putc[s], so everytime a char is dis 15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
16 #undef MATROXFB_DEBUG_HEAVY 16 #undef MATROXFB_DEBUG_HEAVY
17 17
18 /* This one _could_ cause infinite loops */ 18 /* This one _could_ cause infinite loops */
19 /* It _does_ cause lots and lots of messages d 19 /* It _does_ cause lots and lots of messages during idle loops */
20 #undef MATROXFB_DEBUG_LOOP 20 #undef MATROXFB_DEBUG_LOOP
21 21
22 /* Debug register calls, too? */ 22 /* Debug register calls, too? */
23 #undef MATROXFB_DEBUG_REG 23 #undef MATROXFB_DEBUG_REG
24 24
25 /* Guard accelerator accesses with spin_lock_i 25 /* Guard accelerator accesses with spin_lock_irqsave... */
26 #undef MATROXFB_USE_SPINLOCKS 26 #undef MATROXFB_USE_SPINLOCKS
27 27
28 #include <linux/config.h> <<
29 #include <linux/module.h> 28 #include <linux/module.h>
30 #include <linux/kernel.h> 29 #include <linux/kernel.h>
31 #include <linux/errno.h> 30 #include <linux/errno.h>
32 #include <linux/string.h> 31 #include <linux/string.h>
33 #include <linux/mm.h> 32 #include <linux/mm.h>
34 #include <linux/tty.h> <<
35 #include <linux/slab.h> 33 #include <linux/slab.h>
36 #include <linux/delay.h> 34 #include <linux/delay.h>
37 #include <linux/fb.h> 35 #include <linux/fb.h>
38 #include <linux/console.h> 36 #include <linux/console.h>
39 #include <linux/selection.h> 37 #include <linux/selection.h>
40 #include <linux/ioport.h> 38 #include <linux/ioport.h>
41 #include <linux/init.h> 39 #include <linux/init.h>
42 #include <linux/timer.h> 40 #include <linux/timer.h>
43 #include <linux/pci.h> 41 #include <linux/pci.h>
44 #include <linux/spinlock.h> 42 #include <linux/spinlock.h>
45 #include <linux/kd.h> 43 #include <linux/kd.h>
46 44
47 #include <asm/io.h> 45 #include <asm/io.h>
48 #include <asm/unaligned.h> 46 #include <asm/unaligned.h>
49 #ifdef CONFIG_MTRR 47 #ifdef CONFIG_MTRR
50 #include <asm/mtrr.h> 48 #include <asm/mtrr.h>
51 #endif 49 #endif
52 50
53 #include "../console/fbcon.h" <<
54 <<
55 #if defined(CONFIG_PPC_PMAC) 51 #if defined(CONFIG_PPC_PMAC)
56 #include <asm/prom.h> 52 #include <asm/prom.h>
57 #include <asm/pci-bridge.h> 53 #include <asm/pci-bridge.h>
58 #include "../macmodes.h" 54 #include "../macmodes.h"
59 #endif 55 #endif
60 56
61 /* always compile support for 32MB... It cost 57 /* always compile support for 32MB... It cost almost nothing */
62 #define CONFIG_FB_MATROX_32MB 58 #define CONFIG_FB_MATROX_32MB
63 59
64 #ifdef MATROXFB_DEBUG 60 #ifdef MATROXFB_DEBUG
65 61
66 #define DEBUG 62 #define DEBUG
67 #define DBG(x) printk(KERN_DEBUG "mat 63 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
68 64
69 #ifdef MATROXFB_DEBUG_HEAVY 65 #ifdef MATROXFB_DEBUG_HEAVY
70 #define DBG_HEAVY(x) DBG(x) 66 #define DBG_HEAVY(x) DBG(x)
71 #else /* MATROXFB_DEBUG_HEAVY */ 67 #else /* MATROXFB_DEBUG_HEAVY */
72 #define DBG_HEAVY(x) /* DBG_HEAVY */ 68 #define DBG_HEAVY(x) /* DBG_HEAVY */
73 #endif /* MATROXFB_DEBUG_HEAVY */ 69 #endif /* MATROXFB_DEBUG_HEAVY */
74 70
75 #ifdef MATROXFB_DEBUG_LOOP 71 #ifdef MATROXFB_DEBUG_LOOP
76 #define DBG_LOOP(x) DBG(x) 72 #define DBG_LOOP(x) DBG(x)
77 #else /* MATROXFB_DEBUG_LOOP */ 73 #else /* MATROXFB_DEBUG_LOOP */
78 #define DBG_LOOP(x) /* DBG_LOOP */ 74 #define DBG_LOOP(x) /* DBG_LOOP */
79 #endif /* MATROXFB_DEBUG_LOOP */ 75 #endif /* MATROXFB_DEBUG_LOOP */
80 76
81 #ifdef MATROXFB_DEBUG_REG 77 #ifdef MATROXFB_DEBUG_REG
82 #define DBG_REG(x) DBG(x) 78 #define DBG_REG(x) DBG(x)
83 #else /* MATROXFB_DEBUG_REG */ 79 #else /* MATROXFB_DEBUG_REG */
84 #define DBG_REG(x) /* DBG_REG */ 80 #define DBG_REG(x) /* DBG_REG */
85 #endif /* MATROXFB_DEBUG_REG */ 81 #endif /* MATROXFB_DEBUG_REG */
86 82
87 #else /* MATROXFB_DEBUG */ 83 #else /* MATROXFB_DEBUG */
88 84
89 #define DBG(x) /* DBG */ 85 #define DBG(x) /* DBG */
90 #define DBG_HEAVY(x) /* DBG_HEAVY */ 86 #define DBG_HEAVY(x) /* DBG_HEAVY */
91 #define DBG_REG(x) /* DBG_REG */ 87 #define DBG_REG(x) /* DBG_REG */
92 #define DBG_LOOP(x) /* DBG_LOOP */ 88 #define DBG_LOOP(x) /* DBG_LOOP */
93 89
94 #endif /* MATROXFB_DEBUG */ 90 #endif /* MATROXFB_DEBUG */
95 91
96 #ifdef DEBUG 92 #ifdef DEBUG
97 #define dprintk(X...) printk(X) 93 #define dprintk(X...) printk(X)
98 #else 94 #else
99 #define dprintk(X...) 95 #define dprintk(X...)
100 #endif 96 #endif
101 97
102 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 98 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
103 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 99 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
104 #endif 100 #endif
105 #ifndef PCI_SS_VENDOR_ID_MATROX 101 #ifndef PCI_SS_VENDOR_ID_MATROX
106 #define PCI_SS_VENDOR_ID_MATROX PCI_VE 102 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
107 #endif 103 #endif
108 104
109 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 105 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
110 #define PCI_SS_ID_MATROX_GENERIC 106 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
111 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 107 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
112 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 108 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
113 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 109 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
114 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 110 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
115 #define PCI_SS_ID_MATROX_MGA_G100_PCI 111 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
116 #define PCI_SS_ID_MATROX_MGA_G100_AGP 112 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
117 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_A 113 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
118 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 114 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
119 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 115 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
120 #endif 116 #endif
121 117
122 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRE 118 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
123 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUE 119 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
124 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEU 120 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
125 121
126 #define CNVT_TOHW(val,width) ((((val)<<(width) 122 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
127 123
128 /* G-series and Mystique have (almost) same DA 124 /* G-series and Mystique have (almost) same DAC */
129 #undef NEED_DAC1064 125 #undef NEED_DAC1064
130 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defi 126 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
131 #define NEED_DAC1064 1 127 #define NEED_DAC1064 1
132 #endif 128 #endif
133 129
134 typedef struct { 130 typedef struct {
135 void __iomem* vaddr; 131 void __iomem* vaddr;
136 } vaddr_t; 132 } vaddr_t;
137 133
138 static inline unsigned int mga_readb(vaddr_t v 134 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
139 return readb(va.vaddr + offs); 135 return readb(va.vaddr + offs);
140 } 136 }
141 137
142 static inline void mga_writeb(vaddr_t va, unsi 138 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
143 writeb(value, va.vaddr + offs); 139 writeb(value, va.vaddr + offs);
144 } 140 }
145 141
146 static inline void mga_writew(vaddr_t va, unsi 142 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
147 writew(value, va.vaddr + offs); 143 writew(value, va.vaddr + offs);
148 } 144 }
149 145
150 static inline u_int32_t mga_readl(vaddr_t va, 146 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
151 return readl(va.vaddr + offs); 147 return readl(va.vaddr + offs);
152 } 148 }
153 149
154 static inline void mga_writel(vaddr_t va, unsi 150 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
155 writel(value, va.vaddr + offs); 151 writel(value, va.vaddr + offs);
156 } 152 }
157 153
158 static inline void mga_memcpy_toio(vaddr_t va, 154 static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
159 #if defined(__alpha__) || defined(__i386__) || 155 #if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
160 /* 156 /*
161 * memcpy_toio works for us if: 157 * memcpy_toio works for us if:
162 * (1) Copies data as 32bit quantitie 158 * (1) Copies data as 32bit quantities, not byte after byte,
163 * (2) Performs LE ordered stores, an 159 * (2) Performs LE ordered stores, and
164 * (3) It copes with unaligned source 160 * (3) It copes with unaligned source (destination is guaranteed to be page
165 * aligned and length is guarante 161 * aligned and length is guaranteed to be multiple of 4).
166 */ 162 */
167 memcpy_toio(va.vaddr, src, len); 163 memcpy_toio(va.vaddr, src, len);
168 #else 164 #else
169 u_int32_t __iomem* addr = va.vaddr; 165 u_int32_t __iomem* addr = va.vaddr;
170 166
171 if ((unsigned long)src & 3) { 167 if ((unsigned long)src & 3) {
172 while (len >= 4) { 168 while (len >= 4) {
173 writel(get_unaligned(( !! 169 fb_writel(get_unaligned((u32 *)src), addr);
174 addr++; 170 addr++;
175 len -= 4; 171 len -= 4;
176 src += 4; 172 src += 4;
177 } 173 }
178 } else { 174 } else {
179 while (len >= 4) { 175 while (len >= 4) {
180 writel(*(u32 *)src, ad !! 176 fb_writel(*(u32 *)src, addr);
181 addr++; 177 addr++;
182 len -= 4; 178 len -= 4;
183 src += 4; 179 src += 4;
184 } 180 }
185 } 181 }
186 #endif 182 #endif
187 } 183 }
188 184
189 static inline void vaddr_add(vaddr_t* va, unsi 185 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
190 va->vaddr += offs; 186 va->vaddr += offs;
191 } 187 }
192 188
193 static inline void __iomem* vaddr_va(vaddr_t v 189 static inline void __iomem* vaddr_va(vaddr_t va) {
194 return va.vaddr; 190 return va.vaddr;
195 } 191 }
196 192
197 #define MGA_IOREMAP_NORMAL 0 193 #define MGA_IOREMAP_NORMAL 0
198 #define MGA_IOREMAP_NOCACHE 1 194 #define MGA_IOREMAP_NOCACHE 1
199 195
200 #define MGA_IOREMAP_FB MGA_IOREMAP_NO 196 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
201 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NO 197 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
202 static inline int mga_ioremap(unsigned long ph 198 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
203 if (flags & MGA_IOREMAP_NOCACHE) 199 if (flags & MGA_IOREMAP_NOCACHE)
204 virt->vaddr = ioremap_nocache( 200 virt->vaddr = ioremap_nocache(phys, size);
205 else 201 else
206 virt->vaddr = ioremap(phys, si 202 virt->vaddr = ioremap(phys, size);
207 return (virt->vaddr == 0); /* 0, !0... 203 return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
208 } 204 }
209 205
210 static inline void mga_iounmap(vaddr_t va) { 206 static inline void mga_iounmap(vaddr_t va) {
211 iounmap(va.vaddr); 207 iounmap(va.vaddr);
212 } 208 }
213 209
214 struct my_timming { 210 struct my_timming {
215 unsigned int pixclock; 211 unsigned int pixclock;
216 int mnp; 212 int mnp;
217 unsigned int crtc; 213 unsigned int crtc;
218 unsigned int HDisplay; 214 unsigned int HDisplay;
219 unsigned int HSyncStart; 215 unsigned int HSyncStart;
220 unsigned int HSyncEnd; 216 unsigned int HSyncEnd;
221 unsigned int HTotal; 217 unsigned int HTotal;
222 unsigned int VDisplay; 218 unsigned int VDisplay;
223 unsigned int VSyncStart; 219 unsigned int VSyncStart;
224 unsigned int VSyncEnd; 220 unsigned int VSyncEnd;
225 unsigned int VTotal; 221 unsigned int VTotal;
226 unsigned int sync; 222 unsigned int sync;
227 int dblscan; 223 int dblscan;
228 int interlaced; 224 int interlaced;
229 unsigned int delay; /* CRTC delay 225 unsigned int delay; /* CRTC delay */
230 }; 226 };
231 227
232 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PL 228 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
233 229
234 struct matrox_pll_cache { 230 struct matrox_pll_cache {
235 unsigned int valid; 231 unsigned int valid;
236 struct { 232 struct {
237 unsigned int mnp_key; 233 unsigned int mnp_key;
238 unsigned int mnp_value; 234 unsigned int mnp_value;
239 } data[4]; 235 } data[4];
240 }; 236 };
241 237
242 struct matrox_pll_limits { 238 struct matrox_pll_limits {
243 unsigned int vcomin; 239 unsigned int vcomin;
244 unsigned int vcomax; 240 unsigned int vcomax;
245 }; 241 };
246 242
247 struct matrox_pll_features { 243 struct matrox_pll_features {
248 unsigned int vco_freq_min; 244 unsigned int vco_freq_min;
249 unsigned int ref_freq; 245 unsigned int ref_freq;
250 unsigned int feed_div_min; 246 unsigned int feed_div_min;
251 unsigned int feed_div_max; 247 unsigned int feed_div_max;
252 unsigned int in_div_min; 248 unsigned int in_div_min;
253 unsigned int in_div_max; 249 unsigned int in_div_max;
254 unsigned int post_shift_max; 250 unsigned int post_shift_max;
255 }; 251 };
256 252
257 struct matroxfb_par 253 struct matroxfb_par
258 { 254 {
259 unsigned int final_bppShift; 255 unsigned int final_bppShift;
260 unsigned int cmap_len; 256 unsigned int cmap_len;
261 struct { 257 struct {
262 unsigned int bytes; 258 unsigned int bytes;
263 unsigned int pixels; 259 unsigned int pixels;
264 unsigned int chunks; 260 unsigned int chunks;
265 } ydstorg; 261 } ydstorg;
266 }; 262 };
267 263
268 struct matrox_fb_info; 264 struct matrox_fb_info;
269 265
270 struct matrox_DAC1064_features { 266 struct matrox_DAC1064_features {
271 u_int8_t xvrefctrl; 267 u_int8_t xvrefctrl;
272 u_int8_t xmiscctrl; 268 u_int8_t xmiscctrl;
273 }; 269 };
274 270
275 struct matrox_accel_features { <<
276 int has_cacheflush; <<
277 }; <<
278 <<
279 /* current hardware status */ 271 /* current hardware status */
280 struct mavenregs { 272 struct mavenregs {
281 u_int8_t regs[256]; 273 u_int8_t regs[256];
282 int mode; 274 int mode;
283 int vlines; 275 int vlines;
284 int xtal; 276 int xtal;
285 int fv; 277 int fv;
286 278
287 u_int16_t htotal; 279 u_int16_t htotal;
288 u_int16_t hcorr; 280 u_int16_t hcorr;
289 }; 281 };
290 282
291 struct matrox_crtc2 { 283 struct matrox_crtc2 {
292 u_int32_t ctl; 284 u_int32_t ctl;
293 }; 285 };
294 286
295 struct matrox_hw_state { 287 struct matrox_hw_state {
296 u_int32_t MXoptionReg; 288 u_int32_t MXoptionReg;
297 unsigned char DACclk[6]; 289 unsigned char DACclk[6];
298 unsigned char DACreg[80]; 290 unsigned char DACreg[80];
299 unsigned char MiscOutReg; 291 unsigned char MiscOutReg;
300 unsigned char DACpal[768]; 292 unsigned char DACpal[768];
301 unsigned char CRTC[25]; 293 unsigned char CRTC[25];
302 unsigned char CRTCEXT[9]; 294 unsigned char CRTCEXT[9];
303 unsigned char SEQ[5]; 295 unsigned char SEQ[5];
304 /* unused for MGA mode, but who knows. 296 /* unused for MGA mode, but who knows... */
305 unsigned char GCTL[9]; 297 unsigned char GCTL[9];
306 /* unused for MGA mode, but who knows. 298 /* unused for MGA mode, but who knows... */
307 unsigned char ATTR[21]; 299 unsigned char ATTR[21];
308 300
309 /* TVOut only */ 301 /* TVOut only */
310 struct mavenregs maven; 302 struct mavenregs maven;
311 303
312 struct matrox_crtc2 crtc2; 304 struct matrox_crtc2 crtc2;
313 }; 305 };
314 306
315 struct matrox_accel_data { 307 struct matrox_accel_data {
316 #ifdef CONFIG_FB_MATROX_MILLENIUM 308 #ifdef CONFIG_FB_MATROX_MILLENIUM
317 unsigned char ramdac_rev; 309 unsigned char ramdac_rev;
318 #endif 310 #endif
319 u_int32_t m_dwg_rect; 311 u_int32_t m_dwg_rect;
320 u_int32_t m_opmode; 312 u_int32_t m_opmode;
321 }; 313 };
322 314
323 struct v4l2_queryctrl; 315 struct v4l2_queryctrl;
324 struct v4l2_control; 316 struct v4l2_control;
325 317
326 struct matrox_altout { 318 struct matrox_altout {
327 const char *name; 319 const char *name;
328 int (*compute)(void* altou 320 int (*compute)(void* altout_dev, struct my_timming* input);
329 int (*program)(void* altou 321 int (*program)(void* altout_dev);
330 int (*start)(void* altout_ 322 int (*start)(void* altout_dev);
331 int (*verifymode)(void* al 323 int (*verifymode)(void* altout_dev, u_int32_t mode);
332 int (*getqueryctrl)(void* 324 int (*getqueryctrl)(void* altout_dev,
333 struct 325 struct v4l2_queryctrl* ctrl);
334 int (*getctrl)(void* altou 326 int (*getctrl)(void* altout_dev,
335 struct v4l2 327 struct v4l2_control* ctrl);
336 int (*setctrl)(void* altou 328 int (*setctrl)(void* altout_dev,
337 struct v4l2 329 struct v4l2_control* ctrl);
338 }; 330 };
339 331
340 #define MATROXFB_SRC_NONE 0 332 #define MATROXFB_SRC_NONE 0
341 #define MATROXFB_SRC_CRTC1 1 333 #define MATROXFB_SRC_CRTC1 1
342 #define MATROXFB_SRC_CRTC2 2 334 #define MATROXFB_SRC_CRTC2 2
343 335
344 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, 336 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
345 337
346 struct matrox_bios { 338 struct matrox_bios {
347 unsigned int bios_valid : 1; 339 unsigned int bios_valid : 1;
348 unsigned int pins_len; 340 unsigned int pins_len;
349 unsigned char pins[128]; 341 unsigned char pins[128];
350 struct { 342 struct {
351 unsigned char vMaj, vMin, vRev 343 unsigned char vMaj, vMin, vRev;
352 } version; 344 } version;
353 struct { 345 struct {
354 unsigned char state, tvout; 346 unsigned char state, tvout;
355 } output; 347 } output;
356 }; 348 };
357 349
358 extern struct display fb_display[]; <<
359 <<
360 struct matrox_switch; 350 struct matrox_switch;
361 struct matroxfb_driver; 351 struct matroxfb_driver;
362 struct matroxfb_dh_fb_info; 352 struct matroxfb_dh_fb_info;
363 353
364 struct matrox_vsync { 354 struct matrox_vsync {
365 wait_queue_head_t wait; 355 wait_queue_head_t wait;
366 unsigned int cnt; 356 unsigned int cnt;
367 }; 357 };
368 358
369 struct matrox_fb_info { 359 struct matrox_fb_info {
370 struct fb_info fbcon; 360 struct fb_info fbcon;
371 361
372 struct list_head next_fb; 362 struct list_head next_fb;
373 363
374 int dead; 364 int dead;
375 int initialized; 365 int initialized;
376 unsigned int usecount; 366 unsigned int usecount;
377 367
378 unsigned int userusecount; 368 unsigned int userusecount;
379 unsigned long irq_flags; 369 unsigned long irq_flags;
380 370
381 struct matroxfb_par curr; 371 struct matroxfb_par curr;
382 struct matrox_hw_state hw; 372 struct matrox_hw_state hw;
383 373
384 struct matrox_accel_data accel; 374 struct matrox_accel_data accel;
385 375
386 struct pci_dev* pcidev; 376 struct pci_dev* pcidev;
387 377
388 struct { 378 struct {
389 struct matrox_vsync vsync; 379 struct matrox_vsync vsync;
390 unsigned int pixclock; 380 unsigned int pixclock;
391 int mnp; 381 int mnp;
392 int panpos; 382 int panpos;
393 } crtc1; 383 } crtc1;
394 struct { 384 struct {
395 struct matrox_vsync vsync; 385 struct matrox_vsync vsync;
396 unsigned int pixclock; 386 unsigned int pixclock;
397 int mnp; 387 int mnp;
398 struct matroxfb_dh_fb_info* info; 388 struct matroxfb_dh_fb_info* info;
399 struct rw_semaphore lock; 389 struct rw_semaphore lock;
400 } crtc2; 390 } crtc2;
401 struct { 391 struct {
402 struct rw_semaphore lock; 392 struct rw_semaphore lock;
403 struct { 393 struct {
404 int brightness, contrast, satu 394 int brightness, contrast, saturation, hue, gamma;
405 int testout, deflicker; 395 int testout, deflicker;
406 } tvo_params; 396 } tvo_params;
407 } altout; 397 } altout;
408 #define MATROXFB_MAX_OUTPUTS 3 398 #define MATROXFB_MAX_OUTPUTS 3
409 struct { 399 struct {
410 unsigned int src; 400 unsigned int src;
411 struct matrox_altout* output; 401 struct matrox_altout* output;
412 void* data; 402 void* data;
413 unsigned int mode; 403 unsigned int mode;
414 unsigned int default_src; 404 unsigned int default_src;
415 } outputs[MATROX 405 } outputs[MATROXFB_MAX_OUTPUTS];
416 406
417 #define MATROXFB_MAX_FB_DRIVERS 5 407 #define MATROXFB_MAX_FB_DRIVERS 5
418 struct matroxfb_driver* (drivers[MATRO 408 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
419 void* (drivers_data[ 409 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
420 unsigned int drivers_count; 410 unsigned int drivers_count;
421 411
422 struct { 412 struct {
423 unsigned long base; /* physical */ 413 unsigned long base; /* physical */
424 vaddr_t vbase; /* CPU view */ 414 vaddr_t vbase; /* CPU view */
425 unsigned int len; 415 unsigned int len;
426 unsigned int len_usable; 416 unsigned int len_usable;
427 unsigned int len_maximum; 417 unsigned int len_maximum;
428 } video; 418 } video;
429 419
430 struct { 420 struct {
431 unsigned long base; /* physical */ 421 unsigned long base; /* physical */
432 vaddr_t vbase; /* CPU view */ 422 vaddr_t vbase; /* CPU view */
433 unsigned int len; 423 unsigned int len;
434 } mmio; 424 } mmio;
435 425
436 unsigned int max_pixel_clock; 426 unsigned int max_pixel_clock;
>> 427 unsigned int max_pixel_clock_panellink;
437 428
438 struct matrox_switch* hw_switch; 429 struct matrox_switch* hw_switch;
439 430
440 struct { 431 struct {
441 struct matrox_pll_features pll 432 struct matrox_pll_features pll;
442 struct matrox_DAC1064_features 433 struct matrox_DAC1064_features DAC1064;
443 struct matrox_accel_features a <<
444 } features; 434 } features;
445 struct { 435 struct {
446 spinlock_t DAC; 436 spinlock_t DAC;
447 spinlock_t accel; 437 spinlock_t accel;
448 } lock; 438 } lock;
449 439
450 enum mga_chip chip; 440 enum mga_chip chip;
451 441
452 int interleave; 442 int interleave;
453 int millenium; 443 int millenium;
454 int milleniumII; 444 int milleniumII;
455 struct { 445 struct {
456 int cfb4; 446 int cfb4;
457 const int* vxres; 447 const int* vxres;
458 int cross4MB; 448 int cross4MB;
459 int text; 449 int text;
460 int plnwt; 450 int plnwt;
461 int srcorg; 451 int srcorg;
462 } capable; 452 } capable;
463 #ifdef CONFIG_MTRR 453 #ifdef CONFIG_MTRR
464 struct { 454 struct {
465 int vram; 455 int vram;
466 int vram_valid; 456 int vram_valid;
467 } mtrr; 457 } mtrr;
468 #endif 458 #endif
469 struct { 459 struct {
470 int precise_width; 460 int precise_width;
471 int mga_24bpp_fix; 461 int mga_24bpp_fix;
472 int novga; 462 int novga;
473 int nobios; 463 int nobios;
474 int nopciretry; 464 int nopciretry;
475 int noinit; 465 int noinit;
476 int sgram; 466 int sgram;
477 #ifdef CONFIG_FB_MATROX_32MB 467 #ifdef CONFIG_FB_MATROX_32MB
478 int support32MB; 468 int support32MB;
479 #endif 469 #endif
480 470
481 int accelerator; 471 int accelerator;
482 int text_type_aux; 472 int text_type_aux;
483 int video64bits; 473 int video64bits;
484 int crtc2; 474 int crtc2;
485 int maven_capable; 475 int maven_capable;
486 unsigned int vgastep; 476 unsigned int vgastep;
487 unsigned int textmode; 477 unsigned int textmode;
488 unsigned int textstep; 478 unsigned int textstep;
489 unsigned int textvram; 479 unsigned int textvram; /* character cells */
490 unsigned int ydstorg; 480 unsigned int ydstorg; /* offset in bytes from video start to usable memory */
491 481 /* 0 except for 6MB Millenium */
492 int memtype; 482 int memtype;
493 int g450dac; 483 int g450dac;
494 int dfp_type; 484 int dfp_type;
495 int panellink; 485 int panellink; /* G400 DFP possible (not G450/G550) */
496 int dualhead; 486 int dualhead;
497 unsigned int fbResource; 487 unsigned int fbResource;
498 } devflags; 488 } devflags;
499 struct fb_ops fbops; 489 struct fb_ops fbops;
500 struct matrox_bios bios; 490 struct matrox_bios bios;
501 struct { 491 struct {
502 struct matrox_pll_limits 492 struct matrox_pll_limits pixel;
503 struct matrox_pll_limits 493 struct matrox_pll_limits system;
504 struct matrox_pll_limits 494 struct matrox_pll_limits video;
505 } limits; 495 } limits;
506 struct { 496 struct {
507 struct matrox_pll_cache pixel; 497 struct matrox_pll_cache pixel;
508 struct matrox_pll_cache system 498 struct matrox_pll_cache system;
509 struct matrox_pll_cache video; 499 struct matrox_pll_cache video;
510 } cache; 500 } cache;
511 struct { 501 struct {
512 struct { 502 struct {
513 unsigned int video; 503 unsigned int video;
514 unsigned int system 504 unsigned int system;
515 } pll; 505 } pll;
516 struct { 506 struct {
517 u_int32_t opt; 507 u_int32_t opt;
518 u_int32_t opt2; 508 u_int32_t opt2;
519 u_int32_t opt3; 509 u_int32_t opt3;
520 u_int32_t mctlwt 510 u_int32_t mctlwtst;
521 u_int32_t mctlwt 511 u_int32_t mctlwtst_core;
522 u_int32_t memmis 512 u_int32_t memmisc;
523 u_int32_t memrdb 513 u_int32_t memrdbk;
524 u_int32_t macces 514 u_int32_t maccess;
525 } reg; 515 } reg;
526 struct { 516 struct {
527 unsigned int ddr:1, 517 unsigned int ddr:1,
528 emrswe 518 emrswen:1,
529 dll:1; 519 dll:1;
530 } memory 520 } memory;
531 } values; 521 } values;
532 u_int32_t cmap[17]; !! 522 u_int32_t cmap[16];
533 }; 523 };
534 524
535 #define info2minfo(info) container_of(info, st 525 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
536 526
537 #ifdef CONFIG_FB_MATROX_MULTIHEAD 527 #ifdef CONFIG_FB_MATROX_MULTIHEAD
538 #define ACCESS_FBINFO2(info, x) (info->x) 528 #define ACCESS_FBINFO2(info, x) (info->x)
539 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo, 529 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
540 530
541 #define MINFO minfo 531 #define MINFO minfo
542 532
543 #define WPMINFO2 struct matrox_fb_info* minfo 533 #define WPMINFO2 struct matrox_fb_info* minfo
544 #define WPMINFO WPMINFO2 , 534 #define WPMINFO WPMINFO2 ,
545 #define CPMINFO2 const struct matrox_fb_info* 535 #define CPMINFO2 const struct matrox_fb_info* minfo
546 #define CPMINFO CPMINFO2 , 536 #define CPMINFO CPMINFO2 ,
547 #define PMINFO2 minfo 537 #define PMINFO2 minfo
548 #define PMINFO PMINFO2 , 538 #define PMINFO PMINFO2 ,
549 539
550 #define MINFO_FROM(x) struct matrox_fb_in 540 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
551 #else 541 #else
552 542
553 extern struct matrox_fb_info matroxfb_global_m 543 extern struct matrox_fb_info matroxfb_global_mxinfo;
554 544
555 #define ACCESS_FBINFO(x) (matroxfb_global_mxin 545 #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
556 #define ACCESS_FBINFO2(info, x) (matroxfb_glob 546 #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
557 547
558 #define MINFO (&matroxfb_global_mxinfo) 548 #define MINFO (&matroxfb_global_mxinfo)
559 549
560 #define WPMINFO2 void 550 #define WPMINFO2 void
561 #define WPMINFO 551 #define WPMINFO
562 #define CPMINFO2 void 552 #define CPMINFO2 void
563 #define CPMINFO 553 #define CPMINFO
564 #define PMINFO2 554 #define PMINFO2
565 #define PMINFO 555 #define PMINFO
566 556
567 #define MINFO_FROM(x) 557 #define MINFO_FROM(x)
568 558
569 #endif 559 #endif
570 560
571 #define MINFO_FROM_INFO(x) MINFO_FROM(info2min 561 #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
572 562
573 struct matrox_switch { 563 struct matrox_switch {
574 int (*preinit)(WPMINFO2); 564 int (*preinit)(WPMINFO2);
575 void (*reset)(WPMINFO2); 565 void (*reset)(WPMINFO2);
576 int (*init)(WPMINFO struct my_timm 566 int (*init)(WPMINFO struct my_timming*);
577 void (*restore)(WPMINFO2); 567 void (*restore)(WPMINFO2);
578 }; 568 };
579 569
580 struct matroxfb_driver { 570 struct matroxfb_driver {
581 struct list_head node; 571 struct list_head node;
582 char* name; 572 char* name;
583 void* (*probe)(struc 573 void* (*probe)(struct matrox_fb_info* info);
584 void (*remove)(stru 574 void (*remove)(struct matrox_fb_info* info, void* data);
585 }; 575 };
586 576
587 int matroxfb_register_driver(struct matroxfb_d 577 int matroxfb_register_driver(struct matroxfb_driver* drv);
588 void matroxfb_unregister_driver(struct matroxf 578 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
589 579
590 #define PCI_OPTION_REG 0x40 580 #define PCI_OPTION_REG 0x40
591 #define PCI_OPTION_ENABLE_ROM 0x4000 581 #define PCI_OPTION_ENABLE_ROM 0x40000000
592 582
593 #define PCI_MGA_INDEX 0x44 583 #define PCI_MGA_INDEX 0x44
594 #define PCI_MGA_DATA 0x48 584 #define PCI_MGA_DATA 0x48
595 #define PCI_OPTION2_REG 0x50 585 #define PCI_OPTION2_REG 0x50
596 #define PCI_OPTION3_REG 0x54 586 #define PCI_OPTION3_REG 0x54
597 #define PCI_MEMMISC_REG 0x58 587 #define PCI_MEMMISC_REG 0x58
598 588
599 #define M_DWGCTL 0x1C00 589 #define M_DWGCTL 0x1C00
600 #define M_MACCESS 0x1C04 590 #define M_MACCESS 0x1C04
601 #define M_CTLWTST 0x1C08 591 #define M_CTLWTST 0x1C08
602 592
603 #define M_PLNWT 0x1C1C 593 #define M_PLNWT 0x1C1C
604 594
605 #define M_BCOL 0x1C20 595 #define M_BCOL 0x1C20
606 #define M_FCOL 0x1C24 596 #define M_FCOL 0x1C24
607 597
608 #define M_SGN 0x1C58 598 #define M_SGN 0x1C58
609 #define M_LEN 0x1C5C 599 #define M_LEN 0x1C5C
610 #define M_AR0 0x1C60 600 #define M_AR0 0x1C60
611 #define M_AR1 0x1C64 601 #define M_AR1 0x1C64
612 #define M_AR2 0x1C68 602 #define M_AR2 0x1C68
613 #define M_AR3 0x1C6C 603 #define M_AR3 0x1C6C
614 #define M_AR4 0x1C70 604 #define M_AR4 0x1C70
615 #define M_AR5 0x1C74 605 #define M_AR5 0x1C74
616 #define M_AR6 0x1C78 606 #define M_AR6 0x1C78
617 607
618 #define M_CXBNDRY 0x1C80 608 #define M_CXBNDRY 0x1C80
619 #define M_FXBNDRY 0x1C84 609 #define M_FXBNDRY 0x1C84
620 #define M_YDSTLEN 0x1C88 610 #define M_YDSTLEN 0x1C88
621 #define M_PITCH 0x1C8C 611 #define M_PITCH 0x1C8C
622 #define M_YDST 0x1C90 612 #define M_YDST 0x1C90
623 #define M_YDSTORG 0x1C94 613 #define M_YDSTORG 0x1C94
624 #define M_YTOP 0x1C98 614 #define M_YTOP 0x1C98
625 #define M_YBOT 0x1C9C 615 #define M_YBOT 0x1C9C
626 616
627 /* mystique only */ 617 /* mystique only */
628 #define M_CACHEFLUSH 0x1FFF 618 #define M_CACHEFLUSH 0x1FFF
629 619
630 #define M_EXEC 0x0100 620 #define M_EXEC 0x0100
631 621
632 #define M_DWG_TRAP 0x04 622 #define M_DWG_TRAP 0x04
633 #define M_DWG_BITBLT 0x08 623 #define M_DWG_BITBLT 0x08
634 #define M_DWG_ILOAD 0x09 624 #define M_DWG_ILOAD 0x09
635 625
636 #define M_DWG_LINEAR 0x0080 626 #define M_DWG_LINEAR 0x0080
637 #define M_DWG_SOLID 0x0800 627 #define M_DWG_SOLID 0x0800
638 #define M_DWG_ARZERO 0x1000 628 #define M_DWG_ARZERO 0x1000
639 #define M_DWG_SGNZERO 0x2000 629 #define M_DWG_SGNZERO 0x2000
640 #define M_DWG_SHIFTZERO 0x4000 630 #define M_DWG_SHIFTZERO 0x4000
641 631
642 #define M_DWG_REPLACE 0x000C0000 632 #define M_DWG_REPLACE 0x000C0000
643 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40) 633 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
644 #define M_DWG_XOR 0x00060010 634 #define M_DWG_XOR 0x00060010
645 635
646 #define M_DWG_BFCOL 0x04000000 636 #define M_DWG_BFCOL 0x04000000
647 #define M_DWG_BMONOWF 0x08000000 637 #define M_DWG_BMONOWF 0x08000000
648 638
649 #define M_DWG_TRANSC 0x40000000 639 #define M_DWG_TRANSC 0x40000000
650 640
651 #define M_FIFOSTATUS 0x1E10 641 #define M_FIFOSTATUS 0x1E10
652 #define M_STATUS 0x1E14 642 #define M_STATUS 0x1E14
653 #define M_ICLEAR 0x1E18 643 #define M_ICLEAR 0x1E18
654 #define M_IEN 0x1E1C 644 #define M_IEN 0x1E1C
655 645
656 #define M_VCOUNT 0x1E20 646 #define M_VCOUNT 0x1E20
657 647
658 #define M_RESET 0x1E40 648 #define M_RESET 0x1E40
659 #define M_MEMRDBK 0x1E44 649 #define M_MEMRDBK 0x1E44
660 650
661 #define M_AGP2PLL 0x1E4C 651 #define M_AGP2PLL 0x1E4C
662 652
663 #define M_OPMODE 0x1E54 653 #define M_OPMODE 0x1E54
664 #define M_OPMODE_DMA_GEN_WRITE 0x00 654 #define M_OPMODE_DMA_GEN_WRITE 0x00
665 #define M_OPMODE_DMA_BLIT 0x04 655 #define M_OPMODE_DMA_BLIT 0x04
666 #define M_OPMODE_DMA_VECTOR_WRITE 0x08 656 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
667 #define M_OPMODE_DMA_LE 0x0000 657 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
668 #define M_OPMODE_DMA_BE_8BPP 0x0000 658 #define M_OPMODE_DMA_BE_8BPP 0x0000
669 #define M_OPMODE_DMA_BE_16BPP 0x0100 659 #define M_OPMODE_DMA_BE_16BPP 0x0100
670 #define M_OPMODE_DMA_BE_32BPP 0x0200 660 #define M_OPMODE_DMA_BE_32BPP 0x0200
671 #define M_OPMODE_DIR_LE 0x0000 661 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
672 #define M_OPMODE_DIR_BE_8BPP 0x0000 662 #define M_OPMODE_DIR_BE_8BPP 0x000000
673 #define M_OPMODE_DIR_BE_16BPP 0x0100 663 #define M_OPMODE_DIR_BE_16BPP 0x010000
674 #define M_OPMODE_DIR_BE_32BPP 0x0200 664 #define M_OPMODE_DIR_BE_32BPP 0x020000
675 665
676 #define M_ATTR_INDEX 0x1FC0 666 #define M_ATTR_INDEX 0x1FC0
677 #define M_ATTR_DATA 0x1FC1 667 #define M_ATTR_DATA 0x1FC1
678 668
679 #define M_MISC_REG 0x1FC2 669 #define M_MISC_REG 0x1FC2
680 #define M_3C2_RD 0x1FC2 670 #define M_3C2_RD 0x1FC2
681 671
682 #define M_SEQ_INDEX 0x1FC4 672 #define M_SEQ_INDEX 0x1FC4
683 #define M_SEQ_DATA 0x1FC5 673 #define M_SEQ_DATA 0x1FC5
>> 674 #define M_SEQ1 0x01
>> 675 #define M_SEQ1_SCROFF 0x20
684 676
685 #define M_MISC_REG_READ 0x1FCC 677 #define M_MISC_REG_READ 0x1FCC
686 678
687 #define M_GRAPHICS_INDEX 0x1FCE 679 #define M_GRAPHICS_INDEX 0x1FCE
688 #define M_GRAPHICS_DATA 0x1FCF 680 #define M_GRAPHICS_DATA 0x1FCF
689 681
690 #define M_CRTC_INDEX 0x1FD4 682 #define M_CRTC_INDEX 0x1FD4
691 683
692 #define M_ATTR_RESET 0x1FDA 684 #define M_ATTR_RESET 0x1FDA
693 #define M_3DA_WR 0x1FDA 685 #define M_3DA_WR 0x1FDA
694 #define M_INSTS1 0x1FDA 686 #define M_INSTS1 0x1FDA
695 687
696 #define M_EXTVGA_INDEX 0x1FDE 688 #define M_EXTVGA_INDEX 0x1FDE
697 #define M_EXTVGA_DATA 0x1FDF 689 #define M_EXTVGA_DATA 0x1FDF
698 690
699 /* G200 only */ 691 /* G200 only */
700 #define M_SRCORG 0x2CB4 692 #define M_SRCORG 0x2CB4
701 #define M_DSTORG 0x2CB8 693 #define M_DSTORG 0x2CB8
702 694
703 #define M_RAMDAC_BASE 0x3C00 695 #define M_RAMDAC_BASE 0x3C00
704 696
705 /* fortunately, same on TVP3026 and MGA1064 */ 697 /* fortunately, same on TVP3026 and MGA1064 */
706 #define M_DAC_REG (M_RAMDAC_BASE+0) 698 #define M_DAC_REG (M_RAMDAC_BASE+0)
707 #define M_DAC_VAL (M_RAMDAC_BASE+1) 699 #define M_DAC_VAL (M_RAMDAC_BASE+1)
708 #define M_PALETTE_MASK (M_RAMDAC_BASE+2) 700 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
709 701
710 #define M_X_INDEX 0x00 702 #define M_X_INDEX 0x00
711 #define M_X_DATAREG 0x0A 703 #define M_X_DATAREG 0x0A
712 704
713 #define DAC_XGENIOCTRL 0x2A 705 #define DAC_XGENIOCTRL 0x2A
714 #define DAC_XGENIODATA 0x2B 706 #define DAC_XGENIODATA 0x2B
715 707
716 #define M_C2CTL 0x3C10 708 #define M_C2CTL 0x3C10
717 709
718 #define MX_OPTION_BSWAP 0x00000000 710 #define MX_OPTION_BSWAP 0x00000000
719 711
720 #ifdef __LITTLE_ENDIAN 712 #ifdef __LITTLE_ENDIAN
721 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_O 713 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
722 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_O 714 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
723 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_O 715 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
724 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_O 716 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
725 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_O 717 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
726 #else 718 #else
727 #ifdef __BIG_ENDIAN 719 #ifdef __BIG_ENDIAN
728 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_O 720 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
729 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_O 721 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
730 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_O 722 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
731 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_O 723 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
732 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_O 724 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
733 #else 725 #else
734 #error "Byte ordering have to be defined. Cann 726 #error "Byte ordering have to be defined. Cannot continue."
735 #endif 727 #endif
736 #endif 728 #endif
737 729
738 #define mga_inb(addr) mga_readb(ACCE 730 #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
739 #define mga_inl(addr) mga_readl(ACCE 731 #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
740 #define mga_outb(addr,val) mga_writeb(ACC 732 #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
741 #define mga_outw(addr,val) mga_writew(ACC 733 #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
742 #define mga_outl(addr,val) mga_writel(ACC 734 #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
743 #define mga_readr(port,idx) (mga_outb((por 735 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
744 #define mga_setr(addr,port,val) mga_outw(addr, 736 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
745 737
746 #define mga_fifo(n) do {} while ((mga_inl( 738 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
747 739
748 #define WaitTillIdle() do {} while (mga_inl(M 740 #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
749 741
750 /* code speedup */ 742 /* code speedup */
751 #ifdef CONFIG_FB_MATROX_MILLENIUM 743 #ifdef CONFIG_FB_MATROX_MILLENIUM
752 #define isInterleave(x) (x->interleave) 744 #define isInterleave(x) (x->interleave)
753 #define isMillenium(x) (x->millenium) 745 #define isMillenium(x) (x->millenium)
754 #define isMilleniumII(x) (x->milleniumII) 746 #define isMilleniumII(x) (x->milleniumII)
755 #else 747 #else
756 #define isInterleave(x) (0) 748 #define isInterleave(x) (0)
757 #define isMillenium(x) (0) 749 #define isMillenium(x) (0)
758 #define isMilleniumII(x) (0) 750 #define isMilleniumII(x) (0)
759 #endif 751 #endif
760 752
761 #define matroxfb_DAC_lock() 753 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
762 #define matroxfb_DAC_unlock() 754 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
763 #define matroxfb_DAC_lock_irqsave(flags) 755 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
764 #define matroxfb_DAC_unlock_irqrestore(flags) 756 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
765 extern void matroxfb_DAC_out(CPMINFO int reg, 757 extern void matroxfb_DAC_out(CPMINFO int reg, int val);
766 extern int matroxfb_DAC_in(CPMINFO int reg); 758 extern int matroxfb_DAC_in(CPMINFO int reg);
767 extern struct list_head matroxfb_list; <<
768 extern void matroxfb_var2my(struct fb_var_scre 759 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
769 extern int matroxfb_wait_for_sync(WPMINFO u_in 760 extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
770 extern int matroxfb_enable_irq(WPMINFO int ree 761 extern int matroxfb_enable_irq(WPMINFO int reenable);
771 762
772 #ifdef MATROXFB_USE_SPINLOCKS 763 #ifdef MATROXFB_USE_SPINLOCKS
773 #define CRITBEGIN spin_lock_irqsave(&ACCESS_F 764 #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
774 #define CRITEND spin_unlock_irqrestore(&ACC 765 #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
775 #define CRITFLAGS unsigned long critflags; 766 #define CRITFLAGS unsigned long critflags;
776 #else 767 #else
777 #define CRITBEGIN 768 #define CRITBEGIN
778 #define CRITEND 769 #define CRITEND
779 #define CRITFLAGS 770 #define CRITFLAGS
780 #endif 771 #endif
781 772
782 #endif /* __MATROXFB_H__ */ 773 #endif /* __MATROXFB_H__ */
783 774
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