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1 /* 1 /*
2 * 2 *
3 * Hardware accelerated Matrox PCI cards - G45 3 * Hardware accelerated Matrox PCI cards - G450/G550 PLL control.
4 * 4 *
5 * (c) 2001-2002 Petr Vandrovec <vandrove@vc.c 5 * (c) 2001-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 * 6 *
7 * Portions Copyright (c) 2001 Matrox Graphics 7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 * 8 *
9 * Version: 1.64 2002/06/10 9 * Version: 1.64 2002/06/10
10 * 10 *
11 * This file is subject to the terms and condi 11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main d 12 * License. See the file COPYING in the main directory of this archive for
13 * more details. 13 * more details.
14 * 14 *
15 */ 15 */
16 16
17 #include "g450_pll.h" 17 #include "g450_pll.h"
18 #include "matroxfb_DAC1064.h" 18 #include "matroxfb_DAC1064.h"
19 19
20 static inline unsigned int g450_vco2f(unsigned 20 static inline unsigned int g450_vco2f(unsigned char p, unsigned int fvco) {
21 return (p & 0x40) ? fvco : fvco >> ((p 21 return (p & 0x40) ? fvco : fvco >> ((p & 3) + 1);
22 } 22 }
23 23
24 static inline unsigned int g450_f2vco(unsigned 24 static inline unsigned int g450_f2vco(unsigned char p, unsigned int fin) {
25 return (p & 0x40) ? fin : fin << ((p & 25 return (p & 0x40) ? fin : fin << ((p & 3) + 1);
26 } 26 }
27 27
28 static unsigned int g450_mnp2vco(CPMINFO unsig 28 static unsigned int g450_mnp2vco(CPMINFO unsigned int mnp) {
29 unsigned int m, n; 29 unsigned int m, n;
30 30
31 m = ((mnp >> 16) & 0x0FF) + 1; 31 m = ((mnp >> 16) & 0x0FF) + 1;
32 n = ((mnp >> 7) & 0x1FE) + 4; 32 n = ((mnp >> 7) & 0x1FE) + 4;
33 return (ACCESS_FBINFO(features).pll.re 33 return (ACCESS_FBINFO(features).pll.ref_freq * n + (m >> 1)) / m;
34 } 34 }
35 35
36 unsigned int g450_mnp2f(CPMINFO unsigned int m 36 unsigned int g450_mnp2f(CPMINFO unsigned int mnp) {
37 return g450_vco2f(mnp, g450_mnp2vco(PM 37 return g450_vco2f(mnp, g450_mnp2vco(PMINFO mnp));
38 } 38 }
39 39
40 static inline unsigned int pll_freq_delta(unsi 40 static inline unsigned int pll_freq_delta(unsigned int f1, unsigned int f2) {
41 if (f2 < f1) { 41 if (f2 < f1) {
42 f2 = f1 - f2; 42 f2 = f1 - f2;
43 } else { 43 } else {
44 f2 = f2 - f1; 44 f2 = f2 - f1;
45 } 45 }
46 return f2; 46 return f2;
47 } 47 }
48 48
49 #define NO_MORE_MNP 0x01FFFFFF 49 #define NO_MORE_MNP 0x01FFFFFF
50 #define G450_MNP_FREQBITS (0xFFFFFF43) 50 #define G450_MNP_FREQBITS (0xFFFFFF43) /* do not mask high byte so we'll catch NO_MORE_MNP */
51 51
52 static unsigned int g450_nextpll(CPMINFO const 52 static unsigned int g450_nextpll(CPMINFO const struct matrox_pll_limits* pi, unsigned int* fvco, unsigned int mnp) {
53 unsigned int m, n, p; 53 unsigned int m, n, p;
54 unsigned int tvco = *fvco; 54 unsigned int tvco = *fvco;
55 55
56 m = (mnp >> 16) & 0xFF; 56 m = (mnp >> 16) & 0xFF;
57 p = mnp & 0xFF; 57 p = mnp & 0xFF;
58 58
59 do { 59 do {
60 if (m == 0 || m == 0xFF) { 60 if (m == 0 || m == 0xFF) {
61 if (m == 0) { 61 if (m == 0) {
62 if (p & 0x40) 62 if (p & 0x40) {
63 return 63 return NO_MORE_MNP;
64 } 64 }
65 if (p & 3) { 65 if (p & 3) {
66 p--; 66 p--;
67 } else { 67 } else {
68 p = 0x 68 p = 0x40;
69 } 69 }
70 tvco >>= 1; 70 tvco >>= 1;
71 if (tvco < pi- 71 if (tvco < pi->vcomin) {
72 return 72 return NO_MORE_MNP;
73 } 73 }
74 *fvco = tvco; 74 *fvco = tvco;
75 } 75 }
76 76
77 p &= 0x43; 77 p &= 0x43;
78 if (tvco < 550000) { 78 if (tvco < 550000) {
79 /* p |= 0x00; */ 79 /* p |= 0x00; */
80 } else if (tvco < 7000 80 } else if (tvco < 700000) {
81 p |= 0x08; 81 p |= 0x08;
82 } else if (tvco < 1000 82 } else if (tvco < 1000000) {
83 p |= 0x10; 83 p |= 0x10;
84 } else if (tvco < 1150 84 } else if (tvco < 1150000) {
85 p |= 0x18; 85 p |= 0x18;
86 } else { 86 } else {
87 p |= 0x20; 87 p |= 0x20;
88 } 88 }
89 m = 9; 89 m = 9;
90 } else { 90 } else {
91 m--; 91 m--;
92 } 92 }
93 n = ((tvco * (m+1) + ACCESS_FB 93 n = ((tvco * (m+1) + ACCESS_FBINFO(features).pll.ref_freq) / (ACCESS_FBINFO(features).pll.ref_freq * 2)) - 2;
94 } while (n < 0x03 || n > 0x7A); 94 } while (n < 0x03 || n > 0x7A);
95 return (m << 16) | (n << 8) | p; 95 return (m << 16) | (n << 8) | p;
96 } 96 }
97 97
98 static unsigned int g450_firstpll(CPMINFO cons 98 static unsigned int g450_firstpll(CPMINFO const struct matrox_pll_limits* pi, unsigned int* vco, unsigned int fout) {
99 unsigned int p; 99 unsigned int p;
100 unsigned int vcomax; 100 unsigned int vcomax;
101 101
102 vcomax = pi->vcomax; 102 vcomax = pi->vcomax;
103 if (fout > (vcomax / 2)) { 103 if (fout > (vcomax / 2)) {
104 if (fout > vcomax) { 104 if (fout > vcomax) {
105 *vco = vcomax; 105 *vco = vcomax;
106 } else { 106 } else {
107 *vco = fout; 107 *vco = fout;
108 } 108 }
109 p = 0x40; 109 p = 0x40;
110 } else { 110 } else {
111 unsigned int tvco; 111 unsigned int tvco;
112 112
113 p = 3; 113 p = 3;
114 tvco = g450_f2vco(p, fout); 114 tvco = g450_f2vco(p, fout);
115 while (p && (tvco > vcomax)) { 115 while (p && (tvco > vcomax)) {
116 p--; 116 p--;
117 tvco >>= 1; 117 tvco >>= 1;
118 } 118 }
119 if (tvco < pi->vcomin) { 119 if (tvco < pi->vcomin) {
120 tvco = pi->vcomin; 120 tvco = pi->vcomin;
121 } 121 }
122 *vco = tvco; 122 *vco = tvco;
123 } 123 }
124 return g450_nextpll(PMINFO pi, vco, 0x 124 return g450_nextpll(PMINFO pi, vco, 0xFF0000 | p);
125 } 125 }
126 126
127 static inline unsigned int g450_setpll(CPMINFO 127 static inline unsigned int g450_setpll(CPMINFO unsigned int mnp, unsigned int pll) {
128 switch (pll) { 128 switch (pll) {
129 case M_PIXEL_PLL_A: 129 case M_PIXEL_PLL_A:
130 matroxfb_DAC_out(PMINF 130 matroxfb_DAC_out(PMINFO M1064_XPIXPLLAM, mnp >> 16);
131 matroxfb_DAC_out(PMINF 131 matroxfb_DAC_out(PMINFO M1064_XPIXPLLAN, mnp >> 8);
132 matroxfb_DAC_out(PMINF 132 matroxfb_DAC_out(PMINFO M1064_XPIXPLLAP, mnp);
133 return M1064_XPIXPLLST 133 return M1064_XPIXPLLSTAT;
134 134
135 case M_PIXEL_PLL_B: 135 case M_PIXEL_PLL_B:
136 matroxfb_DAC_out(PMINF 136 matroxfb_DAC_out(PMINFO M1064_XPIXPLLBM, mnp >> 16);
137 matroxfb_DAC_out(PMINF 137 matroxfb_DAC_out(PMINFO M1064_XPIXPLLBN, mnp >> 8);
138 matroxfb_DAC_out(PMINF 138 matroxfb_DAC_out(PMINFO M1064_XPIXPLLBP, mnp);
139 return M1064_XPIXPLLST 139 return M1064_XPIXPLLSTAT;
140 140
141 case M_PIXEL_PLL_C: 141 case M_PIXEL_PLL_C:
142 matroxfb_DAC_out(PMINF 142 matroxfb_DAC_out(PMINFO M1064_XPIXPLLCM, mnp >> 16);
143 matroxfb_DAC_out(PMINF 143 matroxfb_DAC_out(PMINFO M1064_XPIXPLLCN, mnp >> 8);
144 matroxfb_DAC_out(PMINF 144 matroxfb_DAC_out(PMINFO M1064_XPIXPLLCP, mnp);
145 return M1064_XPIXPLLST 145 return M1064_XPIXPLLSTAT;
146 146
147 case M_SYSTEM_PLL: 147 case M_SYSTEM_PLL:
148 matroxfb_DAC_out(PMINF 148 matroxfb_DAC_out(PMINFO DAC1064_XSYSPLLM, mnp >> 16);
149 matroxfb_DAC_out(PMINF 149 matroxfb_DAC_out(PMINFO DAC1064_XSYSPLLN, mnp >> 8);
150 matroxfb_DAC_out(PMINF 150 matroxfb_DAC_out(PMINFO DAC1064_XSYSPLLP, mnp);
151 return DAC1064_XSYSPLL 151 return DAC1064_XSYSPLLSTAT;
152 152
153 case M_VIDEO_PLL: 153 case M_VIDEO_PLL:
154 matroxfb_DAC_out(PMINF 154 matroxfb_DAC_out(PMINFO M1064_XVIDPLLM, mnp >> 16);
155 matroxfb_DAC_out(PMINF 155 matroxfb_DAC_out(PMINFO M1064_XVIDPLLN, mnp >> 8);
156 matroxfb_DAC_out(PMINF 156 matroxfb_DAC_out(PMINFO M1064_XVIDPLLP, mnp);
157 return M1064_XVIDPLLST 157 return M1064_XVIDPLLSTAT;
158 } 158 }
159 return 0; 159 return 0;
160 } 160 }
161 161
162 static inline unsigned int g450_cmppll(CPMINFO 162 static inline unsigned int g450_cmppll(CPMINFO unsigned int mnp, unsigned int pll) {
163 unsigned char m = mnp >> 16; 163 unsigned char m = mnp >> 16;
164 unsigned char n = mnp >> 8; 164 unsigned char n = mnp >> 8;
165 unsigned char p = mnp; 165 unsigned char p = mnp;
166 166
167 switch (pll) { 167 switch (pll) {
168 case M_PIXEL_PLL_A: 168 case M_PIXEL_PLL_A:
169 return (matroxfb_DAC_i 169 return (matroxfb_DAC_in(PMINFO M1064_XPIXPLLAM) != m ||
170 matroxfb_DAC_i 170 matroxfb_DAC_in(PMINFO M1064_XPIXPLLAN) != n ||
171 matroxfb_DAC_i 171 matroxfb_DAC_in(PMINFO M1064_XPIXPLLAP) != p);
172 172
173 case M_PIXEL_PLL_B: 173 case M_PIXEL_PLL_B:
174 return (matroxfb_DAC_i 174 return (matroxfb_DAC_in(PMINFO M1064_XPIXPLLBM) != m ||
175 matroxfb_DAC_i 175 matroxfb_DAC_in(PMINFO M1064_XPIXPLLBN) != n ||
176 matroxfb_DAC_i 176 matroxfb_DAC_in(PMINFO M1064_XPIXPLLBP) != p);
177 177
178 case M_PIXEL_PLL_C: 178 case M_PIXEL_PLL_C:
179 return (matroxfb_DAC_i 179 return (matroxfb_DAC_in(PMINFO M1064_XPIXPLLCM) != m ||
180 matroxfb_DAC_i 180 matroxfb_DAC_in(PMINFO M1064_XPIXPLLCN) != n ||
181 matroxfb_DAC_i 181 matroxfb_DAC_in(PMINFO M1064_XPIXPLLCP) != p);
182 182
183 case M_SYSTEM_PLL: 183 case M_SYSTEM_PLL:
184 return (matroxfb_DAC_i 184 return (matroxfb_DAC_in(PMINFO DAC1064_XSYSPLLM) != m ||
185 matroxfb_DAC_i 185 matroxfb_DAC_in(PMINFO DAC1064_XSYSPLLN) != n ||
186 matroxfb_DAC_i 186 matroxfb_DAC_in(PMINFO DAC1064_XSYSPLLP) != p);
187 187
188 case M_VIDEO_PLL: 188 case M_VIDEO_PLL:
189 return (matroxfb_DAC_i 189 return (matroxfb_DAC_in(PMINFO M1064_XVIDPLLM) != m ||
190 matroxfb_DAC_i 190 matroxfb_DAC_in(PMINFO M1064_XVIDPLLN) != n ||
191 matroxfb_DAC_i 191 matroxfb_DAC_in(PMINFO M1064_XVIDPLLP) != p);
192 } 192 }
193 return 1; 193 return 1;
194 } 194 }
195 195
196 static inline int g450_isplllocked(CPMINFO uns 196 static inline int g450_isplllocked(CPMINFO unsigned int regidx) {
197 unsigned int j; 197 unsigned int j;
198 198
199 for (j = 0; j < 1000; j++) { 199 for (j = 0; j < 1000; j++) {
200 if (matroxfb_DAC_in(PMINFO reg 200 if (matroxfb_DAC_in(PMINFO regidx) & 0x40) {
201 unsigned int r = 0; 201 unsigned int r = 0;
202 int i; 202 int i;
203 203
204 for (i = 0; i < 100; i 204 for (i = 0; i < 100; i++) {
205 r += matroxfb_ 205 r += matroxfb_DAC_in(PMINFO regidx) & 0x40;
206 } 206 }
207 return r >= (90 * 0x40 207 return r >= (90 * 0x40);
208 } 208 }
209 /* udelay(1)... but DAC_in is 209 /* udelay(1)... but DAC_in is much slower... */
210 } 210 }
211 return 0; 211 return 0;
212 } 212 }
213 213
214 static int g450_testpll(CPMINFO unsigned int m 214 static int g450_testpll(CPMINFO unsigned int mnp, unsigned int pll) {
215 return g450_isplllocked(PMINFO g450_se 215 return g450_isplllocked(PMINFO g450_setpll(PMINFO mnp, pll));
216 } 216 }
217 217
218 static void updatehwstate_clk(struct matrox_hw 218 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) {
219 switch (pll) { 219 switch (pll) {
220 case M_SYSTEM_PLL: 220 case M_SYSTEM_PLL:
221 hw->DACclk[3] = mnp >> 221 hw->DACclk[3] = mnp >> 16;
222 hw->DACclk[4] = mnp >> 222 hw->DACclk[4] = mnp >> 8;
223 hw->DACclk[5] = mnp; 223 hw->DACclk[5] = mnp;
224 break; 224 break;
225 } 225 }
226 } 226 }
227 227
228 void matroxfb_g450_setpll_cond(WPMINFO unsigne 228 void matroxfb_g450_setpll_cond(WPMINFO unsigned int mnp, unsigned int pll) {
229 if (g450_cmppll(PMINFO mnp, pll)) { 229 if (g450_cmppll(PMINFO mnp, pll)) {
230 g450_setpll(PMINFO mnp, pll); 230 g450_setpll(PMINFO mnp, pll);
231 } 231 }
232 } 232 }
233 233
234 static inline unsigned int g450_findworkingpll 234 static inline unsigned int g450_findworkingpll(WPMINFO unsigned int pll, unsigned int* mnparray, unsigned int mnpcount) {
235 unsigned int found = 0; 235 unsigned int found = 0;
236 unsigned int idx; 236 unsigned int idx;
237 unsigned int mnpfound = mnparray[0]; 237 unsigned int mnpfound = mnparray[0];
238 238
239 for (idx = 0; idx < mnpcount; idx++) { 239 for (idx = 0; idx < mnpcount; idx++) {
240 unsigned int sarray[3]; 240 unsigned int sarray[3];
241 unsigned int *sptr; 241 unsigned int *sptr;
242 { 242 {
243 unsigned int mnp; 243 unsigned int mnp;
244 244
245 sptr = sarray; 245 sptr = sarray;
246 mnp = mnparray[idx]; 246 mnp = mnparray[idx];
247 if (mnp & 0x38) { 247 if (mnp & 0x38) {
248 *sptr++ = mnp 248 *sptr++ = mnp - 8;
249 } 249 }
250 if ((mnp & 0x38) != 0x 250 if ((mnp & 0x38) != 0x38) {
251 *sptr++ = mnp 251 *sptr++ = mnp + 8;
252 } 252 }
253 *sptr = mnp; 253 *sptr = mnp;
254 } 254 }
255 while (sptr >= sarray) { 255 while (sptr >= sarray) {
256 unsigned int mnp = *sp 256 unsigned int mnp = *sptr--;
257 257
258 if (g450_testpll(PMINF 258 if (g450_testpll(PMINFO mnp - 0x0300, pll) &&
259 g450_testpll(PMINF 259 g450_testpll(PMINFO mnp + 0x0300, pll) &&
260 g450_testpll(PMINF 260 g450_testpll(PMINFO mnp - 0x0200, pll) &&
261 g450_testpll(PMINF 261 g450_testpll(PMINFO mnp + 0x0200, pll) &&
262 g450_testpll(PMINF 262 g450_testpll(PMINFO mnp - 0x0100, pll) &&
263 g450_testpll(PMINF 263 g450_testpll(PMINFO mnp + 0x0100, pll)) {
264 if (g450_testp 264 if (g450_testpll(PMINFO mnp, pll)) {
265 return 265 return mnp;
266 } 266 }
267 } else if (!found && g 267 } else if (!found && g450_testpll(PMINFO mnp, pll)) {
268 mnpfound = mnp 268 mnpfound = mnp;
269 found = 1; 269 found = 1;
270 } 270 }
271 } 271 }
272 } 272 }
273 g450_setpll(PMINFO mnpfound, pll); 273 g450_setpll(PMINFO mnpfound, pll);
274 return mnpfound; 274 return mnpfound;
275 } 275 }
276 276
277 static void g450_addcache(struct matrox_pll_ca 277 static void g450_addcache(struct matrox_pll_cache* ci, unsigned int mnp_key, unsigned int mnp_value) {
278 if (++ci->valid > ARRAY_SIZE(ci->data) 278 if (++ci->valid > ARRAY_SIZE(ci->data)) {
279 ci->valid = ARRAY_SIZE(ci->dat 279 ci->valid = ARRAY_SIZE(ci->data);
280 } 280 }
281 memmove(ci->data + 1, ci->data, (ci->v 281 memmove(ci->data + 1, ci->data, (ci->valid - 1) * sizeof(*ci->data));
282 ci->data[0].mnp_key = mnp_key & G450_M 282 ci->data[0].mnp_key = mnp_key & G450_MNP_FREQBITS;
283 ci->data[0].mnp_value = mnp_value; 283 ci->data[0].mnp_value = mnp_value;
284 } 284 }
285 285
286 static int g450_checkcache(WPMINFO struct matr 286 static int g450_checkcache(WPMINFO struct matrox_pll_cache* ci, unsigned int mnp_key) {
287 unsigned int i; 287 unsigned int i;
288 288
289 mnp_key &= G450_MNP_FREQBITS; 289 mnp_key &= G450_MNP_FREQBITS;
290 for (i = 0; i < ci->valid; i++) { 290 for (i = 0; i < ci->valid; i++) {
291 if (ci->data[i].mnp_key == mnp 291 if (ci->data[i].mnp_key == mnp_key) {
292 unsigned int mnp; 292 unsigned int mnp;
293 293
294 mnp = ci->data[i].mnp_ 294 mnp = ci->data[i].mnp_value;
295 if (i) { 295 if (i) {
296 memmove(ci->da 296 memmove(ci->data + 1, ci->data, i * sizeof(*ci->data));
297 ci->data[0].mn 297 ci->data[0].mnp_key = mnp_key;
298 ci->data[0].mn 298 ci->data[0].mnp_value = mnp;
299 } 299 }
300 return mnp; 300 return mnp;
301 } 301 }
302 } 302 }
303 return NO_MORE_MNP; 303 return NO_MORE_MNP;
304 } 304 }
305 305
306 static int __g450_setclk(WPMINFO unsigned int 306 static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
307 unsigned int* mnparray, unsign 307 unsigned int* mnparray, unsigned int* deltaarray) {
308 unsigned int mnpcount; 308 unsigned int mnpcount;
309 unsigned int pixel_vco; 309 unsigned int pixel_vco;
310 const struct matrox_pll_limits* pi; 310 const struct matrox_pll_limits* pi;
311 struct matrox_pll_cache* ci; 311 struct matrox_pll_cache* ci;
312 312
313 pixel_vco = 0; 313 pixel_vco = 0;
314 switch (pll) { 314 switch (pll) {
315 case M_PIXEL_PLL_A: 315 case M_PIXEL_PLL_A:
316 case M_PIXEL_PLL_B: 316 case M_PIXEL_PLL_B:
317 case M_PIXEL_PLL_C: 317 case M_PIXEL_PLL_C:
318 { 318 {
319 u_int8_t tmp, 319 u_int8_t tmp, xpwrctrl;
320 unsigned long 320 unsigned long flags;
321 321
322 matroxfb_DAC_l 322 matroxfb_DAC_lock_irqsave(flags);
323 323
324 xpwrctrl = mat 324 xpwrctrl = matroxfb_DAC_in(PMINFO M1064_XPWRCTRL);
325 matroxfb_DAC_o 325 matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, xpwrctrl & ~M1064_XPWRCTRL_PANELPDN);
326 mga_outb(M_SEQ 326 mga_outb(M_SEQ_INDEX, M_SEQ1);
327 mga_outb(M_SEQ 327 mga_outb(M_SEQ_DATA, mga_inb(M_SEQ_DATA) | M_SEQ1_SCROFF);
328 tmp = matroxfb 328 tmp = matroxfb_DAC_in(PMINFO M1064_XPIXCLKCTRL);
329 tmp |= M1064_X 329 tmp |= M1064_XPIXCLKCTRL_DIS;
330 if (!(tmp & M1 330 if (!(tmp & M1064_XPIXCLKCTRL_PLL_UP)) {
331 tmp |= 331 tmp |= M1064_XPIXCLKCTRL_PLL_UP;
332 } 332 }
333 matroxfb_DAC_o 333 matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp);
334 /* DVI PLL pre 334 /* DVI PLL preferred for frequencies up to
335 panel link 335 panel link max, standard PLL otherwise */
336 if (fout >= MI 336 if (fout >= MINFO->max_pixel_clock_panellink)
337 tmp = 337 tmp = 0;
338 else tmp = 338 else tmp =
339 M1064_ 339 M1064_XDVICLKCTRL_DVIDATAPATHSEL |
340 M1064_ 340 M1064_XDVICLKCTRL_C1DVICLKSEL |
341 M1064_ 341 M1064_XDVICLKCTRL_C1DVICLKEN |
342 M1064_ 342 M1064_XDVICLKCTRL_DVILOOPCTL |
343 M1064_ 343 M1064_XDVICLKCTRL_P1LOOPBWDTCTL;
344 /* Setting thi !! 344 matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL,tmp);
345 /* matroxfb_DA <<
346 matroxfb_DAC_o 345 matroxfb_DAC_out(PMINFO M1064_XPWRCTRL,
347 346 xpwrctrl);
348 347
349 matroxfb_DAC_u 348 matroxfb_DAC_unlock_irqrestore(flags);
350 } 349 }
351 { 350 {
352 u_int8_t misc; 351 u_int8_t misc;
353 352
354 misc = mga_inb 353 misc = mga_inb(M_MISC_REG_READ) & ~0x0C;
355 switch (pll) { 354 switch (pll) {
356 case M 355 case M_PIXEL_PLL_A:
357 356 break;
358 case M 357 case M_PIXEL_PLL_B:
359 358 misc |= 0x04;
360 359 break;
361 defaul 360 default:
362 361 misc |= 0x0C;
363 362 break;
364 } 363 }
365 mga_outb(M_MIS 364 mga_outb(M_MISC_REG, misc);
366 } 365 }
367 pi = &ACCESS_FBINFO(li 366 pi = &ACCESS_FBINFO(limits.pixel);
368 ci = &ACCESS_FBINFO(ca 367 ci = &ACCESS_FBINFO(cache.pixel);
369 break; 368 break;
370 case M_SYSTEM_PLL: 369 case M_SYSTEM_PLL:
371 { 370 {
372 u_int32_t opt; 371 u_int32_t opt;
373 372
374 pci_read_confi 373 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, &opt);
375 if (!(opt & 0x 374 if (!(opt & 0x20)) {
376 pci_wr 375 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, opt | 0x20);
377 } 376 }
378 } 377 }
379 pi = &ACCESS_FBINFO(li 378 pi = &ACCESS_FBINFO(limits.system);
380 ci = &ACCESS_FBINFO(ca 379 ci = &ACCESS_FBINFO(cache.system);
381 break; 380 break;
382 case M_VIDEO_PLL: 381 case M_VIDEO_PLL:
383 { 382 {
384 u_int8_t tmp; 383 u_int8_t tmp;
385 unsigned int m 384 unsigned int mnp;
386 unsigned long 385 unsigned long flags;
387 386
388 matroxfb_DAC_l 387 matroxfb_DAC_lock_irqsave(flags);
389 tmp = matroxfb 388 tmp = matroxfb_DAC_in(PMINFO M1064_XPWRCTRL);
390 if (!(tmp & 2) 389 if (!(tmp & 2)) {
391 matrox 390 matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, tmp | 2);
392 } 391 }
393 392
394 mnp = matroxfb 393 mnp = matroxfb_DAC_in(PMINFO M1064_XPIXPLLCM) << 16;
395 mnp |= matroxf 394 mnp |= matroxfb_DAC_in(PMINFO M1064_XPIXPLLCN) << 8;
396 pixel_vco = g4 395 pixel_vco = g450_mnp2vco(PMINFO mnp);
397 matroxfb_DAC_u 396 matroxfb_DAC_unlock_irqrestore(flags);
398 } 397 }
399 pi = &ACCESS_FBINFO(li 398 pi = &ACCESS_FBINFO(limits.video);
400 ci = &ACCESS_FBINFO(ca 399 ci = &ACCESS_FBINFO(cache.video);
401 break; 400 break;
402 default: 401 default:
403 return -EINVAL; 402 return -EINVAL;
404 } 403 }
405 404
406 mnpcount = 0; 405 mnpcount = 0;
407 { 406 {
408 unsigned int mnp; 407 unsigned int mnp;
409 unsigned int xvco; 408 unsigned int xvco;
410 409
411 for(mnp = g450_firstpll(PMINFO 410 for(mnp = g450_firstpll(PMINFO pi, &xvco, fout); mnp != NO_MORE_MNP; mnp = g450_nextpll(PMINFO pi, &xvco, mnp)) {
412 unsigned int idx; 411 unsigned int idx;
413 unsigned int vco; 412 unsigned int vco;
414 unsigned int delta; 413 unsigned int delta;
415 414
416 vco = g450_mnp2vco(PMI 415 vco = g450_mnp2vco(PMINFO mnp);
417 #if 0 416 #if 0
418 if (pll == M_VIDEO_PLL 417 if (pll == M_VIDEO_PLL) {
419 unsigned int b 418 unsigned int big, small;
420 419
421 if (vco < pixe 420 if (vco < pixel_vco) {
422 small 421 small = vco;
423 big = 422 big = pixel_vco;
424 } else { 423 } else {
425 small 424 small = pixel_vco;
426 big = 425 big = vco;
427 } 426 }
428 while (big > s 427 while (big > small) {
429 big >> 428 big >>= 1;
430 } 429 }
431 if (big == sma 430 if (big == small) {
432 contin 431 continue;
433 } 432 }
434 } 433 }
435 #endif 434 #endif
436 delta = pll_freq_delta 435 delta = pll_freq_delta(fout, g450_vco2f(mnp, vco));
437 for (idx = mnpcount; i 436 for (idx = mnpcount; idx > 0; idx--) {
438 /* == is impor 437 /* == is important; due to nextpll algorithm we get
439 sorted equa 438 sorted equally good frequencies from lower VCO
440 frequency t 439 frequency to higher - with <= lowest wins, while
441 with < high 440 with < highest one wins */
442 if (delta <= d 441 if (delta <= deltaarray[idx-1]) {
443 /* all 442 /* all else being equal except VCO,
444 * cho 443 * choose VCO not near (within 1/16th or so) VCOmin
445 * (fr 444 * (freqs near VCOmin aren't as stable)
446 */ 445 */
447 if (de 446 if (delta == deltaarray[idx-1]
448 && 447 && vco != g450_mnp2vco(PMINFO mnparray[idx-1])
449 && 448 && vco < (pi->vcomin * 17 / 16)) {
450 449 break;
451 } 450 }
452 mnparr 451 mnparray[idx] = mnparray[idx-1];
453 deltaa 452 deltaarray[idx] = deltaarray[idx-1];
454 } else { 453 } else {
455 break; 454 break;
456 } 455 }
457 } 456 }
458 mnparray[idx] = mnp; 457 mnparray[idx] = mnp;
459 deltaarray[idx] = delt 458 deltaarray[idx] = delta;
460 mnpcount++; 459 mnpcount++;
461 } 460 }
462 } 461 }
463 /* VideoPLL and PixelPLL matched: do n 462 /* VideoPLL and PixelPLL matched: do nothing... In all other cases we should get at least one frequency */
464 if (!mnpcount) { 463 if (!mnpcount) {
465 return -EBUSY; 464 return -EBUSY;
466 } 465 }
467 { 466 {
468 unsigned long flags; 467 unsigned long flags;
469 unsigned int mnp; 468 unsigned int mnp;
470 469
471 matroxfb_DAC_lock_irqsave(flag 470 matroxfb_DAC_lock_irqsave(flags);
472 mnp = g450_checkcache(PMINFO c 471 mnp = g450_checkcache(PMINFO ci, mnparray[0]);
473 if (mnp != NO_MORE_MNP) { 472 if (mnp != NO_MORE_MNP) {
474 matroxfb_g450_setpll_c 473 matroxfb_g450_setpll_cond(PMINFO mnp, pll);
475 } else { 474 } else {
476 mnp = g450_findworking 475 mnp = g450_findworkingpll(PMINFO pll, mnparray, mnpcount);
477 g450_addcache(ci, mnpa 476 g450_addcache(ci, mnparray[0], mnp);
478 } 477 }
479 updatehwstate_clk(&ACCESS_FBIN 478 updatehwstate_clk(&ACCESS_FBINFO(hw), mnp, pll);
480 matroxfb_DAC_unlock_irqrestore 479 matroxfb_DAC_unlock_irqrestore(flags);
481 return mnp; 480 return mnp;
482 } 481 }
483 } 482 }
484 483
485 /* It must be greater than number of possible 484 /* It must be greater than number of possible PLL values.
486 * Currently there is 5(p) * 10(m) = 50 possib 485 * Currently there is 5(p) * 10(m) = 50 possible values. */
487 #define MNP_TABLE_SIZE 64 486 #define MNP_TABLE_SIZE 64
488 487
489 int matroxfb_g450_setclk(WPMINFO unsigned int 488 int matroxfb_g450_setclk(WPMINFO unsigned int fout, unsigned int pll) {
490 unsigned int* arr; 489 unsigned int* arr;
491 490
492 arr = kmalloc(sizeof(*arr) * MNP_TABLE 491 arr = kmalloc(sizeof(*arr) * MNP_TABLE_SIZE * 2, GFP_KERNEL);
493 if (arr) { 492 if (arr) {
494 int r; 493 int r;
495 494
496 r = __g450_setclk(PMINFO fout, 495 r = __g450_setclk(PMINFO fout, pll, arr, arr + MNP_TABLE_SIZE);
497 kfree(arr); 496 kfree(arr);
498 return r; 497 return r;
499 } 498 }
500 return -ENOMEM; 499 return -ENOMEM;
501 } 500 }
502 501
503 EXPORT_SYMBOL(matroxfb_g450_setclk); 502 EXPORT_SYMBOL(matroxfb_g450_setclk);
504 EXPORT_SYMBOL(g450_mnp2f); 503 EXPORT_SYMBOL(g450_mnp2f);
505 EXPORT_SYMBOL(matroxfb_g450_setpll_cond); 504 EXPORT_SYMBOL(matroxfb_g450_setpll_cond);
506 505
507 MODULE_AUTHOR("(c) 2001-2002 Petr Vandrovec <v 506 MODULE_AUTHOR("(c) 2001-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
508 MODULE_DESCRIPTION("Matrox G450/G550 PLL drive 507 MODULE_DESCRIPTION("Matrox G450/G550 PLL driver");
509 508
510 MODULE_LICENSE("GPL"); 509 MODULE_LICENSE("GPL");
511 510
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