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1 /* 1 /*
2 * Definitions for MCT (Magic Control Technolo 2 * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
3 * 3 *
4 * Copyright (C) 2000 Wolfgang Grandegger (w 4 * Copyright (C) 2000 Wolfgang Grandegger (wolfgang@ces.ch)
5 * 5 *
6 * This program is free software; you can re 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Pub 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either vers 8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version. 9 * (at your option) any later version.
10 * 10 *
11 * This driver is for the device MCT USB-RS232 11 * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No.
12 * U232-P25) from Magic Control Technology Cor 12 * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin
13 * Model No. U232-P9). See http://www.mct.com. 13 * Model No. U232-P9). See http://www.mct.com.tw/p_u232.html for further
14 * information. The properties of this device 14 * information. The properties of this device are listed at the end of this
15 * file. This device is available from various 15 * file. This device is available from various distributors. I know Hana,
16 * http://www.hana.de and D-Link, http://www.d 16 * http://www.hana.de and D-Link, http://www.dlink.com/products/usb/dsbs25.
17 * 17 *
18 * All of the information about the device was 18 * All of the information about the device was acquired by using SniffUSB
19 * on Windows98. The technical details of the 19 * on Windows98. The technical details of the reverse engineering are
20 * summarized at the end of this file. 20 * summarized at the end of this file.
21 */ 21 */
22 22
23 #ifndef __LINUX_USB_SERIAL_MCT_U232_H 23 #ifndef __LINUX_USB_SERIAL_MCT_U232_H
24 #define __LINUX_USB_SERIAL_MCT_U232_H 24 #define __LINUX_USB_SERIAL_MCT_U232_H
25 25
26 #define MCT_U232_VID 0x0711 26 #define MCT_U232_VID 0x0711 /* Vendor Id */
27 #define MCT_U232_PID 0x0210 27 #define MCT_U232_PID 0x0210 /* Original MCT Product Id */
28 28
29 /* U232-P25, Sitecom */ 29 /* U232-P25, Sitecom */
30 #define MCT_U232_SITECOM_PID 0x0230 30 #define MCT_U232_SITECOM_PID 0x0230 /* Sitecom Product Id */
31 31
32 /* DU-H3SP USB BAY hub */ 32 /* DU-H3SP USB BAY hub */
33 #define MCT_U232_DU_H3SP_PID 0x0200 33 #define MCT_U232_DU_H3SP_PID 0x0200 /* D-Link DU-H3SP USB BAY */
34 34
35 /* Belkin badge the MCT U232-P9 as the F5U109 35 /* Belkin badge the MCT U232-P9 as the F5U109 */
36 #define MCT_U232_BELKIN_F5U109_VID 0x050d 36 #define MCT_U232_BELKIN_F5U109_VID 0x050d /* Vendor Id */
37 #define MCT_U232_BELKIN_F5U109_PID 0x0109 37 #define MCT_U232_BELKIN_F5U109_PID 0x0109 /* Product Id */
38 38
39 /* 39 /*
40 * Vendor Request Interface 40 * Vendor Request Interface
41 */ 41 */
42 #define MCT_U232_SET_REQUEST_TYPE 0x40 42 #define MCT_U232_SET_REQUEST_TYPE 0x40
43 #define MCT_U232_GET_REQUEST_TYPE 0xc0 43 #define MCT_U232_GET_REQUEST_TYPE 0xc0
44 44
45 #define MCT_U232_GET_MODEM_STAT_REQUEST 2 /* 45 #define MCT_U232_GET_MODEM_STAT_REQUEST 2 /* Get Modem Status Register (MSR) */
46 #define MCT_U232_GET_MODEM_STAT_SIZE 1 46 #define MCT_U232_GET_MODEM_STAT_SIZE 1
47 47
48 #define MCT_U232_GET_LINE_CTRL_REQUEST 6 /* 48 #define MCT_U232_GET_LINE_CTRL_REQUEST 6 /* Get Line Control Register (LCR) */
49 #define MCT_U232_GET_LINE_CTRL_SIZE 1 /* 49 #define MCT_U232_GET_LINE_CTRL_SIZE 1 /* ... not used by this driver */
50 50
51 #define MCT_U232_SET_BAUD_RATE_REQUEST 5 /* 51 #define MCT_U232_SET_BAUD_RATE_REQUEST 5 /* Set Baud Rate Divisor */
52 #define MCT_U232_SET_BAUD_RATE_SIZE 4 52 #define MCT_U232_SET_BAUD_RATE_SIZE 4
53 53
54 #define MCT_U232_SET_LINE_CTRL_REQUEST 7 /* 54 #define MCT_U232_SET_LINE_CTRL_REQUEST 7 /* Set Line Control Register (LCR) */
55 #define MCT_U232_SET_LINE_CTRL_SIZE 1 55 #define MCT_U232_SET_LINE_CTRL_SIZE 1
56 56
57 #define MCT_U232_SET_MODEM_CTRL_REQUEST 10 /* 57 #define MCT_U232_SET_MODEM_CTRL_REQUEST 10 /* Set Modem Control Register (MCR) */
58 #define MCT_U232_SET_MODEM_CTRL_SIZE 1 58 #define MCT_U232_SET_MODEM_CTRL_SIZE 1
59 59
60 /* This USB device request code is not well un 60 /* This USB device request code is not well understood. It is transmitted by
61 the MCT-supplied Windows driver whenever th 61 the MCT-supplied Windows driver whenever the baud rate changes.
62 */ 62 */
63 #define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* 63 #define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* Unknown functionality */
64 #define MCT_U232_SET_UNKNOWN1_SIZE 1 64 #define MCT_U232_SET_UNKNOWN1_SIZE 1
65 65
66 /* This USB device request code appears to con !! 66 /* This USB device request code is not well understood. It is transmitted by
67 during transmission. !! 67 the MCT-supplied Windows driver whenever the baud rate changes.
68 68
69 Sending a zero byte allows data transmissio !! 69 Without this USB device request, the USB/RS-232 adapter will not write to
70 asserting CTS. Sending a '1' byte will cau !! 70 RS-232 devices which do not assert the 'CTS' signal.
71 until the device asserts CTS. <<
72 */ 71 */
73 #define MCT_U232_SET_CTS_REQUEST 12 !! 72 #define MCT_U232_SET_UNKNOWN2_REQUEST 12 /* Unknown functionality */
74 #define MCT_U232_SET_CTS_SIZE 1 !! 73 #define MCT_U232_SET_UNKNOWN2_SIZE 1
75 74
76 /* 75 /*
77 * Baud rate (divisor) 76 * Baud rate (divisor)
78 * Actually, there are two of them, MCT websit 77 * Actually, there are two of them, MCT website calls them "Philips solution"
79 * and "Intel solution". They are the regular 78 * and "Intel solution". They are the regular MCT and "Sitecom" for us.
80 * This is pointless to document in the header 79 * This is pointless to document in the header, see the code for the bits.
81 */ 80 */
82 static int mct_u232_calculate_baud_rate(struct !! 81 static int mct_u232_calculate_baud_rate(struct usb_serial *serial, int value);
83 82
84 /* 83 /*
85 * Line Control Register (LCR) 84 * Line Control Register (LCR)
86 */ 85 */
87 #define MCT_U232_SET_BREAK 0x40 86 #define MCT_U232_SET_BREAK 0x40
88 87
89 #define MCT_U232_PARITY_SPACE 0x38 88 #define MCT_U232_PARITY_SPACE 0x38
90 #define MCT_U232_PARITY_MARK 0x28 89 #define MCT_U232_PARITY_MARK 0x28
91 #define MCT_U232_PARITY_EVEN 0x18 90 #define MCT_U232_PARITY_EVEN 0x18
92 #define MCT_U232_PARITY_ODD 0x08 91 #define MCT_U232_PARITY_ODD 0x08
93 #define MCT_U232_PARITY_NONE 0x00 92 #define MCT_U232_PARITY_NONE 0x00
94 93
95 #define MCT_U232_DATA_BITS_5 0x00 94 #define MCT_U232_DATA_BITS_5 0x00
96 #define MCT_U232_DATA_BITS_6 0x01 95 #define MCT_U232_DATA_BITS_6 0x01
97 #define MCT_U232_DATA_BITS_7 0x02 96 #define MCT_U232_DATA_BITS_7 0x02
98 #define MCT_U232_DATA_BITS_8 0x03 97 #define MCT_U232_DATA_BITS_8 0x03
99 98
100 #define MCT_U232_STOP_BITS_2 0x04 99 #define MCT_U232_STOP_BITS_2 0x04
101 #define MCT_U232_STOP_BITS_1 0x00 100 #define MCT_U232_STOP_BITS_1 0x00
102 101
103 /* 102 /*
104 * Modem Control Register (MCR) 103 * Modem Control Register (MCR)
105 */ 104 */
106 #define MCT_U232_MCR_NONE 0x8 105 #define MCT_U232_MCR_NONE 0x8 /* Deactivate DTR and RTS */
107 #define MCT_U232_MCR_RTS 0xa 106 #define MCT_U232_MCR_RTS 0xa /* Activate RTS */
108 #define MCT_U232_MCR_DTR 0x9 107 #define MCT_U232_MCR_DTR 0x9 /* Activate DTR */
109 108
110 /* 109 /*
111 * Modem Status Register (MSR) 110 * Modem Status Register (MSR)
112 */ 111 */
113 #define MCT_U232_MSR_INDEX 0x0 112 #define MCT_U232_MSR_INDEX 0x0 /* data[index] */
114 #define MCT_U232_MSR_CD 0x80 113 #define MCT_U232_MSR_CD 0x80 /* Current CD */
115 #define MCT_U232_MSR_RI 0x40 114 #define MCT_U232_MSR_RI 0x40 /* Current RI */
116 #define MCT_U232_MSR_DSR 0x20 115 #define MCT_U232_MSR_DSR 0x20 /* Current DSR */
117 #define MCT_U232_MSR_CTS 0x10 116 #define MCT_U232_MSR_CTS 0x10 /* Current CTS */
118 #define MCT_U232_MSR_DCD 0x08 117 #define MCT_U232_MSR_DCD 0x08 /* Delta CD */
119 #define MCT_U232_MSR_DRI 0x04 118 #define MCT_U232_MSR_DRI 0x04 /* Delta RI */
120 #define MCT_U232_MSR_DDSR 0x02 119 #define MCT_U232_MSR_DDSR 0x02 /* Delta DSR */
121 #define MCT_U232_MSR_DCTS 0x01 120 #define MCT_U232_MSR_DCTS 0x01 /* Delta CTS */
122 121
123 /* 122 /*
124 * Line Status Register (LSR) 123 * Line Status Register (LSR)
125 */ 124 */
126 #define MCT_U232_LSR_INDEX 1 125 #define MCT_U232_LSR_INDEX 1 /* data[index] */
127 #define MCT_U232_LSR_ERR 0x80 126 #define MCT_U232_LSR_ERR 0x80 /* OE | PE | FE | BI */
128 #define MCT_U232_LSR_TEMT 0x40 127 #define MCT_U232_LSR_TEMT 0x40 /* transmit register empty */
129 #define MCT_U232_LSR_THRE 0x20 128 #define MCT_U232_LSR_THRE 0x20 /* transmit holding register empty */
130 #define MCT_U232_LSR_BI 0x10 129 #define MCT_U232_LSR_BI 0x10 /* break indicator */
131 #define MCT_U232_LSR_FE 0x08 130 #define MCT_U232_LSR_FE 0x08 /* framing error */
132 #define MCT_U232_LSR_OE 0x02 131 #define MCT_U232_LSR_OE 0x02 /* overrun error */
133 #define MCT_U232_LSR_PE 0x04 132 #define MCT_U232_LSR_PE 0x04 /* parity error */
134 #define MCT_U232_LSR_OE 0x02 133 #define MCT_U232_LSR_OE 0x02 /* overrun error */
135 #define MCT_U232_LSR_DR 0x01 134 #define MCT_U232_LSR_DR 0x01 /* receive data ready */
136 135
137 136
138 /* ------------------------------------------- 137 /* -----------------------------------------------------------------------------
139 * Technical Specification reverse engineered 138 * Technical Specification reverse engineered with SniffUSB on Windows98
140 * =========================================== 139 * =====================================================================
141 * 140 *
142 * The technical details of the device have b 141 * The technical details of the device have been acquired be using "SniffUSB"
143 * and the vendor-supplied device driver (ver 142 * and the vendor-supplied device driver (version 2.3A) under Windows98. To
144 * identify the USB vendor-specific requests 143 * identify the USB vendor-specific requests and to assign them to terminal
145 * settings (flow control, baud rate, etc.) t 144 * settings (flow control, baud rate, etc.) the program "SerialSettings" from
146 * William G. Greathouse has been proven to b 145 * William G. Greathouse has been proven to be very useful. I also used the
147 * Win98 "HyperTerminal" and "usb-robot" on L 146 * Win98 "HyperTerminal" and "usb-robot" on Linux for testing. The results and
148 * observations are summarized below: 147 * observations are summarized below:
149 * 148 *
150 * The USB requests seem to be directly mappe 149 * The USB requests seem to be directly mapped to the registers of a 8250,
151 * 16450 or 16550 UART. The FreeBSD handbook 150 * 16450 or 16550 UART. The FreeBSD handbook (appendix F.4 "Input/Output
152 * devices") contains a comprehensive descrip 151 * devices") contains a comprehensive description of UARTs and its registers.
153 * The bit descriptions are actually taken fr 152 * The bit descriptions are actually taken from there.
154 * 153 *
155 * 154 *
156 * Baud rate (divisor) 155 * Baud rate (divisor)
157 * ------------------- 156 * -------------------
158 * 157 *
159 * BmRequestType: 0x40 (0100 0000B) 158 * BmRequestType: 0x40 (0100 0000B)
160 * bRequest: 0x05 159 * bRequest: 0x05
161 * wValue: 0x0000 160 * wValue: 0x0000
162 * wIndex: 0x0000 161 * wIndex: 0x0000
163 * wLength: 0x0004 162 * wLength: 0x0004
164 * Data: divisor = 115200 / baud_r 163 * Data: divisor = 115200 / baud_rate
165 * 164 *
166 * SniffUSB observations (Nov 2003): Contrar 165 * SniffUSB observations (Nov 2003): Contrary to the 'wLength' value of 4
167 * shown above, observations with a Belkin F 166 * shown above, observations with a Belkin F5U109 adapter, using the
168 * MCT-supplied Windows98 driver (U2SPORT.VX 167 * MCT-supplied Windows98 driver (U2SPORT.VXD, "File version: 1.21P.0104 for
169 * Win98/Me"), show this request has a lengt 168 * Win98/Me"), show this request has a length of 1 byte, presumably because
170 * of the fact that the Belkin adapter and t 169 * of the fact that the Belkin adapter and the 'Sitecom U232-P25' adapter
171 * use a baud-rate code instead of a convent 170 * use a baud-rate code instead of a conventional RS-232 baud rate divisor.
172 * The current source code for this driver d 171 * The current source code for this driver does not reflect this fact, but
173 * the driver works fine with this adapter/d 172 * the driver works fine with this adapter/driver combination nonetheless.
174 * 173 *
175 * 174 *
176 * Line Control Register (LCR) 175 * Line Control Register (LCR)
177 * --------------------------- 176 * ---------------------------
178 * 177 *
179 * BmRequestType: 0x40 (0100 0000B) 0xc0 178 * BmRequestType: 0x40 (0100 0000B) 0xc0 (1100 0000B)
180 * bRequest: 0x07 0x06 179 * bRequest: 0x07 0x06
181 * wValue: 0x0000 180 * wValue: 0x0000
182 * wIndex: 0x0000 181 * wIndex: 0x0000
183 * wLength: 0x0001 182 * wLength: 0x0001
184 * Data: LCR (see below) 183 * Data: LCR (see below)
185 * 184 *
186 * Bit 7: Divisor Latch Access Bit (DLAB). Wh 185 * Bit 7: Divisor Latch Access Bit (DLAB). When set, access to the data
187 * transmit/receive register (THR/RBR) 186 * transmit/receive register (THR/RBR) and the Interrupt Enable Register
188 * (IER) is disabled. Any access to th 187 * (IER) is disabled. Any access to these ports is now redirected to the
189 * Divisor Latch Registers. Setting th 188 * Divisor Latch Registers. Setting this bit, loading the Divisor
190 * Registers, and clearing DLAB should 189 * Registers, and clearing DLAB should be done with interrupts disabled.
191 * Bit 6: Set Break. When set to "1", the tra 190 * Bit 6: Set Break. When set to "1", the transmitter begins to transmit
192 * continuous Spacing until this bit i 191 * continuous Spacing until this bit is set to "". This overrides any
193 * bits of characters that are being t 192 * bits of characters that are being transmitted.
194 * Bit 5: Stick Parity. When parity is enable 193 * Bit 5: Stick Parity. When parity is enabled, setting this bit causes parity
195 * to always be "1" or "", based on th 194 * to always be "1" or "", based on the value of Bit 4.
196 * Bit 4: Even Parity Select (EPS). When pari 195 * Bit 4: Even Parity Select (EPS). When parity is enabled and Bit 5 is "",
197 * setting this bit causes even parity 196 * setting this bit causes even parity to be transmitted and expected.
198 * Otherwise, odd parity is used. 197 * Otherwise, odd parity is used.
199 * Bit 3: Parity Enable (PEN). When set to "1 198 * Bit 3: Parity Enable (PEN). When set to "1", a parity bit is inserted
200 * between the last bit of the data an 199 * between the last bit of the data and the Stop Bit. The UART will also
201 * expect parity to be present in the 200 * expect parity to be present in the received data.
202 * Bit 2: Number of Stop Bits (STB). If set t 201 * Bit 2: Number of Stop Bits (STB). If set to "1" and using 5-bit data words,
203 * 1.5 Stop Bits are transmitted and e 202 * 1.5 Stop Bits are transmitted and expected in each data word. For
204 * 6, 7 and 8-bit data words, 2 Stop B 203 * 6, 7 and 8-bit data words, 2 Stop Bits are transmitted and expected.
205 * When this bit is set to "", one Sto 204 * When this bit is set to "", one Stop Bit is used on each data word.
206 * Bit 1: Word Length Select Bit #1 (WLSB1) 205 * Bit 1: Word Length Select Bit #1 (WLSB1)
207 * Bit 0: Word Length Select Bit #0 (WLSB0) 206 * Bit 0: Word Length Select Bit #0 (WLSB0)
208 * Together these bits specify the num 207 * Together these bits specify the number of bits in each data word.
209 * 1 0 Word Length 208 * 1 0 Word Length
210 * 0 0 5 Data Bits 209 * 0 0 5 Data Bits
211 * 0 1 6 Data Bits 210 * 0 1 6 Data Bits
212 * 1 0 7 Data Bits 211 * 1 0 7 Data Bits
213 * 1 1 8 Data Bits 212 * 1 1 8 Data Bits
214 * 213 *
215 * SniffUSB observations: Bit 7 seems not to 214 * SniffUSB observations: Bit 7 seems not to be used. There seem to be two bugs
216 * in the Win98 driver: the break does not wo 215 * in the Win98 driver: the break does not work (bit 6 is not asserted) and the
217 * stick parity bit is not cleared when set o 216 * stick parity bit is not cleared when set once. The LCR can also be read
218 * back with USB request 6 but this has never 217 * back with USB request 6 but this has never been observed with SniffUSB.
219 * 218 *
220 * 219 *
221 * Modem Control Register (MCR) 220 * Modem Control Register (MCR)
222 * ---------------------------- 221 * ----------------------------
223 * 222 *
224 * BmRequestType: 0x40 (0100 0000B) 223 * BmRequestType: 0x40 (0100 0000B)
225 * bRequest: 0x0a 224 * bRequest: 0x0a
226 * wValue: 0x0000 225 * wValue: 0x0000
227 * wIndex: 0x0000 226 * wIndex: 0x0000
228 * wLength: 0x0001 227 * wLength: 0x0001
229 * Data: MCR (Bit 4..7, see below) 228 * Data: MCR (Bit 4..7, see below)
230 * 229 *
231 * Bit 7: Reserved, always 0. 230 * Bit 7: Reserved, always 0.
232 * Bit 6: Reserved, always 0. 231 * Bit 6: Reserved, always 0.
233 * Bit 5: Reserved, always 0. 232 * Bit 5: Reserved, always 0.
234 * Bit 4: Loop-Back Enable. When set to "1", 233 * Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver
235 * are internally connected together t 234 * are internally connected together to allow diagnostic operations. In
236 * addition, the UART modem control ou 235 * addition, the UART modem control outputs are connected to the UART
237 * modem control inputs. CTS is connec 236 * modem control inputs. CTS is connected to RTS, DTR is connected to
238 * DSR, OUT1 is connected to RI, and O 237 * DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD.
239 * Bit 3: OUT 2. An auxiliary output that the 238 * Bit 3: OUT 2. An auxiliary output that the host processor may set high or
240 * low. In the IBM PC serial adapter ( 239 * low. In the IBM PC serial adapter (and most clones), OUT 2 is used
241 * to tri-state (disable) the interrup 240 * to tri-state (disable) the interrupt signal from the
242 * 8250/16450/16550 UART. 241 * 8250/16450/16550 UART.
243 * Bit 2: OUT 1. An auxiliary output that the 242 * Bit 2: OUT 1. An auxiliary output that the host processor may set high or
244 * low. This output is not used on the 243 * low. This output is not used on the IBM PC serial adapter.
245 * Bit 1: Request to Send (RTS). When set to 244 * Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS
246 * line is Low (Active). 245 * line is Low (Active).
247 * Bit 0: Data Terminal Ready (DTR). When set 246 * Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART
248 * -DTR line is Low (Active). 247 * -DTR line is Low (Active).
249 * 248 *
250 * SniffUSB observations: Bit 2 and 4 seem no 249 * SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been
251 * seen _always_ set. 250 * seen _always_ set.
252 * 251 *
253 * 252 *
254 * Modem Status Register (MSR) 253 * Modem Status Register (MSR)
255 * --------------------------- 254 * ---------------------------
256 * 255 *
257 * BmRequestType: 0xc0 (1100 0000B) 256 * BmRequestType: 0xc0 (1100 0000B)
258 * bRequest: 0x02 257 * bRequest: 0x02
259 * wValue: 0x0000 258 * wValue: 0x0000
260 * wIndex: 0x0000 259 * wIndex: 0x0000
261 * wLength: 0x0001 260 * wLength: 0x0001
262 * Data: MSR (see below) 261 * Data: MSR (see below)
263 * 262 *
264 * Bit 7: Data Carrier Detect (CD). Reflects 263 * Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the
265 * UART. 264 * UART.
266 * Bit 6: Ring Indicator (RI). Reflects the s 265 * Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART.
267 * Bit 5: Data Set Ready (DSR). Reflects the 266 * Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART.
268 * Bit 4: Clear To Send (CTS). Reflects the s 267 * Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART.
269 * Bit 3: Delta Data Carrier Detect (DDCD). S 268 * Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has
270 * changed state one more more times s 269 * changed state one more more times since the last time the MSR was
271 * read by the host. 270 * read by the host.
272 * Bit 2: Trailing Edge Ring Indicator (TERI) 271 * Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has
273 * had a low to high transition since 272 * had a low to high transition since the last time the MSR was read by
274 * the host. 273 * the host.
275 * Bit 1: Delta Data Set Ready (DDSR). Set to 274 * Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed
276 * state one more more times since the 275 * state one more more times since the last time the MSR was read by the
277 * host. 276 * host.
278 * Bit 0: Delta Clear To Send (DCTS). Set to 277 * Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed
279 * state one more times since the last 278 * state one more times since the last time the MSR was read by the
280 * host. 279 * host.
281 * 280 *
282 * SniffUSB observations: the MSR is also ret 281 * SniffUSB observations: the MSR is also returned as first byte on the
283 * interrupt-in endpoint 0x83 to signal chang 282 * interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB
284 * request to read MSR cannot be applied duri 283 * request to read MSR cannot be applied during normal device operation.
285 * 284 *
286 * 285 *
287 * Line Status Register (LSR) 286 * Line Status Register (LSR)
288 * -------------------------- 287 * --------------------------
289 * 288 *
290 * Bit 7 Error in Receiver FIFO. On the 825 289 * Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero.
291 * This bit is set to "1" when any of 290 * This bit is set to "1" when any of the bytes in the FIFO have one or
292 * more of the following error condit 291 * more of the following error conditions: PE, FE, or BI.
293 * Bit 6 Transmitter Empty (TEMT). When set 292 * Bit 6 Transmitter Empty (TEMT). When set to "1", there are no words
294 * remaining in the transmit FIFO or 293 * remaining in the transmit FIFO or the transmit shift register. The
295 * transmitter is completely idle. 294 * transmitter is completely idle.
296 * Bit 5 Transmitter Holding Register Empty 295 * Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the FIFO
297 * (or holding register) now has room 296 * (or holding register) now has room for at least one additional word
298 * to transmit. The transmitter may s 297 * to transmit. The transmitter may still be transmitting when this bit
299 * is set to "1". 298 * is set to "1".
300 * Bit 4 Break Interrupt (BI). The receiver 299 * Bit 4 Break Interrupt (BI). The receiver has detected a Break signal.
301 * Bit 3 Framing Error (FE). A Start Bit wa 300 * Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did not
302 * appear at the expected time. The r 301 * appear at the expected time. The received word is probably garbled.
303 * Bit 2 Parity Error (PE). The parity bit 302 * Bit 2 Parity Error (PE). The parity bit was incorrect for the word received.
304 * Bit 1 Overrun Error (OE). A new word was 303 * Bit 1 Overrun Error (OE). A new word was received and there was no room in
305 * the receive buffer. The newly-arri 304 * the receive buffer. The newly-arrived word in the shift register is
306 * discarded. On 8250/16450 UARTs, th 305 * discarded. On 8250/16450 UARTs, the word in the holding register is
307 * discarded and the newly- arrived w 306 * discarded and the newly- arrived word is put in the holding register.
308 * Bit 0 Data Ready (DR). One or more words 307 * Bit 0 Data Ready (DR). One or more words are in the receive FIFO that the
309 * host may read. A word must be comp 308 * host may read. A word must be completely received and moved from the
310 * shift register into the FIFO (or h 309 * shift register into the FIFO (or holding register for 8250/16450
311 * designs) before this bit is set. 310 * designs) before this bit is set.
312 * 311 *
313 * SniffUSB observations: the LSR is returned 312 * SniffUSB observations: the LSR is returned as second byte on the interrupt-in
314 * endpoint 0x83 to signal error conditions. 313 * endpoint 0x83 to signal error conditions. Such errors have been seen with
315 * minicom/zmodem transfers (CRC errors). 314 * minicom/zmodem transfers (CRC errors).
316 * 315 *
317 * 316 *
318 * Unknown #1 317 * Unknown #1
319 * ------------------- 318 * -------------------
320 * 319 *
321 * BmRequestType: 0x40 (0100 0000B) 320 * BmRequestType: 0x40 (0100 0000B)
322 * bRequest: 0x0b 321 * bRequest: 0x0b
323 * wValue: 0x0000 322 * wValue: 0x0000
324 * wIndex: 0x0000 323 * wIndex: 0x0000
325 * wLength: 0x0001 324 * wLength: 0x0001
326 * Data: 0x00 325 * Data: 0x00
327 * 326 *
328 * SniffUSB observations (Nov 2003): With th 327 * SniffUSB observations (Nov 2003): With the MCT-supplied Windows98 driver
329 * (U2SPORT.VXD, "File version: 1.21P.0104 f 328 * (U2SPORT.VXD, "File version: 1.21P.0104 for Win98/Me"), this request
330 * occurs immediately after a "Baud rate (di 329 * occurs immediately after a "Baud rate (divisor)" message. It was not
331 * observed at any other time. It is unclea 330 * observed at any other time. It is unclear what purpose this message
332 * serves. 331 * serves.
333 * 332 *
334 * 333 *
335 * Unknown #2 334 * Unknown #2
336 * ------------------- 335 * -------------------
337 * 336 *
338 * BmRequestType: 0x40 (0100 0000B) 337 * BmRequestType: 0x40 (0100 0000B)
339 * bRequest: 0x0c 338 * bRequest: 0x0c
340 * wValue: 0x0000 339 * wValue: 0x0000
341 * wIndex: 0x0000 340 * wIndex: 0x0000
342 * wLength: 0x0001 341 * wLength: 0x0001
343 * Data: 0x00 342 * Data: 0x00
344 * 343 *
345 * SniffUSB observations (Nov 2003): With th 344 * SniffUSB observations (Nov 2003): With the MCT-supplied Windows98 driver
346 * (U2SPORT.VXD, "File version: 1.21P.0104 f 345 * (U2SPORT.VXD, "File version: 1.21P.0104 for Win98/Me"), this request
347 * occurs immediately after the 'Unknown #1' 346 * occurs immediately after the 'Unknown #1' message (see above). It was
348 * not observed at any other time. It is un 347 * not observed at any other time. It is unclear what other purpose (if
349 * any) this message might serve, but withou 348 * any) this message might serve, but without it, the USB/RS-232 adapter
350 * will not write to RS-232 devices which do 349 * will not write to RS-232 devices which do not assert the 'CTS' signal.
351 * 350 *
352 * 351 *
353 * Flow control 352 * Flow control
354 * ------------ 353 * ------------
355 * 354 *
356 * SniffUSB observations: no flow control spe 355 * SniffUSB observations: no flow control specific requests have been realized
357 * apart from DTR/RTS settings. Both signals 356 * apart from DTR/RTS settings. Both signals are dropped for no flow control
358 * but asserted for hardware or software flow 357 * but asserted for hardware or software flow control.
359 * 358 *
360 * 359 *
361 * Endpoint usage 360 * Endpoint usage
362 * -------------- 361 * --------------
363 * 362 *
364 * SniffUSB observations: the bulk-out endpoi 363 * SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint
365 * 0x81 is used to transmit and receive chara 364 * 0x81 is used to transmit and receive characters. The second interrupt-in
366 * endpoint 0x83 signals exceptional conditio 365 * endpoint 0x83 signals exceptional conditions like modem line changes and
367 * errors. The first byte returned is the MSR 366 * errors. The first byte returned is the MSR and the second byte the LSR.
368 * 367 *
369 * 368 *
370 * Other observations 369 * Other observations
371 * ------------------ 370 * ------------------
372 * 371 *
373 * Queued bulk transfers like used in visor.c 372 * Queued bulk transfers like used in visor.c did not work.
374 * 373 *
375 * 374 *
376 * Properties of the USB device used (as found 375 * Properties of the USB device used (as found in /var/log/messages)
377 * ------------------------------------------- 376 * -----------------------------------------------------------------
378 * 377 *
379 * Manufacturer: MCT Corporation. 378 * Manufacturer: MCT Corporation.
380 * Product: USB-232 Interfact Controller 379 * Product: USB-232 Interfact Controller
381 * SerialNumber: U2S22050 380 * SerialNumber: U2S22050
382 * 381 *
383 * Length = 18 382 * Length = 18
384 * DescriptorType = 01 383 * DescriptorType = 01
385 * USB version = 1.00 384 * USB version = 1.00
386 * Vendor:Product = 0711:0210 385 * Vendor:Product = 0711:0210
387 * MaxPacketSize0 = 8 386 * MaxPacketSize0 = 8
388 * NumConfigurations = 1 387 * NumConfigurations = 1
389 * Device version = 1.02 388 * Device version = 1.02
390 * Device Class:SubClass:Protocol = 00:00:0 389 * Device Class:SubClass:Protocol = 00:00:00
391 * Per-interface classes 390 * Per-interface classes
392 * Configuration: 391 * Configuration:
393 * bLength = 9 392 * bLength = 9
394 * bDescriptorType = 02 393 * bDescriptorType = 02
395 * wTotalLength = 0027 394 * wTotalLength = 0027
396 * bNumInterfaces = 01 395 * bNumInterfaces = 01
397 * bConfigurationValue = 01 396 * bConfigurationValue = 01
398 * iConfiguration = 00 397 * iConfiguration = 00
399 * bmAttributes = c0 398 * bmAttributes = c0
400 * MaxPower = 100mA 399 * MaxPower = 100mA
401 * 400 *
402 * Interface: 0 401 * Interface: 0
403 * Alternate Setting: 0 402 * Alternate Setting: 0
404 * bLength = 9 403 * bLength = 9
405 * bDescriptorType = 04 404 * bDescriptorType = 04
406 * bInterfaceNumber = 00 405 * bInterfaceNumber = 00
407 * bAlternateSetting = 00 406 * bAlternateSetting = 00
408 * bNumEndpoints = 03 407 * bNumEndpoints = 03
409 * bInterface Class:SubClass:Protocol = 408 * bInterface Class:SubClass:Protocol = 00:00:00
410 * iInterface = 00 409 * iInterface = 00
411 * Endpoint: 410 * Endpoint:
412 * bLength = 7 411 * bLength = 7
413 * bDescriptorType = 05 412 * bDescriptorType = 05
414 * bEndpointAddress = 81 (in) 413 * bEndpointAddress = 81 (in)
415 * bmAttributes = 03 (Interrup 414 * bmAttributes = 03 (Interrupt)
416 * wMaxPacketSize = 0040 415 * wMaxPacketSize = 0040
417 * bInterval = 02 416 * bInterval = 02
418 * Endpoint: 417 * Endpoint:
419 * bLength = 7 418 * bLength = 7
420 * bDescriptorType = 05 419 * bDescriptorType = 05
421 * bEndpointAddress = 01 (out) 420 * bEndpointAddress = 01 (out)
422 * bmAttributes = 02 (Bulk) 421 * bmAttributes = 02 (Bulk)
423 * wMaxPacketSize = 0040 422 * wMaxPacketSize = 0040
424 * bInterval = 00 423 * bInterval = 00
425 * Endpoint: 424 * Endpoint:
426 * bLength = 7 425 * bLength = 7
427 * bDescriptorType = 05 426 * bDescriptorType = 05
428 * bEndpointAddress = 83 (in) 427 * bEndpointAddress = 83 (in)
429 * bmAttributes = 03 (Interrup 428 * bmAttributes = 03 (Interrupt)
430 * wMaxPacketSize = 0002 429 * wMaxPacketSize = 0002
431 * bInterval = 02 430 * bInterval = 02
432 * 431 *
433 * 432 *
434 * Hardware details (added by Martin Hamilton, 433 * Hardware details (added by Martin Hamilton, 2001/12/06)
435 * ------------------------------------------- 434 * -----------------------------------------------------------------
436 * 435 *
437 * This info was gleaned from opening a Belkin 436 * This info was gleaned from opening a Belkin F5U109 DB9 USB serial
438 * adaptor, which turns out to simply be a re- 437 * adaptor, which turns out to simply be a re-badged U232-P9. We
439 * know this because there is a sticky label o 438 * know this because there is a sticky label on the circuit board
440 * which says "U232-P9" ;-) 439 * which says "U232-P9" ;-)
441 * 440 *
442 * The circuit board inside the adaptor contai 441 * The circuit board inside the adaptor contains a Philips PDIUSBD12
443 * USB endpoint chip and a Philips P87C52UBAA !! 442 * USB endpoint chip and a Phillips P87C52UBAA microcontroller with
444 * embedded UART. Exhaustive documentation fo 443 * embedded UART. Exhaustive documentation for these is available at:
445 * 444 *
446 * http://www.semiconductors.philips.com/pip 445 * http://www.semiconductors.philips.com/pip/p87c52ubaa
447 * http://www.semiconductors.philips.com/pip 446 * http://www.semiconductors.philips.com/pip/pdiusbd12
448 * 447 *
449 * Thanks to Julian Highfield for the pointer 448 * Thanks to Julian Highfield for the pointer to the Philips database.
450 * 449 *
451 */ 450 */
452 451
453 #endif /* __LINUX_USB_SERIAL_MCT_U232_H */ 452 #endif /* __LINUX_USB_SERIAL_MCT_U232_H */
454 453
455 454
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