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1 /** 1
2 * Driver for Altera PCIe core chaining DMA re
3 *
4 * Copyright (C) 2008 Leon Woestenberg <leon.
5 * Copyright (C) 2008 Nickolas Heppermann <he
6 *
7 * This program is free software; you can redi
8 * it under the terms of the GNU General Publi
9 * the Free Software Foundation; either versio
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope tha
13 * but WITHOUT ANY WARRANTY; without even the
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR
15 * GNU General Public License for more details
16 *
17 * You should have received a copy of the GNU
18 * with this program; if not, write to the Fre
19 * 51 Franklin Street, Fifth Floor, Boston, MA
20 *
21 *
22 * Rationale: This driver exercises the chaini
23 * in the reference design. It is meant as a c
24 * driver that can be used for testing early d
25 * write your custom driver.
26 *
27 * Status: Test results from Leon Woestenberg
28 *
29 * Sendero Board w/ Cyclone II EP2C35F672C6N,
30 * Dell Precision 370 PC, x86, kernel 2.6.20 f
31 *
32 * Sendero Board w/ Cyclone II EP2C35F672C6N,
33 * Freescale MPC8313E-RDB board, PowerPC, 2.6.
34 *
35 * Driver tests passed with PCIe Compiler 8.1.
36 * loopback test had reproducable compare erro
37 * in the compiler or reference design, but co
38 * documentation on a change or fix in that di
39 *
40 * The reference design does not have readable
41 * dummy read, used to flush PCI posted writes
42 *
43 */
44
45 #include <linux/kernel.h>
46 #include <linux/cdev.h>
47 #include <linux/delay.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/init.h>
50 #include <linux/interrupt.h>
51 #include <linux/io.h>
52 #include <linux/jiffies.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55
56
57 /* by default do not build the character devic
58 /* XXX It is non-functional yet */
59 #ifndef ALTPCIECHDMA_CDEV
60 # define ALTPCIECHDMA_CDEV 0
61 #endif
62
63 /* build the character device interface? */
64 #if ALTPCIECHDMA_CDEV
65 # define MAX_CHDMA_SIZE (8 * 1024 * 1024)
66 # include "mapper_user_to_sg.h"
67 #endif
68
69 /** driver name, mimicks Altera naming of the
70 #define DRV_NAME "altpciechdma"
71 /** number of BARs on the device */
72 #define APE_BAR_NUM (6)
73 /** BAR number where the RCSLAVE memory sits *
74 #define APE_BAR_RCSLAVE (0)
75 /** BAR number where the Descriptor Header sit
76 #define APE_BAR_HEADER (2)
77
78 /** maximum size in bytes of the descriptor ta
79 #define APE_CHDMA_TABLE_SIZE (4096)
80 /* single transfer must not exceed 255 table e
81 * achieved by 255 scattered pages, with only
82 * tail pages. 253 * PAGE_SIZE is a safe upper
83 */
84 #define APE_CHDMA_MAX_TRANSFER_LEN (253 * PAGE
85
86 /**
87 * Specifies those BARs to be mapped and the l
88 *
89 * Zero (0) means do not map, otherwise specif
90 * If the actual BAR length is less, this is c
91 * reconfigure your PCIe core.
92 *
93 * @see ug_pci_express 8.0, table 7-2 at page
94 */
95 static const unsigned long bar_min_len[APE_BAR
96 { 32768, 0, 256, 0, 32768, 0 };
97
98 /**
99 * Descriptor Header, controls the DMA read en
100 *
101 * The descriptor header is the main data stru
102 *
103 * It sits in End Point (FPGA) memory BAR[2] f
104 * It references a descriptor table which exis
105 * Writing the rclast field starts the DMA ope
106 * and fields must be setup before doing so.
107 *
108 * @see ug_pci_express 8.0, tables 7-3, 7-4 an
109 * @note This header must be written in four 3
110 */
111 struct ape_chdma_header {
112 /**
113 * w0 consists of two 16-bit fields:
114 * lsb u16 number; number of descripto
115 * msb u16 control; global control fla
116 */
117 u32 w0;
118 /* bus address to ape_chdma_table in R
119 u32 bdt_addr_h;
120 u32 bdt_addr_l;
121 /**
122 * w3 consists of two 16-bit fields:
123 * - lsb u16 rclast; last descriptor n
124 * - zero (0) means the first descr
125 * - one (1) means two descriptors
126 * - msb u16 reserved;
127 *
128 * @note writing to this memory locati
129 */
130 u32 w3;
131 } __attribute__ ((packed));
132
133 /**
134 * Descriptor Entry, describing a (non-scatter
135 *
136 * There is one descriptor for each memory blo
137 * block being a contiguous address range on t
138 *
139 * Multiple descriptors are chained by means o
140 * structure.
141 *
142 * @see ug_pci_express 8.0, tables 7-6, 7-7 an
143 */
144 struct ape_chdma_desc {
145 /**
146 * w0 consists of two 16-bit fields:
147 * number of DWORDS to transfer
148 * - lsb u16 length;
149 * global control
150 * - msb u16 control;
151 */
152 u32 w0;
153 /* address of memory in the End Point
154 u32 ep_addr;
155 /* bus address of source or destinatio
156 u32 rc_addr_h;
157 u32 rc_addr_l;
158 } __attribute__ ((packed));
159
160 /**
161 * Descriptor Table, an array of descriptors d
162 *
163 * An array of descriptors, preceded by worksp
164 * It exists in Root Complex memory.
165 *
166 * The End Point can update its last completed
167 * eplast field if requested by setting the EP
168 * globally in the header's or locally in any
169 *
170 * @note this structure may not exceed 4096 by
171 * maximum of 4096 / (4 * 4) - 1 = 255 descrip
172 *
173 * @see ug_pci_express 8.0, tables 7-9, 7-10 a
174 */
175 struct ape_chdma_table {
176 /* workspace 0x00-0x0b, reserved */
177 u32 reserved1[3];
178 /* workspace 0x0c-0x0f, last descripto
179 u32 w3;
180 /* the actual array of descriptors
181 * 0x10-0x1f, 0x20-0x2f, ... 0xff0-0xfff (2
182 */
183 struct ape_chdma_desc desc[255];
184 } __attribute__ ((packed));
185
186 /**
187 * Altera PCI Express ('ape') board specific b
188 *
189 * Keeps state of the PCIe core and the Chaini
190 * application.
191 */
192 struct ape_dev {
193 /** the kernel pci device data structu
194 struct pci_dev *pci_dev;
195 /**
196 * kernel virtual address of the mappe
197 * the End Point. Used by map_bars()/u
198 */
199 void * __iomem bar[APE_BAR_NUM];
200 /** kernel virtual address for Descrip
201 struct ape_chdma_table *table_virt;
202 /**
203 * bus address for the Descriptor Tabl
204 * CPU-native endianess
205 */
206 dma_addr_t table_bus;
207 /* if the device regions could not be
208 * is in use by another driver; this d
209 */
210 int in_use;
211 /* whether this driver enabled msi for
212 int msi_enabled;
213 /* whether this driver could obtain th
214 int got_regions;
215 /* irq line succesfully requested by t
216 int irq_line;
217 /* board revision */
218 u8 revision;
219 /* interrupt count, incremented by the
220 int irq_count;
221 #if ALTPCIECHDMA_CDEV
222 /* character device */
223 dev_t cdevno;
224 struct cdev cdev;
225 /* user space scatter gather mapper */
226 struct sg_mapping_t *sgm;
227 #endif
228 };
229
230 /**
231 * Using the subsystem vendor id and subsystem
232 * distinguish between different cards bases a
233 * (third-party) logic core.
234 *
235 * Default Altera vendor and device ID's, and
236 * ID's are now used here that are used amongs
237 */
238 static const struct pci_device_id ids[] = {
239 { PCI_DEVICE(0x1172, 0xE001), },
240 { PCI_DEVICE(0x2071, 0x2071), },
241 { 0, }
242 };
243 MODULE_DEVICE_TABLE(pci, ids);
244
245 #if ALTPCIECHDMA_CDEV
246 /* prototypes for character device */
247 static int sg_init(struct ape_dev *ape);
248 static void sg_exit(struct ape_dev *ape);
249 #endif
250
251 /**
252 * altpciechdma_isr() - Interrupt handler
253 *
254 */
255 static irqreturn_t altpciechdma_isr(int irq, v
256 {
257 struct ape_dev *ape = (struct ape_dev
258 if (!ape)
259 return IRQ_NONE;
260 ape->irq_count++;
261 return IRQ_HANDLED;
262 }
263
264 static int __devinit scan_bars(struct ape_dev
265 {
266 int i;
267 for (i = 0; i < APE_BAR_NUM; i++) {
268 unsigned long bar_start = pci_
269 if (bar_start) {
270 unsigned long bar_end
271 unsigned long bar_flag
272 printk(KERN_DEBUG "BAR
273 i, bar_start, bar_en
274 }
275 }
276 return 0;
277 }
278
279 /**
280 * Unmap the BAR regions that had been mapped
281 */
282 static void unmap_bars(struct ape_dev *ape, st
283 {
284 int i;
285 for (i = 0; i < APE_BAR_NUM; i++) {
286 /* is this BAR mapped? */
287 if (ape->bar[i]) {
288 /* unmap BAR */
289 pci_iounmap(dev, ape->
290 ape->bar[i] = NULL;
291 }
292 }
293 }
294
295 /**
296 * Map the device memory regions into kernel v
297 * verifying their sizes respect the minimum s
298 * bar_min_len[] array.
299 */
300 static int __devinit map_bars(struct ape_dev *
301 {
302 int rc;
303 int i;
304 /* iterate through all the BARs */
305 for (i = 0; i < APE_BAR_NUM; i++) {
306 unsigned long bar_start = pci_
307 unsigned long bar_end = pci_re
308 unsigned long bar_length = bar
309 ape->bar[i] = NULL;
310 /* do not map, and skip, BARs
311 if (!bar_min_len[i])
312 continue;
313 /* do not map BARs with addres
314 if (!bar_start || !bar_end) {
315 printk(KERN_DEBUG "BAR
316 rc = -1;
317 goto fail;
318 }
319 bar_length = bar_end - bar_sta
320 /* BAR length is less than dri
321 if (bar_length < bar_min_len[i
322 printk(KERN_DEBUG "BAR
323 "requires at least %lu
324 i, bar_length, bar_min
325 rc = -1;
326 goto fail;
327 }
328 /* map the device memory or IO
329 * address space */
330 ape->bar[i] = pci_iomap(dev, i
331 if (!ape->bar[i]) {
332 printk(KERN_DEBUG "Cou
333 rc = -1;
334 goto fail;
335 }
336 printk(KERN_DEBUG "BAR[%d] map
337 ape->bar[i], bar_min_len[i], b
338 }
339 /* succesfully mapped all required BAR
340 rc = 0;
341 goto success;
342 fail:
343 /* unmap any BARs that we did map */
344 unmap_bars(ape, dev);
345 success:
346 return rc;
347 }
348
349 #if 0 /* not yet implemented fully FIXME add o
350 static void __devinit rcslave_test(struct ape_
351 {
352 u32 *rcslave_mem = (u32 *)ape->bar[APE
353 u32 result = 0;
354 /** this number is assumed to be diffe
355 u32 seed = (u32)jiffies;
356 u32 value = seed;
357 int i;
358
359 /* write loop */
360 value = seed;
361 for (i = 1024; i < 32768 / 4 ; i++) {
362 printk(KERN_DEBUG "Writing 0x%
363 (u32)value, (void *)rc
364 iowrite32(value, rcslave_mem +
365 value++;
366 }
367 /* read-back loop */
368 value = seed;
369 for (i = 1024; i < 32768 / 4; i++) {
370 result = ioread32(rcslave_mem
371 if (result != value) {
372 printk(KERN_DEBUG "Wro
373 (u32)value, (v
374 break;
375 }
376 value++;
377 }
378 }
379 #endif
380
381 /* obtain the 32 most significant (high) bits
382 #define pci_dma_h(addr) ((addr >> 16) >> 16)
383 /* obtain the 32 least significant (low) bits
384 #define pci_dma_l(addr) (addr & 0xffffffffUL)
385
386 /* ape_fill_chdma_desc() - Fill a Altera PCI E
387 *
388 * @desc pointer to descriptor to be filled
389 * @addr root complex address
390 * @ep_addr end point address
391 * @len number of bytes, must be a multiple of
392 */
393 static inline void ape_chdma_desc_set(struct a
394 {
395 BUG_ON(len & 3);
396 desc->w0 = cpu_to_le32(len / 4);
397 desc->ep_addr = cpu_to_le32(ep_addr);
398 desc->rc_addr_h = cpu_to_le32(pci_dma_
399 desc->rc_addr_l = cpu_to_le32(pci_dma_
400 }
401
402 #if ALTPCIECHDMA_CDEV
403 /*
404 * ape_sg_to_chdma_table() - Create a device d
405 *
406 * The scatterlist must have been mapped by pc
407 *
408 * @sgl scatterlist.
409 * @nents Number of entries in the scatterlist
410 * @first Start index in the scatterlist sgm->
411 * @ep_addr End Point address for the scatter/
412 * @desc pointer to first descriptor
413 *
414 * Returns Number of entries in the table on s
415 */
416 static int ape_sg_to_chdma_table(struct scatte
417 {
418 int i = first, j = 0;
419 /* inspect first entry */
420 dma_addr_t addr = sg_dma_address(&sgl[
421 unsigned int len = sg_dma_len(&sgl[i])
422 /* contiguous block */
423 dma_addr_t cont_addr = addr;
424 unsigned int cont_len = len;
425 /* iterate over remaining entries */
426 for (; j < 25 && i < nents - 1; i++) {
427 /* bus address of next entry i
428 dma_addr_t next = sg_dma_addre
429 /* length of this entry i */
430 len = sg_dma_len(&sgl[i]);
431 printk(KERN_DEBUG "%04d: addr=
432 (unsigned long long)ad
433 /* entry i + 1 is non-contiguo
434 if (next != addr + len) {
435 /* TODO create entry h
436 printk(KERN_DEBUG "%4d
437 (unsigned long
438 /* set descriptor for
439 ape_chdma_desc_set(&de
440 /* next end point memo
441 ep_addr += cont_len;
442 /* start new contiguou
443 cont_addr = next;
444 cont_len = 0;
445 j++;
446 }
447 /* add entry i + 1 to current
448 cont_len += len;
449 /* goto entry i + 1 */
450 addr = next;
451 }
452 /* TODO create entry here (we could o
453 printk(KERN_DEBUG "%04d: addr=0x%Lx le
454 (unsigned long long)addr, len)
455 printk(KERN_DEBUG "%4d: cont_addr=0x%L
456 (unsigned long long)cont_addr,
457 j++;
458 return j;
459 }
460 #endif
461
462 /* compare buffers */
463 static inline int compare(u32 *p, u32 *q, int
464 {
465 int result = -1;
466 int fail = 0;
467 int i;
468 for (i = 0; i < len / 4; i++) {
469 if (*p == *q) {
470 /* every so many u32 w
471 if ((i & 255) == 0)
472 printk(KERN_DE
473 } else {
474 fail++;
475 /* show the first few
476 if (fail < 10)
477 printk(KERN_DE
478 /* but stop af
479 else if (fail == 10)
480 printk(KERN_DE
481 else
482 /* stop compar
483 break;
484 }
485 p++;
486 q++;
487 }
488 if (!fail)
489 result = 0;
490 return result;
491 }
492
493 /* dma_test() - Perform DMA loop back test to
494 *
495 * Allocate a cache-coherent buffer in host me
496 *
497 * Fill the four memory pages such that each 3
498 *
499 * Now perform a loop back test, have the end
500 * half to end point memory, then have it copy
501 *
502 * Create a descriptor table to copy the fir
503 * memory. Instruct the End Point to do a DM
504 *
505 * Create a descriptor table to copy End Poi
506 * half. Instruct the End Point to do a DMA
507 *
508 * Compare results, fail or pass.
509 *
510 */
511 static int __devinit dma_test(struct ape_dev *
512 {
513 /* test result; guilty until proven in
514 int result = -1;
515 /* the DMA read header sits at address
516 struct ape_chdma_header *write_header
517 /* the write DMA header sits after the
518 struct ape_chdma_header *read_header =
519 /* virtual address of the allocated bu
520 u8 *buffer_virt = 0;
521 /* bus address of the allocated buffer
522 dma_addr_t buffer_bus = 0;
523 int i, n = 0, irq_count;
524
525 /* temporary value used to construct 3
526 u32 w;
527
528 printk(KERN_DEBUG "bar_tests(), PAGE_S
529 printk(KERN_DEBUG "write_header = 0x%p
530 printk(KERN_DEBUG "read_header = 0x%p.
531 printk(KERN_DEBUG "&write_header->w3 =
532 printk(KERN_DEBUG "&read_header->w3 =
533 printk(KERN_DEBUG "ape->table_virt = 0
534
535 if (!write_header || !read_header || !
536 goto fail;
537
538 /* allocate and map coherently-cached
539 /* @see Documentation/PCI/PCI-DMA-mapp
540 buffer_virt = (u8 *)pci_alloc_consiste
541 if (!buffer_virt) {
542 printk(KERN_DEBUG "Could not a
543 goto fail;
544 }
545 printk(KERN_DEBUG "Allocated cache-coh
546 buffer_virt, (u64)buffer_bus);
547
548 /* fill first half of buffer with its
549 for (i = 0; i < 4 * PAGE_SIZE; i += 4)
550 #if 0
551 *(u32 *)(buffer_virt + i) = i
552 #else
553 *(u32 *)(buffer_virt + i) = (b
554 #endif
555 #if 0
556 compare((u32 *)buffer_virt, (u32 *)(buffer_v
557 #endif
558
559 #if 0
560 /* fill second half of buffer with zer
561 for (i = 2 * PAGE_SIZE; i < 4 * PAGE_S
562 *(u32 *)(buffer_virt + i) = 0;
563 #endif
564
565 /* invalidate EPLAST, outside 0-255, 0
566 ape->table_virt->w3 = cpu_to_le32(0x00
567
568 /* fill in first descriptor */
569 n = 0;
570 /* read 8192 bytes from RC buffer to E
571 ape_chdma_desc_set(&ape->table_virt->d
572 #if 1
573 for (i = 0; i < 255; i++)
574 ape_chdma_desc_set(&ape->table
575 /* index of last descriptor */
576 n = i - 1;
577 #endif
578 #if 0
579 /* fill in next descriptor */
580 n++;
581 /* read 1024 bytes from RC buffer to E
582 ape_chdma_desc_set(&ape->table_virt->d
583 #endif
584
585 #if 1
586 /* enable MSI after the last descripto
587 if (ape->msi_enabled)
588 ape->table_virt->desc[n].w0 |=
589 #endif
590 #if 0
591 /* dump descriptor table for debugging
592 printk(KERN_DEBUG "Descriptor Table (R
593 for (i = 0; i < 4 + (n + 1) * 4; i +=
594 u32 *p = (u32 *)ape->table_vir
595 p += i;
596 printk(KERN_DEBUG "0x%08x/0x%0
597 p++;
598 printk(KERN_DEBUG "0x%08x/0x%0
599 p++;
600 printk(KERN_DEBUG "0x%08x/0x%0
601 p++;
602 printk(KERN_DEBUG "0x%08x/0x%0
603 }
604 #endif
605 /* set available number of descriptors
606 w = (u32)(n + 1);
607 w |= (1UL << 18)/*global EPLAST_EN*/;
608 #if 0
609 if (ape->msi_enabled)
610 w |= (1UL << 17)/*global MSI*/
611 #endif
612 printk(KERN_DEBUG "writing 0x%08x to 0
613 iowrite32(w, &read_header->w0);
614
615 /* write table address (higher 32-bits
616 printk(KERN_DEBUG "writing 0x%08x to 0
617 iowrite32(pci_dma_h(ape->table_bus), &
618
619 /* write table address (lower 32-bits)
620 printk(KERN_DEBUG "writing 0x%08x to 0
621 iowrite32(pci_dma_l(ape->table_bus), &
622
623 /* memory write barrier */
624 wmb();
625 printk(KERN_DEBUG "Flush posted writes
626 /** FIXME Add dummy read to flush post
627 #if 0
628 (void)ioread32();
629 #endif
630
631 /* remember IRQ count before the trans
632 irq_count = ape->irq_count;
633 /* write number of descriptors - this
634 printk(KERN_DEBUG "\nStart DMA read\n"
635 printk(KERN_DEBUG "writing 0x%08x to 0
636 iowrite32(n, &read_header->w3);
637 printk(KERN_DEBUG "EPLAST = %lu\n", le
638
639 /** memory write barrier */
640 wmb();
641 /* dummy read to flush posted writes *
642 /* FIXME Need a readable location! */
643 #if 0
644 (void)ioread32();
645 #endif
646 printk(KERN_DEBUG "POLL FOR READ:\n");
647 /* poll for chain completion, 1000 tim
648 for (i = 0; i < 100; i++) {
649 volatile u32 *p = &ape->table_
650 u32 eplast = le32_to_cpu(*p) &
651 printk(KERN_DEBUG "EPLAST = %u
652 if (eplast == n) {
653 printk(KERN_DEBUG "DON
654 /* print IRQ count bef
655 printk(KERN_DEBUG "#IR
656 break;
657 }
658 udelay(100);
659 }
660
661 /* invalidate EPLAST, outside 0-255, 0
662 ape->table_virt->w3 = cpu_to_le32(0x00
663
664 /* setup first descriptor */
665 n = 0;
666 ape_chdma_desc_set(&ape->table_virt->d
667 #if 1
668 for (i = 0; i < 255; i++)
669 ape_chdma_desc_set(&ape->table
670
671 /* index of last descriptor */
672 n = i - 1;
673 #endif
674 #if 1 /* test variable, make a module option l
675 if (ape->msi_enabled)
676 ape->table_virt->desc[n].w0 |=
677 #endif
678 #if 0
679 /* dump descriptor table for debugging
680 printk(KERN_DEBUG "Descriptor Table (W
681 for (i = 0; i < 4 + (n + 1) * 4; i +=
682 u32 *p = (u32 *)ape->table_vir
683 p += i;
684 printk(KERN_DEBUG "0x%08x/0x%0
685 p++;
686 printk(KERN_DEBUG "0x%08x/0x%0
687 p++;
688 printk(KERN_DEBUG "0x%08x/0x%0
689 p++;
690 printk(KERN_DEBUG "0x%08x/0x%0
691 }
692 #endif
693
694 /* set number of available descriptors
695 w = (u32)(n + 1);
696 /* enable updates of eplast for each d
697 w |= (u32)(1UL << 18)/*global EPLAST_E
698 #if 0 /* test variable, make a module option
699 /* enable MSI for each descriptor comp
700 if (ape->msi_enabled)
701 w |= (1UL << 17)/*global MSI*/
702 #endif
703 iowrite32(w, &write_header->w0);
704 iowrite32(pci_dma_h(ape->table_bus), &
705 iowrite32(pci_dma_l(ape->table_bus), &
706
707 /** memory write barrier and flush pos
708 wmb();
709 /* dummy read to flush posted writes *
710 /* FIXME Need a readable location! */
711 #if 0
712 (void)ioread32();
713 #endif
714 irq_count = ape->irq_count;
715
716 printk(KERN_DEBUG "\nStart DMA write\n
717 iowrite32(n, &write_header->w3);
718
719 /** memory write barrier */
720 wmb();
721 /** dummy read to flush posted writes
722 /* (void) ioread32(); */
723
724 printk(KERN_DEBUG "POLL FOR WRITE:\n")
725 /* poll for completion, 1000 times 1 m
726 for (i = 0; i < 100; i++) {
727 volatile u32 *p = &ape->table_
728 u32 eplast = le32_to_cpu(*p) &
729 printk(KERN_DEBUG "EPLAST = %u
730 if (eplast == n) {
731 printk(KERN_DEBUG "DON
732 /* print IRQ count bef
733 printk(KERN_DEBUG "#IR
734 break;
735 }
736 udelay(100);
737 }
738 /* soft-reset DMA write engine */
739 iowrite32(0x0000ffffUL, &write_header-
740 /* soft-reset DMA read engine */
741 iowrite32(0x0000ffffUL, &read_header->
742
743 /** memory write barrier */
744 wmb();
745 /* dummy read to flush posted writes *
746 /* FIXME Need a readable location! */
747 #if 0
748 (void)ioread32();
749 #endif
750 /* compare first half of buffer with s
751 result = compare((u32 *)buffer_virt, (
752 printk(KERN_DEBUG "DMA loop back test
753
754 pci_free_consistent(dev, 4 * PAGE_SIZE
755 fail:
756 printk(KERN_DEBUG "bar_tests() end, re
757 return result;
758 }
759
760 /* Called when the PCI sub system thinks we ca
761 * Inspect if we can support the device and if
762 *
763 * Return 0 when we have taken control of the
764 *
765 * - allocate board specific bookkeeping
766 * - allocate coherently-mapped memory for the
767 * - enable the board
768 * - verify board revision
769 * - request regions
770 * - query DMA mask
771 * - obtain and request irq
772 * - map regions into kernel address space
773 */
774 static int __devinit probe(struct pci_dev *dev
775 {
776 int rc = 0;
777 struct ape_dev *ape = NULL;
778 u8 irq_pin, irq_line;
779 printk(KERN_DEBUG "probe(dev = 0x%p, p
780
781 /* allocate memory for per-board book
782 ape = kzalloc(sizeof(struct ape_dev),
783 if (!ape) {
784 printk(KERN_DEBUG "Could not k
785 goto err_ape;
786 }
787 ape->pci_dev = dev;
788 dev_set_drvdata(&dev->dev, ape);
789 printk(KERN_DEBUG "probe() ape = 0x%p\
790
791 printk(KERN_DEBUG "sizeof(struct ape_c
792 (int)sizeof(struct ape_chdma_t
793 /* the reference design has a size res
794 BUG_ON(sizeof(struct ape_chdma_table)
795
796 /* allocate and map coherently-cached
797 /* @see LDD3 page 446 */
798 ape->table_virt = (struct ape_chdma_ta
799 APE_CHDMA_TABLE_SIZE, &ape->ta
800 /* could not allocate table? */
801 if (!ape->table_virt) {
802 printk(KERN_DEBUG "Could not d
803 goto err_table;
804 }
805
806 printk(KERN_DEBUG "table_virt = %p, ta
807 ape->table_virt, (u64)ape->tab
808
809 /* enable device */
810 rc = pci_enable_device(dev);
811 if (rc) {
812 printk(KERN_DEBUG "pci_enable_
813 goto err_enable;
814 }
815
816 /* enable bus master capability on dev
817 pci_set_master(dev);
818 /* enable message signaled interrupts
819 rc = pci_enable_msi(dev);
820 /* could not use MSI? */
821 if (rc) {
822 /* resort to legacy interrupts
823 printk(KERN_DEBUG "Could not e
824 ape->msi_enabled = 0;
825 /* MSI enabled, remember for cleanup *
826 } else {
827 printk(KERN_DEBUG "Enabled MSI
828 ape->msi_enabled = 1;
829 }
830
831 pci_read_config_byte(dev, PCI_REVISION
832 #if 0 /* example */
833 /* (for example) this driver does not
834 if (ape->revision == 0x42) {
835 printk(KERN_DEBUG "Revision 0x
836 rc = -ENODEV;
837 goto err_rev;
838 }
839 #endif
840 /** XXX check for native or legacy PCI
841
842 rc = pci_request_regions(dev, DRV_NAME
843 /* could not request all regions? */
844 if (rc) {
845 /* assume device is in use (an
846 ape->in_use = 1;
847 goto err_regions;
848 }
849 ape->got_regions = 1;
850
851 #if 1 /* @todo For now, disable 64-bit, beca
852 /* query for DMA transfer */
853 /* @see Documentation/PCI/PCI-DMA-mapp
854 if (!pci_set_dma_mask(dev, DMA_BIT_MAS
855 pci_set_consistent_dma_mask(de
856 /* use 64-bit DMA */
857 printk(KERN_DEBUG "Using a 64-
858 } else
859 #endif
860 if (!pci_set_dma_mask(dev, DMA_BIT_MAS
861 printk(KERN_DEBUG "Could not s
862 pci_set_consistent_dma_mask(de
863 /* use 32-bit DMA */
864 printk(KERN_DEBUG "Using a 32-
865 } else {
866 printk(KERN_DEBUG "No suitable
867 /** @todo Choose proper error
868 rc = -1;
869 goto err_mask;
870 }
871
872 rc = pci_read_config_byte(dev, PCI_INT
873 /* could not read? */
874 if (rc)
875 goto err_irq;
876 printk(KERN_DEBUG "IRQ pin #%d (0=none
877
878 /* @see LDD3, page 318 */
879 rc = pci_read_config_byte(dev, PCI_INT
880 /* could not read? */
881 if (rc) {
882 printk(KERN_DEBUG "Could not q
883 goto err_irq;
884 }
885 printk(KERN_DEBUG "IRQ line #%d.\n", i
886 #if 1
887 irq_line = dev->irq;
888 /* @see LDD3, page 259 */
889 rc = request_irq(irq_line, altpciechdm
890 if (rc) {
891 printk(KERN_DEBUG "Could not r
892 ape->irq_line = -1;
893 goto err_irq;
894 }
895 /* remember which irq we allocated */
896 ape->irq_line = (int)irq_line;
897 printk(KERN_DEBUG "Succesfully request
898 #endif
899 /* show BARs */
900 scan_bars(ape, dev);
901 /* map BARs */
902 rc = map_bars(ape, dev);
903 if (rc)
904 goto err_map;
905 #if ALTPCIECHDMA_CDEV
906 /* initialize character device */
907 rc = sg_init(ape);
908 if (rc)
909 goto err_cdev;
910 #endif
911 /* perform DMA engines loop back test
912 rc = dma_test(ape, dev);
913 (void)rc;
914 /* succesfully took the device */
915 rc = 0;
916 printk(KERN_DEBUG "probe() successful.
917 goto end;
918 #if ALTPCIECHDMA_CDEV
919 err_cdev:
920 /* unmap the BARs */
921 unmap_bars(ape, dev);
922 #endif
923 err_map:
924 /* free allocated irq */
925 if (ape->irq_line >= 0)
926 free_irq(ape->irq_line, (void
927 err_irq:
928 if (ape->msi_enabled)
929 pci_disable_msi(dev);
930 /* disable the device iff it is not in
931 if (!ape->in_use)
932 pci_disable_device(dev);
933 if (ape->got_regions)
934 pci_release_regions(dev);
935 err_mask:
936 err_regions:
937 /*err_rev:*/
938 /* clean up everything before device enable()
939 err_enable:
940 if (ape->table_virt)
941 pci_free_consistent(dev, APE_C
942 /* clean up everything before allocating descr
943 err_table:
944 if (ape)
945 kfree(ape);
946 err_ape:
947 end:
948 return rc;
949 }
950
951 static void __devexit remove(struct pci_dev *d
952 {
953 struct ape_dev *ape = dev_get_drvdata(
954
955 printk(KERN_DEBUG "remove(0x%p)\n", de
956 printk(KERN_DEBUG "remove(dev = 0x%p)
957
958 /* remove character device */
959 #if ALTPCIECHDMA_CDEV
960 sg_exit(ape);
961 #endif
962
963 if (ape->table_virt)
964 pci_free_consistent(dev, APE_C
965
966 /* free IRQ
967 * @see LDD3 page 279
968 */
969 if (ape->irq_line >= 0) {
970 printk(KERN_DEBUG "Freeing IRQ
971 ape->irq_line, (unsigned long)
972 free_irq(ape->irq_line, (void
973 }
974 /* MSI was enabled? */
975 if (ape->msi_enabled) {
976 /* Disable MSI @see Documentat
977 pci_disable_msi(dev);
978 ape->msi_enabled = 0;
979 }
980 /* unmap the BARs */
981 unmap_bars(ape, dev);
982 if (!ape->in_use)
983 pci_disable_device(dev);
984 if (ape->got_regions)
985 /* to be called after device d
986 pci_release_regions(dev);
987 }
988
989 #if ALTPCIECHDMA_CDEV
990
991 /*
992 * Called when the device goes from unused to
993 */
994 static int sg_open(struct inode *inode, struct
995 {
996 struct ape_dev *ape;
997 printk(KERN_DEBUG DRV_NAME "_open()\n"
998 /* pointer to containing data structur
999 ape = container_of(inode->i_cdev, stru
1000 /* create a reference to our device s
1001 file->private_data = ape;
1002 /* create virtual memory mapper */
1003 ape->sgm = sg_create_mapper(MAX_CHDMA
1004 return 0;
1005 }
1006
1007 /*
1008 * Called when the device goes from used to u
1009 */
1010 static int sg_close(struct inode *inode, stru
1011 {
1012 /* fetch device specific data stored
1013 struct ape_dev *ape = (struct ape_dev
1014 printk(KERN_DEBUG DRV_NAME "_close()\
1015 /* destroy virtual memory mapper */
1016 sg_destroy_mapper(ape->sgm);
1017 return 0;
1018 }
1019
1020 static ssize_t sg_read(struct file *file, cha
1021 {
1022 /* fetch device specific data stored
1023 struct ape_dev *ape = (struct ape_dev
1024 (void)ape;
1025 printk(KERN_DEBUG DRV_NAME "_read(buf
1026 return count;
1027 }
1028
1029 /* sg_write() - Write to the device
1030 *
1031 * @buf userspace buffer
1032 * @count number of bytes in the userspace bu
1033 *
1034 * Iterate over the userspace buffer, taking
1035 * each DMA transfer.
1036 * For each transfer, get the user pages, b
1037 * descriptor table. submit the transfer. w
1038 * to wake us on completion.
1039 */
1040 static ssize_t sg_write(struct file *file, co
1041 {
1042 int hwnents, tents;
1043 size_t transfer_len, remaining = coun
1044 u64 transfer_addr = (u64)buf;
1045 /* fetch device specific data stored
1046 struct ape_dev *ape = (struct ape_dev
1047 printk(KERN_DEBUG DRV_NAME "_write(bu
1048 buf, (s64)count, (u64)*pos);
1049 /* TODO transfer boundaries at PAGE_S
1050 while (remaining > 0) {
1051 /* limit DMA transfer size */
1052 transfer_len = (remaining < A
1053 APE_CHDMA_MAX_TRANSFE
1054 /* get all user space buffer
1055 sgm_map_user_pages(ape->sgm,
1056 printk(KERN_DEBUG DRV_NAME "m
1057 /* map all entries in the sca
1058 hwnents = pci_map_sg(ape->pci
1059 printk(KERN_DEBUG DRV_NAME "h
1060 /* build device descriptor ta
1061 tents = ape_sg_to_chdma_table
1062 printk(KERN_DEBUG DRV_NAME "t
1063 #if 0
1064 while (tables) {
1065 /* TODO build table *
1066 /* TODO submit table
1067 /* if engine stopped
1068 }
1069 put ourselves on wait queue
1070 #endif
1071
1072 dma_unmap_sg(NULL, ape->sgm->
1073 /* dirty and free the pages *
1074 sgm_unmap_user_pages(ape->sgm
1075 /* book keeping */
1076 transfer_addr += transfer_len
1077 remaining -= transfer_len;
1078 done += transfer_len;
1079 }
1080 return done;
1081 }
1082
1083 /*
1084 * character device file operations
1085 */
1086 static const struct file_operations sg_fops =
1087 .owner = THIS_MODULE,
1088 .open = sg_open,
1089 .release = sg_close,
1090 .read = sg_read,
1091 .write = sg_write,
1092 };
1093
1094 /* sg_init() - Initialize character device
1095 *
1096 * XXX Should ideally be tied to the device,
1097 */
1098 static int sg_init(struct ape_dev *ape)
1099 {
1100 int rc;
1101 printk(KERN_DEBUG DRV_NAME " sg_init(
1102 /* allocate a dynamically allocated c
1103 rc = alloc_chrdev_region(&ape->cdevno
1104 /* allocation failed? */
1105 if (rc < 0) {
1106 printk("alloc_chrdev_region()
1107 goto fail_alloc;
1108 }
1109 /* couple the device file operations
1110 cdev_init(&ape->cdev, &sg_fops);
1111 ape->cdev.owner = THIS_MODULE;
1112 /* bring character device live */
1113 rc = cdev_add(&ape->cdev, ape->cdevno
1114 if (rc < 0) {
1115 printk("cdev_add() = %d\n", r
1116 goto fail_add;
1117 }
1118 printk(KERN_DEBUG "altpciechdma = %d:
1119 return 0;
1120 fail_add:
1121 /* free the dynamically allocated cha
1122 unregister_chrdev_region(ape->cdevno, 1/*
1123 fail_alloc:
1124 return -1;
1125 }
1126
1127 /* sg_exit() - Cleanup character device
1128 *
1129 * XXX Should ideally be tied to the device,
1130 */
1131
1132 static void sg_exit(struct ape_dev *ape)
1133 {
1134 printk(KERN_DEBUG DRV_NAME " sg_exit(
1135 /* remove the character device */
1136 cdev_del(&ape->cdev);
1137 /* free the dynamically allocated cha
1138 unregister_chrdev_region(ape->cdevno,
1139 }
1140
1141 #endif /* ALTPCIECHDMA_CDEV */
1142
1143 /* used to register the driver with the PCI k
1144 * @see LDD3 page 311
1145 */
1146 static struct pci_driver pci_driver = {
1147 .name = DRV_NAME,
1148 .id_table = ids,
1149 .probe = probe,
1150 .remove = __devexit_p(remove),
1151 /* resume, suspend are optional */
1152 };
1153
1154 /**
1155 * alterapciechdma_init() - Module initializa
1156 */
1157 static int __init alterapciechdma_init(void)
1158 {
1159 int rc = 0;
1160 printk(KERN_DEBUG DRV_NAME " init(),
1161 /* register this driver with the PCI
1162 rc = pci_register_driver(&pci_driver)
1163 if (rc < 0)
1164 return rc;
1165 return 0;
1166 }
1167
1168 /**
1169 * alterapciechdma_init() - Module cleanup, u
1170 */
1171 static void __exit alterapciechdma_exit(void)
1172 {
1173 printk(KERN_DEBUG DRV_NAME " exit(),
1174 /* unregister this driver from the PC
1175 pci_unregister_driver(&pci_driver);
1176 }
1177
1178 MODULE_LICENSE("GPL");
1179
1180 module_init(alterapciechdma_init);
1181 module_exit(alterapciechdma_exit);
1182
1183
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