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1 /* 1 /*
2 * Sonics Silicon Backplane 2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver 3 * Broadcom PCI-core driver
4 * 4 *
5 * Copyright 2005, Broadcom Corporation 5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 * 7 *
8 * Licensed under the GNU/GPL. See COPYING for 8 * Licensed under the GNU/GPL. See COPYING for details.
9 */ 9 */
10 10
11 #include <linux/ssb/ssb.h> 11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h> 12 #include <linux/pci.h>
13 #include <linux/delay.h> 13 #include <linux/delay.h>
14 #include <linux/ssb/ssb_embedded.h> 14 #include <linux/ssb/ssb_embedded.h>
15 15
16 #include "ssb_private.h" 16 #include "ssb_private.h"
17 17
18 18
19 static inline 19 static inline
20 u32 pcicore_read32(struct ssb_pcicore *pc, u16 20 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
21 { 21 {
22 return ssb_read32(pc->dev, offset); 22 return ssb_read32(pc->dev, offset);
23 } 23 }
24 24
25 static inline 25 static inline
26 void pcicore_write32(struct ssb_pcicore *pc, u 26 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
27 { 27 {
28 ssb_write32(pc->dev, offset, value); 28 ssb_write32(pc->dev, offset, value);
29 } 29 }
30 30
31 static inline 31 static inline
32 u16 pcicore_read16(struct ssb_pcicore *pc, u16 32 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
33 { 33 {
34 return ssb_read16(pc->dev, offset); 34 return ssb_read16(pc->dev, offset);
35 } 35 }
36 36
37 static inline 37 static inline
38 void pcicore_write16(struct ssb_pcicore *pc, u 38 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
39 { 39 {
40 ssb_write16(pc->dev, offset, value); 40 ssb_write16(pc->dev, offset, value);
41 } 41 }
42 42
43 /********************************************* 43 /**************************************************
44 * Code for hostmode operation. 44 * Code for hostmode operation.
45 ********************************************* 45 **************************************************/
46 46
47 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 47 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
48 48
49 #include <asm/paccess.h> 49 #include <asm/paccess.h>
50 /* Probe a 32bit value on the bus and catch bu 50 /* Probe a 32bit value on the bus and catch bus exceptions.
51 * Returns nonzero on a bus exception. 51 * Returns nonzero on a bus exception.
52 * This is MIPS specific */ 52 * This is MIPS specific */
53 #define mips_busprobe32(val, addr) get_db 53 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
54 54
55 /* Assume one-hot slot wiring */ 55 /* Assume one-hot slot wiring */
56 #define SSB_PCI_SLOT_MAX 16 56 #define SSB_PCI_SLOT_MAX 16
57 57
58 /* Global lock is OK, as we won't have more th 58 /* Global lock is OK, as we won't have more than one extpci anyway. */
59 static DEFINE_SPINLOCK(cfgspace_lock); 59 static DEFINE_SPINLOCK(cfgspace_lock);
60 /* Core to access the external PCI config spac 60 /* Core to access the external PCI config space. Can only have one. */
61 static struct ssb_pcicore *extpci_core; 61 static struct ssb_pcicore *extpci_core;
62 62
63 static u32 ssb_pcicore_pcibus_iobase = 0x100; <<
64 static u32 ssb_pcicore_pcibus_membase = SSB_PC <<
65 <<
66 int pcibios_plat_dev_init(struct pci_dev *d) <<
67 { <<
68 struct resource *res; <<
69 int pos, size; <<
70 u32 *base; <<
71 <<
72 ssb_printk(KERN_INFO "PCI: Fixing up d <<
73 pci_name(d)); <<
74 <<
75 /* Fix up resource bases */ <<
76 for (pos = 0; pos < 6; pos++) { <<
77 res = &d->resource[pos]; <<
78 if (res->flags & IORESOURCE_IO <<
79 base = &ssb_pcicore_pc <<
80 else <<
81 base = &ssb_pcicore_pc <<
82 res->flags |= IORESOURCE_PCI_F <<
83 if (res->end) { <<
84 size = res->end - res- <<
85 if (*base & (size - 1) <<
86 *base = (*base <<
87 res->start = *base; <<
88 res->end = res->start <<
89 *base += size; <<
90 pci_write_config_dword <<
91 } <<
92 /* Fix up PCI bridge BAR0 only <<
93 if (d->bus->number == 0 && PCI <<
94 break; <<
95 } <<
96 /* Fix up interrupt lines */ <<
97 d->irq = ssb_mips_irq(extpci_core->dev <<
98 pci_write_config_byte(d, PCI_INTERRUPT <<
99 <<
100 return 0; <<
101 } <<
102 <<
103 static void __init ssb_fixup_pcibridge(struct <<
104 { <<
105 u8 lat; <<
106 <<
107 if (dev->bus->number != 0 || PCI_SLOT( <<
108 return; <<
109 <<
110 ssb_printk(KERN_INFO "PCI: Fixing up b <<
111 <<
112 /* Enable PCI bridge bus mastering and <<
113 pci_set_master(dev); <<
114 if (pcibios_enable_device(dev, ~0) < 0 <<
115 ssb_printk(KERN_ERR "PCI: SSB <<
116 return; <<
117 } <<
118 <<
119 /* Enable PCI bridge BAR1 prefetch and <<
120 pci_write_config_dword(dev, SSB_BAR1_C <<
121 <<
122 /* Make sure our latency is high enoug <<
123 lat = 168; <<
124 ssb_printk(KERN_INFO "PCI: Fixing late <<
125 pci_name(dev), lat); <<
126 pci_write_config_byte(dev, PCI_LATENCY <<
127 } <<
128 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID <<
129 <<
130 int __init pcibios_map_irq(const struct pci_de <<
131 { <<
132 return ssb_mips_irq(extpci_core->dev) <<
133 } <<
134 63
135 static u32 get_cfgspace_addr(struct ssb_pcicor 64 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
136 unsigned int bus, 65 unsigned int bus, unsigned int dev,
137 unsigned int func 66 unsigned int func, unsigned int off)
138 { 67 {
139 u32 addr = 0; 68 u32 addr = 0;
140 u32 tmp; 69 u32 tmp;
141 70
142 /* We do only have one cardbus device 71 /* We do only have one cardbus device behind the bridge. */
143 if (pc->cardbusmode && (dev >= 1)) 72 if (pc->cardbusmode && (dev >= 1))
144 goto out; 73 goto out;
145 74
146 if (bus == 0) { 75 if (bus == 0) {
147 /* Type 0 transaction */ 76 /* Type 0 transaction */
148 if (unlikely(dev >= SSB_PCI_SL 77 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
149 goto out; 78 goto out;
150 /* Slide the window */ 79 /* Slide the window */
151 tmp = SSB_PCICORE_SBTOPCI_CFG0 80 tmp = SSB_PCICORE_SBTOPCI_CFG0;
152 tmp |= ((1 << (dev + 16)) & SS 81 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
153 pcicore_write32(pc, SSB_PCICOR 82 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
154 /* Calculate the address */ 83 /* Calculate the address */
155 addr = SSB_PCI_CFG; 84 addr = SSB_PCI_CFG;
156 addr |= ((1 << (dev + 16)) & ~ 85 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
157 addr |= (func << 8); 86 addr |= (func << 8);
158 addr |= (off & ~3); 87 addr |= (off & ~3);
159 } else { 88 } else {
160 /* Type 1 transaction */ 89 /* Type 1 transaction */
161 pcicore_write32(pc, SSB_PCICOR 90 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
162 SSB_PCICORE_SB 91 SSB_PCICORE_SBTOPCI_CFG1);
163 /* Calculate the address */ 92 /* Calculate the address */
164 addr = SSB_PCI_CFG; 93 addr = SSB_PCI_CFG;
165 addr |= (bus << 16); 94 addr |= (bus << 16);
166 addr |= (dev << 11); 95 addr |= (dev << 11);
167 addr |= (func << 8); 96 addr |= (func << 8);
168 addr |= (off & ~3); 97 addr |= (off & ~3);
169 } 98 }
170 out: 99 out:
171 return addr; 100 return addr;
172 } 101 }
173 102
174 static int ssb_extpci_read_config(struct ssb_p 103 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
175 unsigned int 104 unsigned int bus, unsigned int dev,
176 unsigned int 105 unsigned int func, unsigned int off,
177 void *buf, i 106 void *buf, int len)
178 { 107 {
179 int err = -EINVAL; 108 int err = -EINVAL;
180 u32 addr, val; 109 u32 addr, val;
181 void __iomem *mmio; 110 void __iomem *mmio;
182 111
183 SSB_WARN_ON(!pc->hostmode); 112 SSB_WARN_ON(!pc->hostmode);
184 if (unlikely(len != 1 && len != 2 && l 113 if (unlikely(len != 1 && len != 2 && len != 4))
185 goto out; 114 goto out;
186 addr = get_cfgspace_addr(pc, bus, dev, 115 addr = get_cfgspace_addr(pc, bus, dev, func, off);
187 if (unlikely(!addr)) 116 if (unlikely(!addr))
188 goto out; 117 goto out;
189 err = -ENOMEM; 118 err = -ENOMEM;
190 mmio = ioremap_nocache(addr, len); 119 mmio = ioremap_nocache(addr, len);
191 if (!mmio) 120 if (!mmio)
192 goto out; 121 goto out;
193 122
194 if (mips_busprobe32(val, mmio)) { 123 if (mips_busprobe32(val, mmio)) {
195 val = 0xffffffff; 124 val = 0xffffffff;
196 goto unmap; 125 goto unmap;
197 } 126 }
198 127
199 val = readl(mmio); 128 val = readl(mmio);
200 val >>= (8 * (off & 3)); 129 val >>= (8 * (off & 3));
201 130
202 switch (len) { 131 switch (len) {
203 case 1: 132 case 1:
204 *((u8 *)buf) = (u8)val; 133 *((u8 *)buf) = (u8)val;
205 break; 134 break;
206 case 2: 135 case 2:
207 *((u16 *)buf) = (u16)val; 136 *((u16 *)buf) = (u16)val;
208 break; 137 break;
209 case 4: 138 case 4:
210 *((u32 *)buf) = (u32)val; 139 *((u32 *)buf) = (u32)val;
211 break; 140 break;
212 } 141 }
213 err = 0; 142 err = 0;
214 unmap: 143 unmap:
215 iounmap(mmio); 144 iounmap(mmio);
216 out: 145 out:
217 return err; 146 return err;
218 } 147 }
219 148
220 static int ssb_extpci_write_config(struct ssb_ 149 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
221 unsigned in 150 unsigned int bus, unsigned int dev,
222 unsigned in 151 unsigned int func, unsigned int off,
223 const void 152 const void *buf, int len)
224 { 153 {
225 int err = -EINVAL; 154 int err = -EINVAL;
226 u32 addr, val = 0; 155 u32 addr, val = 0;
227 void __iomem *mmio; 156 void __iomem *mmio;
228 157
229 SSB_WARN_ON(!pc->hostmode); 158 SSB_WARN_ON(!pc->hostmode);
230 if (unlikely(len != 1 && len != 2 && l 159 if (unlikely(len != 1 && len != 2 && len != 4))
231 goto out; 160 goto out;
232 addr = get_cfgspace_addr(pc, bus, dev, 161 addr = get_cfgspace_addr(pc, bus, dev, func, off);
233 if (unlikely(!addr)) 162 if (unlikely(!addr))
234 goto out; 163 goto out;
235 err = -ENOMEM; 164 err = -ENOMEM;
236 mmio = ioremap_nocache(addr, len); 165 mmio = ioremap_nocache(addr, len);
237 if (!mmio) 166 if (!mmio)
238 goto out; 167 goto out;
239 168
240 if (mips_busprobe32(val, mmio)) { 169 if (mips_busprobe32(val, mmio)) {
241 val = 0xffffffff; 170 val = 0xffffffff;
242 goto unmap; 171 goto unmap;
243 } 172 }
244 173
245 switch (len) { 174 switch (len) {
246 case 1: 175 case 1:
247 val = readl(mmio); 176 val = readl(mmio);
248 val &= ~(0xFF << (8 * (off & 3 177 val &= ~(0xFF << (8 * (off & 3)));
249 val |= *((const u8 *)buf) << ( 178 val |= *((const u8 *)buf) << (8 * (off & 3));
250 break; 179 break;
251 case 2: 180 case 2:
252 val = readl(mmio); 181 val = readl(mmio);
253 val &= ~(0xFFFF << (8 * (off & 182 val &= ~(0xFFFF << (8 * (off & 3)));
254 val |= *((const u16 *)buf) << 183 val |= *((const u16 *)buf) << (8 * (off & 3));
255 break; 184 break;
256 case 4: 185 case 4:
257 val = *((const u32 *)buf); 186 val = *((const u32 *)buf);
258 break; 187 break;
259 } 188 }
260 writel(val, mmio); 189 writel(val, mmio);
261 190
262 err = 0; 191 err = 0;
263 unmap: 192 unmap:
264 iounmap(mmio); 193 iounmap(mmio);
265 out: 194 out:
266 return err; 195 return err;
267 } 196 }
268 197
269 static int ssb_pcicore_read_config(struct pci_ 198 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
270 int reg, in 199 int reg, int size, u32 *val)
271 { 200 {
272 unsigned long flags; 201 unsigned long flags;
273 int err; 202 int err;
274 203
275 spin_lock_irqsave(&cfgspace_lock, flag 204 spin_lock_irqsave(&cfgspace_lock, flags);
276 err = ssb_extpci_read_config(extpci_co 205 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
277 PCI_FUNC( 206 PCI_FUNC(devfn), reg, val, size);
278 spin_unlock_irqrestore(&cfgspace_lock, 207 spin_unlock_irqrestore(&cfgspace_lock, flags);
279 208
280 return err ? PCIBIOS_DEVICE_NOT_FOUND 209 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
281 } 210 }
282 211
283 static int ssb_pcicore_write_config(struct pci 212 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
284 int reg, i 213 int reg, int size, u32 val)
285 { 214 {
286 unsigned long flags; 215 unsigned long flags;
287 int err; 216 int err;
288 217
289 spin_lock_irqsave(&cfgspace_lock, flag 218 spin_lock_irqsave(&cfgspace_lock, flags);
290 err = ssb_extpci_write_config(extpci_c 219 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
291 PCI_FUNC 220 PCI_FUNC(devfn), reg, &val, size);
292 spin_unlock_irqrestore(&cfgspace_lock, 221 spin_unlock_irqrestore(&cfgspace_lock, flags);
293 222
294 return err ? PCIBIOS_DEVICE_NOT_FOUND 223 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
295 } 224 }
296 225
297 static struct pci_ops ssb_pcicore_pciops = { 226 static struct pci_ops ssb_pcicore_pciops = {
298 .read = ssb_pcicore_read_config, 227 .read = ssb_pcicore_read_config,
299 .write = ssb_pcicore_write_config, 228 .write = ssb_pcicore_write_config,
300 }; 229 };
301 230
302 static struct resource ssb_pcicore_mem_resourc 231 static struct resource ssb_pcicore_mem_resource = {
303 .name = "SSB PCIcore external memory 232 .name = "SSB PCIcore external memory",
304 .start = SSB_PCI_DMA, 233 .start = SSB_PCI_DMA,
305 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ 234 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
306 .flags = IORESOURCE_MEM | IORESOURCE_ 235 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
307 }; 236 };
308 237
309 static struct resource ssb_pcicore_io_resource 238 static struct resource ssb_pcicore_io_resource = {
310 .name = "SSB PCIcore external I/O", 239 .name = "SSB PCIcore external I/O",
311 .start = 0x100, 240 .start = 0x100,
312 .end = 0x7FF, 241 .end = 0x7FF,
313 .flags = IORESOURCE_IO | IORESOURCE_P 242 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
314 }; 243 };
315 244
316 static struct pci_controller ssb_pcicore_contr 245 static struct pci_controller ssb_pcicore_controller = {
317 .pci_ops = &ssb_pcicore_pciops, 246 .pci_ops = &ssb_pcicore_pciops,
318 .io_resource = &ssb_pcicore_io_reso 247 .io_resource = &ssb_pcicore_io_resource,
319 .mem_resource = &ssb_pcicore_mem_res 248 .mem_resource = &ssb_pcicore_mem_resource,
320 .mem_offset = 0x24000000, 249 .mem_offset = 0x24000000,
321 }; 250 };
322 251
>> 252 static u32 ssb_pcicore_pcibus_iobase = 0x100;
>> 253 static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
>> 254
>> 255 /* This function is called when doing a pci_enable_device().
>> 256 * We must first check if the device is a device on the PCI-core bridge. */
>> 257 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
>> 258 {
>> 259 struct resource *res;
>> 260 int pos, size;
>> 261 u32 *base;
>> 262
>> 263 if (d->bus->ops != &ssb_pcicore_pciops) {
>> 264 /* This is not a device on the PCI-core bridge. */
>> 265 return -ENODEV;
>> 266 }
>> 267
>> 268 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
>> 269 pci_name(d));
>> 270
>> 271 /* Fix up resource bases */
>> 272 for (pos = 0; pos < 6; pos++) {
>> 273 res = &d->resource[pos];
>> 274 if (res->flags & IORESOURCE_IO)
>> 275 base = &ssb_pcicore_pcibus_iobase;
>> 276 else
>> 277 base = &ssb_pcicore_pcibus_membase;
>> 278 res->flags |= IORESOURCE_PCI_FIXED;
>> 279 if (res->end) {
>> 280 size = res->end - res->start + 1;
>> 281 if (*base & (size - 1))
>> 282 *base = (*base + size) & ~(size - 1);
>> 283 res->start = *base;
>> 284 res->end = res->start + size - 1;
>> 285 *base += size;
>> 286 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
>> 287 }
>> 288 /* Fix up PCI bridge BAR0 only */
>> 289 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
>> 290 break;
>> 291 }
>> 292 /* Fix up interrupt lines */
>> 293 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
>> 294 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
>> 295
>> 296 return 0;
>> 297 }
>> 298
>> 299 /* Early PCI fixup for a device on the PCI-core bridge. */
>> 300 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
>> 301 {
>> 302 u8 lat;
>> 303
>> 304 if (dev->bus->ops != &ssb_pcicore_pciops) {
>> 305 /* This is not a device on the PCI-core bridge. */
>> 306 return;
>> 307 }
>> 308 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
>> 309 return;
>> 310
>> 311 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
>> 312
>> 313 /* Enable PCI bridge bus mastering and memory space */
>> 314 pci_set_master(dev);
>> 315 if (pcibios_enable_device(dev, ~0) < 0) {
>> 316 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
>> 317 return;
>> 318 }
>> 319
>> 320 /* Enable PCI bridge BAR1 prefetch and burst */
>> 321 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
>> 322
>> 323 /* Make sure our latency is high enough to handle the devices behind us */
>> 324 lat = 168;
>> 325 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
>> 326 pci_name(dev), lat);
>> 327 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
>> 328 }
>> 329 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
>> 330
>> 331 /* PCI device IRQ mapping. */
>> 332 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
>> 333 {
>> 334 if (dev->bus->ops != &ssb_pcicore_pciops) {
>> 335 /* This is not a device on the PCI-core bridge. */
>> 336 return -ENODEV;
>> 337 }
>> 338 return ssb_mips_irq(extpci_core->dev) + 2;
>> 339 }
>> 340
323 static void ssb_pcicore_init_hostmode(struct s 341 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
324 { 342 {
325 u32 val; 343 u32 val;
326 344
327 if (WARN_ON(extpci_core)) 345 if (WARN_ON(extpci_core))
328 return; 346 return;
329 extpci_core = pc; 347 extpci_core = pc;
330 348
331 ssb_dprintk(KERN_INFO PFX "PCIcore in 349 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
332 /* Reset devices on the external PCI b 350 /* Reset devices on the external PCI bus */
333 val = SSB_PCICORE_CTL_RST_OE; 351 val = SSB_PCICORE_CTL_RST_OE;
334 val |= SSB_PCICORE_CTL_CLK_OE; 352 val |= SSB_PCICORE_CTL_CLK_OE;
335 pcicore_write32(pc, SSB_PCICORE_CTL, v 353 pcicore_write32(pc, SSB_PCICORE_CTL, val);
336 val |= SSB_PCICORE_CTL_CLK; /* Clock o 354 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
337 pcicore_write32(pc, SSB_PCICORE_CTL, v 355 pcicore_write32(pc, SSB_PCICORE_CTL, val);
338 udelay(150); /* Assertion time demande 356 udelay(150); /* Assertion time demanded by the PCI standard */
339 val |= SSB_PCICORE_CTL_RST; /* Deasser 357 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
340 pcicore_write32(pc, SSB_PCICORE_CTL, v 358 pcicore_write32(pc, SSB_PCICORE_CTL, val);
341 val = SSB_PCICORE_ARBCTL_INTERN; 359 val = SSB_PCICORE_ARBCTL_INTERN;
342 pcicore_write32(pc, SSB_PCICORE_ARBCTL 360 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
343 udelay(1); /* Assertion time demanded 361 udelay(1); /* Assertion time demanded by the PCI standard */
344 362
345 if (pc->dev->bus->has_cardbus_slot) { 363 if (pc->dev->bus->has_cardbus_slot) {
346 ssb_dprintk(KERN_INFO PFX "Car 364 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
347 pc->cardbusmode = 1; 365 pc->cardbusmode = 1;
348 /* GPIO 1 resets the bridge */ 366 /* GPIO 1 resets the bridge */
349 ssb_gpio_out(pc->dev->bus, 1, 367 ssb_gpio_out(pc->dev->bus, 1, 1);
350 ssb_gpio_outen(pc->dev->bus, 1 368 ssb_gpio_outen(pc->dev->bus, 1, 1);
351 pcicore_write16(pc, SSB_PCICOR 369 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
352 pcicore_read16 370 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
353 | 0x0400); 371 | 0x0400);
354 } 372 }
355 373
356 /* 64MB I/O window */ 374 /* 64MB I/O window */
357 pcicore_write32(pc, SSB_PCICORE_SBTOPC 375 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
358 SSB_PCICORE_SBTOPCI_IO 376 SSB_PCICORE_SBTOPCI_IO);
359 /* 64MB config space */ 377 /* 64MB config space */
360 pcicore_write32(pc, SSB_PCICORE_SBTOPC 378 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
361 SSB_PCICORE_SBTOPCI_CF 379 SSB_PCICORE_SBTOPCI_CFG0);
362 /* 1GB memory window */ 380 /* 1GB memory window */
363 pcicore_write32(pc, SSB_PCICORE_SBTOPC 381 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
364 SSB_PCICORE_SBTOPCI_ME 382 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
365 383
366 /* Enable PCI bridge BAR0 prefetch and 384 /* Enable PCI bridge BAR0 prefetch and burst */
367 val = PCI_COMMAND_MASTER | PCI_COMMAND 385 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
368 ssb_extpci_write_config(pc, 0, 0, 0, P 386 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
369 /* Clear error conditions */ 387 /* Clear error conditions */
370 val = 0; 388 val = 0;
371 ssb_extpci_write_config(pc, 0, 0, 0, P 389 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
372 390
373 /* Enable PCI interrupts */ 391 /* Enable PCI interrupts */
374 pcicore_write32(pc, SSB_PCICORE_IMASK, 392 pcicore_write32(pc, SSB_PCICORE_IMASK,
375 SSB_PCICORE_IMASK_INTA 393 SSB_PCICORE_IMASK_INTA);
376 394
377 /* Ok, ready to run, register it to th 395 /* Ok, ready to run, register it to the system.
378 * The following needs change, if we w 396 * The following needs change, if we want to port hostmode
379 * to non-MIPS platform. */ 397 * to non-MIPS platform. */
380 ssb_pcicore_controller.io_map_base = ( 398 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
381 set_io_port_base(ssb_pcicore_controlle 399 set_io_port_base(ssb_pcicore_controller.io_map_base);
382 /* Give some time to the PCI controlle 400 /* Give some time to the PCI controller to configure itself with the new
383 * values. Not waiting at this point c 401 * values. Not waiting at this point causes crashes of the machine. */
384 mdelay(10); 402 mdelay(10);
385 register_pci_controller(&ssb_pcicore_c 403 register_pci_controller(&ssb_pcicore_controller);
386 } 404 }
387 405
388 static int pcicore_is_in_hostmode(struct ssb_p 406 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
389 { 407 {
390 struct ssb_bus *bus = pc->dev->bus; 408 struct ssb_bus *bus = pc->dev->bus;
391 u16 chipid_top; 409 u16 chipid_top;
392 u32 tmp; 410 u32 tmp;
393 411
394 chipid_top = (bus->chip_id & 0xFF00); 412 chipid_top = (bus->chip_id & 0xFF00);
395 if (chipid_top != 0x4700 && 413 if (chipid_top != 0x4700 &&
396 chipid_top != 0x5300) 414 chipid_top != 0x5300)
397 return 0; 415 return 0;
398 416
399 if (bus->sprom.boardflags_lo & SSB_PCI 417 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
400 return 0; 418 return 0;
401 419
402 /* The 200-pin BCM4712 package does no 420 /* The 200-pin BCM4712 package does not bond out PCI. Even when
403 * PCI is bonded out, some boards may 421 * PCI is bonded out, some boards may leave the pins floating. */
404 if (bus->chip_id == 0x4712) { 422 if (bus->chip_id == 0x4712) {
405 if (bus->chip_package == SSB_C 423 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
406 return 0; 424 return 0;
407 if (bus->chip_package == SSB_C 425 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
408 return 0; 426 return 0;
409 } 427 }
410 if (bus->chip_id == 0x5350) 428 if (bus->chip_id == 0x5350)
411 return 0; 429 return 0;
412 430
413 return !mips_busprobe32(tmp, (bus->mmi 431 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
414 } 432 }
415 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 433 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
416 434
417 435
418 /********************************************* 436 /**************************************************
419 * Generic and Clientmode operation code. 437 * Generic and Clientmode operation code.
420 ********************************************* 438 **************************************************/
421 439
422 static void ssb_pcicore_init_clientmode(struct 440 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
423 { 441 {
424 /* Disable PCI interrupts. */ 442 /* Disable PCI interrupts. */
425 ssb_write32(pc->dev, SSB_INTVEC, 0); 443 ssb_write32(pc->dev, SSB_INTVEC, 0);
426 } 444 }
427 445
428 void ssb_pcicore_init(struct ssb_pcicore *pc) 446 void ssb_pcicore_init(struct ssb_pcicore *pc)
429 { 447 {
430 struct ssb_device *dev = pc->dev; 448 struct ssb_device *dev = pc->dev;
431 struct ssb_bus *bus; 449 struct ssb_bus *bus;
432 450
433 if (!dev) 451 if (!dev)
434 return; 452 return;
435 bus = dev->bus; 453 bus = dev->bus;
436 if (!ssb_device_is_enabled(dev)) 454 if (!ssb_device_is_enabled(dev))
437 ssb_device_enable(dev, 0); 455 ssb_device_enable(dev, 0);
438 456
439 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 457 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
440 pc->hostmode = pcicore_is_in_hostmode( 458 pc->hostmode = pcicore_is_in_hostmode(pc);
441 if (pc->hostmode) 459 if (pc->hostmode)
442 ssb_pcicore_init_hostmode(pc); 460 ssb_pcicore_init_hostmode(pc);
443 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 461 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
444 if (!pc->hostmode) 462 if (!pc->hostmode)
445 ssb_pcicore_init_clientmode(pc 463 ssb_pcicore_init_clientmode(pc);
446 } 464 }
447 465
448 static u32 ssb_pcie_read(struct ssb_pcicore *p 466 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
449 { 467 {
450 pcicore_write32(pc, 0x130, address); 468 pcicore_write32(pc, 0x130, address);
451 return pcicore_read32(pc, 0x134); 469 return pcicore_read32(pc, 0x134);
452 } 470 }
453 471
454 static void ssb_pcie_write(struct ssb_pcicore 472 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
455 { 473 {
456 pcicore_write32(pc, 0x130, address); 474 pcicore_write32(pc, 0x130, address);
457 pcicore_write32(pc, 0x134, data); 475 pcicore_write32(pc, 0x134, data);
458 } 476 }
459 477
460 static void ssb_pcie_mdio_write(struct ssb_pci 478 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
461 u8 address, u1 479 u8 address, u16 data)
462 { 480 {
463 const u16 mdio_control = 0x128; 481 const u16 mdio_control = 0x128;
464 const u16 mdio_data = 0x12C; 482 const u16 mdio_data = 0x12C;
465 u32 v; 483 u32 v;
466 int i; 484 int i;
467 485
468 v = 0x80; /* Enable Preamble Sequence 486 v = 0x80; /* Enable Preamble Sequence */
469 v |= 0x2; /* MDIO Clock Divisor */ 487 v |= 0x2; /* MDIO Clock Divisor */
470 pcicore_write32(pc, mdio_control, v); 488 pcicore_write32(pc, mdio_control, v);
471 489
472 v = (1 << 30); /* Start of Transaction 490 v = (1 << 30); /* Start of Transaction */
473 v |= (1 << 28); /* Write Transaction * 491 v |= (1 << 28); /* Write Transaction */
474 v |= (1 << 17); /* Turnaround */ 492 v |= (1 << 17); /* Turnaround */
475 v |= (u32)device << 22; 493 v |= (u32)device << 22;
476 v |= (u32)address << 18; 494 v |= (u32)address << 18;
477 v |= data; 495 v |= data;
478 pcicore_write32(pc, mdio_data, v); 496 pcicore_write32(pc, mdio_data, v);
479 /* Wait for the device to complete the 497 /* Wait for the device to complete the transaction */
480 udelay(10); 498 udelay(10);
481 for (i = 0; i < 10; i++) { 499 for (i = 0; i < 10; i++) {
482 v = pcicore_read32(pc, mdio_co 500 v = pcicore_read32(pc, mdio_control);
483 if (v & 0x100 /* Trans complet 501 if (v & 0x100 /* Trans complete */)
484 break; 502 break;
485 msleep(1); 503 msleep(1);
486 } 504 }
487 pcicore_write32(pc, mdio_control, 0); 505 pcicore_write32(pc, mdio_control, 0);
488 } 506 }
489 507
490 static void ssb_broadcast_value(struct ssb_dev 508 static void ssb_broadcast_value(struct ssb_device *dev,
491 u32 address, u 509 u32 address, u32 data)
492 { 510 {
493 /* This is used for both, PCI and Chip 511 /* This is used for both, PCI and ChipCommon core, so be careful. */
494 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != 512 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
495 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != 513 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
496 514
497 ssb_write32(dev, SSB_PCICORE_BCAST_ADD 515 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
498 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR 516 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
499 ssb_write32(dev, SSB_PCICORE_BCAST_DAT 517 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
500 ssb_read32(dev, SSB_PCICORE_BCAST_DATA 518 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
501 } 519 }
502 520
503 static void ssb_commit_settings(struct ssb_bus 521 static void ssb_commit_settings(struct ssb_bus *bus)
504 { 522 {
505 struct ssb_device *dev; 523 struct ssb_device *dev;
506 524
507 dev = bus->chipco.dev ? bus->chipco.de 525 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
508 if (WARN_ON(!dev)) 526 if (WARN_ON(!dev))
509 return; 527 return;
510 /* This forces an update of the cached 528 /* This forces an update of the cached registers. */
511 ssb_broadcast_value(dev, 0xFD8, 0); 529 ssb_broadcast_value(dev, 0xFD8, 0);
512 } 530 }
513 531
514 int ssb_pcicore_dev_irqvecs_enable(struct ssb_ 532 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
515 struct ssb_ 533 struct ssb_device *dev)
516 { 534 {
517 struct ssb_device *pdev = pc->dev; 535 struct ssb_device *pdev = pc->dev;
518 struct ssb_bus *bus; 536 struct ssb_bus *bus;
519 int err = 0; 537 int err = 0;
520 u32 tmp; 538 u32 tmp;
521 539
>> 540 if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
>> 541 /* This SSB device is not on a PCI host-bus. So the IRQs are
>> 542 * not routed through the PCI core.
>> 543 * So we must not enable routing through the PCI core. */
>> 544 goto out;
>> 545 }
>> 546
522 if (!pdev) 547 if (!pdev)
523 goto out; 548 goto out;
524 bus = pdev->bus; 549 bus = pdev->bus;
525 550
526 might_sleep_if(pdev->id.coreid != SSB_ 551 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
527 552
528 /* Enable interrupts for this device. 553 /* Enable interrupts for this device. */
529 if (bus->host_pci && 554 if (bus->host_pci &&
530 ((pdev->id.revision >= 6) || (pdev 555 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
531 u32 coremask; 556 u32 coremask;
532 557
533 /* Calculate the "coremask" fo 558 /* Calculate the "coremask" for the device. */
534 coremask = (1 << dev->core_ind 559 coremask = (1 << dev->core_index);
535 560
536 err = pci_read_config_dword(bu 561 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
537 if (err) 562 if (err)
538 goto out; 563 goto out;
539 tmp |= coremask << 8; 564 tmp |= coremask << 8;
540 err = pci_write_config_dword(b 565 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
541 if (err) 566 if (err)
542 goto out; 567 goto out;
543 } else { 568 } else {
544 u32 intvec; 569 u32 intvec;
545 570
546 intvec = ssb_read32(pdev, SSB_ 571 intvec = ssb_read32(pdev, SSB_INTVEC);
547 if ((bus->chip_id & 0xFF00) == !! 572 tmp = ssb_read32(dev, SSB_TPSFLAG);
548 /* Workaround: On the !! 573 tmp &= SSB_TPSFLAG_BPFLAG;
549 * bit is wrong. Use a !! 574 intvec |= (1 << tmp);
550 intvec |= 0x00000002; <<
551 } else { <<
552 tmp = ssb_read32(dev, <<
553 tmp &= SSB_TPSFLAG_BPF <<
554 intvec |= (1 << tmp); <<
555 } <<
556 ssb_write32(pdev, SSB_INTVEC, 575 ssb_write32(pdev, SSB_INTVEC, intvec);
557 } 576 }
558 577
559 /* Setup PCIcore operation. */ 578 /* Setup PCIcore operation. */
560 if (pc->setup_done) 579 if (pc->setup_done)
561 goto out; 580 goto out;
562 if (pdev->id.coreid == SSB_DEV_PCI) { 581 if (pdev->id.coreid == SSB_DEV_PCI) {
563 tmp = pcicore_read32(pc, SSB_P 582 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
564 tmp |= SSB_PCICORE_SBTOPCI_PRE 583 tmp |= SSB_PCICORE_SBTOPCI_PREF;
565 tmp |= SSB_PCICORE_SBTOPCI_BUR 584 tmp |= SSB_PCICORE_SBTOPCI_BURST;
566 pcicore_write32(pc, SSB_PCICOR 585 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
567 586
568 if (pdev->id.revision < 5) { 587 if (pdev->id.revision < 5) {
569 tmp = ssb_read32(pdev, 588 tmp = ssb_read32(pdev, SSB_IMCFGLO);
570 tmp &= ~SSB_IMCFGLO_SE 589 tmp &= ~SSB_IMCFGLO_SERTO;
571 tmp |= 2; 590 tmp |= 2;
572 tmp &= ~SSB_IMCFGLO_RE 591 tmp &= ~SSB_IMCFGLO_REQTO;
573 tmp |= 3 << SSB_IMCFGL 592 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
574 ssb_write32(pdev, SSB_ 593 ssb_write32(pdev, SSB_IMCFGLO, tmp);
575 ssb_commit_settings(bu 594 ssb_commit_settings(bus);
576 } else if (pdev->id.revision > 595 } else if (pdev->id.revision >= 11) {
577 tmp = pcicore_read32(p 596 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
578 tmp |= SSB_PCICORE_SBT 597 tmp |= SSB_PCICORE_SBTOPCI_MRM;
579 pcicore_write32(pc, SS 598 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
580 } 599 }
581 } else { 600 } else {
582 WARN_ON(pdev->id.coreid != SSB 601 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
583 //TODO: Better make defines fo 602 //TODO: Better make defines for all these magic PCIE values.
584 if ((pdev->id.revision == 0) | 603 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
585 /* TLP Workaround regi 604 /* TLP Workaround register. */
586 tmp = ssb_pcie_read(pc 605 tmp = ssb_pcie_read(pc, 0x4);
587 tmp |= 0x8; 606 tmp |= 0x8;
588 ssb_pcie_write(pc, 0x4 607 ssb_pcie_write(pc, 0x4, tmp);
589 } 608 }
590 if (pdev->id.revision == 0) { 609 if (pdev->id.revision == 0) {
591 const u8 serdes_rx_dev 610 const u8 serdes_rx_device = 0x1F;
592 611
593 ssb_pcie_mdio_write(pc 612 ssb_pcie_mdio_write(pc, serdes_rx_device,
594 2 613 2 /* Timer */, 0x8128);
595 ssb_pcie_mdio_write(pc 614 ssb_pcie_mdio_write(pc, serdes_rx_device,
596 6 615 6 /* CDR */, 0x0100);
597 ssb_pcie_mdio_write(pc 616 ssb_pcie_mdio_write(pc, serdes_rx_device,
598 7 617 7 /* CDR BW */, 0x1466);
599 } else if (pdev->id.revision = 618 } else if (pdev->id.revision == 1) {
600 /* DLLP Link Control r 619 /* DLLP Link Control register. */
601 tmp = ssb_pcie_read(pc 620 tmp = ssb_pcie_read(pc, 0x100);
602 tmp |= 0x40; 621 tmp |= 0x40;
603 ssb_pcie_write(pc, 0x1 622 ssb_pcie_write(pc, 0x100, tmp);
604 } 623 }
605 } 624 }
606 pc->setup_done = 1; 625 pc->setup_done = 1;
607 out: 626 out:
608 return err; 627 return err;
609 } 628 }
610 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); 629 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
611 630
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