Diff markup
1 /* 1 /*
2 * drivers/serial/sb1250-duart.c 2 * drivers/serial/sb1250-duart.c
3 * 3 *
4 * Support for the asynchronous serial in 4 * Support for the asynchronous serial interface (DUART) included
5 * in the BCM1250 and derived System-On-a 5 * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
6 * 6 *
7 * Copyright (c) 2007 Maciej W. Rozycki 7 * Copyright (c) 2007 Maciej W. Rozycki
8 * 8 *
9 * Derived from drivers/char/sb1250_duart 9 * Derived from drivers/char/sb1250_duart.c for which the following
10 * copyright applies: 10 * copyright applies:
11 * 11 *
12 * Copyright (c) 2000, 2001, 2002, 2003, 12 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
13 * 13 *
14 * This program is free software; you can 14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU G 15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foun 16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) 17 * 2 of the License, or (at your option) any later version.
18 * 18 *
19 * References: 19 * References:
20 * 20 *
21 * "BCM1250/BCM1125/BCM1125H User Manual" 21 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
22 */ 22 */
23 23
24 #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE 24 #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #define SUPPORT_SYSRQ 25 #define SUPPORT_SYSRQ
26 #endif 26 #endif
27 27
28 #include <linux/compiler.h> 28 #include <linux/compiler.h>
29 #include <linux/console.h> 29 #include <linux/console.h>
30 #include <linux/delay.h> 30 #include <linux/delay.h>
31 #include <linux/errno.h> 31 #include <linux/errno.h>
32 #include <linux/init.h> 32 #include <linux/init.h>
33 #include <linux/interrupt.h> 33 #include <linux/interrupt.h>
34 #include <linux/ioport.h> 34 #include <linux/ioport.h>
35 #include <linux/kernel.h> 35 #include <linux/kernel.h>
36 #include <linux/major.h> 36 #include <linux/major.h>
37 #include <linux/serial.h> 37 #include <linux/serial.h>
38 #include <linux/serial_core.h> 38 #include <linux/serial_core.h>
39 #include <linux/spinlock.h> 39 #include <linux/spinlock.h>
40 #include <linux/sysrq.h> 40 #include <linux/sysrq.h>
41 #include <linux/tty.h> 41 #include <linux/tty.h>
42 #include <linux/types.h> 42 #include <linux/types.h>
43 43
44 #include <asm/atomic.h> 44 #include <asm/atomic.h>
45 #include <asm/io.h> 45 #include <asm/io.h>
46 #include <asm/war.h> 46 #include <asm/war.h>
47 47
48 #include <asm/sibyte/sb1250.h> 48 #include <asm/sibyte/sb1250.h>
49 #include <asm/sibyte/sb1250_uart.h> 49 #include <asm/sibyte/sb1250_uart.h>
50 #include <asm/sibyte/swarm.h> 50 #include <asm/sibyte/swarm.h>
51 51
52 52
53 #if defined(CONFIG_SIBYTE_BCM1x55) || defined( 53 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
54 #include <asm/sibyte/bcm1480_regs.h> 54 #include <asm/sibyte/bcm1480_regs.h>
55 #include <asm/sibyte/bcm1480_int.h> 55 #include <asm/sibyte/bcm1480_int.h>
56 56
57 #define SBD_CHANREGS(line) A_BCM1480_DUAR 57 #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
58 #define SBD_CTRLREGS(line) A_BCM1480_DUAR 58 #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
59 #define SBD_INT(line) (K_BCM1480_INT 59 #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
60 60
61 #define DUART_CHANREG_SPACING BCM1480_DUART_ 61 #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING
62 62
63 #define R_DUART_IMRREG(line) R_BCM1480_DUAR 63 #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line)
64 #define R_DUART_INCHREG(line) R_BCM1480_DUAR 64 #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line)
65 #define R_DUART_ISRREG(line) R_BCM1480_DUAR 65 #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line)
66 66
67 #elif defined(CONFIG_SIBYTE_SB1250) || defined 67 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
68 #include <asm/sibyte/sb1250_regs.h> 68 #include <asm/sibyte/sb1250_regs.h>
69 #include <asm/sibyte/sb1250_int.h> 69 #include <asm/sibyte/sb1250_int.h>
70 70
71 #define SBD_CHANREGS(line) A_DUART_CHANRE 71 #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
72 #define SBD_CTRLREGS(line) A_DUART_CTRLRE 72 #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
73 #define SBD_INT(line) (K_INT_UART_0 73 #define SBD_INT(line) (K_INT_UART_0 + (line))
74 74
75 #else 75 #else
76 #error invalid SB1250 UART configuration 76 #error invalid SB1250 UART configuration
77 77
78 #endif 78 #endif
79 79
80 80
81 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux- 81 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
82 MODULE_DESCRIPTION("BCM1xxx on-chip DUART seri 82 MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
83 MODULE_LICENSE("GPL"); 83 MODULE_LICENSE("GPL");
84 84
85 85
86 #define DUART_MAX_CHIP 2 86 #define DUART_MAX_CHIP 2
87 #define DUART_MAX_SIDE 2 87 #define DUART_MAX_SIDE 2
88 88
89 /* 89 /*
90 * Per-port state. 90 * Per-port state.
91 */ 91 */
92 struct sbd_port { 92 struct sbd_port {
93 struct sbd_duart *duart; 93 struct sbd_duart *duart;
94 struct uart_port port; 94 struct uart_port port;
95 unsigned char __iomem *memctrl; 95 unsigned char __iomem *memctrl;
96 int tx_stopped; 96 int tx_stopped;
97 int initialised; 97 int initialised;
98 }; 98 };
99 99
100 /* 100 /*
101 * Per-DUART state for the shared register spa 101 * Per-DUART state for the shared register space.
102 */ 102 */
103 struct sbd_duart { 103 struct sbd_duart {
104 struct sbd_port sport[2]; 104 struct sbd_port sport[2];
105 unsigned long mapctrl; 105 unsigned long mapctrl;
106 atomic_t map_guard; 106 atomic_t map_guard;
107 }; 107 };
108 108
109 #define to_sport(uport) container_of(uport, st 109 #define to_sport(uport) container_of(uport, struct sbd_port, port)
110 110
111 static struct sbd_duart sbd_duarts[DUART_MAX_C 111 static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
112 112
113 113
114 /* 114 /*
115 * Reading and writing SB1250 DUART registers. 115 * Reading and writing SB1250 DUART registers.
116 * 116 *
117 * There are three register spaces: two per-ch 117 * There are three register spaces: two per-channel ones and
118 * a shared one. We have to define accessors 118 * a shared one. We have to define accessors appropriately.
119 * All registers are 64-bit and all but the Ba 119 * All registers are 64-bit and all but the Baud Rate Clock
120 * registers only define 8 least significant b 120 * registers only define 8 least significant bits. There is
121 * also a workaround to take into account. Ra 121 * also a workaround to take into account. Raw accessors use
122 * the full register width, but cooked ones tr 122 * the full register width, but cooked ones truncate it
123 * intentionally so that the rest of the drive 123 * intentionally so that the rest of the driver does not care.
124 */ 124 */
125 static u64 __read_sbdchn(struct sbd_port *spor 125 static u64 __read_sbdchn(struct sbd_port *sport, int reg)
126 { 126 {
127 void __iomem *csr = sport->port.membas 127 void __iomem *csr = sport->port.membase + reg;
128 128
129 return __raw_readq(csr); 129 return __raw_readq(csr);
130 } 130 }
131 131
132 static u64 __read_sbdshr(struct sbd_port *spor 132 static u64 __read_sbdshr(struct sbd_port *sport, int reg)
133 { 133 {
134 void __iomem *csr = sport->memctrl + r 134 void __iomem *csr = sport->memctrl + reg;
135 135
136 return __raw_readq(csr); 136 return __raw_readq(csr);
137 } 137 }
138 138
139 static void __write_sbdchn(struct sbd_port *sp 139 static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
140 { 140 {
141 void __iomem *csr = sport->port.membas 141 void __iomem *csr = sport->port.membase + reg;
142 142
143 __raw_writeq(value, csr); 143 __raw_writeq(value, csr);
144 } 144 }
145 145
146 static void __write_sbdshr(struct sbd_port *sp 146 static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
147 { 147 {
148 void __iomem *csr = sport->memctrl + r 148 void __iomem *csr = sport->memctrl + reg;
149 149
150 __raw_writeq(value, csr); 150 __raw_writeq(value, csr);
151 } 151 }
152 152
153 /* 153 /*
154 * In bug 1956, we get glitches that can mess 154 * In bug 1956, we get glitches that can mess up uart registers. This
155 * "read-mode-reg after any register access" i 155 * "read-mode-reg after any register access" is an accepted workaround.
156 */ 156 */
157 static void __war_sbd1956(struct sbd_port *spo 157 static void __war_sbd1956(struct sbd_port *sport)
158 { 158 {
159 __read_sbdchn(sport, R_DUART_MODE_REG_ 159 __read_sbdchn(sport, R_DUART_MODE_REG_1);
160 __read_sbdchn(sport, R_DUART_MODE_REG_ 160 __read_sbdchn(sport, R_DUART_MODE_REG_2);
161 } 161 }
162 162
163 static unsigned char read_sbdchn(struct sbd_po 163 static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
164 { 164 {
165 unsigned char retval; 165 unsigned char retval;
166 166
167 retval = __read_sbdchn(sport, reg); 167 retval = __read_sbdchn(sport, reg);
168 if (SIBYTE_1956_WAR) 168 if (SIBYTE_1956_WAR)
169 __war_sbd1956(sport); 169 __war_sbd1956(sport);
170 return retval; 170 return retval;
171 } 171 }
172 172
173 static unsigned char read_sbdshr(struct sbd_po 173 static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
174 { 174 {
175 unsigned char retval; 175 unsigned char retval;
176 176
177 retval = __read_sbdshr(sport, reg); 177 retval = __read_sbdshr(sport, reg);
178 if (SIBYTE_1956_WAR) 178 if (SIBYTE_1956_WAR)
179 __war_sbd1956(sport); 179 __war_sbd1956(sport);
180 return retval; 180 return retval;
181 } 181 }
182 182
183 static void write_sbdchn(struct sbd_port *spor 183 static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
184 { 184 {
185 __write_sbdchn(sport, reg, value); 185 __write_sbdchn(sport, reg, value);
186 if (SIBYTE_1956_WAR) 186 if (SIBYTE_1956_WAR)
187 __war_sbd1956(sport); 187 __war_sbd1956(sport);
188 } 188 }
189 189
190 static void write_sbdshr(struct sbd_port *spor 190 static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
191 { 191 {
192 __write_sbdshr(sport, reg, value); 192 __write_sbdshr(sport, reg, value);
193 if (SIBYTE_1956_WAR) 193 if (SIBYTE_1956_WAR)
194 __war_sbd1956(sport); 194 __war_sbd1956(sport);
195 } 195 }
196 196
197 197
198 static int sbd_receive_ready(struct sbd_port * 198 static int sbd_receive_ready(struct sbd_port *sport)
199 { 199 {
200 return read_sbdchn(sport, R_DUART_STAT 200 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
201 } 201 }
202 202
203 static int sbd_receive_drain(struct sbd_port * 203 static int sbd_receive_drain(struct sbd_port *sport)
204 { 204 {
205 int loops = 10000; 205 int loops = 10000;
206 206
207 while (sbd_receive_ready(sport) && loo !! 207 while (sbd_receive_ready(sport) && --loops)
208 read_sbdchn(sport, R_DUART_RX_ 208 read_sbdchn(sport, R_DUART_RX_HOLD);
209 return loops; 209 return loops;
210 } 210 }
211 211
212 static int __maybe_unused sbd_transmit_ready(s 212 static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
213 { 213 {
214 return read_sbdchn(sport, R_DUART_STAT 214 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
215 } 215 }
216 216
217 static int __maybe_unused sbd_transmit_drain(s 217 static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
218 { 218 {
219 int loops = 10000; 219 int loops = 10000;
220 220
221 while (!sbd_transmit_ready(sport) && l !! 221 while (!sbd_transmit_ready(sport) && --loops)
222 udelay(2); 222 udelay(2);
223 return loops; 223 return loops;
224 } 224 }
225 225
226 static int sbd_transmit_empty(struct sbd_port 226 static int sbd_transmit_empty(struct sbd_port *sport)
227 { 227 {
228 return read_sbdchn(sport, R_DUART_STAT 228 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
229 } 229 }
230 230
231 static int sbd_line_drain(struct sbd_port *spo 231 static int sbd_line_drain(struct sbd_port *sport)
232 { 232 {
233 int loops = 10000; 233 int loops = 10000;
234 234
235 while (!sbd_transmit_empty(sport) && l !! 235 while (!sbd_transmit_empty(sport) && --loops)
236 udelay(2); 236 udelay(2);
237 return loops; 237 return loops;
238 } 238 }
239 239
240 240
241 static unsigned int sbd_tx_empty(struct uart_p 241 static unsigned int sbd_tx_empty(struct uart_port *uport)
242 { 242 {
243 struct sbd_port *sport = to_sport(upor 243 struct sbd_port *sport = to_sport(uport);
244 244
245 return sbd_transmit_empty(sport) ? TIO 245 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
246 } 246 }
247 247
248 static unsigned int sbd_get_mctrl(struct uart_ 248 static unsigned int sbd_get_mctrl(struct uart_port *uport)
249 { 249 {
250 struct sbd_port *sport = to_sport(upor 250 struct sbd_port *sport = to_sport(uport);
251 unsigned int mctrl, status; 251 unsigned int mctrl, status;
252 252
253 status = read_sbdshr(sport, R_DUART_IN 253 status = read_sbdshr(sport, R_DUART_IN_PORT);
254 status >>= (uport->line) % 2; 254 status >>= (uport->line) % 2;
255 mctrl = (!(status & M_DUART_IN_PIN0_VA 255 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
256 (!(status & M_DUART_IN_PIN4_VA 256 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
257 (!(status & M_DUART_RIN0_PIN) 257 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
258 (!(status & M_DUART_IN_PIN2_VA 258 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
259 return mctrl; 259 return mctrl;
260 } 260 }
261 261
262 static void sbd_set_mctrl(struct uart_port *up 262 static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
263 { 263 {
264 struct sbd_port *sport = to_sport(upor 264 struct sbd_port *sport = to_sport(uport);
265 unsigned int clr = 0, set = 0, mode2; 265 unsigned int clr = 0, set = 0, mode2;
266 266
267 if (mctrl & TIOCM_DTR) 267 if (mctrl & TIOCM_DTR)
268 set |= M_DUART_SET_OPR2; 268 set |= M_DUART_SET_OPR2;
269 else 269 else
270 clr |= M_DUART_CLR_OPR2; 270 clr |= M_DUART_CLR_OPR2;
271 if (mctrl & TIOCM_RTS) 271 if (mctrl & TIOCM_RTS)
272 set |= M_DUART_SET_OPR0; 272 set |= M_DUART_SET_OPR0;
273 else 273 else
274 clr |= M_DUART_CLR_OPR0; 274 clr |= M_DUART_CLR_OPR0;
275 clr <<= (uport->line) % 2; 275 clr <<= (uport->line) % 2;
276 set <<= (uport->line) % 2; 276 set <<= (uport->line) % 2;
277 277
278 mode2 = read_sbdchn(sport, R_DUART_MOD 278 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
279 mode2 &= ~M_DUART_CHAN_MODE; 279 mode2 &= ~M_DUART_CHAN_MODE;
280 if (mctrl & TIOCM_LOOP) 280 if (mctrl & TIOCM_LOOP)
281 mode2 |= V_DUART_CHAN_MODE_LCL 281 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
282 else 282 else
283 mode2 |= V_DUART_CHAN_MODE_NOR 283 mode2 |= V_DUART_CHAN_MODE_NORMAL;
284 284
285 write_sbdshr(sport, R_DUART_CLEAR_OPR, 285 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
286 write_sbdshr(sport, R_DUART_SET_OPR, s 286 write_sbdshr(sport, R_DUART_SET_OPR, set);
287 write_sbdchn(sport, R_DUART_MODE_REG_2 287 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
288 } 288 }
289 289
290 static void sbd_stop_tx(struct uart_port *upor 290 static void sbd_stop_tx(struct uart_port *uport)
291 { 291 {
292 struct sbd_port *sport = to_sport(upor 292 struct sbd_port *sport = to_sport(uport);
293 293
294 write_sbdchn(sport, R_DUART_CMD, M_DUA 294 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
295 sport->tx_stopped = 1; 295 sport->tx_stopped = 1;
296 }; 296 };
297 297
298 static void sbd_start_tx(struct uart_port *upo 298 static void sbd_start_tx(struct uart_port *uport)
299 { 299 {
300 struct sbd_port *sport = to_sport(upor 300 struct sbd_port *sport = to_sport(uport);
301 unsigned int mask; 301 unsigned int mask;
302 302
303 /* Enable tx interrupts. */ 303 /* Enable tx interrupts. */
304 mask = read_sbdshr(sport, R_DUART_IMRR 304 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
305 mask |= M_DUART_IMR_TX; 305 mask |= M_DUART_IMR_TX;
306 write_sbdshr(sport, R_DUART_IMRREG((up 306 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
307 307
308 /* Go!, go!, go!... */ 308 /* Go!, go!, go!... */
309 write_sbdchn(sport, R_DUART_CMD, M_DUA 309 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
310 sport->tx_stopped = 0; 310 sport->tx_stopped = 0;
311 }; 311 };
312 312
313 static void sbd_stop_rx(struct uart_port *upor 313 static void sbd_stop_rx(struct uart_port *uport)
314 { 314 {
315 struct sbd_port *sport = to_sport(upor 315 struct sbd_port *sport = to_sport(uport);
316 316
317 write_sbdshr(sport, R_DUART_IMRREG((up 317 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
318 }; 318 };
319 319
320 static void sbd_enable_ms(struct uart_port *up 320 static void sbd_enable_ms(struct uart_port *uport)
321 { 321 {
322 struct sbd_port *sport = to_sport(upor 322 struct sbd_port *sport = to_sport(uport);
323 323
324 write_sbdchn(sport, R_DUART_AUXCTL_X, 324 write_sbdchn(sport, R_DUART_AUXCTL_X,
325 M_DUART_CIN_CHNG_ENA | M_ 325 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
326 } 326 }
327 327
328 static void sbd_break_ctl(struct uart_port *up 328 static void sbd_break_ctl(struct uart_port *uport, int break_state)
329 { 329 {
330 struct sbd_port *sport = to_sport(upor 330 struct sbd_port *sport = to_sport(uport);
331 331
332 if (break_state == -1) 332 if (break_state == -1)
333 write_sbdchn(sport, R_DUART_CM 333 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
334 else 334 else
335 write_sbdchn(sport, R_DUART_CM 335 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
336 } 336 }
337 337
338 338
339 static void sbd_receive_chars(struct sbd_port 339 static void sbd_receive_chars(struct sbd_port *sport)
340 { 340 {
341 struct uart_port *uport = &sport->port 341 struct uart_port *uport = &sport->port;
342 struct uart_icount *icount; 342 struct uart_icount *icount;
343 unsigned int status, ch, flag; 343 unsigned int status, ch, flag;
344 int count; 344 int count;
345 345
346 for (count = 16; count; count--) { 346 for (count = 16; count; count--) {
347 status = read_sbdchn(sport, R_ 347 status = read_sbdchn(sport, R_DUART_STATUS);
348 if (!(status & M_DUART_RX_RDY) 348 if (!(status & M_DUART_RX_RDY))
349 break; 349 break;
350 350
351 ch = read_sbdchn(sport, R_DUAR 351 ch = read_sbdchn(sport, R_DUART_RX_HOLD);
352 352
353 flag = TTY_NORMAL; 353 flag = TTY_NORMAL;
354 354
355 icount = &uport->icount; 355 icount = &uport->icount;
356 icount->rx++; 356 icount->rx++;
357 357
358 if (unlikely(status & 358 if (unlikely(status &
359 (M_DUART_RCVD_BRK 359 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
360 M_DUART_PARITY_E 360 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
361 if (status & M_DUART_R 361 if (status & M_DUART_RCVD_BRK) {
362 icount->brk++; 362 icount->brk++;
363 if (uart_handl 363 if (uart_handle_break(uport))
364 contin 364 continue;
365 } else if (status & M_ 365 } else if (status & M_DUART_FRM_ERR)
366 icount->frame+ 366 icount->frame++;
367 else if (status & M_DU 367 else if (status & M_DUART_PARITY_ERR)
368 icount->parity 368 icount->parity++;
369 if (status & M_DUART_O 369 if (status & M_DUART_OVRUN_ERR)
370 icount->overru 370 icount->overrun++;
371 371
372 status &= uport->read_ 372 status &= uport->read_status_mask;
373 if (status & M_DUART_R 373 if (status & M_DUART_RCVD_BRK)
374 flag = TTY_BRE 374 flag = TTY_BREAK;
375 else if (status & M_DU 375 else if (status & M_DUART_FRM_ERR)
376 flag = TTY_FRA 376 flag = TTY_FRAME;
377 else if (status & M_DU 377 else if (status & M_DUART_PARITY_ERR)
378 flag = TTY_PAR 378 flag = TTY_PARITY;
379 } 379 }
380 380
381 if (uart_handle_sysrq_char(upo 381 if (uart_handle_sysrq_char(uport, ch))
382 continue; 382 continue;
383 383
384 uart_insert_char(uport, status 384 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
385 } 385 }
386 386
387 tty_flip_buffer_push(uport->info->tty) !! 387 tty_flip_buffer_push(uport->info->port.tty);
388 } 388 }
389 389
390 static void sbd_transmit_chars(struct sbd_port 390 static void sbd_transmit_chars(struct sbd_port *sport)
391 { 391 {
392 struct uart_port *uport = &sport->port 392 struct uart_port *uport = &sport->port;
393 struct circ_buf *xmit = &sport->port.i 393 struct circ_buf *xmit = &sport->port.info->xmit;
394 unsigned int mask; 394 unsigned int mask;
395 int stop_tx; 395 int stop_tx;
396 396
397 /* XON/XOFF chars. */ 397 /* XON/XOFF chars. */
398 if (sport->port.x_char) { 398 if (sport->port.x_char) {
399 write_sbdchn(sport, R_DUART_TX 399 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
400 sport->port.icount.tx++; 400 sport->port.icount.tx++;
401 sport->port.x_char = 0; 401 sport->port.x_char = 0;
402 return; 402 return;
403 } 403 }
404 404
405 /* If nothing to do or stopped or hard 405 /* If nothing to do or stopped or hardware stopped. */
406 stop_tx = (uart_circ_empty(xmit) || ua 406 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
407 407
408 /* Send char. */ 408 /* Send char. */
409 if (!stop_tx) { 409 if (!stop_tx) {
410 write_sbdchn(sport, R_DUART_TX 410 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
411 xmit->tail = (xmit->tail + 1) 411 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
412 sport->port.icount.tx++; 412 sport->port.icount.tx++;
413 413
414 if (uart_circ_chars_pending(xm 414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
415 uart_write_wakeup(&spo 415 uart_write_wakeup(&sport->port);
416 } 416 }
417 417
418 /* Are we are done? */ 418 /* Are we are done? */
419 if (stop_tx || uart_circ_empty(xmit)) 419 if (stop_tx || uart_circ_empty(xmit)) {
420 /* Disable tx interrupts. */ 420 /* Disable tx interrupts. */
421 mask = read_sbdshr(sport, R_DU 421 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
422 mask &= ~M_DUART_IMR_TX; 422 mask &= ~M_DUART_IMR_TX;
423 write_sbdshr(sport, R_DUART_IM 423 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
424 } 424 }
425 } 425 }
426 426
427 static void sbd_status_handle(struct sbd_port 427 static void sbd_status_handle(struct sbd_port *sport)
428 { 428 {
429 struct uart_port *uport = &sport->port 429 struct uart_port *uport = &sport->port;
430 unsigned int delta; 430 unsigned int delta;
431 431
432 delta = read_sbdshr(sport, R_DUART_INC 432 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
433 delta >>= (uport->line) % 2; 433 delta >>= (uport->line) % 2;
434 434
435 if (delta & (M_DUART_IN_PIN0_VAL << S_ 435 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
436 uart_handle_cts_change(uport, 436 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
437 437
438 if (delta & (M_DUART_IN_PIN2_VAL << S_ 438 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
439 uport->icount.dsr++; 439 uport->icount.dsr++;
440 440
441 if (delta & ((M_DUART_IN_PIN2_VAL | M_ 441 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
442 S_DUART_IN_PIN_CHNG)) 442 S_DUART_IN_PIN_CHNG))
443 wake_up_interruptible(&uport-> 443 wake_up_interruptible(&uport->info->delta_msr_wait);
444 } 444 }
445 445
446 static irqreturn_t sbd_interrupt(int irq, void 446 static irqreturn_t sbd_interrupt(int irq, void *dev_id)
447 { 447 {
448 struct sbd_port *sport = dev_id; 448 struct sbd_port *sport = dev_id;
449 struct uart_port *uport = &sport->port 449 struct uart_port *uport = &sport->port;
450 irqreturn_t status = IRQ_NONE; 450 irqreturn_t status = IRQ_NONE;
451 unsigned int intstat; 451 unsigned int intstat;
452 int count; 452 int count;
453 453
454 for (count = 16; count; count--) { 454 for (count = 16; count; count--) {
455 intstat = read_sbdshr(sport, 455 intstat = read_sbdshr(sport,
456 R_DUART_ 456 R_DUART_ISRREG((uport->line) % 2));
457 intstat &= read_sbdshr(sport, 457 intstat &= read_sbdshr(sport,
458 R_DUART 458 R_DUART_IMRREG((uport->line) % 2));
459 intstat &= M_DUART_ISR_ALL; 459 intstat &= M_DUART_ISR_ALL;
460 if (!intstat) 460 if (!intstat)
461 break; 461 break;
462 462
463 if (intstat & M_DUART_ISR_RX) 463 if (intstat & M_DUART_ISR_RX)
464 sbd_receive_chars(spor 464 sbd_receive_chars(sport);
465 if (intstat & M_DUART_ISR_IN) 465 if (intstat & M_DUART_ISR_IN)
466 sbd_status_handle(spor 466 sbd_status_handle(sport);
467 if (intstat & M_DUART_ISR_TX) 467 if (intstat & M_DUART_ISR_TX)
468 sbd_transmit_chars(spo 468 sbd_transmit_chars(sport);
469 469
470 status = IRQ_HANDLED; 470 status = IRQ_HANDLED;
471 } 471 }
472 472
473 return status; 473 return status;
474 } 474 }
475 475
476 476
477 static int sbd_startup(struct uart_port *uport 477 static int sbd_startup(struct uart_port *uport)
478 { 478 {
479 struct sbd_port *sport = to_sport(upor 479 struct sbd_port *sport = to_sport(uport);
480 unsigned int mode1; 480 unsigned int mode1;
481 int ret; 481 int ret;
482 482
483 ret = request_irq(sport->port.irq, sbd 483 ret = request_irq(sport->port.irq, sbd_interrupt,
484 IRQF_SHARED, "sb1250 484 IRQF_SHARED, "sb1250-duart", sport);
485 if (ret) 485 if (ret)
486 return ret; 486 return ret;
487 487
488 /* Clear the receive FIFO. */ 488 /* Clear the receive FIFO. */
489 sbd_receive_drain(sport); 489 sbd_receive_drain(sport);
490 490
491 /* Clear the interrupt registers. */ 491 /* Clear the interrupt registers. */
492 write_sbdchn(sport, R_DUART_CMD, V_DUA 492 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
493 read_sbdshr(sport, R_DUART_INCHREG((up 493 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
494 494
495 /* Set rx/tx interrupt to FIFO availab 495 /* Set rx/tx interrupt to FIFO available. */
496 mode1 = read_sbdchn(sport, R_DUART_MOD 496 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
497 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | 497 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
498 write_sbdchn(sport, R_DUART_MODE_REG_1 498 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
499 499
500 /* Disable tx, enable rx. */ 500 /* Disable tx, enable rx. */
501 write_sbdchn(sport, R_DUART_CMD, M_DUA 501 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
502 sport->tx_stopped = 1; 502 sport->tx_stopped = 1;
503 503
504 /* Enable interrupts. */ 504 /* Enable interrupts. */
505 write_sbdshr(sport, R_DUART_IMRREG((up 505 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
506 M_DUART_IMR_IN | M_DUART_ 506 M_DUART_IMR_IN | M_DUART_IMR_RX);
507 507
508 return 0; 508 return 0;
509 } 509 }
510 510
511 static void sbd_shutdown(struct uart_port *upo 511 static void sbd_shutdown(struct uart_port *uport)
512 { 512 {
513 struct sbd_port *sport = to_sport(upor 513 struct sbd_port *sport = to_sport(uport);
514 514
515 write_sbdchn(sport, R_DUART_CMD, M_DUA 515 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
516 sport->tx_stopped = 1; 516 sport->tx_stopped = 1;
517 free_irq(sport->port.irq, sport); 517 free_irq(sport->port.irq, sport);
518 } 518 }
519 519
520 520
521 static void sbd_init_port(struct sbd_port *spo 521 static void sbd_init_port(struct sbd_port *sport)
522 { 522 {
523 struct uart_port *uport = &sport->port 523 struct uart_port *uport = &sport->port;
524 524
525 if (sport->initialised) 525 if (sport->initialised)
526 return; 526 return;
527 527
528 /* There is no DUART reset feature, so 528 /* There is no DUART reset feature, so just set some sane defaults. */
529 write_sbdchn(sport, R_DUART_CMD, V_DUA 529 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
530 write_sbdchn(sport, R_DUART_CMD, V_DUA 530 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
531 write_sbdchn(sport, R_DUART_MODE_REG_1 531 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
532 write_sbdchn(sport, R_DUART_MODE_REG_2 532 write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
533 write_sbdchn(sport, R_DUART_FULL_CTL, 533 write_sbdchn(sport, R_DUART_FULL_CTL,
534 V_DUART_INT_TIME(0) | V_D 534 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
535 write_sbdchn(sport, R_DUART_OPCR_X, 0) 535 write_sbdchn(sport, R_DUART_OPCR_X, 0);
536 write_sbdchn(sport, R_DUART_AUXCTL_X, 536 write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
537 write_sbdshr(sport, R_DUART_IMRREG((up 537 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
538 538
539 sport->initialised = 1; 539 sport->initialised = 1;
540 } 540 }
541 541
542 static void sbd_set_termios(struct uart_port * 542 static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
543 struct ktermios *o 543 struct ktermios *old_termios)
544 { 544 {
545 struct sbd_port *sport = to_sport(upor 545 struct sbd_port *sport = to_sport(uport);
546 unsigned int mode1 = 0, mode2 = 0, aux 546 unsigned int mode1 = 0, mode2 = 0, aux = 0;
547 unsigned int mode1mask = 0, mode2mask 547 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
548 unsigned int oldmode1, oldmode2, oldau 548 unsigned int oldmode1, oldmode2, oldaux;
549 unsigned int baud, brg; 549 unsigned int baud, brg;
550 unsigned int command; 550 unsigned int command;
551 551
552 mode1mask |= ~(M_DUART_PARITY_MODE | M 552 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
553 M_DUART_BITS_PER_CHAR); 553 M_DUART_BITS_PER_CHAR);
554 mode2mask |= ~M_DUART_STOP_BIT_LEN_2; 554 mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
555 auxmask |= ~M_DUART_CTS_CHNG_ENA; 555 auxmask |= ~M_DUART_CTS_CHNG_ENA;
556 556
557 /* Byte size. */ 557 /* Byte size. */
558 switch (termios->c_cflag & CSIZE) { 558 switch (termios->c_cflag & CSIZE) {
559 case CS5: 559 case CS5:
560 case CS6: 560 case CS6:
561 /* Unsupported, leave unchange 561 /* Unsupported, leave unchanged. */
562 mode1mask |= M_DUART_PARITY_MO 562 mode1mask |= M_DUART_PARITY_MODE;
563 break; 563 break;
564 case CS7: 564 case CS7:
565 mode1 |= V_DUART_BITS_PER_CHAR 565 mode1 |= V_DUART_BITS_PER_CHAR_7;
566 break; 566 break;
567 case CS8: 567 case CS8:
568 default: 568 default:
569 mode1 |= V_DUART_BITS_PER_CHAR 569 mode1 |= V_DUART_BITS_PER_CHAR_8;
570 break; 570 break;
571 } 571 }
572 572
573 /* Parity and stop bits. */ 573 /* Parity and stop bits. */
574 if (termios->c_cflag & CSTOPB) 574 if (termios->c_cflag & CSTOPB)
575 mode2 |= M_DUART_STOP_BIT_LEN_ 575 mode2 |= M_DUART_STOP_BIT_LEN_2;
576 else 576 else
577 mode2 |= M_DUART_STOP_BIT_LEN_ 577 mode2 |= M_DUART_STOP_BIT_LEN_1;
578 if (termios->c_cflag & PARENB) 578 if (termios->c_cflag & PARENB)
579 mode1 |= V_DUART_PARITY_MODE_A 579 mode1 |= V_DUART_PARITY_MODE_ADD;
580 else 580 else
581 mode1 |= V_DUART_PARITY_MODE_N 581 mode1 |= V_DUART_PARITY_MODE_NONE;
582 if (termios->c_cflag & PARODD) 582 if (termios->c_cflag & PARODD)
583 mode1 |= M_DUART_PARITY_TYPE_O 583 mode1 |= M_DUART_PARITY_TYPE_ODD;
584 else 584 else
585 mode1 |= M_DUART_PARITY_TYPE_E 585 mode1 |= M_DUART_PARITY_TYPE_EVEN;
586 586
587 baud = uart_get_baud_rate(uport, termi 587 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
588 brg = V_DUART_BAUD_RATE(baud); 588 brg = V_DUART_BAUD_RATE(baud);
589 /* The actual lower bound is 1221bps, 589 /* The actual lower bound is 1221bps, so compensate. */
590 if (brg > M_DUART_CLK_COUNTER) 590 if (brg > M_DUART_CLK_COUNTER)
591 brg = M_DUART_CLK_COUNTER; 591 brg = M_DUART_CLK_COUNTER;
592 592
593 uart_update_timeout(uport, termios->c_ 593 uart_update_timeout(uport, termios->c_cflag, baud);
594 594
595 uport->read_status_mask = M_DUART_OVRU 595 uport->read_status_mask = M_DUART_OVRUN_ERR;
596 if (termios->c_iflag & INPCK) 596 if (termios->c_iflag & INPCK)
597 uport->read_status_mask |= M_D 597 uport->read_status_mask |= M_DUART_FRM_ERR |
598 M_D 598 M_DUART_PARITY_ERR;
599 if (termios->c_iflag & (BRKINT | PARMR 599 if (termios->c_iflag & (BRKINT | PARMRK))
600 uport->read_status_mask |= M_D 600 uport->read_status_mask |= M_DUART_RCVD_BRK;
601 601
602 uport->ignore_status_mask = 0; 602 uport->ignore_status_mask = 0;
603 if (termios->c_iflag & IGNPAR) 603 if (termios->c_iflag & IGNPAR)
604 uport->ignore_status_mask |= M 604 uport->ignore_status_mask |= M_DUART_FRM_ERR |
605 M 605 M_DUART_PARITY_ERR;
606 if (termios->c_iflag & IGNBRK) { 606 if (termios->c_iflag & IGNBRK) {
607 uport->ignore_status_mask |= M 607 uport->ignore_status_mask |= M_DUART_RCVD_BRK;
608 if (termios->c_iflag & IGNPAR) 608 if (termios->c_iflag & IGNPAR)
609 uport->ignore_status_m 609 uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
610 } 610 }
611 611
612 if (termios->c_cflag & CREAD) 612 if (termios->c_cflag & CREAD)
613 command = M_DUART_RX_EN; 613 command = M_DUART_RX_EN;
614 else 614 else
615 command = M_DUART_RX_DIS; 615 command = M_DUART_RX_DIS;
616 616
617 if (termios->c_cflag & CRTSCTS) 617 if (termios->c_cflag & CRTSCTS)
618 aux |= M_DUART_CTS_CHNG_ENA; 618 aux |= M_DUART_CTS_CHNG_ENA;
619 else 619 else
620 aux &= ~M_DUART_CTS_CHNG_ENA; 620 aux &= ~M_DUART_CTS_CHNG_ENA;
621 621
622 spin_lock(&uport->lock); 622 spin_lock(&uport->lock);
623 623
624 if (sport->tx_stopped) 624 if (sport->tx_stopped)
625 command |= M_DUART_TX_DIS; 625 command |= M_DUART_TX_DIS;
626 else 626 else
627 command |= M_DUART_TX_EN; 627 command |= M_DUART_TX_EN;
628 628
629 oldmode1 = read_sbdchn(sport, R_DUART_ 629 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
630 oldmode2 = read_sbdchn(sport, R_DUART_ 630 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
631 oldaux = read_sbdchn(sport, R_DUART_AU 631 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
632 632
633 if (!sport->tx_stopped) 633 if (!sport->tx_stopped)
634 sbd_line_drain(sport); 634 sbd_line_drain(sport);
635 write_sbdchn(sport, R_DUART_CMD, M_DUA 635 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
636 636
637 write_sbdchn(sport, R_DUART_MODE_REG_1 637 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
638 write_sbdchn(sport, R_DUART_MODE_REG_2 638 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
639 write_sbdchn(sport, R_DUART_CLK_SEL, b 639 write_sbdchn(sport, R_DUART_CLK_SEL, brg);
640 write_sbdchn(sport, R_DUART_AUXCTL_X, 640 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
641 641
642 write_sbdchn(sport, R_DUART_CMD, comma 642 write_sbdchn(sport, R_DUART_CMD, command);
643 643
644 spin_unlock(&uport->lock); 644 spin_unlock(&uport->lock);
645 } 645 }
646 646
647 647
648 static const char *sbd_type(struct uart_port * 648 static const char *sbd_type(struct uart_port *uport)
649 { 649 {
650 return "SB1250 DUART"; 650 return "SB1250 DUART";
651 } 651 }
652 652
653 static void sbd_release_port(struct uart_port 653 static void sbd_release_port(struct uart_port *uport)
654 { 654 {
655 struct sbd_port *sport = to_sport(upor 655 struct sbd_port *sport = to_sport(uport);
656 struct sbd_duart *duart = sport->duart 656 struct sbd_duart *duart = sport->duart;
657 int map_guard; 657 int map_guard;
658 658
659 iounmap(sport->memctrl); 659 iounmap(sport->memctrl);
660 sport->memctrl = NULL; 660 sport->memctrl = NULL;
661 iounmap(uport->membase); 661 iounmap(uport->membase);
662 uport->membase = NULL; 662 uport->membase = NULL;
663 663
664 map_guard = atomic_add_return(-1, &dua 664 map_guard = atomic_add_return(-1, &duart->map_guard);
665 if (!map_guard) 665 if (!map_guard)
666 release_mem_region(duart->mapc 666 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
667 release_mem_region(uport->mapbase, DUA 667 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
668 } 668 }
669 669
670 static int sbd_map_port(struct uart_port *upor 670 static int sbd_map_port(struct uart_port *uport)
671 { 671 {
672 const char *err = KERN_ERR "sbd: Canno 672 const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
673 struct sbd_port *sport = to_sport(upor 673 struct sbd_port *sport = to_sport(uport);
674 struct sbd_duart *duart = sport->duart 674 struct sbd_duart *duart = sport->duart;
675 675
676 if (!uport->membase) 676 if (!uport->membase)
677 uport->membase = ioremap_nocac 677 uport->membase = ioremap_nocache(uport->mapbase,
678 678 DUART_CHANREG_SPACING);
679 if (!uport->membase) { 679 if (!uport->membase) {
680 printk(err); 680 printk(err);
681 return -ENOMEM; 681 return -ENOMEM;
682 } 682 }
683 683
684 if (!sport->memctrl) 684 if (!sport->memctrl)
685 sport->memctrl = ioremap_nocac 685 sport->memctrl = ioremap_nocache(duart->mapctrl,
686 686 DUART_CHANREG_SPACING);
687 if (!sport->memctrl) { 687 if (!sport->memctrl) {
688 printk(err); 688 printk(err);
689 iounmap(uport->membase); 689 iounmap(uport->membase);
690 uport->membase = NULL; 690 uport->membase = NULL;
691 return -ENOMEM; 691 return -ENOMEM;
692 } 692 }
693 693
694 return 0; 694 return 0;
695 } 695 }
696 696
697 static int sbd_request_port(struct uart_port * 697 static int sbd_request_port(struct uart_port *uport)
698 { 698 {
699 const char *err = KERN_ERR "sbd: Unabl 699 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
700 struct sbd_duart *duart = to_sport(upo 700 struct sbd_duart *duart = to_sport(uport)->duart;
701 int map_guard; 701 int map_guard;
702 int ret = 0; 702 int ret = 0;
703 703
704 if (!request_mem_region(uport->mapbase 704 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
705 "sb1250-duart" 705 "sb1250-duart")) {
706 printk(err); 706 printk(err);
707 return -EBUSY; 707 return -EBUSY;
708 } 708 }
709 map_guard = atomic_add_return(1, &duar 709 map_guard = atomic_add_return(1, &duart->map_guard);
710 if (map_guard == 1) { 710 if (map_guard == 1) {
711 if (!request_mem_region(duart- 711 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
712 "sb125 712 "sb1250-duart")) {
713 atomic_add(-1, &duart- 713 atomic_add(-1, &duart->map_guard);
714 printk(err); 714 printk(err);
715 ret = -EBUSY; 715 ret = -EBUSY;
716 } 716 }
717 } 717 }
718 if (!ret) { 718 if (!ret) {
719 ret = sbd_map_port(uport); 719 ret = sbd_map_port(uport);
720 if (ret) { 720 if (ret) {
721 map_guard = atomic_add 721 map_guard = atomic_add_return(-1, &duart->map_guard);
722 if (!map_guard) 722 if (!map_guard)
723 release_mem_re 723 release_mem_region(duart->mapctrl,
724 724 DUART_CHANREG_SPACING);
725 } 725 }
726 } 726 }
727 if (ret) { 727 if (ret) {
728 release_mem_region(uport->mapb 728 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
729 return ret; 729 return ret;
730 } 730 }
731 return 0; 731 return 0;
732 } 732 }
733 733
734 static void sbd_config_port(struct uart_port * 734 static void sbd_config_port(struct uart_port *uport, int flags)
735 { 735 {
736 struct sbd_port *sport = to_sport(upor 736 struct sbd_port *sport = to_sport(uport);
737 737
738 if (flags & UART_CONFIG_TYPE) { 738 if (flags & UART_CONFIG_TYPE) {
739 if (sbd_request_port(uport)) 739 if (sbd_request_port(uport))
740 return; 740 return;
741 741
742 uport->type = PORT_SB1250_DUAR 742 uport->type = PORT_SB1250_DUART;
743 743
744 sbd_init_port(sport); 744 sbd_init_port(sport);
745 } 745 }
746 } 746 }
747 747
748 static int sbd_verify_port(struct uart_port *u 748 static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
749 { 749 {
750 int ret = 0; 750 int ret = 0;
751 751
752 if (ser->type != PORT_UNKNOWN && ser-> 752 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
753 ret = -EINVAL; 753 ret = -EINVAL;
754 if (ser->irq != uport->irq) 754 if (ser->irq != uport->irq)
755 ret = -EINVAL; 755 ret = -EINVAL;
756 if (ser->baud_base != uport->uartclk / 756 if (ser->baud_base != uport->uartclk / 16)
757 ret = -EINVAL; 757 ret = -EINVAL;
758 return ret; 758 return ret;
759 } 759 }
760 760
761 761
762 static const struct uart_ops sbd_ops = { 762 static const struct uart_ops sbd_ops = {
763 .tx_empty = sbd_tx_empty, 763 .tx_empty = sbd_tx_empty,
764 .set_mctrl = sbd_set_mctrl, 764 .set_mctrl = sbd_set_mctrl,
765 .get_mctrl = sbd_get_mctrl, 765 .get_mctrl = sbd_get_mctrl,
766 .stop_tx = sbd_stop_tx, 766 .stop_tx = sbd_stop_tx,
767 .start_tx = sbd_start_tx, 767 .start_tx = sbd_start_tx,
768 .stop_rx = sbd_stop_rx, 768 .stop_rx = sbd_stop_rx,
769 .enable_ms = sbd_enable_ms, 769 .enable_ms = sbd_enable_ms,
770 .break_ctl = sbd_break_ctl, 770 .break_ctl = sbd_break_ctl,
771 .startup = sbd_startup, 771 .startup = sbd_startup,
772 .shutdown = sbd_shutdown, 772 .shutdown = sbd_shutdown,
773 .set_termios = sbd_set_termios, 773 .set_termios = sbd_set_termios,
774 .type = sbd_type, 774 .type = sbd_type,
775 .release_port = sbd_release_port, 775 .release_port = sbd_release_port,
776 .request_port = sbd_request_port, 776 .request_port = sbd_request_port,
777 .config_port = sbd_config_port, 777 .config_port = sbd_config_port,
778 .verify_port = sbd_verify_port, 778 .verify_port = sbd_verify_port,
779 }; 779 };
780 780
781 /* Initialize SB1250 DUART port structures. * 781 /* Initialize SB1250 DUART port structures. */
782 static void __init sbd_probe_duarts(void) 782 static void __init sbd_probe_duarts(void)
783 { 783 {
784 static int probed; 784 static int probed;
785 int chip, side; 785 int chip, side;
786 int max_lines, line; 786 int max_lines, line;
787 787
788 if (probed) 788 if (probed)
789 return; 789 return;
790 790
791 /* Set the number of available units b 791 /* Set the number of available units based on the SOC type. */
792 switch (soc_type) { 792 switch (soc_type) {
793 case K_SYS_SOC_TYPE_BCM1x55: 793 case K_SYS_SOC_TYPE_BCM1x55:
794 case K_SYS_SOC_TYPE_BCM1x80: 794 case K_SYS_SOC_TYPE_BCM1x80:
795 max_lines = 4; 795 max_lines = 4;
796 break; 796 break;
797 default: 797 default:
798 /* Assume at least two serial 798 /* Assume at least two serial ports at the normal address. */
799 max_lines = 2; 799 max_lines = 2;
800 break; 800 break;
801 } 801 }
802 802
803 probed = 1; 803 probed = 1;
804 804
805 for (chip = 0, line = 0; chip < DUART_ 805 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
806 chip++) { 806 chip++) {
807 sbd_duarts[chip].mapctrl = SBD 807 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
808 808
809 for (side = 0; side < DUART_MA 809 for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
810 side++, line++) { 810 side++, line++) {
811 struct sbd_port *sport 811 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
812 struct uart_port *upor 812 struct uart_port *uport = &sport->port;
813 813
814 sport->duart = &sbd 814 sport->duart = &sbd_duarts[chip];
815 815
816 uport->irq = SBD_ 816 uport->irq = SBD_INT(line);
817 uport->uartclk = 1000 817 uport->uartclk = 100000000 / 20 * 16;
818 uport->fifosize = 16; 818 uport->fifosize = 16;
819 uport->iotype = UPIO 819 uport->iotype = UPIO_MEM;
820 uport->flags = UPF_ 820 uport->flags = UPF_BOOT_AUTOCONF;
821 uport->ops = &sbd 821 uport->ops = &sbd_ops;
822 uport->line = line 822 uport->line = line;
823 uport->mapbase = SBD_ 823 uport->mapbase = SBD_CHANREGS(line);
824 } 824 }
825 } 825 }
826 } 826 }
827 827
828 828
829 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE 829 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
830 /* 830 /*
831 * Serial console stuff. Very basic, polling 831 * Serial console stuff. Very basic, polling driver for doing serial
832 * console output. The console_sem is held by 832 * console output. The console_sem is held by the caller, so we
833 * shouldn't be interrupted for more console a 833 * shouldn't be interrupted for more console activity.
834 */ 834 */
835 static void sbd_console_putchar(struct uart_po 835 static void sbd_console_putchar(struct uart_port *uport, int ch)
836 { 836 {
837 struct sbd_port *sport = to_sport(upor 837 struct sbd_port *sport = to_sport(uport);
838 838
839 sbd_transmit_drain(sport); 839 sbd_transmit_drain(sport);
840 write_sbdchn(sport, R_DUART_TX_HOLD, c 840 write_sbdchn(sport, R_DUART_TX_HOLD, ch);
841 } 841 }
842 842
843 static void sbd_console_write(struct console * 843 static void sbd_console_write(struct console *co, const char *s,
844 unsigned int cou 844 unsigned int count)
845 { 845 {
846 int chip = co->index / DUART_MAX_SIDE; 846 int chip = co->index / DUART_MAX_SIDE;
847 int side = co->index % DUART_MAX_SIDE; 847 int side = co->index % DUART_MAX_SIDE;
848 struct sbd_port *sport = &sbd_duarts[c 848 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
849 struct uart_port *uport = &sport->port 849 struct uart_port *uport = &sport->port;
850 unsigned long flags; 850 unsigned long flags;
851 unsigned int mask; 851 unsigned int mask;
852 852
853 /* Disable transmit interrupts and ena 853 /* Disable transmit interrupts and enable the transmitter. */
854 spin_lock_irqsave(&uport->lock, flags) 854 spin_lock_irqsave(&uport->lock, flags);
855 mask = read_sbdshr(sport, R_DUART_IMRR 855 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
856 write_sbdshr(sport, R_DUART_IMRREG((up 856 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
857 mask & ~M_DUART_IMR_TX); 857 mask & ~M_DUART_IMR_TX);
858 write_sbdchn(sport, R_DUART_CMD, M_DUA 858 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
859 spin_unlock_irqrestore(&uport->lock, f 859 spin_unlock_irqrestore(&uport->lock, flags);
860 860
861 uart_console_write(&sport->port, s, co 861 uart_console_write(&sport->port, s, count, sbd_console_putchar);
862 862
863 /* Restore transmit interrupts and the 863 /* Restore transmit interrupts and the transmitter enable. */
864 spin_lock_irqsave(&uport->lock, flags) 864 spin_lock_irqsave(&uport->lock, flags);
865 sbd_line_drain(sport); 865 sbd_line_drain(sport);
866 if (sport->tx_stopped) 866 if (sport->tx_stopped)
867 write_sbdchn(sport, R_DUART_CM 867 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
868 write_sbdshr(sport, R_DUART_IMRREG((up 868 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
869 spin_unlock_irqrestore(&uport->lock, f 869 spin_unlock_irqrestore(&uport->lock, flags);
870 } 870 }
871 871
872 static int __init sbd_console_setup(struct con 872 static int __init sbd_console_setup(struct console *co, char *options)
873 { 873 {
874 int chip = co->index / DUART_MAX_SIDE; 874 int chip = co->index / DUART_MAX_SIDE;
875 int side = co->index % DUART_MAX_SIDE; 875 int side = co->index % DUART_MAX_SIDE;
876 struct sbd_port *sport = &sbd_duarts[c 876 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
877 struct uart_port *uport = &sport->port 877 struct uart_port *uport = &sport->port;
878 int baud = 115200; 878 int baud = 115200;
879 int bits = 8; 879 int bits = 8;
880 int parity = 'n'; 880 int parity = 'n';
881 int flow = 'n'; 881 int flow = 'n';
882 int ret; 882 int ret;
883 883
884 if (!sport->duart) 884 if (!sport->duart)
885 return -ENXIO; 885 return -ENXIO;
886 886
887 ret = sbd_map_port(uport); 887 ret = sbd_map_port(uport);
888 if (ret) 888 if (ret)
889 return ret; 889 return ret;
890 890
891 sbd_init_port(sport); 891 sbd_init_port(sport);
892 892
893 if (options) 893 if (options)
894 uart_parse_options(options, &b 894 uart_parse_options(options, &baud, &parity, &bits, &flow);
895 return uart_set_options(uport, co, bau 895 return uart_set_options(uport, co, baud, parity, bits, flow);
896 } 896 }
897 897
898 static struct uart_driver sbd_reg; 898 static struct uart_driver sbd_reg;
899 static struct console sbd_console = { 899 static struct console sbd_console = {
900 .name = "duart", 900 .name = "duart",
901 .write = sbd_console_write, 901 .write = sbd_console_write,
902 .device = uart_console_device, 902 .device = uart_console_device,
903 .setup = sbd_console_setup, 903 .setup = sbd_console_setup,
904 .flags = CON_PRINTBUFFER, 904 .flags = CON_PRINTBUFFER,
905 .index = -1, 905 .index = -1,
906 .data = &sbd_reg 906 .data = &sbd_reg
907 }; 907 };
908 908
909 static int __init sbd_serial_console_init(void 909 static int __init sbd_serial_console_init(void)
910 { 910 {
911 sbd_probe_duarts(); 911 sbd_probe_duarts();
912 register_console(&sbd_console); 912 register_console(&sbd_console);
913 913
914 return 0; 914 return 0;
915 } 915 }
916 916
917 console_initcall(sbd_serial_console_init); 917 console_initcall(sbd_serial_console_init);
918 918
919 #define SERIAL_SB1250_DUART_CONSOLE &sbd_c 919 #define SERIAL_SB1250_DUART_CONSOLE &sbd_console
920 #else 920 #else
921 #define SERIAL_SB1250_DUART_CONSOLE NULL 921 #define SERIAL_SB1250_DUART_CONSOLE NULL
922 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE * 922 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
923 923
924 924
925 static struct uart_driver sbd_reg = { 925 static struct uart_driver sbd_reg = {
926 .owner = THIS_MODULE, 926 .owner = THIS_MODULE,
927 .driver_name = "serial", !! 927 .driver_name = "sb1250_duart",
928 .dev_name = "duart", 928 .dev_name = "duart",
929 .major = TTY_MAJOR, 929 .major = TTY_MAJOR,
930 .minor = SB1250_DUART_MINOR_B 930 .minor = SB1250_DUART_MINOR_BASE,
931 .nr = DUART_MAX_CHIP * DUA 931 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
932 .cons = SERIAL_SB1250_DUART_ 932 .cons = SERIAL_SB1250_DUART_CONSOLE,
933 }; 933 };
934 934
935 /* Set up the driver and register it. */ 935 /* Set up the driver and register it. */
936 static int __init sbd_init(void) 936 static int __init sbd_init(void)
937 { 937 {
938 int i, ret; 938 int i, ret;
939 939
940 sbd_probe_duarts(); 940 sbd_probe_duarts();
941 941
942 ret = uart_register_driver(&sbd_reg); 942 ret = uart_register_driver(&sbd_reg);
943 if (ret) 943 if (ret)
944 return ret; 944 return ret;
945 945
946 for (i = 0; i < DUART_MAX_CHIP * DUART 946 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
947 struct sbd_duart *duart = &sbd 947 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
948 struct sbd_port *sport = &duar 948 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
949 struct uart_port *uport = &spo 949 struct uart_port *uport = &sport->port;
950 950
951 if (sport->duart) 951 if (sport->duart)
952 uart_add_one_port(&sbd 952 uart_add_one_port(&sbd_reg, uport);
953 } 953 }
954 954
955 return 0; 955 return 0;
956 } 956 }
957 957
958 /* Unload the driver. Unregister stuff, get r 958 /* Unload the driver. Unregister stuff, get ready to go away. */
959 static void __exit sbd_exit(void) 959 static void __exit sbd_exit(void)
960 { 960 {
961 int i; 961 int i;
962 962
963 for (i = DUART_MAX_CHIP * DUART_MAX_SI 963 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
964 struct sbd_duart *duart = &sbd 964 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
965 struct sbd_port *sport = &duar 965 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
966 struct uart_port *uport = &spo 966 struct uart_port *uport = &sport->port;
967 967
968 if (sport->duart) 968 if (sport->duart)
969 uart_remove_one_port(& 969 uart_remove_one_port(&sbd_reg, uport);
970 } 970 }
971 971
972 uart_unregister_driver(&sbd_reg); 972 uart_unregister_driver(&sbd_reg);
973 } 973 }
974 974
975 module_init(sbd_init); 975 module_init(sbd_init);
976 module_exit(sbd_exit); 976 module_exit(sbd_exit);
977 977
|
This page was automatically generated by the
LXR engine.
|