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1 /* 1 /*
2 * Driver for NEC VR4100 series Real Time Clo 2 * Driver for NEC VR4100 series Real Time Clock unit.
3 * 3 *
4 * Copyright (C) 2003-2008 Yoichi Yuasa <yua !! 4 * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can red 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Publ 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either versi 8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version. 9 * (at your option) any later version.
10 * 10 *
11 * This program is distributed in the hope th 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULA 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more detail 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 3 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 #include <linux/err.h> 20 #include <linux/err.h>
21 #include <linux/fs.h> 21 #include <linux/fs.h>
22 #include <linux/init.h> 22 #include <linux/init.h>
23 #include <linux/ioport.h> 23 #include <linux/ioport.h>
24 #include <linux/interrupt.h> 24 #include <linux/interrupt.h>
25 #include <linux/module.h> 25 #include <linux/module.h>
26 #include <linux/platform_device.h> 26 #include <linux/platform_device.h>
27 #include <linux/rtc.h> 27 #include <linux/rtc.h>
28 #include <linux/spinlock.h> 28 #include <linux/spinlock.h>
29 #include <linux/types.h> 29 #include <linux/types.h>
30 #include <linux/log2.h> <<
31 30
32 #include <asm/div64.h> 31 #include <asm/div64.h>
33 #include <asm/io.h> 32 #include <asm/io.h>
34 #include <asm/uaccess.h> 33 #include <asm/uaccess.h>
35 34
36 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips. !! 35 MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
37 MODULE_DESCRIPTION("NEC VR4100 series RTC driv 36 MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
38 MODULE_LICENSE("GPL v2"); !! 37 MODULE_LICENSE("GPL");
39 38
40 /* RTC 1 registers */ 39 /* RTC 1 registers */
41 #define ETIMELREG 0x00 40 #define ETIMELREG 0x00
42 #define ETIMEMREG 0x02 41 #define ETIMEMREG 0x02
43 #define ETIMEHREG 0x04 42 #define ETIMEHREG 0x04
44 /* RFU */ 43 /* RFU */
45 #define ECMPLREG 0x08 44 #define ECMPLREG 0x08
46 #define ECMPMREG 0x0a 45 #define ECMPMREG 0x0a
47 #define ECMPHREG 0x0c 46 #define ECMPHREG 0x0c
48 /* RFU */ 47 /* RFU */
49 #define RTCL1LREG 0x10 48 #define RTCL1LREG 0x10
50 #define RTCL1HREG 0x12 49 #define RTCL1HREG 0x12
51 #define RTCL1CNTLREG 0x14 50 #define RTCL1CNTLREG 0x14
52 #define RTCL1CNTHREG 0x16 51 #define RTCL1CNTHREG 0x16
53 #define RTCL2LREG 0x18 52 #define RTCL2LREG 0x18
54 #define RTCL2HREG 0x1a 53 #define RTCL2HREG 0x1a
55 #define RTCL2CNTLREG 0x1c 54 #define RTCL2CNTLREG 0x1c
56 #define RTCL2CNTHREG 0x1e 55 #define RTCL2CNTHREG 0x1e
57 56
58 /* RTC 2 registers */ 57 /* RTC 2 registers */
59 #define TCLKLREG 0x00 58 #define TCLKLREG 0x00
60 #define TCLKHREG 0x02 59 #define TCLKHREG 0x02
61 #define TCLKCNTLREG 0x04 60 #define TCLKCNTLREG 0x04
62 #define TCLKCNTHREG 0x06 61 #define TCLKCNTHREG 0x06
63 /* RFU */ 62 /* RFU */
64 #define RTCINTREG 0x1e 63 #define RTCINTREG 0x1e
65 #define TCLOCK_INT 0x08 64 #define TCLOCK_INT 0x08
66 #define RTCLONG2_INT 0x04 65 #define RTCLONG2_INT 0x04
67 #define RTCLONG1_INT 0x02 66 #define RTCLONG1_INT 0x02
68 #define ELAPSEDTIME_INT 0x01 67 #define ELAPSEDTIME_INT 0x01
69 68
70 #define RTC_FREQUENCY 32768 69 #define RTC_FREQUENCY 32768
71 #define MAX_PERIODIC_RATE 6553 70 #define MAX_PERIODIC_RATE 6553
72 71
73 static void __iomem *rtc1_base; 72 static void __iomem *rtc1_base;
74 static void __iomem *rtc2_base; 73 static void __iomem *rtc2_base;
75 74
76 #define rtc1_read(offset) readw( 75 #define rtc1_read(offset) readw(rtc1_base + (offset))
77 #define rtc1_write(offset, value) writew 76 #define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
78 77
79 #define rtc2_read(offset) readw( 78 #define rtc2_read(offset) readw(rtc2_base + (offset))
80 #define rtc2_write(offset, value) writew 79 #define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
81 80
82 static unsigned long epoch = 1970; /* Jan 81 static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
83 82
84 static DEFINE_SPINLOCK(rtc_lock); 83 static DEFINE_SPINLOCK(rtc_lock);
85 static char rtc_name[] = "RTC"; 84 static char rtc_name[] = "RTC";
>> 85 static unsigned long periodic_frequency;
86 static unsigned long periodic_count; 86 static unsigned long periodic_count;
87 static unsigned int alarm_enabled; 87 static unsigned int alarm_enabled;
88 static int aie_irq; !! 88 static int aie_irq = -1;
89 static int pie_irq; !! 89 static int pie_irq = -1;
90 90
91 static inline unsigned long read_elapsed_secon 91 static inline unsigned long read_elapsed_second(void)
92 { 92 {
93 93
94 unsigned long first_low, first_mid, fi 94 unsigned long first_low, first_mid, first_high;
95 95
96 unsigned long second_low, second_mid, 96 unsigned long second_low, second_mid, second_high;
97 97
98 do { 98 do {
99 first_low = rtc1_read(ETIMELRE 99 first_low = rtc1_read(ETIMELREG);
100 first_mid = rtc1_read(ETIMEMRE 100 first_mid = rtc1_read(ETIMEMREG);
101 first_high = rtc1_read(ETIMEHR 101 first_high = rtc1_read(ETIMEHREG);
102 second_low = rtc1_read(ETIMELR 102 second_low = rtc1_read(ETIMELREG);
103 second_mid = rtc1_read(ETIMEMR 103 second_mid = rtc1_read(ETIMEMREG);
104 second_high = rtc1_read(ETIMEH 104 second_high = rtc1_read(ETIMEHREG);
105 } while (first_low != second_low || fi 105 } while (first_low != second_low || first_mid != second_mid ||
106 first_high != second_high); 106 first_high != second_high);
107 107
108 return (first_high << 17) | (first_mid 108 return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
109 } 109 }
110 110
111 static inline void write_elapsed_second(unsign 111 static inline void write_elapsed_second(unsigned long sec)
112 { 112 {
113 spin_lock_irq(&rtc_lock); 113 spin_lock_irq(&rtc_lock);
114 114
115 rtc1_write(ETIMELREG, (uint16_t)(sec < 115 rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
116 rtc1_write(ETIMEMREG, (uint16_t)(sec > 116 rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
117 rtc1_write(ETIMEHREG, (uint16_t)(sec > 117 rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
118 118
119 spin_unlock_irq(&rtc_lock); 119 spin_unlock_irq(&rtc_lock);
120 } 120 }
121 121
122 static void vr41xx_rtc_release(struct device * 122 static void vr41xx_rtc_release(struct device *dev)
123 { 123 {
124 124
125 spin_lock_irq(&rtc_lock); 125 spin_lock_irq(&rtc_lock);
126 126
127 rtc1_write(ECMPLREG, 0); 127 rtc1_write(ECMPLREG, 0);
128 rtc1_write(ECMPMREG, 0); 128 rtc1_write(ECMPMREG, 0);
129 rtc1_write(ECMPHREG, 0); 129 rtc1_write(ECMPHREG, 0);
130 rtc1_write(RTCL1LREG, 0); 130 rtc1_write(RTCL1LREG, 0);
131 rtc1_write(RTCL1HREG, 0); 131 rtc1_write(RTCL1HREG, 0);
132 132
133 spin_unlock_irq(&rtc_lock); 133 spin_unlock_irq(&rtc_lock);
134 134
135 disable_irq(aie_irq); 135 disable_irq(aie_irq);
136 disable_irq(pie_irq); 136 disable_irq(pie_irq);
137 } 137 }
138 138
139 static int vr41xx_rtc_read_time(struct device 139 static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
140 { 140 {
141 unsigned long epoch_sec, elapsed_sec; 141 unsigned long epoch_sec, elapsed_sec;
142 142
143 epoch_sec = mktime(epoch, 1, 1, 0, 0, 143 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
144 elapsed_sec = read_elapsed_second(); 144 elapsed_sec = read_elapsed_second();
145 145
146 rtc_time_to_tm(epoch_sec + elapsed_sec 146 rtc_time_to_tm(epoch_sec + elapsed_sec, time);
147 147
148 return 0; 148 return 0;
149 } 149 }
150 150
151 static int vr41xx_rtc_set_time(struct device * 151 static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
152 { 152 {
153 unsigned long epoch_sec, current_sec; 153 unsigned long epoch_sec, current_sec;
154 154
155 epoch_sec = mktime(epoch, 1, 1, 0, 0, 155 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
156 current_sec = mktime(time->tm_year + 1 156 current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
157 time->tm_hour, ti 157 time->tm_hour, time->tm_min, time->tm_sec);
158 158
159 write_elapsed_second(current_sec - epo 159 write_elapsed_second(current_sec - epoch_sec);
160 160
161 return 0; 161 return 0;
162 } 162 }
163 163
164 static int vr41xx_rtc_read_alarm(struct device 164 static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
165 { 165 {
166 unsigned long low, mid, high; 166 unsigned long low, mid, high;
167 struct rtc_time *time = &wkalrm->time; 167 struct rtc_time *time = &wkalrm->time;
168 168
169 spin_lock_irq(&rtc_lock); 169 spin_lock_irq(&rtc_lock);
170 170
171 low = rtc1_read(ECMPLREG); 171 low = rtc1_read(ECMPLREG);
172 mid = rtc1_read(ECMPMREG); 172 mid = rtc1_read(ECMPMREG);
173 high = rtc1_read(ECMPHREG); 173 high = rtc1_read(ECMPHREG);
174 wkalrm->enabled = alarm_enabled; 174 wkalrm->enabled = alarm_enabled;
175 175
176 spin_unlock_irq(&rtc_lock); 176 spin_unlock_irq(&rtc_lock);
177 177
178 rtc_time_to_tm((high << 17) | (mid << 178 rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
179 179
180 return 0; 180 return 0;
181 } 181 }
182 182
183 static int vr41xx_rtc_set_alarm(struct device 183 static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
184 { 184 {
185 unsigned long alarm_sec; 185 unsigned long alarm_sec;
186 struct rtc_time *time = &wkalrm->time; 186 struct rtc_time *time = &wkalrm->time;
187 187
188 alarm_sec = mktime(time->tm_year + 190 188 alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
189 time->tm_hour, time 189 time->tm_hour, time->tm_min, time->tm_sec);
190 190
191 spin_lock_irq(&rtc_lock); 191 spin_lock_irq(&rtc_lock);
192 192
193 if (alarm_enabled) 193 if (alarm_enabled)
194 disable_irq(aie_irq); 194 disable_irq(aie_irq);
195 195
196 rtc1_write(ECMPLREG, (uint16_t)(alarm_ 196 rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
197 rtc1_write(ECMPMREG, (uint16_t)(alarm_ 197 rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
198 rtc1_write(ECMPHREG, (uint16_t)(alarm_ 198 rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
199 199
200 if (wkalrm->enabled) 200 if (wkalrm->enabled)
201 enable_irq(aie_irq); 201 enable_irq(aie_irq);
202 202
203 alarm_enabled = wkalrm->enabled; 203 alarm_enabled = wkalrm->enabled;
204 204
205 spin_unlock_irq(&rtc_lock); 205 spin_unlock_irq(&rtc_lock);
206 206
207 return 0; 207 return 0;
208 } 208 }
209 209
210 static int vr41xx_rtc_irq_set_freq(struct devi !! 210 static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
211 { 211 {
212 unsigned long count; 212 unsigned long count;
213 213
214 if (!is_power_of_2(freq)) <<
215 return -EINVAL; <<
216 count = RTC_FREQUENCY; <<
217 do_div(count, freq); <<
218 <<
219 periodic_count = count; <<
220 <<
221 spin_lock_irq(&rtc_lock); <<
222 <<
223 rtc1_write(RTCL1LREG, count); <<
224 rtc1_write(RTCL1HREG, count >> 16); <<
225 <<
226 spin_unlock_irq(&rtc_lock); <<
227 <<
228 return 0; <<
229 } <<
230 <<
231 static int vr41xx_rtc_irq_set_state(struct dev <<
232 { <<
233 if (enabled) <<
234 enable_irq(pie_irq); <<
235 else <<
236 disable_irq(pie_irq); <<
237 <<
238 return 0; <<
239 } <<
240 <<
241 static int vr41xx_rtc_ioctl(struct device *dev <<
242 { <<
243 switch (cmd) { 214 switch (cmd) {
244 case RTC_AIE_ON: 215 case RTC_AIE_ON:
245 spin_lock_irq(&rtc_lock); 216 spin_lock_irq(&rtc_lock);
246 217
247 if (!alarm_enabled) { 218 if (!alarm_enabled) {
248 enable_irq(aie_irq); 219 enable_irq(aie_irq);
249 alarm_enabled = 1; 220 alarm_enabled = 1;
250 } 221 }
251 222
252 spin_unlock_irq(&rtc_lock); 223 spin_unlock_irq(&rtc_lock);
253 break; 224 break;
254 case RTC_AIE_OFF: 225 case RTC_AIE_OFF:
255 spin_lock_irq(&rtc_lock); 226 spin_lock_irq(&rtc_lock);
256 227
257 if (alarm_enabled) { 228 if (alarm_enabled) {
258 disable_irq(aie_irq); 229 disable_irq(aie_irq);
259 alarm_enabled = 0; 230 alarm_enabled = 0;
260 } 231 }
261 232
262 spin_unlock_irq(&rtc_lock); 233 spin_unlock_irq(&rtc_lock);
263 break; 234 break;
>> 235 case RTC_PIE_ON:
>> 236 enable_irq(pie_irq);
>> 237 break;
>> 238 case RTC_PIE_OFF:
>> 239 disable_irq(pie_irq);
>> 240 break;
>> 241 case RTC_IRQP_READ:
>> 242 return put_user(periodic_frequency, (unsigned long __user *)arg);
>> 243 break;
>> 244 case RTC_IRQP_SET:
>> 245 if (arg > MAX_PERIODIC_RATE)
>> 246 return -EINVAL;
>> 247
>> 248 periodic_frequency = arg;
>> 249
>> 250 count = RTC_FREQUENCY;
>> 251 do_div(count, arg);
>> 252
>> 253 periodic_count = count;
>> 254
>> 255 spin_lock_irq(&rtc_lock);
>> 256
>> 257 rtc1_write(RTCL1LREG, count);
>> 258 rtc1_write(RTCL1HREG, count >> 16);
>> 259
>> 260 spin_unlock_irq(&rtc_lock);
>> 261 break;
264 case RTC_EPOCH_READ: 262 case RTC_EPOCH_READ:
265 return put_user(epoch, (unsign 263 return put_user(epoch, (unsigned long __user *)arg);
266 case RTC_EPOCH_SET: 264 case RTC_EPOCH_SET:
267 /* Doesn't support before 1900 265 /* Doesn't support before 1900 */
268 if (arg < 1900) 266 if (arg < 1900)
269 return -EINVAL; 267 return -EINVAL;
270 epoch = arg; 268 epoch = arg;
271 break; 269 break;
272 default: 270 default:
273 return -ENOIOCTLCMD; 271 return -ENOIOCTLCMD;
274 } 272 }
275 273
276 return 0; 274 return 0;
277 } 275 }
278 276
279 static irqreturn_t elapsedtime_interrupt(int i 277 static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
280 { 278 {
281 struct platform_device *pdev = (struct 279 struct platform_device *pdev = (struct platform_device *)dev_id;
282 struct rtc_device *rtc = platform_get_ 280 struct rtc_device *rtc = platform_get_drvdata(pdev);
283 281
284 rtc2_write(RTCINTREG, ELAPSEDTIME_INT) 282 rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
285 283
286 rtc_update_irq(rtc, 1, RTC_AF); 284 rtc_update_irq(rtc, 1, RTC_AF);
287 285
288 return IRQ_HANDLED; 286 return IRQ_HANDLED;
289 } 287 }
290 288
291 static irqreturn_t rtclong1_interrupt(int irq, 289 static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
292 { 290 {
293 struct platform_device *pdev = (struct 291 struct platform_device *pdev = (struct platform_device *)dev_id;
294 struct rtc_device *rtc = platform_get_ 292 struct rtc_device *rtc = platform_get_drvdata(pdev);
295 unsigned long count = periodic_count; 293 unsigned long count = periodic_count;
296 294
297 rtc2_write(RTCINTREG, RTCLONG1_INT); 295 rtc2_write(RTCINTREG, RTCLONG1_INT);
298 296
299 rtc1_write(RTCL1LREG, count); 297 rtc1_write(RTCL1LREG, count);
300 rtc1_write(RTCL1HREG, count >> 16); 298 rtc1_write(RTCL1HREG, count >> 16);
301 299
302 rtc_update_irq(rtc, 1, RTC_PF); 300 rtc_update_irq(rtc, 1, RTC_PF);
303 301
304 return IRQ_HANDLED; 302 return IRQ_HANDLED;
305 } 303 }
306 304
307 static const struct rtc_class_ops vr41xx_rtc_o 305 static const struct rtc_class_ops vr41xx_rtc_ops = {
308 .release = vr41xx_rtc_release, 306 .release = vr41xx_rtc_release,
309 .ioctl = vr41xx_rtc_ioctl, 307 .ioctl = vr41xx_rtc_ioctl,
310 .read_time = vr41xx_rtc_read_time 308 .read_time = vr41xx_rtc_read_time,
311 .set_time = vr41xx_rtc_set_time, 309 .set_time = vr41xx_rtc_set_time,
312 .read_alarm = vr41xx_rtc_read_alar 310 .read_alarm = vr41xx_rtc_read_alarm,
313 .set_alarm = vr41xx_rtc_set_alarm 311 .set_alarm = vr41xx_rtc_set_alarm,
314 .irq_set_freq = vr41xx_rtc_irq_set_f <<
315 .irq_set_state = vr41xx_rtc_irq_set_s <<
316 }; 312 };
317 313
318 static int __devinit rtc_probe(struct platform 314 static int __devinit rtc_probe(struct platform_device *pdev)
319 { 315 {
320 struct resource *res; 316 struct resource *res;
321 struct rtc_device *rtc; 317 struct rtc_device *rtc;
322 int retval; 318 int retval;
323 319
324 if (pdev->num_resources != 4) 320 if (pdev->num_resources != 4)
325 return -EBUSY; 321 return -EBUSY;
326 322
327 res = platform_get_resource(pdev, IORE 323 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
328 if (!res) 324 if (!res)
329 return -EBUSY; 325 return -EBUSY;
330 326
331 rtc1_base = ioremap(res->start, res->e 327 rtc1_base = ioremap(res->start, res->end - res->start + 1);
332 if (!rtc1_base) 328 if (!rtc1_base)
333 return -EBUSY; 329 return -EBUSY;
334 330
335 res = platform_get_resource(pdev, IORE 331 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
336 if (!res) { 332 if (!res) {
337 retval = -EBUSY; 333 retval = -EBUSY;
338 goto err_rtc1_iounmap; 334 goto err_rtc1_iounmap;
339 } 335 }
340 336
341 rtc2_base = ioremap(res->start, res->e 337 rtc2_base = ioremap(res->start, res->end - res->start + 1);
342 if (!rtc2_base) { 338 if (!rtc2_base) {
343 retval = -EBUSY; 339 retval = -EBUSY;
344 goto err_rtc1_iounmap; 340 goto err_rtc1_iounmap;
345 } 341 }
346 342
347 rtc = rtc_device_register(rtc_name, &p 343 rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
348 if (IS_ERR(rtc)) { 344 if (IS_ERR(rtc)) {
349 retval = PTR_ERR(rtc); 345 retval = PTR_ERR(rtc);
350 goto err_iounmap_all; 346 goto err_iounmap_all;
351 } 347 }
352 348
353 rtc->max_user_freq = MAX_PERIODIC_RATE <<
354 <<
355 spin_lock_irq(&rtc_lock); 349 spin_lock_irq(&rtc_lock);
356 350
357 rtc1_write(ECMPLREG, 0); 351 rtc1_write(ECMPLREG, 0);
358 rtc1_write(ECMPMREG, 0); 352 rtc1_write(ECMPMREG, 0);
359 rtc1_write(ECMPHREG, 0); 353 rtc1_write(ECMPHREG, 0);
360 rtc1_write(RTCL1LREG, 0); 354 rtc1_write(RTCL1LREG, 0);
361 rtc1_write(RTCL1HREG, 0); 355 rtc1_write(RTCL1HREG, 0);
362 356
363 spin_unlock_irq(&rtc_lock); 357 spin_unlock_irq(&rtc_lock);
364 358
365 aie_irq = platform_get_irq(pdev, 0); 359 aie_irq = platform_get_irq(pdev, 0);
366 if (aie_irq <= 0) { !! 360 if (aie_irq < 0 || aie_irq >= NR_IRQS) {
367 retval = -EBUSY; 361 retval = -EBUSY;
368 goto err_device_unregister; 362 goto err_device_unregister;
369 } 363 }
370 364
371 retval = request_irq(aie_irq, elapsedt 365 retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
372 "elapsed_time", p 366 "elapsed_time", pdev);
373 if (retval < 0) 367 if (retval < 0)
374 goto err_device_unregister; 368 goto err_device_unregister;
375 369
376 pie_irq = platform_get_irq(pdev, 1); 370 pie_irq = platform_get_irq(pdev, 1);
377 if (pie_irq <= 0) !! 371 if (pie_irq < 0 || pie_irq >= NR_IRQS)
378 goto err_free_irq; 372 goto err_free_irq;
379 373
380 retval = request_irq(pie_irq, rtclong1 374 retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
381 "rtclong1", pdev) 375 "rtclong1", pdev);
382 if (retval < 0) 376 if (retval < 0)
383 goto err_free_irq; 377 goto err_free_irq;
384 378
385 platform_set_drvdata(pdev, rtc); 379 platform_set_drvdata(pdev, rtc);
386 380
387 disable_irq(aie_irq); 381 disable_irq(aie_irq);
388 disable_irq(pie_irq); 382 disable_irq(pie_irq);
389 383
390 printk(KERN_INFO "rtc: Real Time Clock 384 printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
391 385
392 return 0; 386 return 0;
393 387
394 err_free_irq: 388 err_free_irq:
395 free_irq(aie_irq, pdev); 389 free_irq(aie_irq, pdev);
396 390
397 err_device_unregister: 391 err_device_unregister:
398 rtc_device_unregister(rtc); 392 rtc_device_unregister(rtc);
399 393
400 err_iounmap_all: 394 err_iounmap_all:
401 iounmap(rtc2_base); 395 iounmap(rtc2_base);
402 rtc2_base = NULL; 396 rtc2_base = NULL;
403 397
404 err_rtc1_iounmap: 398 err_rtc1_iounmap:
405 iounmap(rtc1_base); 399 iounmap(rtc1_base);
406 rtc1_base = NULL; 400 rtc1_base = NULL;
407 401
408 return retval; 402 return retval;
409 } 403 }
410 404
411 static int __devexit rtc_remove(struct platfor 405 static int __devexit rtc_remove(struct platform_device *pdev)
412 { 406 {
413 struct rtc_device *rtc; 407 struct rtc_device *rtc;
414 408
415 rtc = platform_get_drvdata(pdev); 409 rtc = platform_get_drvdata(pdev);
416 if (rtc) 410 if (rtc)
417 rtc_device_unregister(rtc); 411 rtc_device_unregister(rtc);
418 412
419 platform_set_drvdata(pdev, NULL); 413 platform_set_drvdata(pdev, NULL);
420 414
421 free_irq(aie_irq, pdev); 415 free_irq(aie_irq, pdev);
422 free_irq(pie_irq, pdev); 416 free_irq(pie_irq, pdev);
423 if (rtc1_base) 417 if (rtc1_base)
424 iounmap(rtc1_base); 418 iounmap(rtc1_base);
425 if (rtc2_base) 419 if (rtc2_base)
426 iounmap(rtc2_base); 420 iounmap(rtc2_base);
427 421
428 return 0; 422 return 0;
429 } 423 }
430 424
431 /* work with hotplug and coldplug */ 425 /* work with hotplug and coldplug */
432 MODULE_ALIAS("platform:RTC"); 426 MODULE_ALIAS("platform:RTC");
433 427
434 static struct platform_driver rtc_platform_dri 428 static struct platform_driver rtc_platform_driver = {
435 .probe = rtc_probe, 429 .probe = rtc_probe,
436 .remove = __devexit_p(rtc_remo 430 .remove = __devexit_p(rtc_remove),
437 .driver = { 431 .driver = {
438 .name = rtc_name, 432 .name = rtc_name,
439 .owner = THIS_MODULE, 433 .owner = THIS_MODULE,
440 }, 434 },
441 }; 435 };
442 436
443 static int __init vr41xx_rtc_init(void) 437 static int __init vr41xx_rtc_init(void)
444 { 438 {
445 return platform_driver_register(&rtc_p 439 return platform_driver_register(&rtc_platform_driver);
446 } 440 }
447 441
448 static void __exit vr41xx_rtc_exit(void) 442 static void __exit vr41xx_rtc_exit(void)
449 { 443 {
450 platform_driver_unregister(&rtc_platfo 444 platform_driver_unregister(&rtc_platform_driver);
451 } 445 }
452 446
453 module_init(vr41xx_rtc_init); 447 module_init(vr41xx_rtc_init);
454 module_exit(vr41xx_rtc_exit); 448 module_exit(vr41xx_rtc_exit);
455 449
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