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1 /********************************************* 1
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation.
4 *
5 * Portions of this file are derived from the
6 * as portions of the ieee80211 subsystem head
7 *
8 * This program is free software; you can redi
9 * under the terms of version 2 of the GNU Gen
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope tha
13 * ANY WARRANTY; without even the implied warr
14 * FITNESS FOR A PARTICULAR PURPOSE. See the
15 * more details.
16 *
17 * You should have received a copy of the GNU
18 * this program; if not, write to the Free Sof
19 * 51 Franklin Street, Fifth Floor, Boston, MA
20 *
21 * The full GNU General Public License is incl
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Par
27 *
28 *********************************************
29
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include <asm/unaligned.h>
33 #include "iwl-eeprom.h"
34 #include "iwl-dev.h"
35 #include "iwl-core.h"
36 #include "iwl-sta.h"
37 #include "iwl-io.h"
38 #include "iwl-calib.h"
39 #include "iwl-helpers.h"
40 /************************** RX-FUNCTIONS *****
41 /*
42 * Rx theory of operation
43 *
44 * Driver allocates a circular buffer of Recei
45 * each of which point to Receive Buffers to b
46 * used not only for Rx frames, but for any co
47 * from the NIC. The driver and NIC manage th
48 * of indexes into the circular buffer.
49 *
50 * Rx Queue Indexes
51 * The host/firmware share two index registers
52 *
53 * The READ index maps to the first position t
54 * to -- the driver can read up to (but not in
55 * good data.
56 * The READ index is managed by the firmware o
57 *
58 * The WRITE index maps to the last position t
59 * position preceding WRITE is the last slot t
60 *
61 * The queue is empty (no good data) if WRITE
62 * WRITE = READ.
63 *
64 * During initialization, the host sets up the
65 * INDEX position, and WRITE to the last (READ
66 *
67 * When the firmware places a packet in a buff
68 * and fire the RX interrupt. The driver can
69 * process as many packets as possible, moving
70 * resets the Rx queue buffers with new memory
71 *
72 * The management in the driver is as follows:
73 * + A list of pre-allocated SKBs is stored in
74 * iwl->rxq->free_count drops to or below RX
75 * to replenish the iwl->rxq->rx_free.
76 * + In iwl_rx_replenish (scheduled) if 'proce
77 * iwl->rxq is replenished and the READ INDE
78 * 'processed' and 'read' driver indexes as
79 * + A received packet is processed and handed
80 * detached from the iwl->rxq. The driver '
81 * + The Host/Firmware iwl->rxq is replenished
82 * list. If there are no allocated buffers i
83 * INDEX is not incremented and iwl->status(
84 * were enough free buffers and RX_STALLED i
85 *
86 *
87 * Driver sequence:
88 *
89 * iwl_rx_queue_alloc() Allocates rx_free
90 * iwl_rx_replenish() Replenishes rx_free
91 * iwl_rx_queue_res
92 * iwl_rx_queue_restock() Moves available buff
93 * queue, updates f
94 * the WRITE index.
95 * are available, s
96 *
97 * -- enable interrupts --
98 * ISR - iwl_rx() Detach iwl_rx_mem_bu
99 * READ INDEX, deta
100 * Moves the packet
101 * Calls iwl_rx_que
102 * slots.
103 * ...
104 *
105 */
106
107 /**
108 * iwl_rx_queue_space - Return number of free
109 */
110 int iwl_rx_queue_space(const struct iwl_rx_que
111 {
112 int s = q->read - q->write;
113 if (s <= 0)
114 s += RX_QUEUE_SIZE;
115 /* keep some buffer to not confuse ful
116 s -= 2;
117 if (s < 0)
118 s = 0;
119 return s;
120 }
121 EXPORT_SYMBOL(iwl_rx_queue_space);
122
123 /**
124 * iwl_rx_queue_update_write_ptr - Update the
125 */
126 int iwl_rx_queue_update_write_ptr(struct iwl_p
127 {
128 unsigned long flags;
129 u32 rx_wrt_ptr_reg = priv->hw_params.r
130 u32 reg;
131 int ret = 0;
132
133 spin_lock_irqsave(&q->lock, flags);
134
135 if (q->need_update == 0)
136 goto exit_unlock;
137
138 /* If power-saving is in use, make sur
139 if (test_bit(STATUS_POWER_PMI, &priv->
140 reg = iwl_read32(priv, CSR_UCO
141
142 if (reg & CSR_UCODE_DRV_GP1_BI
143 iwl_set_bit(priv, CSR_
144 CSR_GP_CNT
145 goto exit_unlock;
146 }
147
148 q->write_actual = (q->write &
149 iwl_write_direct32(priv, rx_wr
150
151 /* Else device is assumed to be awake
152 } else {
153 /* Device expects a multiple o
154 q->write_actual = (q->write &
155 iwl_write_direct32(priv, rx_wr
156 }
157
158 q->need_update = 0;
159
160 exit_unlock:
161 spin_unlock_irqrestore(&q->lock, flags
162 return ret;
163 }
164 EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
165 /**
166 * iwl_dma_addr2rbd_ptr - convert a DMA addres
167 */
168 static inline __le32 iwl_dma_addr2rbd_ptr(stru
169 dma_
170 {
171 return cpu_to_le32((u32)(dma_addr >> 8
172 }
173
174 /**
175 * iwl_rx_queue_restock - refill RX queue from
176 *
177 * If there are slots in the RX queue that nee
178 * and we have free pre-allocated buffers, fil
179 * as we can, pulling from rx_free.
180 *
181 * This moves the 'write' index forward to cat
182 * also updates the memory address in the firm
183 * target buffer.
184 */
185 int iwl_rx_queue_restock(struct iwl_priv *priv
186 {
187 struct iwl_rx_queue *rxq = &priv->rxq;
188 struct list_head *element;
189 struct iwl_rx_mem_buffer *rxb;
190 unsigned long flags;
191 int write;
192 int ret = 0;
193
194 spin_lock_irqsave(&rxq->lock, flags);
195 write = rxq->write & ~0x7;
196 while ((iwl_rx_queue_space(rxq) > 0) &
197 /* Get next free Rx buffer, re
198 element = rxq->rx_free.next;
199 rxb = list_entry(element, stru
200 list_del(element);
201
202 /* Point to Rx buffer via next
203 rxq->bd[rxq->write] = iwl_dma_
204 rxq->queue[rxq->write] = rxb;
205 rxq->write = (rxq->write + 1)
206 rxq->free_count--;
207 }
208 spin_unlock_irqrestore(&rxq->lock, fla
209 /* If the pre-allocated buffer pool is
210 * refill it */
211 if (rxq->free_count <= RX_LOW_WATERMAR
212 queue_work(priv->workqueue, &p
213
214
215 /* If we've added more space for the f
216 * Increment device's write pointer in
217 if (rxq->write_actual != (rxq->write &
218 spin_lock_irqsave(&rxq->lock,
219 rxq->need_update = 1;
220 spin_unlock_irqrestore(&rxq->l
221 ret = iwl_rx_queue_update_writ
222 }
223
224 return ret;
225 }
226 EXPORT_SYMBOL(iwl_rx_queue_restock);
227
228
229 /**
230 * iwl_rx_replenish - Move all used packet fro
231 *
232 * When moving to rx_free an SKB is allocated
233 *
234 * Also restock the Rx queue via iwl_rx_queue_
235 * This is called as a scheduled work item (ex
236 */
237 void iwl_rx_allocate(struct iwl_priv *priv, gf
238 {
239 struct iwl_rx_queue *rxq = &priv->rxq;
240 struct list_head *element;
241 struct iwl_rx_mem_buffer *rxb;
242 struct sk_buff *skb;
243 unsigned long flags;
244
245 while (1) {
246 spin_lock_irqsave(&rxq->lock,
247 if (list_empty(&rxq->rx_used))
248 spin_unlock_irqrestore
249 return;
250 }
251 spin_unlock_irqrestore(&rxq->l
252
253 if (rxq->free_count > RX_LOW_W
254 priority |= __GFP_NOWA
255 /* Alloc a new receive buffer
256 skb = alloc_skb(priv->hw_param
257
258
259 if (!skb) {
260 if (net_ratelimit())
261 IWL_DEBUG_INFO
262 if ((rxq->free_count <
263 net_ratelimit())
264 IWL_CRIT(priv,
265 prior
266 rxq->
267 /* We don't reschedule
268 * call the restock me
269 * more buffers it wil
270 break;
271 }
272
273 spin_lock_irqsave(&rxq->lock,
274
275 if (list_empty(&rxq->rx_used))
276 spin_unlock_irqrestore
277 dev_kfree_skb_any(skb)
278 return;
279 }
280 element = rxq->rx_used.next;
281 rxb = list_entry(element, stru
282 list_del(element);
283
284 spin_unlock_irqrestore(&rxq->l
285
286 rxb->skb = skb;
287 /* Get physical address of RB/
288 rxb->real_dma_addr = pci_map_s
289 priv->
290 rxb->s
291 priv->
292 PCI_DM
293 /* dma address must be no more
294 BUG_ON(rxb->real_dma_addr & ~D
295 /* and also 256 byte aligned!
296 rxb->aligned_dma_addr = ALIGN(
297 skb_reserve(rxb->skb, rxb->ali
298
299 spin_lock_irqsave(&rxq->lock,
300
301 list_add_tail(&rxb->list, &rxq
302 rxq->free_count++;
303 priv->alloc_rxb_skb++;
304
305 spin_unlock_irqrestore(&rxq->l
306 }
307 }
308
309 void iwl_rx_replenish(struct iwl_priv *priv)
310 {
311 unsigned long flags;
312
313 iwl_rx_allocate(priv, GFP_KERNEL);
314
315 spin_lock_irqsave(&priv->lock, flags);
316 iwl_rx_queue_restock(priv);
317 spin_unlock_irqrestore(&priv->lock, fl
318 }
319 EXPORT_SYMBOL(iwl_rx_replenish);
320
321 void iwl_rx_replenish_now(struct iwl_priv *pri
322 {
323 iwl_rx_allocate(priv, GFP_ATOMIC);
324
325 iwl_rx_queue_restock(priv);
326 }
327 EXPORT_SYMBOL(iwl_rx_replenish_now);
328
329
330 /* Assumes that the skb field of the buffers i
331 * If an SKB has been detached, the POOL needs
332 * This free routine walks the list of POOL en
333 * non NULL it is unmapped and freed
334 */
335 void iwl_rx_queue_free(struct iwl_priv *priv,
336 {
337 int i;
338 for (i = 0; i < RX_QUEUE_SIZE + RX_FRE
339 if (rxq->pool[i].skb != NULL)
340 pci_unmap_single(priv-
341 rxq->
342 priv-
343 PCI_D
344 dev_kfree_skb(rxq->poo
345 }
346 }
347
348 pci_free_consistent(priv->pci_dev, 4 *
349 rxq->dma_addr);
350 pci_free_consistent(priv->pci_dev, siz
351 rxq->rb_stts, rxq-
352 rxq->bd = NULL;
353 rxq->rb_stts = NULL;
354 }
355 EXPORT_SYMBOL(iwl_rx_queue_free);
356
357 int iwl_rx_queue_alloc(struct iwl_priv *priv)
358 {
359 struct iwl_rx_queue *rxq = &priv->rxq;
360 struct pci_dev *dev = priv->pci_dev;
361 int i;
362
363 spin_lock_init(&rxq->lock);
364 INIT_LIST_HEAD(&rxq->rx_free);
365 INIT_LIST_HEAD(&rxq->rx_used);
366
367 /* Alloc the circular buffer of Read B
368 rxq->bd = pci_alloc_consistent(dev, 4
369 if (!rxq->bd)
370 goto err_bd;
371
372 rxq->rb_stts = pci_alloc_consistent(de
373 &rxq->
374 if (!rxq->rb_stts)
375 goto err_rb;
376
377 /* Fill the rx_used queue with _all_ o
378 for (i = 0; i < RX_FREE_BUFFERS + RX_Q
379 list_add_tail(&rxq->pool[i].li
380
381 /* Set us so that we have processed an
382 * not restocked the Rx queue with fre
383 rxq->read = rxq->write = 0;
384 rxq->write_actual = 0;
385 rxq->free_count = 0;
386 rxq->need_update = 0;
387 return 0;
388
389 err_rb:
390 pci_free_consistent(priv->pci_dev, 4 *
391 rxq->dma_addr);
392 err_bd:
393 return -ENOMEM;
394 }
395 EXPORT_SYMBOL(iwl_rx_queue_alloc);
396
397 void iwl_rx_queue_reset(struct iwl_priv *priv,
398 {
399 unsigned long flags;
400 int i;
401 spin_lock_irqsave(&rxq->lock, flags);
402 INIT_LIST_HEAD(&rxq->rx_free);
403 INIT_LIST_HEAD(&rxq->rx_used);
404 /* Fill the rx_used queue with _all_ o
405 for (i = 0; i < RX_FREE_BUFFERS + RX_Q
406 /* In the reset function, thes
407 * to an SKB, so we need to un
408 if (rxq->pool[i].skb != NULL)
409 pci_unmap_single(priv-
410 rxq->
411 priv-
412 PCI_D
413 priv->alloc_rxb_skb--;
414 dev_kfree_skb(rxq->poo
415 rxq->pool[i].skb = NUL
416 }
417 list_add_tail(&rxq->pool[i].li
418 }
419
420 /* Set us so that we have processed an
421 * not restocked the Rx queue with fre
422 rxq->read = rxq->write = 0;
423 rxq->write_actual = 0;
424 rxq->free_count = 0;
425 spin_unlock_irqrestore(&rxq->lock, fla
426 }
427 EXPORT_SYMBOL(iwl_rx_queue_reset);
428
429 int iwl_rx_init(struct iwl_priv *priv, struct
430 {
431 u32 rb_size;
432 const u32 rfdnlog = RX_QUEUE_SIZE_LOG;
433 u32 rb_timeout = 0; /* FIXME: RX_RB_TI
434
435 if (!priv->cfg->use_isr_legacy)
436 rb_timeout = RX_RB_TIMEOUT;
437
438 if (priv->cfg->mod_params->amsdu_size_
439 rb_size = FH_RCSR_RX_CONFIG_RE
440 else
441 rb_size = FH_RCSR_RX_CONFIG_RE
442
443 /* Stop Rx DMA */
444 iwl_write_direct32(priv, FH_MEM_RCSR_C
445
446 /* Reset driver's Rx queue write index
447 iwl_write_direct32(priv, FH_RSCSR_CHNL
448
449 /* Tell device where to find RBD circu
450 iwl_write_direct32(priv, FH_RSCSR_CHNL
451 (u32)(rxq->dma_addr
452
453 /* Tell device where in DRAM to update
454 iwl_write_direct32(priv, FH_RSCSR_CHNL
455 rxq->rb_stts_dma >>
456
457 /* Enable Rx DMA
458 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY i
459 * the credit mechanism in 5000 H
460 * Direct rx interrupts to hosts
461 * Rx buffer size 4 or 8k
462 * RB timeout 0x10
463 * 256 RBDs
464 */
465 iwl_write_direct32(priv, FH_MEM_RCSR_C
466 FH_RCSR_RX_CONFIG_C
467 FH_RCSR_CHNL0_RX_IG
468 FH_RCSR_CHNL0_RX_CO
469 FH_RCSR_CHNL0_RX_CO
470 rb_size|
471 (rb_timeout << FH_R
472 (rfdnlog << FH_RCSR
473
474 iwl_write32(priv, CSR_INT_COALESCING,
475
476 return 0;
477 }
478
479 int iwl_rxq_stop(struct iwl_priv *priv)
480 {
481
482 /* stop Rx DMA */
483 iwl_write_direct32(priv, FH_MEM_RCSR_C
484 iwl_poll_direct_bit(priv, FH_MEM_RSSR_
485 FH_RSSR_CHNL0_RX_S
486
487 return 0;
488 }
489 EXPORT_SYMBOL(iwl_rxq_stop);
490
491 void iwl_rx_missed_beacon_notif(struct iwl_pri
492 struct iwl_rx_
493
494 {
495 struct iwl_rx_packet *pkt = (struct iw
496 struct iwl_missed_beacon_notif *missed
497
498 missed_beacon = &pkt->u.missed_beacon;
499 if (le32_to_cpu(missed_beacon->consequ
500 IWL_DEBUG_CALIB(priv, "missed
501 le32_to_cpu(missed_beacon-
502 le32_to_cpu(missed_beacon-
503 le32_to_cpu(missed_beacon-
504 le32_to_cpu(missed_beacon-
505 if (!test_bit(STATUS_SCANNING,
506 iwl_init_sensitivity(p
507 }
508 }
509 EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
510
511
512 /* Calculate noise level, based on measurement
513 * before arriving beacon. This measurement
514 * exactly when to expect beacons, therefore
515 static void iwl_rx_calc_noise(struct iwl_priv
516 {
517 struct statistics_rx_non_phy *rx_info
518 = &(priv->stat
519 int num_active_rx = 0;
520 int total_silence = 0;
521 int bcn_silence_a =
522 le32_to_cpu(rx_info->beacon_si
523 int bcn_silence_b =
524 le32_to_cpu(rx_info->beacon_si
525 int bcn_silence_c =
526 le32_to_cpu(rx_info->beacon_si
527
528 if (bcn_silence_a) {
529 total_silence += bcn_silence_a
530 num_active_rx++;
531 }
532 if (bcn_silence_b) {
533 total_silence += bcn_silence_b
534 num_active_rx++;
535 }
536 if (bcn_silence_c) {
537 total_silence += bcn_silence_c
538 num_active_rx++;
539 }
540
541 /* Average among active antennas */
542 if (num_active_rx)
543 priv->last_rx_noise = (total_s
544 else
545 priv->last_rx_noise = IWL_NOIS
546
547 IWL_DEBUG_CALIB(priv, "inband silence
548 bcn_silence_a, bcn_sil
549 priv->last_rx_noise);
550 }
551
552 #define REG_RECALIB_PERIOD (60)
553
554 void iwl_rx_statistics(struct iwl_priv *priv,
555 struct iwl_rx_me
556 {
557 int change;
558 struct iwl_rx_packet *pkt = (struct iw
559
560 IWL_DEBUG_RX(priv, "Statistics notific
561 (int)sizeof(priv->statist
562
563 change = ((priv->statistics.general.te
564 pkt->u.stats.general.temper
565 ((priv->statistics.flag &
566 STATISTICS_REPLY_FLG_FAT_M
567 (pkt->u.stats.flag & STATIS
568
569 memcpy(&priv->statistics, &pkt->u.stat
570
571 set_bit(STATUS_STATISTICS, &priv->stat
572
573 /* Reschedule the statistics timer to
574 * REG_RECALIB_PERIOD seconds to ensur
575 * thermal update even if the uCode do
576 * us one */
577 mod_timer(&priv->statistics_periodic,
578 msecs_to_jiffies(REG_RECALIB
579
580 if (unlikely(!test_bit(STATUS_SCANNING
581 (pkt->hdr.cmd == STATISTICS_NOTIFI
582 iwl_rx_calc_noise(priv);
583 queue_work(priv->workqueue, &p
584 }
585
586 iwl_leds_background(priv);
587
588 if (priv->cfg->ops->lib->temp_ops.temp
589 priv->cfg->ops->lib->temp_ops.
590 }
591 EXPORT_SYMBOL(iwl_rx_statistics);
592
593 #define PERFECT_RSSI (-20) /* dBm */
594 #define WORST_RSSI (-95) /* dBm */
595 #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
596
597 /* Calculate an indication of rx signal qualit
598 * See http://www.ces.clemson.edu/linux/signal
599 * about formulas used below. */
600 static int iwl_calc_sig_qual(int rssi_dbm, int
601 {
602 int sig_qual;
603 int degradation = PERFECT_RSSI - rssi_
604
605 /* If we get a noise measurement, use
606 * as indicator; formula is (signal db
607 * SNR at or above 40 is a great signa
608 * Below that, scale to fit SNR of 0 -
609 * Weakest usable signal is usually 10
610 if (noise_dbm) {
611 if (rssi_dbm - noise_dbm >= 40
612 return 100;
613 else if (rssi_dbm < noise_dbm)
614 return 0;
615 sig_qual = ((rssi_dbm - noise_
616
617 /* Else use just the signal level.
618 * This formula is a least squares fit
619 * compared with a reference system
620 * for signal quality. */
621 } else
622 sig_qual = (100 * (RSSI_RANGE
623 (15 * RSSI_RANGE +
624 (RSSI_RANGE * RSSI_
625
626 if (sig_qual > 100)
627 sig_qual = 100;
628 else if (sig_qual < 1)
629 sig_qual = 0;
630
631 return sig_qual;
632 }
633
634 /* Calc max signal level (dBm) among 3 possibl
635 static inline int iwl_calc_rssi(struct iwl_pri
636 struct iwl_rx_
637 {
638 return priv->cfg->ops->utils->calc_rss
639 }
640
641 #ifdef CONFIG_IWLWIFI_DEBUG
642 /**
643 * iwl_dbg_report_frame - dump frame to syslog
644 *
645 * You may hack this function to show differen
646 * including selective frame dumps.
647 * group100 parameter selects whether to show
648 * All beacon and probe response frames are
649 */
650 static void iwl_dbg_report_frame(struct iwl_pr
651 struct iwl_rx_phy_res *p
652 struct ieee80211_hdr *he
653 {
654 u32 to_us;
655 u32 print_summary = 0;
656 u32 print_dump = 0; /* set to 1 to
657 u32 hundred = 0;
658 u32 dataframe = 0;
659 __le16 fc;
660 u16 seq_ctl;
661 u16 channel;
662 u16 phy_flags;
663 u32 rate_n_flags;
664 u32 tsf_low;
665 int rssi;
666
667 if (likely(!(priv->debug_level & IWL_D
668 return;
669
670 /* MAC header */
671 fc = header->frame_control;
672 seq_ctl = le16_to_cpu(header->seq_ctrl
673
674 /* metadata */
675 channel = le16_to_cpu(phy_res->channel
676 phy_flags = le16_to_cpu(phy_res->phy_f
677 rate_n_flags = le32_to_cpu(phy_res->ra
678
679 /* signal statistics */
680 rssi = iwl_calc_rssi(priv, phy_res);
681 tsf_low = le64_to_cpu(phy_res->timesta
682
683 to_us = !compare_ether_addr(header->ad
684
685 /* if data frame is to us and all is g
686 * (optionally) print summary for on
687 if (to_us && (fc & ~cpu_to_le16(IEEE80
688 cpu_to_le16(IEEE80211_FCTL_FROMDS
689 dataframe = 1;
690 if (!group100)
691 print_summary = 1;
692 else if (priv->framecnt_to_us
693 priv->framecnt_to_us++
694 print_summary = 0;
695 } else {
696 priv->framecnt_to_us =
697 print_summary = 1;
698 hundred = 1;
699 }
700 } else {
701 /* print summary for all other
702 print_summary = 1;
703 }
704
705 if (print_summary) {
706 char *title;
707 int rate_idx;
708 u32 bitrate;
709
710 if (hundred)
711 title = "100Frames";
712 else if (ieee80211_has_retry(f
713 title = "Retry";
714 else if (ieee80211_is_assoc_re
715 title = "AscRsp";
716 else if (ieee80211_is_reassoc_
717 title = "RasRsp";
718 else if (ieee80211_is_probe_re
719 title = "PrbRsp";
720 print_dump = 1; /* dum
721 } else if (ieee80211_is_beacon
722 title = "Beacon";
723 print_dump = 1; /* dum
724 } else if (ieee80211_is_atim(f
725 title = "ATIM";
726 else if (ieee80211_is_auth(fc)
727 title = "Auth";
728 else if (ieee80211_is_deauth(f
729 title = "DeAuth";
730 else if (ieee80211_is_disassoc
731 title = "DisAssoc";
732 else
733 title = "Frame";
734
735 rate_idx = iwl_hwrate_to_plcp_
736 if (unlikely((rate_idx < 0) ||
737 bitrate = 0;
738 WARN_ON_ONCE(1);
739 } else {
740 bitrate = iwl_rates[ra
741 }
742
743 /* print frame summary.
744 * MAC addresses show just the
745 * but you can hack it to s
746 if (dataframe)
747 IWL_DEBUG_RX(priv, "%s
748 "len=%u,
749 title, le
750 length, r
751 else {
752 /* src/dst addresses a
753 IWL_DEBUG_RX(priv, "%s
754 "len=%u,
755 "phy=0x%0
756 title, le
757 header->a
758 tsf_low -
759 phy_flags
760 }
761 }
762 if (print_dump)
763 iwl_print_hex_dump(priv, IWL_D
764 }
765 #endif
766
767 static void iwl_update_rx_stats(struct iwl_pri
768 {
769 /* 0 - mgmt, 1 - cnt, 2 - data */
770 int idx = (fc & IEEE80211_FCTL_FTYPE)
771 priv->rx_stats[idx].cnt++;
772 priv->rx_stats[idx].bytes += len;
773 }
774
775 /*
776 * returns non-zero if packet should be droppe
777 */
778 int iwl_set_decrypted_flag(struct iwl_priv *pr
779 struct ieee80211_hd
780 u32 decrypt_res,
781 struct ieee80211_rx
782 {
783 u16 fc = le16_to_cpu(hdr->frame_contro
784
785 if (priv->active_rxon.filter_flags & R
786 return 0;
787
788 if (!(fc & IEEE80211_FCTL_PROTECTED))
789 return 0;
790
791 IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n
792 switch (decrypt_res & RX_RES_STATUS_SE
793 case RX_RES_STATUS_SEC_TYPE_TKIP:
794 /* The uCode has got a bad pha
795 * Decryption will be done in
796 if ((decrypt_res & RX_RES_STAT
797 RX_RES_STATUS_BAD_KEY_TTAK
798 break;
799
800 case RX_RES_STATUS_SEC_TYPE_WEP:
801 if ((decrypt_res & RX_RES_STAT
802 RX_RES_STATUS_BAD_ICV_MIC)
803 /* bad ICV, the packet
804 * decryption is inpla
805 IWL_DEBUG_RX(priv, "Pa
806 return -1;
807 }
808 case RX_RES_STATUS_SEC_TYPE_CCMP:
809 if ((decrypt_res & RX_RES_STAT
810 RX_RES_STATUS_DECRYPT_OK)
811 IWL_DEBUG_RX(priv, "hw
812 stats->flag |= RX_FLAG
813 }
814 break;
815
816 default:
817 break;
818 }
819 return 0;
820 }
821 EXPORT_SYMBOL(iwl_set_decrypted_flag);
822
823 static u32 iwl_translate_rx_status(struct iwl_
824 {
825 u32 decrypt_out = 0;
826
827 if ((decrypt_in & RX_RES_STATUS_STATIO
828 RX_RES
829 decrypt_out |= (RX_RES_STATUS_
830 RX_RES_STATUS_
831
832 decrypt_out |= (decrypt_in & RX_RES_ST
833
834 /* packet was not encrypted */
835 if ((decrypt_in & RX_RES_STATUS_SEC_TY
836 RX_RES
837 return decrypt_out;
838
839 /* packet was encrypted with unknown a
840 if ((decrypt_in & RX_RES_STATUS_SEC_TY
841 RX_RES
842 return decrypt_out;
843
844 /* decryption was not done in HW */
845 if ((decrypt_in & RX_MPDU_RES_STATUS_D
846 RX_MPD
847 return decrypt_out;
848
849 switch (decrypt_in & RX_RES_STATUS_SEC
850
851 case RX_RES_STATUS_SEC_TYPE_CCMP:
852 /* alg is CCM: check MIC only
853 if (!(decrypt_in & RX_MPDU_RES
854 /* Bad MIC */
855 decrypt_out |= RX_RES_
856 else
857 decrypt_out |= RX_RES_
858
859 break;
860
861 case RX_RES_STATUS_SEC_TYPE_TKIP:
862 if (!(decrypt_in & RX_MPDU_RES
863 /* Bad TTAK */
864 decrypt_out |= RX_RES_
865 break;
866 }
867 /* fall through if TTAK OK */
868 default:
869 if (!(decrypt_in & RX_MPDU_RES
870 decrypt_out |= RX_RES_
871 else
872 decrypt_out |= RX_RES_
873 break;
874 };
875
876 IWL_DEBUG_RX(priv, "decrypt_in:0x%x d
877 decryp
878
879 return decrypt_out;
880 }
881
882 static void iwl_pass_packet_to_mac80211(struct
883 int inc
884 struct
885 struct
886 {
887 struct iwl_rx_packet *pkt = (struct iw
888 struct iwl_rx_phy_res *rx_start = (inc
889 (struct iwl_rx_phy_res *)&(pkt->u.
890 struct ieee80211_hdr *hdr;
891 u16 len;
892 __le32 *rx_end;
893 unsigned int skblen;
894 u32 ampdu_status;
895 u32 ampdu_status_legacy;
896
897 if (!include_phy && priv->last_phy_res
898 rx_start = (struct iwl_rx_phy_
899
900 if (!rx_start) {
901 IWL_ERR(priv, "MPDU frame with
902 return;
903 }
904 if (include_phy) {
905 hdr = (struct ieee80211_hdr *)
906
907
908 len = le16_to_cpu(rx_start->by
909
910 rx_end = (__le32 *)((u8 *) &pk
911 sizeof(struc
912 rx_start->cf
913
914 } else {
915 struct iwl4965_rx_mpdu_res_sta
916 (struct iwl4965_rx_mpdu_re
917
918 hdr = (struct ieee80211_hdr *)
919 sizeof(struct i
920 len = le16_to_cpu(amsdu->byte
921 rx_start->byte_count = amsdu->
922 rx_end = (__le32 *) (((u8 *) h
923 }
924
925 ampdu_status = le32_to_cpu(*rx_end);
926 skblen = ((u8 *) rx_end - (u8 *) &pkt-
927
928 if (!include_phy) {
929 /* New status scheme, need to
930 ampdu_status_legacy = ampdu_st
931 ampdu_status = iwl_translate_r
932 }
933
934 /* start from MAC */
935 skb_reserve(rxb->skb, (void *)hdr - (v
936 skb_put(rxb->skb, len); /* end where d
937
938 /* We only process data packets if the
939 if (unlikely(!priv->is_open)) {
940 IWL_DEBUG_DROP_LIMIT(priv,
941 "Dropping packet while int
942 return;
943 }
944
945 hdr = (struct ieee80211_hdr *)rxb->skb
946
947 /* in case of HW accelerated crypto a
948 if (!priv->hw_params.sw_crypto &&
949 iwl_set_decrypted_flag(priv, hdr,
950 return;
951
952 iwl_update_rx_stats(priv, le16_to_cpu(
953 ieee80211_rx_irqsafe(priv->hw, rxb->sk
954 priv->alloc_rxb_skb--;
955 rxb->skb = NULL;
956 }
957
958 /* This is necessary only for a number of stat
959 static int iwl_is_network_packet(struct iwl_pr
960 struct ieee80211_hdr *header)
961 {
962 /* Filter incoming packets to determin
963 * this network, discarding packets co
964 switch (priv->iw_mode) {
965 case NL80211_IFTYPE_ADHOC: /* Header:
966 /* packets to our IBSS update
967 return !compare_ether_addr(hea
968 case NL80211_IFTYPE_STATION: /* Header
969 /* packets to our IBSS update
970 return !compare_ether_addr(hea
971 default:
972 return 1;
973 }
974 }
975
976 /* Called for REPLY_RX (legacy ABG frames), or
977 * REPLY_RX_MPDU_CMD (HT high-throughput N fra
978 void iwl_rx_reply_rx(struct iwl_priv *priv,
979 struct iwl_rx_
980 {
981 struct ieee80211_hdr *header;
982 struct ieee80211_rx_status rx_status;
983 struct iwl_rx_packet *pkt = (struct iw
984 /* Use phy data (Rx signal strength, e
985 * this rx packet for legacy frames,
986 * or phy data cached from REPLY_RX_
987 int include_phy = (pkt->hdr.cmd == REP
988 struct iwl_rx_phy_res *rx_start = (inc
989 (struct iwl_rx_phy_res *)&(pkt
990 (struct iwl_rx_phy_res *)&priv
991 __le32 *rx_end;
992 unsigned int len = 0;
993 u16 fc;
994 u8 network_packet;
995
996 rx_status.mactime = le64_to_cpu(rx_sta
997 rx_status.freq =
998 ieee80211_channel_to_frequency
999 rx_status.band = (rx_start->phy_flags
1000 IEEE80211_BAN
1001 rx_status.rate_idx =
1002 iwl_hwrate_to_plcp_idx(le32_t
1003 if (rx_status.band == IEEE80211_BAND_
1004 rx_status.rate_idx -= IWL_FIR
1005
1006 rx_status.flag = 0;
1007
1008 /* TSF isn't reliable. In order to al
1009 * this W/A doesn't propagate it to t
1010 /*rx_status.flag |= RX_FLAG_TSFT;*/
1011
1012 if ((unlikely(rx_start->cfg_phy_cnt >
1013 IWL_DEBUG_DROP(priv, "dsp siz
1014 rx_start->cfg
1015 return;
1016 }
1017
1018 if (!include_phy) {
1019 if (priv->last_phy_res[0])
1020 rx_start = (struct iw
1021 &priv->last_p
1022 else
1023 rx_start = NULL;
1024 }
1025
1026 if (!rx_start) {
1027 IWL_ERR(priv, "MPDU frame wit
1028 return;
1029 }
1030
1031 if (include_phy) {
1032 header = (struct ieee80211_hd
1033
1034
1035 len = le16_to_cpu(rx_start->b
1036 rx_end = (__le32 *)(pkt->u.ra
1037 sizeof(stru
1038 } else {
1039 struct iwl4965_rx_mpdu_res_st
1040 (struct iwl4965_rx_mp
1041
1042 header = (void *)(pkt->u.raw
1043 sizeof(struct iwl4965
1044 len = le16_to_cpu(amsdu->byte
1045 rx_end = (__le32 *) (pkt->u.r
1046 sizeof(struct iwl4965
1047 }
1048
1049 if (!(*rx_end & RX_RES_STATUS_NO_CRC3
1050 !(*rx_end & RX_RES_STATUS_NO_RXE_
1051 IWL_DEBUG_RX(priv, "Bad CRC o
1052 le32_to_cpu(*
1053 return;
1054 }
1055
1056 priv->ucode_beacon_time = le32_to_cpu
1057
1058 /* Find max signal strength (dBm) amo
1059 rx_status.signal = iwl_calc_rssi(priv
1060
1061 /* Meaningful noise values are availa
1062 * which are gathered only when ass
1063 * only for the associated network
1064 * Ignore these noise values while sc
1065 if (iwl_is_associated(priv) &&
1066 !test_bit(STATUS_SCANNING, &priv-
1067 rx_status.noise = priv->last_
1068 rx_status.qual = iwl_calc_sig
1069
1070 } else {
1071 rx_status.noise = IWL_NOISE_M
1072 rx_status.qual = iwl_calc_sig
1073 }
1074
1075 /* Reset beacon noise level if not as
1076 if (!iwl_is_associated(priv))
1077 priv->last_rx_noise = IWL_NOI
1078
1079 /* Set "1" to report good data frames
1080 #ifdef CONFIG_IWLWIFI_DEBUG
1081 if (unlikely(priv->debug_level & IWL_
1082 iwl_dbg_report_frame(priv, rx
1083 #endif
1084 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d,
1085 rx_status.signal, rx_status.n
1086 (unsigned long long)rx_status
1087
1088 /*
1089 * "antenna number"
1090 *
1091 * It seems that the antenna field in
1092 * is actually a bit field. This is u
1093 * it wants an actual antenna number
1094 * for most legacy frames I receive i
1095 * same frame was received on all thr
1096 *
1097 * I think this field should be remov
1098 * new 802.11n radiotap field "RX cha
1099 * as a bitmask.
1100 */
1101 rx_status.antenna = le16_to_cpu(rx_st
1102 RX_RE
1103
1104 /* set the preamble flag if appropria
1105 if (rx_start->phy_flags & RX_RES_PHY_
1106 rx_status.flag |= RX_FLAG_SHO
1107
1108 network_packet = iwl_is_network_packe
1109 if (network_packet) {
1110 priv->last_rx_rssi = rx_statu
1111 priv->last_beacon_time = pri
1112 priv->last_tsf = le64_to_cpu(
1113 }
1114
1115 fc = le16_to_cpu(header->frame_contro
1116 switch (fc & IEEE80211_FCTL_FTYPE) {
1117 case IEEE80211_FTYPE_MGMT:
1118 case IEEE80211_FTYPE_DATA:
1119 if (priv->iw_mode == NL80211_
1120 iwl_update_ps_mode(pr
1121
1122 /* fall through */
1123 default:
1124 iwl_pass_packet_to_ma
1125 &rx_status
1126 break;
1127
1128 }
1129 }
1130 EXPORT_SYMBOL(iwl_rx_reply_rx);
1131
1132 /* Cache phy data (Rx signal strength, etc) f
1133 * This will be used later in iwl_rx_reply_rx
1134 void iwl_rx_reply_rx_phy(struct iwl_priv *pri
1135 struct iw
1136 {
1137 struct iwl_rx_packet *pkt = (struct i
1138 priv->last_phy_res[0] = 1;
1139 memcpy(&priv->last_phy_res[1], &(pkt-
1140 sizeof(struct iwl_rx_phy_res))
1141 }
1142 EXPORT_SYMBOL(iwl_rx_reply_rx_phy);
1143
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