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1 /* 1
2
3 Broadcom BCM43xx wireless driver
4
5 DMA ringbuffer and descriptor allocation/man
6
7 Copyright (c) 2005, 2006 Michael Buesch <mbu
8
9 Some code in this file is derived from the b
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redis
14 it under the terms of the GNU General Public
15 the Free Software Foundation; either version
16 (at your option) any later version.
17
18 This program is distributed in the hope that
19 but WITHOUT ANY WARRANTY; without even the i
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU G
24 along with this program; see the file COPYIN
25 the Free Software Foundation, Inc., 51 Frank
26 Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "bcm43xx.h"
31 #include "bcm43xx_dma.h"
32 #include "bcm43xx_main.h"
33 #include "bcm43xx_debugfs.h"
34 #include "bcm43xx_power.h"
35 #include "bcm43xx_xmit.h"
36
37 #include <linux/dma-mapping.h>
38 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <linux/skbuff.h>
41
42
43 static inline int free_slots(struct bcm43xx_dm
44 {
45 return (ring->nr_slots - ring->used_sl
46 }
47
48 static inline int next_slot(struct bcm43xx_dma
49 {
50 assert(slot >= -1 && slot <= ring->nr_
51 if (slot == ring->nr_slots - 1)
52 return 0;
53 return slot + 1;
54 }
55
56 static inline int prev_slot(struct bcm43xx_dma
57 {
58 assert(slot >= 0 && slot <= ring->nr_s
59 if (slot == 0)
60 return ring->nr_slots - 1;
61 return slot - 1;
62 }
63
64 /* Request a slot for usage. */
65 static inline
66 int request_slot(struct bcm43xx_dmaring *ring)
67 {
68 int slot;
69
70 assert(ring->tx);
71 assert(!ring->suspended);
72 assert(free_slots(ring) != 0);
73
74 slot = next_slot(ring, ring->current_s
75 ring->current_slot = slot;
76 ring->used_slots++;
77
78 /* Check the number of available slots
79 * if we are running low on free slots
80 */
81 if (unlikely(free_slots(ring) < ring->
82 netif_stop_queue(ring->bcm->ne
83 ring->suspended = 1;
84 }
85 #ifdef CONFIG_BCM43XX_DEBUG
86 if (ring->used_slots > ring->max_used_
87 ring->max_used_slots = ring->u
88 #endif /* CONFIG_BCM43XX_DEBUG*/
89
90 return slot;
91 }
92
93 /* Return a slot to the free slots. */
94 static inline
95 void return_slot(struct bcm43xx_dmaring *ring,
96 {
97 assert(ring->tx);
98
99 ring->used_slots--;
100
101 /* Check if TX is suspended and check
102 * enough free slots to resume it agai
103 */
104 if (unlikely(ring->suspended)) {
105 if (free_slots(ring) >= ring->
106 ring->suspended = 0;
107 netif_wake_queue(ring-
108 }
109 }
110 }
111
112 u16 bcm43xx_dmacontroller_base(int dma64bit, i
113 {
114 static const u16 map64[] = {
115 BCM43xx_MMIO_DMA64_BASE0,
116 BCM43xx_MMIO_DMA64_BASE1,
117 BCM43xx_MMIO_DMA64_BASE2,
118 BCM43xx_MMIO_DMA64_BASE3,
119 BCM43xx_MMIO_DMA64_BASE4,
120 BCM43xx_MMIO_DMA64_BASE5,
121 };
122 static const u16 map32[] = {
123 BCM43xx_MMIO_DMA32_BASE0,
124 BCM43xx_MMIO_DMA32_BASE1,
125 BCM43xx_MMIO_DMA32_BASE2,
126 BCM43xx_MMIO_DMA32_BASE3,
127 BCM43xx_MMIO_DMA32_BASE4,
128 BCM43xx_MMIO_DMA32_BASE5,
129 };
130
131 if (dma64bit) {
132 assert(controller_idx >= 0 &&
133 controller_idx < ARRAY_
134 return map64[controller_idx];
135 }
136 assert(controller_idx >= 0 &&
137 controller_idx < ARRAY_SIZE(map
138 return map32[controller_idx];
139 }
140
141 static inline
142 dma_addr_t map_descbuffer(struct bcm43xx_dmari
143 unsigned char *buf,
144 size_t len,
145 int tx)
146 {
147 dma_addr_t dmaaddr;
148 int direction = PCI_DMA_FROMDEVICE;
149
150 if (tx)
151 direction = PCI_DMA_TODEVICE;
152
153 dmaaddr = pci_map_single(ring->bcm->pc
154 buf,
155 direc
156
157 return dmaaddr;
158 }
159
160 static inline
161 void unmap_descbuffer(struct bcm43xx_dmaring *
162 dma_addr_t addr,
163 size_t len,
164 int tx)
165 {
166 if (tx) {
167 pci_unmap_single(ring->bcm->pc
168 addr, len,
169 PCI_DMA_TODEV
170 } else {
171 pci_unmap_single(ring->bcm->pc
172 addr, len,
173 PCI_DMA_FROMD
174 }
175 }
176
177 static inline
178 void sync_descbuffer_for_cpu(struct bcm43xx_dm
179 dma_addr_t addr,
180 size_t len)
181 {
182 assert(!ring->tx);
183
184 pci_dma_sync_single_for_cpu(ring->bcm-
185 addr, len,
186 }
187
188 static inline
189 void sync_descbuffer_for_device(struct bcm43xx
190 dma_addr_t add
191 size_t len)
192 {
193 assert(!ring->tx);
194
195 pci_dma_sync_single_for_cpu(ring->bcm-
196 addr, len,
197 }
198
199 /* Unmap and free a descriptor buffer. */
200 static inline
201 void free_descriptor_buffer(struct bcm43xx_dma
202 struct bcm43xx_dma
203 int irq_context)
204 {
205 assert(meta->skb);
206 if (irq_context)
207 dev_kfree_skb_irq(meta->skb);
208 else
209 dev_kfree_skb(meta->skb);
210 meta->skb = NULL;
211 }
212
213 static int alloc_ringmemory(struct bcm43xx_dma
214 {
215 ring->descbase = pci_alloc_consistent(
216 &(
217 if (!ring->descbase) {
218 /* Allocation may have failed
219 insisting on use of GFP_DMA
220 than necessary... */
221 struct dma_desc *rx_ring;
222 dma_addr_t rx_ring_dma;
223
224 rx_ring = kzalloc(BCM43xx_DMA_
225 if (!rx_ring)
226 goto out_err;
227
228 rx_ring_dma = pci_map_single(r
229 B
230 P
231
232 if (pci_dma_mapping_error(rx_r
233 rx_ring_dma + BCM43xx_DMA_
234 /* Sigh... */
235 if (!pci_dma_mapping_e
236 pci_unmap_sing
237
238
239 rx_ring_dma = pci_map_
240
241
242 if (pci_dma_mapping_er
243 rx_ring_dma + BCM4
244 assert(0);
245 if (!pci_dma_m
246 pci_un
247
248
249 goto out_err;
250 }
251 }
252
253 ring->descbase = rx_ring;
254 ring->dmabase = rx_ring_dma;
255 }
256 memset(ring->descbase, 0, BCM43xx_DMA_
257
258 return 0;
259 out_err:
260 printk(KERN_ERR PFX "DMA ringmemory al
261 return -ENOMEM;
262 }
263
264 static void free_ringmemory(struct bcm43xx_dma
265 {
266 struct device *dev = &(ring->bcm->pci_
267
268 dma_free_coherent(dev, BCM43xx_DMA_RIN
269 ring->descbase, ring
270 }
271
272 /* Reset the RX DMA channel */
273 int bcm43xx_dmacontroller_rx_reset(struct bcm4
274 u16 mmio_ba
275 {
276 int i;
277 u32 value;
278 u16 offset;
279
280 offset = dma64 ? BCM43xx_DMA64_RXCTL :
281 bcm43xx_write32(bcm, mmio_base + offse
282 for (i = 0; i < 1000; i++) {
283 offset = dma64 ? BCM43xx_DMA64
284 value = bcm43xx_read32(bcm, mm
285 if (dma64) {
286 value &= BCM43xx_DMA64
287 if (value == BCM43xx_D
288 i = -1;
289 break;
290 }
291 } else {
292 value &= BCM43xx_DMA32
293 if (value == BCM43xx_D
294 i = -1;
295 break;
296 }
297 }
298 udelay(10);
299 }
300 if (i != -1) {
301 printk(KERN_ERR PFX "Error: Wa
302 return -ENODEV;
303 }
304
305 return 0;
306 }
307
308 /* Reset the RX DMA channel */
309 int bcm43xx_dmacontroller_tx_reset(struct bcm4
310 u16 mmio_ba
311 {
312 int i;
313 u32 value;
314 u16 offset;
315
316 for (i = 0; i < 1000; i++) {
317 offset = dma64 ? BCM43xx_DMA64
318 value = bcm43xx_read32(bcm, mm
319 if (dma64) {
320 value &= BCM43xx_DMA64
321 if (value == BCM43xx_D
322 value == BCM43xx_D
323 value == BCM43xx_D
324 break;
325 } else {
326 value &= BCM43xx_DMA32
327 if (value == BCM43xx_D
328 value == BCM43xx_D
329 value == BCM43xx_D
330 break;
331 }
332 udelay(10);
333 }
334 offset = dma64 ? BCM43xx_DMA64_TXCTL :
335 bcm43xx_write32(bcm, mmio_base + offse
336 for (i = 0; i < 1000; i++) {
337 offset = dma64 ? BCM43xx_DMA64
338 value = bcm43xx_read32(bcm, mm
339 if (dma64) {
340 value &= BCM43xx_DMA64
341 if (value == BCM43xx_D
342 i = -1;
343 break;
344 }
345 } else {
346 value &= BCM43xx_DMA32
347 if (value == BCM43xx_D
348 i = -1;
349 break;
350 }
351 }
352 udelay(10);
353 }
354 if (i != -1) {
355 printk(KERN_ERR PFX "Error: Wa
356 return -ENODEV;
357 }
358 /* ensure the reset is completed. */
359 udelay(300);
360
361 return 0;
362 }
363
364 static void fill_descriptor(struct bcm43xx_dma
365 struct bcm43xx_dma
366 dma_addr_t dmaaddr
367 u16 bufsize,
368 int start, int end
369 {
370 int slot;
371
372 slot = bcm43xx_dma_desc2idx(ring, desc
373 assert(slot >= 0 && slot < ring->nr_sl
374
375 if (ring->dma64) {
376 u32 ctl0 = 0, ctl1 = 0;
377 u32 addrlo, addrhi;
378 u32 addrext;
379
380 addrlo = (u32)(dmaaddr & 0xFFF
381 addrhi = (((u64)dmaaddr >> 32)
382 addrext = (((u64)dmaaddr >> 32
383 addrhi |= ring->routing;
384 if (slot == ring->nr_slots - 1
385 ctl0 |= BCM43xx_DMA64_
386 if (start)
387 ctl0 |= BCM43xx_DMA64_
388 if (end)
389 ctl0 |= BCM43xx_DMA64_
390 if (irq)
391 ctl0 |= BCM43xx_DMA64_
392 ctl1 |= (bufsize - ring->frame
393 & BCM43xx_DMA64_DCTL1_
394 ctl1 |= (addrext << BCM43xx_DM
395 & BCM43xx_DMA64_DCTL1_
396
397 desc->dma64.control0 = cpu_to_
398 desc->dma64.control1 = cpu_to_
399 desc->dma64.address_low = cpu_
400 desc->dma64.address_high = cpu
401 } else {
402 u32 ctl;
403 u32 addr;
404 u32 addrext;
405
406 addr = (u32)(dmaaddr & ~BCM43x
407 addrext = (u32)(dmaaddr & BCM4
408 >> BCM43xx_DMA32_RO
409 addr |= ring->routing;
410 ctl = (bufsize - ring->frameof
411 & BCM43xx_DMA32_DCTL_BYT
412 if (slot == ring->nr_slots - 1
413 ctl |= BCM43xx_DMA32_D
414 if (start)
415 ctl |= BCM43xx_DMA32_D
416 if (end)
417 ctl |= BCM43xx_DMA32_D
418 if (irq)
419 ctl |= BCM43xx_DMA32_D
420 ctl |= (addrext << BCM43xx_DMA
421 & BCM43xx_DMA32_DCTL_AD
422
423 desc->dma32.control = cpu_to_l
424 desc->dma32.address = cpu_to_l
425 }
426 }
427
428 static int setup_rx_descbuffer(struct bcm43xx_
429 struct bcm43xx_
430 struct bcm43xx_
431 gfp_t gfp_flags
432 {
433 struct bcm43xx_rxhdr *rxhdr;
434 struct bcm43xx_hwxmitstatus *xmitstat;
435 dma_addr_t dmaaddr;
436 struct sk_buff *skb;
437
438 assert(!ring->tx);
439
440 skb = __dev_alloc_skb(ring->rx_buffers
441 if (unlikely(!skb))
442 return -ENOMEM;
443 dmaaddr = map_descbuffer(ring, skb->da
444 /* This hardware bug work-around adapt
445 The chip may be unable to do PCI DM
446 if (pci_dma_mapping_error(dmaaddr) ||
447 dmaaddr + ring->rx_buffersize > ri
448 /* This one has 30-bit address
449 if (!pci_dma_mapping_error(dma
450 pci_unmap_single(ring-
451 dmaad
452 PCI_D
453 dev_kfree_skb_any(skb);
454 skb = __dev_alloc_skb(ring->rx
455 if (skb == NULL)
456 return -ENOMEM;
457 dmaaddr = pci_map_single(ring-
458 skb->
459 PCI_D
460 if (pci_dma_mapping_error(dmaa
461 dmaaddr + ring->rx_buffers
462 assert(0);
463 dev_kfree_skb_any(skb)
464 return -ENOMEM;
465 }
466 }
467 meta->skb = skb;
468 meta->dmaaddr = dmaaddr;
469 skb->dev = ring->bcm->net_dev;
470
471 fill_descriptor(ring, desc, dmaaddr,
472 ring->rx_buffersize, 0
473
474 rxhdr = (struct bcm43xx_rxhdr *)(skb->
475 rxhdr->frame_length = 0;
476 rxhdr->flags1 = 0;
477 xmitstat = (struct bcm43xx_hwxmitstatu
478 xmitstat->cookie = 0;
479
480 return 0;
481 }
482
483 /* Allocate the initial descbuffers.
484 * This is used for an RX ring only.
485 */
486 static int alloc_initial_descbuffers(struct bc
487 {
488 int i, err = -ENOMEM;
489 struct bcm43xx_dmadesc_generic *desc;
490 struct bcm43xx_dmadesc_meta *meta;
491
492 for (i = 0; i < ring->nr_slots; i++) {
493 desc = bcm43xx_dma_idx2desc(ri
494
495 err = setup_rx_descbuffer(ring
496 if (err)
497 goto err_unwind;
498 }
499 mb();
500 ring->used_slots = ring->nr_slots;
501 err = 0;
502 out:
503 return err;
504
505 err_unwind:
506 for (i--; i >= 0; i--) {
507 desc = bcm43xx_dma_idx2desc(ri
508
509 unmap_descbuffer(ring, meta->d
510 dev_kfree_skb(meta->skb);
511 }
512 goto out;
513 }
514
515 /* Do initial setup of the DMA controller.
516 * Reset the controller, write the ring busadd
517 * and switch the "enable" bit on.
518 */
519 static int dmacontroller_setup(struct bcm43xx_
520 {
521 int err = 0;
522 u32 value;
523 u32 addrext;
524
525 if (ring->tx) {
526 if (ring->dma64) {
527 u64 ringbase = (u64)(r
528
529 addrext = ((ringbase >
530 value = BCM43xx_DMA64_
531 value |= (addrext << B
532 & BCM43xx_DMA6
533 bcm43xx_dma_write(ring
534 bcm43xx_dma_write(ring
535 (ringb
536 bcm43xx_dma_write(ring
537 ((ring
538 | ring
539 } else {
540 u32 ringbase = (u32)(r
541
542 addrext = (ringbase >>
543 value = BCM43xx_DMA32_
544 value |= (addrext << B
545 & BCM43xx_DMA3
546 bcm43xx_dma_write(ring
547 bcm43xx_dma_write(ring
548 (ringb
549 | ring
550 }
551 } else {
552 err = alloc_initial_descbuffer
553 if (err)
554 goto out;
555 if (ring->dma64) {
556 u64 ringbase = (u64)(r
557
558 addrext = ((ringbase >
559 value = (ring->frameof
560 value |= BCM43xx_DMA64
561 value |= (addrext << B
562 & BCM43xx_DMA6
563 bcm43xx_dma_write(ring
564 bcm43xx_dma_write(ring
565 (ringb
566 bcm43xx_dma_write(ring
567 ((ring
568 | ring
569 bcm43xx_dma_write(ring
570 } else {
571 u32 ringbase = (u32)(r
572
573 addrext = (ringbase >>
574 value = (ring->frameof
575 value |= BCM43xx_DMA32
576 value |= (addrext << B
577 & BCM43xx_DMA3
578 bcm43xx_dma_write(ring
579 bcm43xx_dma_write(ring
580 (ringb
581 | ring
582 bcm43xx_dma_write(ring
583 }
584 }
585
586 out:
587 return err;
588 }
589
590 /* Shutdown the DMA controller. */
591 static void dmacontroller_cleanup(struct bcm43
592 {
593 if (ring->tx) {
594 bcm43xx_dmacontroller_tx_reset
595 if (ring->dma64) {
596 bcm43xx_dma_write(ring
597 bcm43xx_dma_write(ring
598 } else
599 bcm43xx_dma_write(ring
600 } else {
601 bcm43xx_dmacontroller_rx_reset
602 if (ring->dma64) {
603 bcm43xx_dma_write(ring
604 bcm43xx_dma_write(ring
605 } else
606 bcm43xx_dma_write(ring
607 }
608 }
609
610 static void free_all_descbuffers(struct bcm43x
611 {
612 struct bcm43xx_dmadesc_generic *desc;
613 struct bcm43xx_dmadesc_meta *meta;
614 int i;
615
616 if (!ring->used_slots)
617 return;
618 for (i = 0; i < ring->nr_slots; i++) {
619 desc = bcm43xx_dma_idx2desc(ri
620
621 if (!meta->skb) {
622 assert(ring->tx);
623 continue;
624 }
625 if (ring->tx) {
626 unmap_descbuffer(ring,
627 meta->
628 } else {
629 unmap_descbuffer(ring,
630 ring->
631 }
632 free_descriptor_buffer(ring, m
633 }
634 }
635
636 /* Main initialization function. */
637 static
638 struct bcm43xx_dmaring * bcm43xx_setup_dmaring
639
640
641
642 {
643 struct bcm43xx_dmaring *ring;
644 int err;
645 int nr_slots;
646
647 ring = kzalloc(sizeof(*ring), GFP_KERN
648 if (!ring)
649 goto out;
650
651 nr_slots = BCM43xx_RXRING_SLOTS;
652 if (for_tx)
653 nr_slots = BCM43xx_TXRING_SLOT
654
655 ring->meta = kcalloc(nr_slots, sizeof(
656 GFP_KERNEL);
657 if (!ring->meta)
658 goto err_kfree_ring;
659
660 ring->routing = BCM43xx_DMA32_CLIENTTR
661 if (dma64)
662 ring->routing = BCM43xx_DMA64_
663
664 ring->bcm = bcm;
665 ring->nr_slots = nr_slots;
666 ring->suspend_mark = ring->nr_slots *
667 ring->resume_mark = ring->nr_slots * B
668 assert(ring->suspend_mark < ring->resu
669 ring->mmio_base = bcm43xx_dmacontrolle
670 ring->index = controller_index;
671 ring->dma64 = !!dma64;
672 if (for_tx) {
673 ring->tx = 1;
674 ring->current_slot = -1;
675 } else {
676 if (ring->index == 0) {
677 ring->rx_buffersize =
678 ring->frameoffset = BC
679 } else if (ring->index == 3) {
680 ring->rx_buffersize =
681 ring->frameoffset = BC
682 } else
683 assert(0);
684 }
685
686 err = alloc_ringmemory(ring);
687 if (err)
688 goto err_kfree_meta;
689 err = dmacontroller_setup(ring);
690 if (err)
691 goto err_free_ringmemory;
692 return ring;
693
694 out:
695 printk(KERN_ERR PFX "Error in bcm43xx_
696 return ring;
697
698 err_free_ringmemory:
699 free_ringmemory(ring);
700 err_kfree_meta:
701 kfree(ring->meta);
702 err_kfree_ring:
703 kfree(ring);
704 ring = NULL;
705 goto out;
706 }
707
708 /* Main cleanup function. */
709 static void bcm43xx_destroy_dmaring(struct bcm
710 {
711 if (!ring)
712 return;
713
714 dprintk(KERN_INFO PFX "DMA-%s 0x%04X (
715 (ring->dma64) ? "64" : "32",
716 ring->mmio_base,
717 (ring->tx) ? "TX" : "RX",
718 ring->max_used_slots, ring->nr
719 /* Device IRQs are disabled prior ente
720 * so no need to take care of concurre
721 */
722 dmacontroller_cleanup(ring);
723 free_all_descbuffers(ring);
724 free_ringmemory(ring);
725
726 kfree(ring->meta);
727 kfree(ring);
728 }
729
730 void bcm43xx_dma_free(struct bcm43xx_private *
731 {
732 struct bcm43xx_dma *dma;
733
734 if (bcm43xx_using_pio(bcm))
735 return;
736 dma = bcm43xx_current_dma(bcm);
737
738 bcm43xx_destroy_dmaring(dma->rx_ring3)
739 dma->rx_ring3 = NULL;
740 bcm43xx_destroy_dmaring(dma->rx_ring0)
741 dma->rx_ring0 = NULL;
742
743 bcm43xx_destroy_dmaring(dma->tx_ring5)
744 dma->tx_ring5 = NULL;
745 bcm43xx_destroy_dmaring(dma->tx_ring4)
746 dma->tx_ring4 = NULL;
747 bcm43xx_destroy_dmaring(dma->tx_ring3)
748 dma->tx_ring3 = NULL;
749 bcm43xx_destroy_dmaring(dma->tx_ring2)
750 dma->tx_ring2 = NULL;
751 bcm43xx_destroy_dmaring(dma->tx_ring1)
752 dma->tx_ring1 = NULL;
753 bcm43xx_destroy_dmaring(dma->tx_ring0)
754 dma->tx_ring0 = NULL;
755 }
756
757 int bcm43xx_dma_init(struct bcm43xx_private *b
758 {
759 struct bcm43xx_dma *dma = bcm43xx_curr
760 struct bcm43xx_dmaring *ring;
761 int err = -ENOMEM;
762 int dma64 = 0;
763
764 bcm->dma_mask = bcm43xx_get_supported_
765 if (bcm->dma_mask == DMA_64BIT_MASK)
766 dma64 = 1;
767 err = pci_set_dma_mask(bcm->pci_dev, b
768 if (err)
769 goto no_dma;
770 err = pci_set_consistent_dma_mask(bcm-
771 if (err)
772 goto no_dma;
773
774 /* setup TX DMA channels. */
775 ring = bcm43xx_setup_dmaring(bcm, 0, 1
776 if (!ring)
777 goto out;
778 dma->tx_ring0 = ring;
779
780 ring = bcm43xx_setup_dmaring(bcm, 1, 1
781 if (!ring)
782 goto err_destroy_tx0;
783 dma->tx_ring1 = ring;
784
785 ring = bcm43xx_setup_dmaring(bcm, 2, 1
786 if (!ring)
787 goto err_destroy_tx1;
788 dma->tx_ring2 = ring;
789
790 ring = bcm43xx_setup_dmaring(bcm, 3, 1
791 if (!ring)
792 goto err_destroy_tx2;
793 dma->tx_ring3 = ring;
794
795 ring = bcm43xx_setup_dmaring(bcm, 4, 1
796 if (!ring)
797 goto err_destroy_tx3;
798 dma->tx_ring4 = ring;
799
800 ring = bcm43xx_setup_dmaring(bcm, 5, 1
801 if (!ring)
802 goto err_destroy_tx4;
803 dma->tx_ring5 = ring;
804
805 /* setup RX DMA channels. */
806 ring = bcm43xx_setup_dmaring(bcm, 0, 0
807 if (!ring)
808 goto err_destroy_tx5;
809 dma->rx_ring0 = ring;
810
811 if (bcm->current_core->rev < 5) {
812 ring = bcm43xx_setup_dmaring(b
813 if (!ring)
814 goto err_destroy_rx0;
815 dma->rx_ring3 = ring;
816 }
817
818 dprintk(KERN_INFO PFX "%d-bit DMA init
819 (bcm->dma_mask == DMA_64BIT_MA
820 (bcm->dma_mask == DMA_32BIT_MA
821 err = 0;
822 out:
823 return err;
824
825 err_destroy_rx0:
826 bcm43xx_destroy_dmaring(dma->rx_ring0)
827 dma->rx_ring0 = NULL;
828 err_destroy_tx5:
829 bcm43xx_destroy_dmaring(dma->tx_ring5)
830 dma->tx_ring5 = NULL;
831 err_destroy_tx4:
832 bcm43xx_destroy_dmaring(dma->tx_ring4)
833 dma->tx_ring4 = NULL;
834 err_destroy_tx3:
835 bcm43xx_destroy_dmaring(dma->tx_ring3)
836 dma->tx_ring3 = NULL;
837 err_destroy_tx2:
838 bcm43xx_destroy_dmaring(dma->tx_ring2)
839 dma->tx_ring2 = NULL;
840 err_destroy_tx1:
841 bcm43xx_destroy_dmaring(dma->tx_ring1)
842 dma->tx_ring1 = NULL;
843 err_destroy_tx0:
844 bcm43xx_destroy_dmaring(dma->tx_ring0)
845 dma->tx_ring0 = NULL;
846 no_dma:
847 #ifdef CONFIG_BCM43XX_PIO
848 printk(KERN_WARNING PFX "DMA not suppo
849 " Falling back
850 bcm->__using_pio = 1;
851 return -ENOSYS;
852 #else
853 printk(KERN_ERR PFX "FATAL: DMA not su
854 "Please recompile
855 return -ENODEV;
856 #endif /* CONFIG_BCM43XX_PIO */
857 }
858
859 /* Generate a cookie for the TX header. */
860 static u16 generate_cookie(struct bcm43xx_dmar
861 int slot)
862 {
863 u16 cookie = 0x1000;
864
865 /* Use the upper 4 bits of the cookie
866 * DMA controller ID and store the slo
867 * in the lower 12 bits.
868 * Note that the cookie must never be
869 * is a special value used in RX path.
870 */
871 switch (ring->index) {
872 case 0:
873 cookie = 0xA000;
874 break;
875 case 1:
876 cookie = 0xB000;
877 break;
878 case 2:
879 cookie = 0xC000;
880 break;
881 case 3:
882 cookie = 0xD000;
883 break;
884 case 4:
885 cookie = 0xE000;
886 break;
887 case 5:
888 cookie = 0xF000;
889 break;
890 }
891 assert(((u16)slot & 0xF000) == 0x0000)
892 cookie |= (u16)slot;
893
894 return cookie;
895 }
896
897 /* Inspect a cookie and find out to which cont
898 static
899 struct bcm43xx_dmaring * parse_cookie(struct b
900 u16 cook
901 {
902 struct bcm43xx_dma *dma = bcm43xx_curr
903 struct bcm43xx_dmaring *ring = NULL;
904
905 switch (cookie & 0xF000) {
906 case 0xA000:
907 ring = dma->tx_ring0;
908 break;
909 case 0xB000:
910 ring = dma->tx_ring1;
911 break;
912 case 0xC000:
913 ring = dma->tx_ring2;
914 break;
915 case 0xD000:
916 ring = dma->tx_ring3;
917 break;
918 case 0xE000:
919 ring = dma->tx_ring4;
920 break;
921 case 0xF000:
922 ring = dma->tx_ring5;
923 break;
924 default:
925 assert(0);
926 }
927 *slot = (cookie & 0x0FFF);
928 assert(*slot >= 0 && *slot < ring->nr_
929
930 return ring;
931 }
932
933 static void dmacontroller_poke_tx(struct bcm43
934 int slot)
935 {
936 u16 offset;
937 int descsize;
938
939 /* Everything is ready to start. Buffe
940 * associated with slots.
941 * "slot" is the last slot of the new
942 * Close your seat belts now, please.
943 */
944 wmb();
945 slot = next_slot(ring, slot);
946 offset = (ring->dma64) ? BCM43xx_DMA64
947 descsize = (ring->dma64) ? sizeof(stru
948 : sizeof(struct bcm43xx_dmades
949 bcm43xx_dma_write(ring, offset,
950 (u32)(slot * descsize)
951 }
952
953 static void dma_tx_fragment(struct bcm43xx_dma
954 struct sk_buff *sk
955 u8 cur_frag)
956 {
957 int slot;
958 struct bcm43xx_dmadesc_generic *desc;
959 struct bcm43xx_dmadesc_meta *meta;
960 dma_addr_t dmaaddr;
961 struct sk_buff *bounce_skb;
962
963 assert(skb_shinfo(skb)->nr_frags == 0)
964
965 slot = request_slot(ring);
966 desc = bcm43xx_dma_idx2desc(ring, slot
967
968 /* Add a device specific TX header. */
969 assert(skb_headroom(skb) >= sizeof(str
970 /* Reserve enough headroom for the dev
971 __skb_push(skb, sizeof(struct bcm43xx_
972 /* Now calculate and add the tx header
973 * The tx header includes the PLCP hea
974 */
975 bcm43xx_generate_txhdr(ring->bcm,
976 (struct bcm43xx
977 skb->data + siz
978 skb->len - size
979 (cur_frag == 0)
980 generate_cookie
981 dmaaddr = map_descbuffer(ring, skb->da
982 if (dma_mapping_error(dmaaddr) || dmaa
983 /* chip cannot handle DMA to/f
984 if (!dma_mapping_error(dmaaddr
985 unmap_descbuffer(ring,
986 bounce_skb = __dev_alloc_skb(s
987 if (!bounce_skb)
988 return;
989 dmaaddr = map_descbuffer(ring,
990 if (dma_mapping_error(dmaaddr)
991 if (!dma_mapping_error
992 unmap_descbuff
993 dev_kfree_skb_any(boun
994 assert(0);
995 return;
996 }
997 skb_copy_from_linear_data(skb,
998 skb-
999 dev_kfree_skb_any(skb);
1000 skb = bounce_skb;
1001 }
1002
1003 meta->skb = skb;
1004 meta->dmaaddr = dmaaddr;
1005
1006 fill_descriptor(ring, desc, dmaaddr,
1007 skb->len, 1, 1, 1);
1008
1009 /* Now transfer the whole frame. */
1010 dmacontroller_poke_tx(ring, slot);
1011 }
1012
1013 int bcm43xx_dma_tx(struct bcm43xx_private *bc
1014 struct ieee80211_txb *txb)
1015 {
1016 /* We just received a packet from the
1017 * Add headers and DMA map the memory
1018 * the device to send the stuff.
1019 * Note that this is called from atom
1020 */
1021 struct bcm43xx_dmaring *ring = bcm43x
1022 u8 i;
1023 struct sk_buff *skb;
1024
1025 assert(ring->tx);
1026 if (unlikely(free_slots(ring) < txb->
1027 /* The queue should be stoppe
1028 * if we are low on free slot
1029 * If this ever triggers, we
1030 */
1031 dprintkl(KERN_ERR PFX "Out of
1032 return -ENOMEM;
1033 }
1034
1035 for (i = 0; i < txb->nr_frags; i++) {
1036 skb = txb->fragments[i];
1037 /* Take skb from ieee80211_tx
1038 txb->fragments[i] = NULL;
1039 dma_tx_fragment(ring, skb, i)
1040 }
1041 ieee80211_txb_free(txb);
1042
1043 return 0;
1044 }
1045
1046 void bcm43xx_dma_handle_xmitstatus(struct bcm
1047 struct bcm
1048 {
1049 struct bcm43xx_dmaring *ring;
1050 struct bcm43xx_dmadesc_generic *desc;
1051 struct bcm43xx_dmadesc_meta *meta;
1052 int is_last_fragment;
1053 int slot;
1054 u32 tmp;
1055
1056 ring = parse_cookie(bcm, status->cook
1057 assert(ring);
1058 assert(ring->tx);
1059 while (1) {
1060 assert(slot >= 0 && slot < ri
1061 desc = bcm43xx_dma_idx2desc(r
1062
1063 if (ring->dma64) {
1064 tmp = le32_to_cpu(des
1065 is_last_fragment = !!
1066 } else {
1067 tmp = le32_to_cpu(des
1068 is_last_fragment = !!
1069 }
1070 unmap_descbuffer(ring, meta->
1071 free_descriptor_buffer(ring,
1072 /* Everything belonging to th
1073 * and freed, so we can retur
1074 */
1075 return_slot(ring, slot);
1076
1077 if (is_last_fragment)
1078 break;
1079 slot = next_slot(ring, slot);
1080 }
1081 bcm->stats.last_tx = jiffies;
1082 }
1083
1084 static void dma_rx(struct bcm43xx_dmaring *ri
1085 int *slot)
1086 {
1087 struct bcm43xx_dmadesc_generic *desc;
1088 struct bcm43xx_dmadesc_meta *meta;
1089 struct bcm43xx_rxhdr *rxhdr;
1090 struct sk_buff *skb;
1091 u16 len;
1092 int err;
1093 dma_addr_t dmaaddr;
1094
1095 desc = bcm43xx_dma_idx2desc(ring, *sl
1096
1097 sync_descbuffer_for_cpu(ring, meta->d
1098 skb = meta->skb;
1099
1100 if (ring->index == 3) {
1101 /* We received an xmit status
1102 struct bcm43xx_hwxmitstatus *
1103 struct bcm43xx_xmitstatus sta
1104 int i = 0;
1105
1106 stat.cookie = le16_to_cpu(hw-
1107 while (stat.cookie == 0) {
1108 if (unlikely(++i >= 1
1109 assert(0);
1110 break;
1111 }
1112 udelay(2);
1113 barrier();
1114 stat.cookie = le16_to
1115 }
1116 stat.flags = hw->flags;
1117 stat.cnt1 = hw->cnt1;
1118 stat.cnt2 = hw->cnt2;
1119 stat.seq = le16_to_cpu(hw->se
1120 stat.unknown = le16_to_cpu(hw
1121
1122 bcm43xx_debugfs_log_txstat(ri
1123 bcm43xx_dma_handle_xmitstatus
1124 /* recycle the descriptor buf
1125 sync_descbuffer_for_device(ri
1126
1127 return;
1128 }
1129 rxhdr = (struct bcm43xx_rxhdr *)skb->
1130 len = le16_to_cpu(rxhdr->frame_length
1131 if (len == 0) {
1132 int i = 0;
1133
1134 do {
1135 udelay(2);
1136 barrier();
1137 len = le16_to_cpu(rxh
1138 } while (len == 0 && i++ < 5)
1139 if (unlikely(len == 0)) {
1140 /* recycle the descri
1141 sync_descbuffer_for_d
1142
1143 goto drop;
1144 }
1145 }
1146 if (unlikely(len > ring->rx_buffersiz
1147 /* The data did not fit into
1148 * and is split over multiple
1149 * This should never happen,
1150 * big enough. So simply igno
1151 */
1152 int cnt = 0;
1153 s32 tmp = len;
1154
1155 while (1) {
1156 desc = bcm43xx_dma_id
1157 /* recycle the descri
1158 sync_descbuffer_for_d
1159
1160 *slot = next_slot(rin
1161 cnt++;
1162 tmp -= ring->rx_buffe
1163 if (tmp <= 0)
1164 break;
1165 }
1166 printkl(KERN_ERR PFX "DMA RX
1167 "(len: %u, buffer: %u
1168 len, ring->rx_buffers
1169 goto drop;
1170 }
1171 len -= IEEE80211_FCS_LEN;
1172
1173 dmaaddr = meta->dmaaddr;
1174 err = setup_rx_descbuffer(ring, desc,
1175 if (unlikely(err)) {
1176 dprintkl(KERN_ERR PFX "DMA RX
1177 sync_descbuffer_for_device(ri
1178 ri
1179 goto drop;
1180 }
1181
1182 unmap_descbuffer(ring, dmaaddr, ring-
1183 skb_put(skb, len + ring->frameoffset)
1184 skb_pull(skb, ring->frameoffset);
1185
1186 err = bcm43xx_rx(ring->bcm, skb, rxhd
1187 if (err) {
1188 dev_kfree_skb_irq(skb);
1189 goto drop;
1190 }
1191
1192 drop:
1193 return;
1194 }
1195
1196 void bcm43xx_dma_rx(struct bcm43xx_dmaring *r
1197 {
1198 u32 status;
1199 u16 descptr;
1200 int slot, current_slot;
1201 #ifdef CONFIG_BCM43XX_DEBUG
1202 int used_slots = 0;
1203 #endif
1204
1205 assert(!ring->tx);
1206 if (ring->dma64) {
1207 status = bcm43xx_dma_read(rin
1208 descptr = (status & BCM43xx_D
1209 current_slot = descptr / size
1210 } else {
1211 status = bcm43xx_dma_read(rin
1212 descptr = (status & BCM43xx_D
1213 current_slot = descptr / size
1214 }
1215 assert(current_slot >= 0 && current_s
1216
1217 slot = ring->current_slot;
1218 for ( ; slot != current_slot; slot =
1219 dma_rx(ring, &slot);
1220 #ifdef CONFIG_BCM43XX_DEBUG
1221 if (++used_slots > ring->max_
1222 ring->max_used_slots
1223 #endif
1224 }
1225 if (ring->dma64) {
1226 bcm43xx_dma_write(ring, BCM43
1227 (u32)(slot *
1228 } else {
1229 bcm43xx_dma_write(ring, BCM43
1230 (u32)(slot *
1231 }
1232 ring->current_slot = slot;
1233 }
1234
1235 void bcm43xx_dma_tx_suspend(struct bcm43xx_dm
1236 {
1237 assert(ring->tx);
1238 bcm43xx_power_saving_ctl_bits(ring->b
1239 if (ring->dma64) {
1240 bcm43xx_dma_write(ring, BCM43
1241 bcm43xx_dma_r
1242 | BCM43xx_DMA
1243 } else {
1244 bcm43xx_dma_write(ring, BCM43
1245 bcm43xx_dma_r
1246 | BCM43xx_DMA
1247 }
1248 }
1249
1250 void bcm43xx_dma_tx_resume(struct bcm43xx_dma
1251 {
1252 assert(ring->tx);
1253 if (ring->dma64) {
1254 bcm43xx_dma_write(ring, BCM43
1255 bcm43xx_dma_r
1256 & ~BCM43xx_DM
1257 } else {
1258 bcm43xx_dma_write(ring, BCM43
1259 bcm43xx_dma_r
1260 & ~BCM43xx_DM
1261 }
1262 bcm43xx_power_saving_ctl_bits(ring->b
1263 }
1264
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