Diff markup
1 #ifndef B43_H_ 1 #ifndef B43_H_
2 #define B43_H_ 2 #define B43_H_
3 3
4 #include <linux/kernel.h> 4 #include <linux/kernel.h>
5 #include <linux/spinlock.h> 5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h> 6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h> 7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h> 8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h> 9 #include <net/mac80211.h>
10 10
11 #include "debugfs.h" 11 #include "debugfs.h"
12 #include "leds.h" 12 #include "leds.h"
13 #include "rfkill.h" 13 #include "rfkill.h"
14 #include "lo.h" 14 #include "lo.h"
15 #include "phy.h" !! 15 #include "phy_common.h"
16 16
17 17
18 /* The unique identifier of the firmware that' 18 /* The unique identifier of the firmware that's officially supported by
19 * this driver version. */ 19 * this driver version. */
20 #define B43_SUPPORTED_FIRMWARE_ID "FW13" 20 #define B43_SUPPORTED_FIRMWARE_ID "FW13"
21 21
22 22
23 #ifdef CONFIG_B43_DEBUG 23 #ifdef CONFIG_B43_DEBUG
24 # define B43_DEBUG 1 24 # define B43_DEBUG 1
25 #else 25 #else
26 # define B43_DEBUG 0 26 # define B43_DEBUG 0
27 #endif 27 #endif
28 28
29 #define B43_RX_MAX_SSI 60 29 #define B43_RX_MAX_SSI 60
30 30
31 /* MMIO offsets */ 31 /* MMIO offsets */
32 #define B43_MMIO_DMA0_REASON 0x20 32 #define B43_MMIO_DMA0_REASON 0x20
33 #define B43_MMIO_DMA0_IRQ_MASK 0x24 33 #define B43_MMIO_DMA0_IRQ_MASK 0x24
34 #define B43_MMIO_DMA1_REASON 0x28 34 #define B43_MMIO_DMA1_REASON 0x28
35 #define B43_MMIO_DMA1_IRQ_MASK 0x2C 35 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
36 #define B43_MMIO_DMA2_REASON 0x30 36 #define B43_MMIO_DMA2_REASON 0x30
37 #define B43_MMIO_DMA2_IRQ_MASK 0x34 37 #define B43_MMIO_DMA2_IRQ_MASK 0x34
38 #define B43_MMIO_DMA3_REASON 0x38 38 #define B43_MMIO_DMA3_REASON 0x38
39 #define B43_MMIO_DMA3_IRQ_MASK 0x3C 39 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
40 #define B43_MMIO_DMA4_REASON 0x40 40 #define B43_MMIO_DMA4_REASON 0x40
41 #define B43_MMIO_DMA4_IRQ_MASK 0x44 41 #define B43_MMIO_DMA4_IRQ_MASK 0x44
42 #define B43_MMIO_DMA5_REASON 0x48 42 #define B43_MMIO_DMA5_REASON 0x48
43 #define B43_MMIO_DMA5_IRQ_MASK 0x4C 43 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
44 #define B43_MMIO_MACCTL 0x120 44 #define B43_MMIO_MACCTL 0x120 /* MAC control */
45 #define B43_MMIO_MACCMD 0x124 45 #define B43_MMIO_MACCMD 0x124 /* MAC command */
46 #define B43_MMIO_GEN_IRQ_REASON 0x128 46 #define B43_MMIO_GEN_IRQ_REASON 0x128
47 #define B43_MMIO_GEN_IRQ_MASK 0x12C 47 #define B43_MMIO_GEN_IRQ_MASK 0x12C
48 #define B43_MMIO_RAM_CONTROL 0x130 48 #define B43_MMIO_RAM_CONTROL 0x130
49 #define B43_MMIO_RAM_DATA 0x134 49 #define B43_MMIO_RAM_DATA 0x134
50 #define B43_MMIO_PS_STATUS 0x140 50 #define B43_MMIO_PS_STATUS 0x140
51 #define B43_MMIO_RADIO_HWENABLED_HI 0x158 51 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
52 #define B43_MMIO_SHM_CONTROL 0x160 52 #define B43_MMIO_SHM_CONTROL 0x160
53 #define B43_MMIO_SHM_DATA 0x164 53 #define B43_MMIO_SHM_DATA 0x164
54 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166 54 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
55 #define B43_MMIO_XMITSTAT_0 0x170 55 #define B43_MMIO_XMITSTAT_0 0x170
56 #define B43_MMIO_XMITSTAT_1 0x174 56 #define B43_MMIO_XMITSTAT_1 0x174
57 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 57 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
58 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 58 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
59 #define B43_MMIO_TSF_CFP_REP 0x188 59 #define B43_MMIO_TSF_CFP_REP 0x188
60 #define B43_MMIO_TSF_CFP_START 0x18C 60 #define B43_MMIO_TSF_CFP_START 0x18C
61 #define B43_MMIO_TSF_CFP_MAXDUR 0x190 61 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
62 62
63 /* 32-bit DMA */ 63 /* 32-bit DMA */
64 #define B43_MMIO_DMA32_BASE0 0x200 64 #define B43_MMIO_DMA32_BASE0 0x200
65 #define B43_MMIO_DMA32_BASE1 0x220 65 #define B43_MMIO_DMA32_BASE1 0x220
66 #define B43_MMIO_DMA32_BASE2 0x240 66 #define B43_MMIO_DMA32_BASE2 0x240
67 #define B43_MMIO_DMA32_BASE3 0x260 67 #define B43_MMIO_DMA32_BASE3 0x260
68 #define B43_MMIO_DMA32_BASE4 0x280 68 #define B43_MMIO_DMA32_BASE4 0x280
69 #define B43_MMIO_DMA32_BASE5 0x2A0 69 #define B43_MMIO_DMA32_BASE5 0x2A0
70 /* 64-bit DMA */ 70 /* 64-bit DMA */
71 #define B43_MMIO_DMA64_BASE0 0x200 71 #define B43_MMIO_DMA64_BASE0 0x200
72 #define B43_MMIO_DMA64_BASE1 0x240 72 #define B43_MMIO_DMA64_BASE1 0x240
73 #define B43_MMIO_DMA64_BASE2 0x280 73 #define B43_MMIO_DMA64_BASE2 0x280
74 #define B43_MMIO_DMA64_BASE3 0x2C0 74 #define B43_MMIO_DMA64_BASE3 0x2C0
75 #define B43_MMIO_DMA64_BASE4 0x300 75 #define B43_MMIO_DMA64_BASE4 0x300
76 #define B43_MMIO_DMA64_BASE5 0x340 76 #define B43_MMIO_DMA64_BASE5 0x340
77 77
>> 78 /* PIO on core rev < 11 */
>> 79 #define B43_MMIO_PIO_BASE0 0x300
>> 80 #define B43_MMIO_PIO_BASE1 0x310
>> 81 #define B43_MMIO_PIO_BASE2 0x320
>> 82 #define B43_MMIO_PIO_BASE3 0x330
>> 83 #define B43_MMIO_PIO_BASE4 0x340
>> 84 #define B43_MMIO_PIO_BASE5 0x350
>> 85 #define B43_MMIO_PIO_BASE6 0x360
>> 86 #define B43_MMIO_PIO_BASE7 0x370
>> 87 /* PIO on core rev >= 11 */
>> 88 #define B43_MMIO_PIO11_BASE0 0x200
>> 89 #define B43_MMIO_PIO11_BASE1 0x240
>> 90 #define B43_MMIO_PIO11_BASE2 0x280
>> 91 #define B43_MMIO_PIO11_BASE3 0x2C0
>> 92 #define B43_MMIO_PIO11_BASE4 0x300
>> 93 #define B43_MMIO_PIO11_BASE5 0x340
>> 94
78 #define B43_MMIO_PHY_VER 0x3E0 95 #define B43_MMIO_PHY_VER 0x3E0
79 #define B43_MMIO_PHY_RADIO 0x3E2 96 #define B43_MMIO_PHY_RADIO 0x3E2
80 #define B43_MMIO_PHY0 0x3E6 97 #define B43_MMIO_PHY0 0x3E6
81 #define B43_MMIO_ANTENNA 0x3E8 98 #define B43_MMIO_ANTENNA 0x3E8
82 #define B43_MMIO_CHANNEL 0x3F0 99 #define B43_MMIO_CHANNEL 0x3F0
83 #define B43_MMIO_CHANNEL_EXT 0x3F4 100 #define B43_MMIO_CHANNEL_EXT 0x3F4
84 #define B43_MMIO_RADIO_CONTROL 0x3F6 101 #define B43_MMIO_RADIO_CONTROL 0x3F6
85 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8 102 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
86 #define B43_MMIO_RADIO_DATA_LOW 0x3FA 103 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
87 #define B43_MMIO_PHY_CONTROL 0x3FC 104 #define B43_MMIO_PHY_CONTROL 0x3FC
88 #define B43_MMIO_PHY_DATA 0x3FE 105 #define B43_MMIO_PHY_DATA 0x3FE
89 #define B43_MMIO_MACFILTER_CONTROL 0x420 106 #define B43_MMIO_MACFILTER_CONTROL 0x420
90 #define B43_MMIO_MACFILTER_DATA 0x422 107 #define B43_MMIO_MACFILTER_DATA 0x422
91 #define B43_MMIO_RCMTA_COUNT 0x43C 108 #define B43_MMIO_RCMTA_COUNT 0x43C
92 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A 109 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
93 #define B43_MMIO_GPIO_CONTROL 0x49C 110 #define B43_MMIO_GPIO_CONTROL 0x49C
94 #define B43_MMIO_GPIO_MASK 0x49E 111 #define B43_MMIO_GPIO_MASK 0x49E
95 #define B43_MMIO_TSF_CFP_START_LOW 0x604 112 #define B43_MMIO_TSF_CFP_START_LOW 0x604
96 #define B43_MMIO_TSF_CFP_START_HIGH 0x606 113 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
>> 114 #define B43_MMIO_TSF_CFP_PRETBTT 0x612
97 #define B43_MMIO_TSF_0 0x632 115 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
98 #define B43_MMIO_TSF_1 0x634 116 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
99 #define B43_MMIO_TSF_2 0x636 117 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
100 #define B43_MMIO_TSF_3 0x638 118 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
101 #define B43_MMIO_RNG 0x65A 119 #define B43_MMIO_RNG 0x65A
>> 120 #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */
>> 121 #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
>> 122 #define B43_MMIO_IFSCTL_USE_EDCF 0x0004
102 #define B43_MMIO_POWERUP_DELAY 0x6A8 123 #define B43_MMIO_POWERUP_DELAY 0x6A8
>> 124 #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */
>> 125 #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */
>> 126 #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */
103 127
104 /* SPROM boardflags_lo values */ 128 /* SPROM boardflags_lo values */
105 #define B43_BFL_BTCOEXIST 0x0001 129 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
106 #define B43_BFL_PACTRL 0x0002 130 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
107 #define B43_BFL_AIRLINEMODE 0x0004 131 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
108 #define B43_BFL_RSSI 0x0008 132 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
109 #define B43_BFL_ENETSPI 0x0010 133 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
110 #define B43_BFL_XTAL_NOSLOW 0x0020 134 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
111 #define B43_BFL_CCKHIPWR 0x0040 135 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
112 #define B43_BFL_ENETADM 0x0080 136 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
113 #define B43_BFL_ENETVLAN 0x0100 137 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
114 #define B43_BFL_AFTERBURNER 0x0200 138 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
115 #define B43_BFL_NOPCI 0x0400 139 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
116 #define B43_BFL_FEM 0x0800 140 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
117 #define B43_BFL_EXTLNA 0x1000 141 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
118 #define B43_BFL_HGPA 0x2000 142 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
119 #define B43_BFL_BTCMOD 0x4000 143 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
120 #define B43_BFL_ALTIQ 0x8000 144 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
121 145
122 /* GPIO register offset, in both ChipCommon an 146 /* GPIO register offset, in both ChipCommon and PCI core. */
123 #define B43_GPIO_CONTROL 0x6c 147 #define B43_GPIO_CONTROL 0x6c
124 148
125 /* SHM Routing */ 149 /* SHM Routing */
126 enum { 150 enum {
127 B43_SHM_UCODE, /* Microcode m 151 B43_SHM_UCODE, /* Microcode memory */
128 B43_SHM_SHARED, /* Shared memo 152 B43_SHM_SHARED, /* Shared memory */
129 B43_SHM_SCRATCH, /* Scratch mem 153 B43_SHM_SCRATCH, /* Scratch memory */
130 B43_SHM_HW, /* Internal ha 154 B43_SHM_HW, /* Internal hardware register */
131 B43_SHM_RCMTA, /* Receive mat 155 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
132 }; 156 };
133 /* SHM Routing modifiers */ 157 /* SHM Routing modifiers */
134 #define B43_SHM_AUTOINC_R 0x0200 158 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
135 #define B43_SHM_AUTOINC_W 0x0100 159 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
136 #define B43_SHM_AUTOINC_RW (B43_S 160 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
137 B43_S 161 B43_SHM_AUTOINC_W)
138 162
139 /* Misc SHM_SHARED offsets */ 163 /* Misc SHM_SHARED offsets */
140 #define B43_SHM_SH_WLCOREREV 0x0016 164 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
141 #define B43_SHM_SH_PCTLWDPOS 0x0008 165 #define B43_SHM_SH_PCTLWDPOS 0x0008
142 #define B43_SHM_SH_RXPADOFF 0x0034 166 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
>> 167 #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */
143 #define B43_SHM_SH_PHYVER 0x0050 168 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
144 #define B43_SHM_SH_PHYTYPE 0x0052 169 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
145 #define B43_SHM_SH_ANTSWAP 0x005C 170 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
146 #define B43_SHM_SH_HOSTFLO 0x005E 171 #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
147 #define B43_SHM_SH_HOSTFHI 0x0060 !! 172 #define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */
>> 173 #define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */
148 #define B43_SHM_SH_RFATT 0x0064 174 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
149 #define B43_SHM_SH_RADAR 0x0066 175 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
150 #define B43_SHM_SH_PHYTXNOI 0x006E 176 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
151 #define B43_SHM_SH_RFRXSP1 0x0072 177 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
152 #define B43_SHM_SH_CHAN 0x00A0 178 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
153 #define B43_SHM_SH_CHAN_5GHZ 0x0100 179 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
154 #define B43_SHM_SH_BCMCFIFOID 0x0108 180 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
>> 181 /* TSSI information */
>> 182 #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
>> 183 #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */
>> 184 #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */
>> 185 #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */
155 /* SHM_SHARED TX FIFO variables */ 186 /* SHM_SHARED TX FIFO variables */
156 #define B43_SHM_SH_SIZE01 0x0098 187 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
157 #define B43_SHM_SH_SIZE23 0x009A 188 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
158 #define B43_SHM_SH_SIZE45 0x009C 189 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
159 #define B43_SHM_SH_SIZE67 0x009E 190 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
160 /* SHM_SHARED background noise */ 191 /* SHM_SHARED background noise */
161 #define B43_SHM_SH_JSSI0 0x0088 192 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
162 #define B43_SHM_SH_JSSI1 0x008A 193 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
163 #define B43_SHM_SH_JSSIAUX 0x008C 194 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
164 /* SHM_SHARED crypto engine */ 195 /* SHM_SHARED crypto engine */
165 #define B43_SHM_SH_DEFAULTIV 0x003C 196 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
166 #define B43_SHM_SH_NRRXTRANS 0x003E 197 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
167 #define B43_SHM_SH_KTP 0x0056 198 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
168 #define B43_SHM_SH_TKIPTSCTTAK 0x0318 199 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
169 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 200 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
170 #define B43_SHM_SH_PSM 0x05F4 201 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
171 /* SHM_SHARED WME variables */ 202 /* SHM_SHARED WME variables */
172 #define B43_SHM_SH_EDCFSTAT 0x000E 203 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
173 #define B43_SHM_SH_TXFCUR 0x0030 204 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
174 #define B43_SHM_SH_EDCFQ 0x0240 205 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
175 /* SHM_SHARED powersave mode related */ 206 /* SHM_SHARED powersave mode related */
176 #define B43_SHM_SH_SLOTT 0x0010 207 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
177 #define B43_SHM_SH_DTIMPER 0x0012 208 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
178 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C 209 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
179 /* SHM_SHARED beacon/AP variables */ 210 /* SHM_SHARED beacon/AP variables */
180 #define B43_SHM_SH_BTL0 0x0018 211 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
181 #define B43_SHM_SH_BTL1 0x001A 212 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
182 #define B43_SHM_SH_BTSFOFF 0x001C 213 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
183 #define B43_SHM_SH_TIMBPOS 0x001E 214 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
184 #define B43_SHM_SH_DTIMP 0x0012 215 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
185 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 216 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
186 #define B43_SHM_SH_SFFBLIM 0x0044 217 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
187 #define B43_SHM_SH_LFFBLIM 0x0046 218 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
188 #define B43_SHM_SH_BEACPHYCTL 0x0054 219 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
189 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 220 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
190 /* SHM_SHARED ACK/CTS control */ 221 /* SHM_SHARED ACK/CTS control */
191 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 222 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
192 /* SHM_SHARED probe response variables */ 223 /* SHM_SHARED probe response variables */
193 #define B43_SHM_SH_PRSSID 0x0160 224 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
194 #define B43_SHM_SH_PRSSIDLEN 0x0048 225 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
195 #define B43_SHM_SH_PRTLEN 0x004A 226 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
196 #define B43_SHM_SH_PRMAXTIME 0x0074 227 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
197 #define B43_SHM_SH_PRPHYCTL 0x0188 228 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
198 /* SHM_SHARED rate tables */ 229 /* SHM_SHARED rate tables */
199 #define B43_SHM_SH_OFDMDIRECT 0x01C0 230 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
200 #define B43_SHM_SH_OFDMBASIC 0x01E0 231 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
201 #define B43_SHM_SH_CCKDIRECT 0x0200 232 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
202 #define B43_SHM_SH_CCKBASIC 0x0220 233 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
203 /* SHM_SHARED microcode soft registers */ 234 /* SHM_SHARED microcode soft registers */
204 #define B43_SHM_SH_UCODEREV 0x0000 235 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
205 #define B43_SHM_SH_UCODEPATCH 0x0002 236 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
206 #define B43_SHM_SH_UCODEDATE 0x0004 237 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
207 #define B43_SHM_SH_UCODETIME 0x0006 238 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
208 #define B43_SHM_SH_UCODESTAT 0x0040 239 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
209 #define B43_SHM_SH_UCODESTAT_INVALID 0 240 #define B43_SHM_SH_UCODESTAT_INVALID 0
210 #define B43_SHM_SH_UCODESTAT_INIT 1 241 #define B43_SHM_SH_UCODESTAT_INIT 1
211 #define B43_SHM_SH_UCODESTAT_ACTIVE 2 242 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
212 #define B43_SHM_SH_UCODESTAT_SUSP 3 243 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
213 #define B43_SHM_SH_UCODESTAT_SLEEP 4 244 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
214 #define B43_SHM_SH_MAXBFRAMES 0x0080 245 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
215 #define B43_SHM_SH_SPUWKUP 0x0094 246 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
216 #define B43_SHM_SH_PRETBTT 0x0096 247 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
217 248
218 /* SHM_SCRATCH offsets */ 249 /* SHM_SCRATCH offsets */
219 #define B43_SHM_SC_MINCONT 0x0003 250 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
220 #define B43_SHM_SC_MAXCONT 0x0004 251 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
221 #define B43_SHM_SC_CURCONT 0x0005 252 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
222 #define B43_SHM_SC_SRLIMIT 0x0006 253 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
223 #define B43_SHM_SC_LRLIMIT 0x0007 254 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
224 #define B43_SHM_SC_DTIMC 0x0008 255 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
225 #define B43_SHM_SC_BTL0LEN 0x0015 256 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
226 #define B43_SHM_SC_BTL1LEN 0x0016 257 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
227 #define B43_SHM_SC_SCFB 0x0017 258 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
228 #define B43_SHM_SC_LCFB 0x0018 259 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
229 260
230 /* Hardware Radio Enable masks */ 261 /* Hardware Radio Enable masks */
231 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 262 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
232 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 263 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
233 264
234 /* HostFlags. See b43_hf_read/write() */ 265 /* HostFlags. See b43_hf_read/write() */
235 #define B43_HF_ANTDIVHELP 0x0000 !! 266 #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */
236 #define B43_HF_SYMW 0x0000 !! 267 #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */
237 #define B43_HF_RXPULLW 0x0000 !! 268 #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */
238 #define B43_HF_CCKBOOST 0x0000 !! 269 #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
239 #define B43_HF_BTCOEX 0x0000 !! 270 #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */
240 #define B43_HF_GDCW 0x0000 !! 271 #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
241 #define B43_HF_OFDMPABOOST 0x0000 !! 272 #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */
242 #define B43_HF_ACPR 0x0000 !! 273 #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */
243 #define B43_HF_EDCF 0x0000 !! 274 #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */
244 #define B43_HF_TSSIRPSMW 0x0000 !! 275 #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */
245 #define B43_HF_DSCRQ 0x0000 !! 276 #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
246 #define B43_HF_ACIW 0x0000 !! 277 #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */
247 #define B43_HF_2060W 0x0000 !! 278 #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
248 #define B43_HF_RADARW 0x0000 !! 279 #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */
249 #define B43_HF_USEDEFKEYS 0x0000 !! 280 #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */
250 #define B43_HF_BT4PRIOCOEX 0x0001 !! 281 #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */
251 #define B43_HF_FWKUP 0x0002 !! 282 #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */
252 #define B43_HF_VCORECALC 0x0004 !! 283 #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */
253 #define B43_HF_PCISCW 0x0008 !! 284 #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */
254 #define B43_HF_4318TSSI 0x0020 !! 285 #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
255 #define B43_HF_FBCMCFIFO 0x0040 !! 286 #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */
256 #define B43_HF_HWPCTL 0x0080 !! 287 #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */
257 #define B43_HF_BTCOEXALT 0x0100 !! 288 #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
258 #define B43_HF_TXBTCHECK 0x0200 !! 289 #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */
259 #define B43_HF_SKCFPUP 0x0400 !! 290 #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */
>> 291 #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */
>> 292 #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */
>> 293 #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
>> 294 #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
>> 295 #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
>> 296 #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
>> 297 #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
>> 298 #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
>> 299 #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
>> 300 #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
>> 301
>> 302 /* Firmware capabilities field in SHM (Opensource firmware only) */
>> 303 #define B43_FWCAPA_HWCRYPTO 0x0001
>> 304 #define B43_FWCAPA_QOS 0x0002
260 305
261 /* MacFilter offsets. */ 306 /* MacFilter offsets. */
262 #define B43_MACFILTER_SELF 0x0000 307 #define B43_MACFILTER_SELF 0x0000
263 #define B43_MACFILTER_BSSID 0x0003 308 #define B43_MACFILTER_BSSID 0x0003
264 309
265 /* PowerControl */ 310 /* PowerControl */
266 #define B43_PCTL_IN 0xB0 311 #define B43_PCTL_IN 0xB0
267 #define B43_PCTL_OUT 0xB4 312 #define B43_PCTL_OUT 0xB4
268 #define B43_PCTL_OUTENABLE 0xB8 313 #define B43_PCTL_OUTENABLE 0xB8
269 #define B43_PCTL_XTAL_POWERUP 0x40 314 #define B43_PCTL_XTAL_POWERUP 0x40
270 #define B43_PCTL_PLL_POWERDOWN 0x80 315 #define B43_PCTL_PLL_POWERDOWN 0x80
271 316
272 /* PowerControl Clock Modes */ 317 /* PowerControl Clock Modes */
273 #define B43_PCTL_CLK_FAST 0x00 318 #define B43_PCTL_CLK_FAST 0x00
274 #define B43_PCTL_CLK_SLOW 0x01 319 #define B43_PCTL_CLK_SLOW 0x01
275 #define B43_PCTL_CLK_DYNAMIC 0x02 320 #define B43_PCTL_CLK_DYNAMIC 0x02
276 321
277 #define B43_PCTL_FORCE_SLOW 0x0800 322 #define B43_PCTL_FORCE_SLOW 0x0800
278 #define B43_PCTL_FORCE_PLL 0x1000 323 #define B43_PCTL_FORCE_PLL 0x1000
279 #define B43_PCTL_DYN_XTAL 0x2000 324 #define B43_PCTL_DYN_XTAL 0x2000
280 325
281 /* PHYVersioning */ 326 /* PHYVersioning */
282 #define B43_PHYTYPE_A 0x00 327 #define B43_PHYTYPE_A 0x00
283 #define B43_PHYTYPE_B 0x01 328 #define B43_PHYTYPE_B 0x01
284 #define B43_PHYTYPE_G 0x02 329 #define B43_PHYTYPE_G 0x02
285 #define B43_PHYTYPE_N 0x04 330 #define B43_PHYTYPE_N 0x04
286 #define B43_PHYTYPE_LP 0x05 331 #define B43_PHYTYPE_LP 0x05
287 332
288 /* PHYRegisters */ 333 /* PHYRegisters */
289 #define B43_PHY_ILT_A_CTRL 0x0072 334 #define B43_PHY_ILT_A_CTRL 0x0072
290 #define B43_PHY_ILT_A_DATA1 0x0073 335 #define B43_PHY_ILT_A_DATA1 0x0073
291 #define B43_PHY_ILT_A_DATA2 0x0074 336 #define B43_PHY_ILT_A_DATA2 0x0074
292 #define B43_PHY_G_LO_CONTROL 0x0810 337 #define B43_PHY_G_LO_CONTROL 0x0810
293 #define B43_PHY_ILT_G_CTRL 0x0472 338 #define B43_PHY_ILT_G_CTRL 0x0472
294 #define B43_PHY_ILT_G_DATA1 0x0473 339 #define B43_PHY_ILT_G_DATA1 0x0473
295 #define B43_PHY_ILT_G_DATA2 0x0474 340 #define B43_PHY_ILT_G_DATA2 0x0474
296 #define B43_PHY_A_PCTL 0x007B 341 #define B43_PHY_A_PCTL 0x007B
297 #define B43_PHY_G_PCTL 0x0029 342 #define B43_PHY_G_PCTL 0x0029
298 #define B43_PHY_A_CRS 0x0029 343 #define B43_PHY_A_CRS 0x0029
299 #define B43_PHY_RADIO_BITFIELD 0x0401 344 #define B43_PHY_RADIO_BITFIELD 0x0401
300 #define B43_PHY_G_CRS 0x0429 345 #define B43_PHY_G_CRS 0x0429
301 #define B43_PHY_NRSSILT_CTRL 0x0803 346 #define B43_PHY_NRSSILT_CTRL 0x0803
302 #define B43_PHY_NRSSILT_DATA 0x0804 347 #define B43_PHY_NRSSILT_DATA 0x0804
303 348
304 /* RadioRegisters */ 349 /* RadioRegisters */
305 #define B43_RADIOCTL_ID 0x01 350 #define B43_RADIOCTL_ID 0x01
306 351
307 /* MAC Control bitfield */ 352 /* MAC Control bitfield */
308 #define B43_MACCTL_ENABLED 0x0000 353 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
309 #define B43_MACCTL_PSM_RUN 0x0000 354 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
310 #define B43_MACCTL_PSM_JMP0 0x0000 355 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
311 #define B43_MACCTL_SHM_ENABLED 0x0000 356 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
312 #define B43_MACCTL_SHM_UPPER 0x0000 357 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
313 #define B43_MACCTL_IHR_ENABLED 0x0000 358 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
314 #define B43_MACCTL_PSM_DBG 0x0000 359 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
315 #define B43_MACCTL_GPOUTSMSK 0x0000 360 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
316 #define B43_MACCTL_BE 0x0001 361 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
317 #define B43_MACCTL_INFRA 0x0002 362 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
318 #define B43_MACCTL_AP 0x0004 363 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
319 #define B43_MACCTL_RADIOLOCK 0x0008 364 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
320 #define B43_MACCTL_BEACPROMISC 0x0010 365 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
321 #define B43_MACCTL_KEEP_BADPLCP 0x0020 366 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
322 #define B43_MACCTL_KEEP_CTL 0x0040 367 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
323 #define B43_MACCTL_KEEP_BAD 0x0080 368 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
324 #define B43_MACCTL_PROMISC 0x0100 369 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
325 #define B43_MACCTL_HWPS 0x0200 370 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
326 #define B43_MACCTL_AWAKE 0x0400 371 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
327 #define B43_MACCTL_CLOSEDNET 0x0800 372 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
328 #define B43_MACCTL_TBTTHOLD 0x1000 373 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
329 #define B43_MACCTL_DISCTXSTAT 0x2000 374 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
330 #define B43_MACCTL_DISCPMQ 0x4000 375 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
331 #define B43_MACCTL_GMODE 0x8000 376 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
332 377
333 /* MAC Command bitfield */ 378 /* MAC Command bitfield */
334 #define B43_MACCMD_BEACON0_VALID 0x0000 379 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
335 #define B43_MACCMD_BEACON1_VALID 0x0000 380 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
336 #define B43_MACCMD_DFQ_VALID 0x0000 381 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
337 #define B43_MACCMD_CCA 0x0000 382 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
338 #define B43_MACCMD_BGNOISE 0x0000 383 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
339 384
340 /* 802.11 core specific TM State Low (SSB_TMSL 385 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
341 #define B43_TMSLOW_GMODE 0x2000 386 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
342 #define B43_TMSLOW_PHYCLKSPEED 0x00C0 387 #define B43_TMSLOW_PHYCLKSPEED 0x00C00000 /* PHY clock speed mask (N-PHY only) */
343 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x0000 388 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000 /* 40 MHz PHY */
344 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x0040 389 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000 /* 80 MHz PHY */
345 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x0080 390 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000 /* 160 MHz PHY */
346 #define B43_TMSLOW_PLLREFSEL 0x0020 391 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
347 #define B43_TMSLOW_MACPHYCLKEN 0x0010 392 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
348 #define B43_TMSLOW_PHYRESET 0x0008 393 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
349 #define B43_TMSLOW_PHYCLKEN 0x0004 394 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
350 395
351 /* 802.11 core specific TM State High (SSB_TMS 396 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
352 #define B43_TMSHIGH_DUALBAND_PHY 0x0008 397 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
353 #define B43_TMSHIGH_FCLOCK 0x0004 398 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
354 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x0002 399 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
355 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x0001 400 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
356 401
357 /* Generic-Interrupt reasons. */ 402 /* Generic-Interrupt reasons. */
358 #define B43_IRQ_MAC_SUSPENDED 0x0000 403 #define B43_IRQ_MAC_SUSPENDED 0x00000001
359 #define B43_IRQ_BEACON 0x0000 404 #define B43_IRQ_BEACON 0x00000002
360 #define B43_IRQ_TBTT_INDI 0x0000 405 #define B43_IRQ_TBTT_INDI 0x00000004
361 #define B43_IRQ_BEACON_TX_OK 0x0000 406 #define B43_IRQ_BEACON_TX_OK 0x00000008
362 #define B43_IRQ_BEACON_CANCEL 0x0000 407 #define B43_IRQ_BEACON_CANCEL 0x00000010
363 #define B43_IRQ_ATIM_END 0x0000 408 #define B43_IRQ_ATIM_END 0x00000020
364 #define B43_IRQ_PMQ 0x0000 409 #define B43_IRQ_PMQ 0x00000040
365 #define B43_IRQ_PIO_WORKAROUND 0x0000 410 #define B43_IRQ_PIO_WORKAROUND 0x00000100
366 #define B43_IRQ_MAC_TXERR 0x0000 411 #define B43_IRQ_MAC_TXERR 0x00000200
367 #define B43_IRQ_PHY_TXERR 0x0000 412 #define B43_IRQ_PHY_TXERR 0x00000800
368 #define B43_IRQ_PMEVENT 0x0000 413 #define B43_IRQ_PMEVENT 0x00001000
369 #define B43_IRQ_TIMER0 0x0000 414 #define B43_IRQ_TIMER0 0x00002000
370 #define B43_IRQ_TIMER1 0x0000 415 #define B43_IRQ_TIMER1 0x00004000
371 #define B43_IRQ_DMA 0x0000 416 #define B43_IRQ_DMA 0x00008000
372 #define B43_IRQ_TXFIFO_FLUSH_OK 0x0001 417 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
373 #define B43_IRQ_CCA_MEASURE_OK 0x0002 418 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
374 #define B43_IRQ_NOISESAMPLE_OK 0x0004 419 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
375 #define B43_IRQ_UCODE_DEBUG 0x0800 420 #define B43_IRQ_UCODE_DEBUG 0x08000000
376 #define B43_IRQ_RFKILL 0x1000 421 #define B43_IRQ_RFKILL 0x10000000
377 #define B43_IRQ_TX_OK 0x2000 422 #define B43_IRQ_TX_OK 0x20000000
378 #define B43_IRQ_PHY_G_CHANGED 0x4000 423 #define B43_IRQ_PHY_G_CHANGED 0x40000000
379 #define B43_IRQ_TIMEOUT 0x8000 424 #define B43_IRQ_TIMEOUT 0x80000000
380 425
381 #define B43_IRQ_ALL 0xFFFF 426 #define B43_IRQ_ALL 0xFFFFFFFF
382 #define B43_IRQ_MASKTEMPLATE (B43_I !! 427 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
383 B43_I <<
384 B43_I <<
385 B43_I 428 B43_IRQ_ATIM_END | \
386 B43_I 429 B43_IRQ_PMQ | \
387 B43_I 430 B43_IRQ_MAC_TXERR | \
388 B43_I 431 B43_IRQ_PHY_TXERR | \
389 B43_I 432 B43_IRQ_DMA | \
390 B43_I 433 B43_IRQ_TXFIFO_FLUSH_OK | \
391 B43_I 434 B43_IRQ_NOISESAMPLE_OK | \
392 B43_I 435 B43_IRQ_UCODE_DEBUG | \
393 B43_I 436 B43_IRQ_RFKILL | \
394 B43_I 437 B43_IRQ_TX_OK)
395 438
>> 439 /* The firmware register to fetch the debug-IRQ reason from. */
>> 440 #define B43_DEBUGIRQ_REASON_REG 63
>> 441 /* Debug-IRQ reasons. */
>> 442 #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
>> 443 #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
>> 444 #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
>> 445 #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
>> 446 #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
>> 447
>> 448 /* The firmware register that contains the "marker" line. */
>> 449 #define B43_MARKER_ID_REG 2
>> 450 #define B43_MARKER_LINE_REG 3
>> 451
>> 452 /* The firmware register to fetch the panic reason from. */
>> 453 #define B43_FWPANIC_REASON_REG 3
>> 454 /* Firmware panic reason codes */
>> 455 #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
>> 456 #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
>> 457
>> 458 /* The firmware register that contains the watchdog counter. */
>> 459 #define B43_WATCHDOG_REG 1
>> 460
396 /* Device specific rate values. 461 /* Device specific rate values.
397 * The actual values defined here are (rate_in 462 * The actual values defined here are (rate_in_mbps * 2).
398 * Some code depends on this. Don't change it. 463 * Some code depends on this. Don't change it. */
399 #define B43_CCK_RATE_1MB 0x02 464 #define B43_CCK_RATE_1MB 0x02
400 #define B43_CCK_RATE_2MB 0x04 465 #define B43_CCK_RATE_2MB 0x04
401 #define B43_CCK_RATE_5MB 0x0B 466 #define B43_CCK_RATE_5MB 0x0B
402 #define B43_CCK_RATE_11MB 0x16 467 #define B43_CCK_RATE_11MB 0x16
403 #define B43_OFDM_RATE_6MB 0x0C 468 #define B43_OFDM_RATE_6MB 0x0C
404 #define B43_OFDM_RATE_9MB 0x12 469 #define B43_OFDM_RATE_9MB 0x12
405 #define B43_OFDM_RATE_12MB 0x18 470 #define B43_OFDM_RATE_12MB 0x18
406 #define B43_OFDM_RATE_18MB 0x24 471 #define B43_OFDM_RATE_18MB 0x24
407 #define B43_OFDM_RATE_24MB 0x30 472 #define B43_OFDM_RATE_24MB 0x30
408 #define B43_OFDM_RATE_36MB 0x48 473 #define B43_OFDM_RATE_36MB 0x48
409 #define B43_OFDM_RATE_48MB 0x60 474 #define B43_OFDM_RATE_48MB 0x60
410 #define B43_OFDM_RATE_54MB 0x6C 475 #define B43_OFDM_RATE_54MB 0x6C
411 /* Convert a b43 rate value to a rate in 100kb 476 /* Convert a b43 rate value to a rate in 100kbps */
412 #define B43_RATE_TO_BASE100KBPS(rate) (((rat 477 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
413 478
414 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7 479 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
415 #define B43_DEFAULT_LONG_RETRY_LIMIT 4 480 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
416 481
417 #define B43_PHY_TX_BADNESS_LIMIT 1000 482 #define B43_PHY_TX_BADNESS_LIMIT 1000
418 483
419 /* Max size of a security key */ 484 /* Max size of a security key */
420 #define B43_SEC_KEYSIZE 16 485 #define B43_SEC_KEYSIZE 16
421 /* Security algorithms. */ 486 /* Security algorithms. */
422 enum { 487 enum {
423 B43_SEC_ALGO_NONE = 0, /* unencrypted 488 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
424 B43_SEC_ALGO_WEP40, 489 B43_SEC_ALGO_WEP40,
425 B43_SEC_ALGO_TKIP, 490 B43_SEC_ALGO_TKIP,
426 B43_SEC_ALGO_AES, 491 B43_SEC_ALGO_AES,
427 B43_SEC_ALGO_WEP104, 492 B43_SEC_ALGO_WEP104,
428 B43_SEC_ALGO_AES_LEGACY, 493 B43_SEC_ALGO_AES_LEGACY,
429 }; 494 };
430 495
431 struct b43_dmaring; 496 struct b43_dmaring;
432 struct b43_pioqueue; <<
433 497
434 /* The firmware file header */ 498 /* The firmware file header */
435 #define B43_FW_TYPE_UCODE 'u' 499 #define B43_FW_TYPE_UCODE 'u'
436 #define B43_FW_TYPE_PCM 'p' 500 #define B43_FW_TYPE_PCM 'p'
437 #define B43_FW_TYPE_IV 'i' 501 #define B43_FW_TYPE_IV 'i'
438 struct b43_fw_header { 502 struct b43_fw_header {
439 /* File type */ 503 /* File type */
440 u8 type; 504 u8 type;
441 /* File format version */ 505 /* File format version */
442 u8 ver; 506 u8 ver;
443 u8 __padding[2]; 507 u8 __padding[2];
444 /* Size of the data. For ucode and PCM 508 /* Size of the data. For ucode and PCM this is in bytes.
445 * For IV this is number-of-ivs. */ 509 * For IV this is number-of-ivs. */
446 __be32 size; 510 __be32 size;
447 } __attribute__((__packed__)); 511 } __attribute__((__packed__));
448 512
449 /* Initial Value file format */ 513 /* Initial Value file format */
450 #define B43_IV_OFFSET_MASK 0x7FFF 514 #define B43_IV_OFFSET_MASK 0x7FFF
451 #define B43_IV_32BIT 0x8000 515 #define B43_IV_32BIT 0x8000
452 struct b43_iv { 516 struct b43_iv {
453 __be16 offset_size; 517 __be16 offset_size;
454 union { 518 union {
455 __be16 d16; 519 __be16 d16;
456 __be32 d32; 520 __be32 d32;
457 } data __attribute__((__packed__)); 521 } data __attribute__((__packed__));
458 } __attribute__((__packed__)); 522 } __attribute__((__packed__));
459 523
460 524
461 #define B43_PHYMODE(phytype) (1 << <<
462 #define B43_PHYMODE_A B43_PH <<
463 #define B43_PHYMODE_B B43_PH <<
464 #define B43_PHYMODE_G B43_PH <<
465 <<
466 struct b43_phy { <<
467 /* Possible PHYMODEs on this PHY */ <<
468 u8 possible_phymodes; <<
469 /* GMODE bit enabled? */ <<
470 bool gmode; <<
471 /* Possible ieee80211 subsystem hwmode <<
472 * Which mode is selected, depends on <<
473 #define B43_MAX_PHYHWMODES 2 <<
474 struct ieee80211_hw_mode hwmodes[B43_M <<
475 <<
476 /* Analog Type */ <<
477 u8 analog; <<
478 /* B43_PHYTYPE_ */ <<
479 u8 type; <<
480 /* PHY revision number. */ <<
481 u8 rev; <<
482 <<
483 /* Radio versioning */ <<
484 u16 radio_manuf; /* Radio manuf <<
485 u16 radio_ver; /* Radio versi <<
486 u8 radio_rev; /* Radio revis <<
487 <<
488 bool dyn_tssi_tbl; /* tssi2dbm is <<
489 <<
490 /* ACI (adjacent channel interference) <<
491 bool aci_enable; <<
492 bool aci_wlan_automatic; <<
493 bool aci_hw_rssi; <<
494 <<
495 /* Radio switched on/off */ <<
496 bool radio_on; <<
497 struct { <<
498 /* Values saved when turning t <<
499 * They are needed when turnin <<
500 bool valid; <<
501 u16 rfover; <<
502 u16 rfoverval; <<
503 } radio_off_context; <<
504 <<
505 u16 minlowsig[2]; <<
506 u16 minlowsigpos[2]; <<
507 <<
508 /* TSSI to dBm table in use */ <<
509 const s8 *tssi2dbm; <<
510 /* Target idle TSSI */ <<
511 int tgt_idle_tssi; <<
512 /* Current idle TSSI */ <<
513 int cur_idle_tssi; <<
514 <<
515 /* LocalOscillator control values. */ <<
516 struct b43_txpower_lo_control *lo_cont <<
517 /* Values from b43_calc_loopback_gain( <<
518 s16 max_lb_gain; /* Maximum Loo <<
519 s16 trsw_rx_gain; /* TRSW RX gai <<
520 s16 lna_lod_gain; /* LNA lod */ <<
521 s16 lna_gain; /* LNA */ <<
522 s16 pga_gain; /* PGA */ <<
523 <<
524 /* Desired TX power level (in dBm). <<
525 * This is set by the user and adjuste <<
526 u8 power_level; <<
527 /* A-PHY TX Power control value. */ <<
528 u16 txpwr_offset; <<
529 <<
530 /* Current TX power level attenuation <<
531 struct b43_bbatt bbatt; <<
532 struct b43_rfatt rfatt; <<
533 u8 tx_control; /* B43_TXCTL_X <<
534 <<
535 /* Hardware Power Control enabled? */ <<
536 bool hardware_power_control; <<
537 <<
538 /* Current Interference Mitigation mod <<
539 int interfmode; <<
540 /* Stack of saved values from the Inte <<
541 * Each value in the stack is layed ou <<
542 * bit 0-11: offset <<
543 * bit 12-15: register ID <<
544 * bit 16-32: value <<
545 * register ID is: 0x1 PHY, 0x2 Radio, <<
546 */ <<
547 #define B43_INTERFSTACK_SIZE 26 <<
548 u32 interfstack[B43_INTERFSTACK_SIZE]; <<
549 <<
550 /* Saved values from the NRSSI Slope c <<
551 s16 nrssi[2]; <<
552 s32 nrssislope; <<
553 /* In memory nrssi lookup table. */ <<
554 s8 nrssi_lt[64]; <<
555 <<
556 /* current channel */ <<
557 u8 channel; <<
558 <<
559 u16 lofcal; <<
560 <<
561 u16 initval; //FIXME rename <<
562 <<
563 /* PHY TX errors counter. */ <<
564 atomic_t txerr_cnt; <<
565 <<
566 /* The device does address auto increm <<
567 * We cache the previously used addres <<
568 * write on the next table access, if <<
569 u16 ofdmtab_addr; /* The address curre <<
570 enum { /* The last data flow direction <<
571 B43_OFDMTAB_DIRECTION_UNKNOWN <<
572 B43_OFDMTAB_DIRECTION_READ, <<
573 B43_OFDMTAB_DIRECTION_WRITE, <<
574 } ofdmtab_addr_direction; <<
575 <<
576 #if B43_DEBUG <<
577 /* Manual TX-power control enabled? */ <<
578 bool manual_txpower_control; <<
579 /* PHY registers locked by b43_phy_loc <<
580 bool phy_locked; <<
581 #endif /* B43_DEBUG */ <<
582 }; <<
583 <<
584 /* Data structures for DMA transmission, per 8 525 /* Data structures for DMA transmission, per 80211 core. */
585 struct b43_dma { 526 struct b43_dma {
586 struct b43_dmaring *tx_ring0; !! 527 struct b43_dmaring *tx_ring_AC_BK; /* Background */
587 struct b43_dmaring *tx_ring1; !! 528 struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
588 struct b43_dmaring *tx_ring2; !! 529 struct b43_dmaring *tx_ring_AC_VI; /* Video */
589 struct b43_dmaring *tx_ring3; !! 530 struct b43_dmaring *tx_ring_AC_VO; /* Voice */
590 struct b43_dmaring *tx_ring4; !! 531 struct b43_dmaring *tx_ring_mcast; /* Multicast */
591 struct b43_dmaring *tx_ring5; !! 532
>> 533 struct b43_dmaring *rx_ring;
>> 534 };
>> 535
>> 536 struct b43_pio_txqueue;
>> 537 struct b43_pio_rxqueue;
>> 538
>> 539 /* Data structures for PIO transmission, per 80211 core. */
>> 540 struct b43_pio {
>> 541 struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
>> 542 struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
>> 543 struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
>> 544 struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
>> 545 struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
592 546
593 struct b43_dmaring *rx_ring0; !! 547 struct b43_pio_rxqueue *rx_queue;
594 struct b43_dmaring *rx_ring3; /* onl <<
595 }; 548 };
596 549
597 /* Context information for a noise calculation 550 /* Context information for a noise calculation (Link Quality). */
598 struct b43_noise_calculation { 551 struct b43_noise_calculation {
599 u8 channel_at_start; <<
600 bool calculation_running; 552 bool calculation_running;
601 u8 nr_samples; 553 u8 nr_samples;
602 s8 samples[8][4]; 554 s8 samples[8][4];
603 }; 555 };
604 556
605 struct b43_stats { 557 struct b43_stats {
606 u8 link_noise; 558 u8 link_noise;
607 /* Store the last TX/RX times here for <<
608 unsigned long last_tx; <<
609 unsigned long last_rx; <<
610 }; 559 };
611 560
612 struct b43_key { 561 struct b43_key {
613 /* If keyconf is NULL, this key is dis 562 /* If keyconf is NULL, this key is disabled.
614 * keyconf is a cookie. Don't derefenr 563 * keyconf is a cookie. Don't derefenrence it outside of the set_key
615 * path, because b43 doesn't own it. * 564 * path, because b43 doesn't own it. */
616 struct ieee80211_key_conf *keyconf; 565 struct ieee80211_key_conf *keyconf;
617 u8 algorithm; 566 u8 algorithm;
618 }; 567 };
619 568
>> 569 /* SHM offsets to the QOS data structures for the 4 different queues. */
>> 570 #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
>> 571 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
>> 572 #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
>> 573 #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
>> 574 #define B43_QOS_VIDEO B43_QOS_PARAMS(2)
>> 575 #define B43_QOS_VOICE B43_QOS_PARAMS(3)
>> 576
>> 577 /* QOS parameter hardware data structure offsets. */
>> 578 #define B43_NR_QOSPARAMS 16
>> 579 enum {
>> 580 B43_QOSPARAM_TXOP = 0,
>> 581 B43_QOSPARAM_CWMIN,
>> 582 B43_QOSPARAM_CWMAX,
>> 583 B43_QOSPARAM_CWCUR,
>> 584 B43_QOSPARAM_AIFS,
>> 585 B43_QOSPARAM_BSLOTS,
>> 586 B43_QOSPARAM_REGGAP,
>> 587 B43_QOSPARAM_STATUS,
>> 588 };
>> 589
>> 590 /* QOS parameters for a queue. */
>> 591 struct b43_qos_params {
>> 592 /* The QOS parameters */
>> 593 struct ieee80211_tx_queue_params p;
>> 594 };
>> 595
620 struct b43_wldev; 596 struct b43_wldev;
621 597
622 /* Data structure for the WLAN parts (802.11 c 598 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
623 struct b43_wl { 599 struct b43_wl {
624 /* Pointer to the active wireless devi 600 /* Pointer to the active wireless device on this chip */
625 struct b43_wldev *current_dev; 601 struct b43_wldev *current_dev;
626 /* Pointer to the ieee80211 hardware d 602 /* Pointer to the ieee80211 hardware data structure */
627 struct ieee80211_hw *hw; 603 struct ieee80211_hw *hw;
628 604
>> 605 /* The number of queues that were registered with the mac80211 subsystem
>> 606 * initially. This is a backup copy of hw->queues in case hw->queues has
>> 607 * to be dynamically lowered at runtime (Firmware does not support QoS).
>> 608 * hw->queues has to be restored to the original value before unregistering
>> 609 * from the mac80211 subsystem. */
>> 610 u16 mac80211_initially_registered_queues;
>> 611
629 struct mutex mutex; 612 struct mutex mutex;
630 spinlock_t irq_lock; 613 spinlock_t irq_lock;
>> 614 /* R/W lock for data transmission.
>> 615 * Transmissions on 2+ queues can run concurrently, but somebody else
>> 616 * might sync with TX by write_lock_irqsave()'ing. */
>> 617 rwlock_t tx_lock;
631 /* Lock for LEDs access. */ 618 /* Lock for LEDs access. */
632 spinlock_t leds_lock; 619 spinlock_t leds_lock;
633 /* Lock for SHM access. */ 620 /* Lock for SHM access. */
634 spinlock_t shm_lock; 621 spinlock_t shm_lock;
635 622
636 /* We can only have one operating inte 623 /* We can only have one operating interface (802.11 core)
637 * at a time. General information abou 624 * at a time. General information about this interface follows.
638 */ 625 */
639 626
640 struct ieee80211_vif *vif; 627 struct ieee80211_vif *vif;
641 /* The MAC address of the operating in 628 /* The MAC address of the operating interface. */
642 u8 mac_addr[ETH_ALEN]; 629 u8 mac_addr[ETH_ALEN];
643 /* Current BSSID */ 630 /* Current BSSID */
644 u8 bssid[ETH_ALEN]; 631 u8 bssid[ETH_ALEN];
645 /* Interface type. (IEEE80211_IF_TYPE_ 632 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
646 int if_type; 633 int if_type;
647 /* Is the card operating in AP, STA or 634 /* Is the card operating in AP, STA or IBSS mode? */
648 bool operating; 635 bool operating;
649 /* filter flags */ 636 /* filter flags */
650 unsigned int filter_flags; 637 unsigned int filter_flags;
651 /* Stats about the wireless interface 638 /* Stats about the wireless interface */
652 struct ieee80211_low_level_stats ieee_ 639 struct ieee80211_low_level_stats ieee_stats;
653 640
>> 641 #ifdef CONFIG_B43_HWRNG
654 struct hwrng rng; 642 struct hwrng rng;
655 u8 rng_initialized; !! 643 bool rng_initialized;
656 char rng_name[30 + 1]; 644 char rng_name[30 + 1];
657 !! 645 #endif /* CONFIG_B43_HWRNG */
658 /* The RF-kill button */ <<
659 struct b43_rfkill rfkill; <<
660 646
661 /* List of all wireless devices on thi 647 /* List of all wireless devices on this chip */
662 struct list_head devlist; 648 struct list_head devlist;
663 u8 nr_devs; 649 u8 nr_devs;
664 650
665 bool radiotap_enabled; 651 bool radiotap_enabled;
>> 652 bool radio_enabled;
666 653
667 /* The beacon we are currently using ( 654 /* The beacon we are currently using (AP or IBSS mode).
668 * This beacon stuff is protected by t 655 * This beacon stuff is protected by the irq_lock. */
669 struct sk_buff *current_beacon; 656 struct sk_buff *current_beacon;
670 bool beacon0_uploaded; 657 bool beacon0_uploaded;
671 bool beacon1_uploaded; 658 bool beacon1_uploaded;
>> 659 bool beacon_templates_virgin; /* Never wrote the templates? */
>> 660 struct work_struct beacon_update_trigger;
>> 661
>> 662 /* The current QOS parameters for the 4 queues. */
>> 663 struct b43_qos_params qos_params[4];
>> 664
>> 665 /* Work for adjustment of the transmission power.
>> 666 * This is scheduled when we determine that the actual TX output
>> 667 * power doesn't match what we want. */
>> 668 struct work_struct txpower_adjust_work;
>> 669 };
>> 670
>> 671 /* The type of the firmware file. */
>> 672 enum b43_firmware_file_type {
>> 673 B43_FWTYPE_PROPRIETARY,
>> 674 B43_FWTYPE_OPENSOURCE,
>> 675 B43_NR_FWTYPES,
>> 676 };
>> 677
>> 678 /* Context data for fetching firmware. */
>> 679 struct b43_request_fw_context {
>> 680 /* The device we are requesting the fw for. */
>> 681 struct b43_wldev *dev;
>> 682 /* The type of firmware to request. */
>> 683 enum b43_firmware_file_type req_type;
>> 684 /* Error messages for each firmware type. */
>> 685 char errors[B43_NR_FWTYPES][128];
>> 686 /* Temporary buffer for storing the firmware name. */
>> 687 char fwname[64];
>> 688 /* A fatal error occured while requesting. Firmware reqest
>> 689 * can not continue, as any other reqest will also fail. */
>> 690 int fatal_failure;
672 }; 691 };
673 692
674 /* In-memory representation of a cached microc 693 /* In-memory representation of a cached microcode file. */
675 struct b43_firmware_file { 694 struct b43_firmware_file {
676 const char *filename; 695 const char *filename;
677 const struct firmware *data; 696 const struct firmware *data;
>> 697 /* Type of the firmware file name. Note that this does only indicate
>> 698 * the type by the firmware name. NOT the file contents.
>> 699 * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource
>> 700 * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware
>> 701 * binary code, not just the filename.
>> 702 */
>> 703 enum b43_firmware_file_type type;
678 }; 704 };
679 705
680 /* Pointers to the firmware data and meta info 706 /* Pointers to the firmware data and meta information about it. */
681 struct b43_firmware { 707 struct b43_firmware {
682 /* Microcode */ 708 /* Microcode */
683 struct b43_firmware_file ucode; 709 struct b43_firmware_file ucode;
684 /* PCM code */ 710 /* PCM code */
685 struct b43_firmware_file pcm; 711 struct b43_firmware_file pcm;
686 /* Initial MMIO values for the firmwar 712 /* Initial MMIO values for the firmware */
687 struct b43_firmware_file initvals; 713 struct b43_firmware_file initvals;
688 /* Initial MMIO values for the firmwar 714 /* Initial MMIO values for the firmware, band-specific */
689 struct b43_firmware_file initvals_band 715 struct b43_firmware_file initvals_band;
690 716
691 /* Firmware revision */ 717 /* Firmware revision */
692 u16 rev; 718 u16 rev;
693 /* Firmware patchlevel */ 719 /* Firmware patchlevel */
694 u16 patch; 720 u16 patch;
>> 721
>> 722 /* Set to true, if we are using an opensource firmware.
>> 723 * Use this to check for proprietary vs opensource. */
>> 724 bool opensource;
>> 725 /* Set to true, if the core needs a PCM firmware, but
>> 726 * we failed to load one. This is always false for
>> 727 * core rev > 10, as these don't need PCM firmware. */
>> 728 bool pcm_request_failed;
695 }; 729 };
696 730
697 /* Device (802.11 core) initialization status. 731 /* Device (802.11 core) initialization status. */
698 enum { 732 enum {
699 B43_STAT_UNINIT = 0, /* Uninitializ 733 B43_STAT_UNINIT = 0, /* Uninitialized. */
700 B43_STAT_INITIALIZED = 1, /* Ini 734 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
701 B43_STAT_STARTED = 2, /* Up and runn 735 B43_STAT_STARTED = 2, /* Up and running. */
702 }; 736 };
703 #define b43_status(wldev) atomic 737 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
704 #define b43_set_status(wldev, stat) do { 738 #define b43_set_status(wldev, stat) do { \
705 atomic_set(&(wldev)->__init_st 739 atomic_set(&(wldev)->__init_status, (stat)); \
706 smp_wmb(); 740 smp_wmb(); \
707 } whil 741 } while (0)
708 742
709 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX 743 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX
710 * 744 *
711 * You should always acquire both, wl->mutex a 745 * You should always acquire both, wl->mutex and wl->irq_lock unless:
712 * - You don't need to acquire wl->irq_lock, i 746 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
713 * - You don't need to acquire wl->mutex in th 747 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
714 * and packet TX path (and _ONLY_ there.) 748 * and packet TX path (and _ONLY_ there.)
715 */ 749 */
716 750
717 /* Data structure for one wireless device (802 751 /* Data structure for one wireless device (802.11 core) */
718 struct b43_wldev { 752 struct b43_wldev {
719 struct ssb_device *dev; 753 struct ssb_device *dev;
720 struct b43_wl *wl; 754 struct b43_wl *wl;
721 755
722 /* The device initialization status. 756 /* The device initialization status.
723 * Use b43_status() to query. */ 757 * Use b43_status() to query. */
724 atomic_t __init_status; 758 atomic_t __init_status;
725 /* Saved init status for handling susp 759 /* Saved init status for handling suspend. */
726 int suspend_init_status; 760 int suspend_init_status;
727 761
728 bool bad_frames_preempt; /* Use 762 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
729 bool dfq_valid; /* Directed fr 763 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
730 bool short_preamble; /* TRUE, if sh <<
731 bool short_slot; /* TRUE, if sh <<
732 bool radio_hw_enable; /* saved state 764 bool radio_hw_enable; /* saved state of radio hardware enabled state */
733 bool suspend_in_progress; /* TRU 765 bool suspend_in_progress; /* TRUE, if we are in a suspend/resume cycle */
>> 766 bool qos_enabled; /* TRUE, if QoS is used. */
>> 767 bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */
734 768
735 /* PHY/Radio device. */ 769 /* PHY/Radio device. */
736 struct b43_phy phy; 770 struct b43_phy phy;
737 771
738 /* DMA engines. */ !! 772 union {
739 struct b43_dma dma; !! 773 /* DMA engines. */
>> 774 struct b43_dma dma;
>> 775 /* PIO engines. */
>> 776 struct b43_pio pio;
>> 777 };
>> 778 /* Use b43_using_pio_transfers() to check whether we are using
>> 779 * DMA or PIO data transfers. */
>> 780 bool __using_pio_transfers;
740 781
741 /* Various statistics about the physic 782 /* Various statistics about the physical device. */
742 struct b43_stats stats; 783 struct b43_stats stats;
743 784
744 /* The device LEDs. */ 785 /* The device LEDs. */
745 struct b43_led led_tx; 786 struct b43_led led_tx;
746 struct b43_led led_rx; 787 struct b43_led led_rx;
747 struct b43_led led_assoc; 788 struct b43_led led_assoc;
748 struct b43_led led_radio; 789 struct b43_led led_radio;
749 790
750 /* Reason code of the last interrupt. 791 /* Reason code of the last interrupt. */
751 u32 irq_reason; 792 u32 irq_reason;
752 u32 dma_reason[6]; 793 u32 dma_reason[6];
753 /* saved irq enable/disable state bitf !! 794 /* The currently active generic-interrupt mask. */
754 u32 irq_savedstate; !! 795 u32 irq_mask;
755 /* Link Quality calculation context. * 796 /* Link Quality calculation context. */
756 struct b43_noise_calculation noisecalc 797 struct b43_noise_calculation noisecalc;
757 /* if > 0 MAC is suspended. if == 0 MA 798 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
758 int mac_suspended; 799 int mac_suspended;
759 800
760 /* Interrupt Service Routine tasklet ( 801 /* Interrupt Service Routine tasklet (bottom-half) */
761 struct tasklet_struct isr_tasklet; 802 struct tasklet_struct isr_tasklet;
762 803
763 /* Periodic tasks */ 804 /* Periodic tasks */
764 struct delayed_work periodic_work; 805 struct delayed_work periodic_work;
765 unsigned int periodic_state; 806 unsigned int periodic_state;
766 807
767 struct work_struct restart_work; 808 struct work_struct restart_work;
768 809
769 /* encryption/decryption */ 810 /* encryption/decryption */
770 u16 ktp; /* Key table p 811 u16 ktp; /* Key table pointer */
771 u8 max_nr_keys; 812 u8 max_nr_keys;
772 struct b43_key key[58]; 813 struct b43_key key[58];
773 814
774 /* Firmware data */ 815 /* Firmware data */
775 struct b43_firmware fw; 816 struct b43_firmware fw;
776 817
777 /* Devicelist in struct b43_wl (all 80 818 /* Devicelist in struct b43_wl (all 802.11 cores) */
778 struct list_head list; 819 struct list_head list;
779 820
780 /* Debugging stuff follows. */ 821 /* Debugging stuff follows. */
781 #ifdef CONFIG_B43_DEBUG 822 #ifdef CONFIG_B43_DEBUG
782 struct b43_dfsentry *dfsentry; 823 struct b43_dfsentry *dfsentry;
783 #endif 824 #endif
784 }; 825 };
785 826
786 static inline struct b43_wl *hw_to_b43_wl(stru 827 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
787 { 828 {
788 return hw->priv; 829 return hw->priv;
789 } 830 }
790 831
791 static inline struct b43_wldev *dev_to_b43_wld 832 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
792 { 833 {
793 struct ssb_device *ssb_dev = dev_to_ss 834 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
794 return ssb_get_drvdata(ssb_dev); 835 return ssb_get_drvdata(ssb_dev);
795 } 836 }
796 837
797 /* Is the device operating in a specified mode 838 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
798 static inline int b43_is_mode(struct b43_wl *w 839 static inline int b43_is_mode(struct b43_wl *wl, int type)
799 { 840 {
800 return (wl->operating && wl->if_type = 841 return (wl->operating && wl->if_type == type);
801 } 842 }
802 843
>> 844 /**
>> 845 * b43_current_band - Returns the currently used band.
>> 846 * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
>> 847 */
>> 848 static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
>> 849 {
>> 850 return wl->hw->conf.channel->band;
>> 851 }
>> 852
803 static inline u16 b43_read16(struct b43_wldev 853 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
804 { 854 {
805 return ssb_read16(dev->dev, offset); 855 return ssb_read16(dev->dev, offset);
806 } 856 }
807 857
808 static inline void b43_write16(struct b43_wlde 858 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
809 { 859 {
810 ssb_write16(dev->dev, offset, value); 860 ssb_write16(dev->dev, offset, value);
811 } 861 }
812 862
813 static inline u32 b43_read32(struct b43_wldev 863 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
814 { 864 {
815 return ssb_read32(dev->dev, offset); 865 return ssb_read32(dev->dev, offset);
816 } 866 }
817 867
818 static inline void b43_write32(struct b43_wlde 868 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
819 { 869 {
820 ssb_write32(dev->dev, offset, value); 870 ssb_write32(dev->dev, offset, value);
821 } 871 }
822 872
>> 873 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
>> 874 {
>> 875 #ifdef CONFIG_B43_PIO
>> 876 return dev->__using_pio_transfers;
>> 877 #else
>> 878 return 0;
>> 879 #endif
>> 880 }
>> 881
>> 882 #ifdef CONFIG_B43_FORCE_PIO
>> 883 # define B43_FORCE_PIO 1
>> 884 #else
>> 885 # define B43_FORCE_PIO 0
>> 886 #endif
>> 887
>> 888
823 /* Message printing */ 889 /* Message printing */
824 void b43info(struct b43_wl *wl, const char *fm 890 void b43info(struct b43_wl *wl, const char *fmt, ...)
825 __attribute__ ((format(printf, 2, 3))); 891 __attribute__ ((format(printf, 2, 3)));
826 void b43err(struct b43_wl *wl, const char *fmt 892 void b43err(struct b43_wl *wl, const char *fmt, ...)
827 __attribute__ ((format(printf, 2, 3))); 893 __attribute__ ((format(printf, 2, 3)));
828 void b43warn(struct b43_wl *wl, const char *fm 894 void b43warn(struct b43_wl *wl, const char *fmt, ...)
829 __attribute__ ((format(printf, 2, 3))); 895 __attribute__ ((format(printf, 2, 3)));
830 #if B43_DEBUG <<
831 void b43dbg(struct b43_wl *wl, const char *fmt 896 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
832 __attribute__ ((format(printf, 2, 3))); 897 __attribute__ ((format(printf, 2, 3)));
833 #else /* DEBUG */ !! 898
834 # define b43dbg(wl, fmt...) do { /* nothing */ <<
835 #endif /* DEBUG */ <<
836 899
837 /* A WARN_ON variant that vanishes when b43 de 900 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
838 * This _also_ evaluates the arg with debuggin 901 * This _also_ evaluates the arg with debugging disabled. */
839 #if B43_DEBUG 902 #if B43_DEBUG
840 # define B43_WARN_ON(x) WARN_ON(x) 903 # define B43_WARN_ON(x) WARN_ON(x)
841 #else 904 #else
842 static inline bool __b43_warn_on_dummy(bool x) 905 static inline bool __b43_warn_on_dummy(bool x) { return x; }
843 # define B43_WARN_ON(x) __b43_warn_on_dummy(un 906 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
844 #endif 907 #endif
845 908
846 /** Limit a value between two limits */ <<
847 #ifdef limit_value <<
848 # undef limit_value <<
849 #endif <<
850 #define limit_value(value, min, max) \ <<
851 ({ <<
852 typeof(value) __value = (value <<
853 typeof(value) __min = (min); <<
854 typeof(value) __max = (max); <<
855 if (__value < __min) <<
856 __value = __min; <<
857 else if (__value > __max) <<
858 __value = __max; <<
859 __value; <<
860 }) <<
861 <<
862 /* Convert an integer to a Q5.2 value */ 909 /* Convert an integer to a Q5.2 value */
863 #define INT_TO_Q52(i) ((i) << 2) 910 #define INT_TO_Q52(i) ((i) << 2)
864 /* Convert a Q5.2 value to an integer (precisi 911 /* Convert a Q5.2 value to an integer (precision loss!) */
865 #define Q52_TO_INT(q52) ((q52) >> 2) 912 #define Q52_TO_INT(q52) ((q52) >> 2)
866 /* Macros for printing a value in Q5.2 format 913 /* Macros for printing a value in Q5.2 format */
867 #define Q52_FMT "%u.%u" 914 #define Q52_FMT "%u.%u"
868 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q 915 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
869 916
870 #endif /* B43_H_ */ 917 #endif /* B43_H_ */
871 918
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