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1 #ifndef B43_H_ 1 #ifndef B43_H_
2 #define B43_H_ 2 #define B43_H_
3 3
4 #include <linux/kernel.h> 4 #include <linux/kernel.h>
5 #include <linux/spinlock.h> 5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h> 6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h> 7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h> 8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h> 9 #include <net/mac80211.h>
10 10
11 #include "debugfs.h" 11 #include "debugfs.h"
12 #include "leds.h" 12 #include "leds.h"
13 #include "rfkill.h" 13 #include "rfkill.h"
14 #include "lo.h" 14 #include "lo.h"
15 #include "phy.h" 15 #include "phy.h"
16 16
17 17
18 /* The unique identifier of the firmware that' 18 /* The unique identifier of the firmware that's officially supported by
19 * this driver version. */ 19 * this driver version. */
20 #define B43_SUPPORTED_FIRMWARE_ID "FW13" 20 #define B43_SUPPORTED_FIRMWARE_ID "FW13"
21 21
22 22
23 #ifdef CONFIG_B43_DEBUG 23 #ifdef CONFIG_B43_DEBUG
24 # define B43_DEBUG 1 24 # define B43_DEBUG 1
25 #else 25 #else
26 # define B43_DEBUG 0 26 # define B43_DEBUG 0
27 #endif 27 #endif
28 28
29 #define B43_RX_MAX_SSI 60 29 #define B43_RX_MAX_SSI 60
30 30
31 /* MMIO offsets */ 31 /* MMIO offsets */
32 #define B43_MMIO_DMA0_REASON 0x20 32 #define B43_MMIO_DMA0_REASON 0x20
33 #define B43_MMIO_DMA0_IRQ_MASK 0x24 33 #define B43_MMIO_DMA0_IRQ_MASK 0x24
34 #define B43_MMIO_DMA1_REASON 0x28 34 #define B43_MMIO_DMA1_REASON 0x28
35 #define B43_MMIO_DMA1_IRQ_MASK 0x2C 35 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
36 #define B43_MMIO_DMA2_REASON 0x30 36 #define B43_MMIO_DMA2_REASON 0x30
37 #define B43_MMIO_DMA2_IRQ_MASK 0x34 37 #define B43_MMIO_DMA2_IRQ_MASK 0x34
38 #define B43_MMIO_DMA3_REASON 0x38 38 #define B43_MMIO_DMA3_REASON 0x38
39 #define B43_MMIO_DMA3_IRQ_MASK 0x3C 39 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
40 #define B43_MMIO_DMA4_REASON 0x40 40 #define B43_MMIO_DMA4_REASON 0x40
41 #define B43_MMIO_DMA4_IRQ_MASK 0x44 41 #define B43_MMIO_DMA4_IRQ_MASK 0x44
42 #define B43_MMIO_DMA5_REASON 0x48 42 #define B43_MMIO_DMA5_REASON 0x48
43 #define B43_MMIO_DMA5_IRQ_MASK 0x4C 43 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
44 #define B43_MMIO_MACCTL 0x120 44 #define B43_MMIO_MACCTL 0x120 /* MAC control */
45 #define B43_MMIO_MACCMD 0x124 45 #define B43_MMIO_MACCMD 0x124 /* MAC command */
46 #define B43_MMIO_GEN_IRQ_REASON 0x128 46 #define B43_MMIO_GEN_IRQ_REASON 0x128
47 #define B43_MMIO_GEN_IRQ_MASK 0x12C 47 #define B43_MMIO_GEN_IRQ_MASK 0x12C
48 #define B43_MMIO_RAM_CONTROL 0x130 48 #define B43_MMIO_RAM_CONTROL 0x130
49 #define B43_MMIO_RAM_DATA 0x134 49 #define B43_MMIO_RAM_DATA 0x134
50 #define B43_MMIO_PS_STATUS 0x140 50 #define B43_MMIO_PS_STATUS 0x140
51 #define B43_MMIO_RADIO_HWENABLED_HI 0x158 51 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
52 #define B43_MMIO_SHM_CONTROL 0x160 52 #define B43_MMIO_SHM_CONTROL 0x160
53 #define B43_MMIO_SHM_DATA 0x164 53 #define B43_MMIO_SHM_DATA 0x164
54 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166 54 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
55 #define B43_MMIO_XMITSTAT_0 0x170 55 #define B43_MMIO_XMITSTAT_0 0x170
56 #define B43_MMIO_XMITSTAT_1 0x174 56 #define B43_MMIO_XMITSTAT_1 0x174
57 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 57 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
58 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 58 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
59 #define B43_MMIO_TSF_CFP_REP 0x188 59 #define B43_MMIO_TSF_CFP_REP 0x188
60 #define B43_MMIO_TSF_CFP_START 0x18C 60 #define B43_MMIO_TSF_CFP_START 0x18C
61 #define B43_MMIO_TSF_CFP_MAXDUR 0x190 61 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
62 62
63 /* 32-bit DMA */ 63 /* 32-bit DMA */
64 #define B43_MMIO_DMA32_BASE0 0x200 64 #define B43_MMIO_DMA32_BASE0 0x200
65 #define B43_MMIO_DMA32_BASE1 0x220 65 #define B43_MMIO_DMA32_BASE1 0x220
66 #define B43_MMIO_DMA32_BASE2 0x240 66 #define B43_MMIO_DMA32_BASE2 0x240
67 #define B43_MMIO_DMA32_BASE3 0x260 67 #define B43_MMIO_DMA32_BASE3 0x260
68 #define B43_MMIO_DMA32_BASE4 0x280 68 #define B43_MMIO_DMA32_BASE4 0x280
69 #define B43_MMIO_DMA32_BASE5 0x2A0 69 #define B43_MMIO_DMA32_BASE5 0x2A0
70 /* 64-bit DMA */ 70 /* 64-bit DMA */
71 #define B43_MMIO_DMA64_BASE0 0x200 71 #define B43_MMIO_DMA64_BASE0 0x200
72 #define B43_MMIO_DMA64_BASE1 0x240 72 #define B43_MMIO_DMA64_BASE1 0x240
73 #define B43_MMIO_DMA64_BASE2 0x280 73 #define B43_MMIO_DMA64_BASE2 0x280
74 #define B43_MMIO_DMA64_BASE3 0x2C0 74 #define B43_MMIO_DMA64_BASE3 0x2C0
75 #define B43_MMIO_DMA64_BASE4 0x300 75 #define B43_MMIO_DMA64_BASE4 0x300
76 #define B43_MMIO_DMA64_BASE5 0x340 76 #define B43_MMIO_DMA64_BASE5 0x340
77 77
78 #define B43_MMIO_PHY_VER 0x3E0 78 #define B43_MMIO_PHY_VER 0x3E0
79 #define B43_MMIO_PHY_RADIO 0x3E2 79 #define B43_MMIO_PHY_RADIO 0x3E2
80 #define B43_MMIO_PHY0 0x3E6 80 #define B43_MMIO_PHY0 0x3E6
81 #define B43_MMIO_ANTENNA 0x3E8 81 #define B43_MMIO_ANTENNA 0x3E8
82 #define B43_MMIO_CHANNEL 0x3F0 82 #define B43_MMIO_CHANNEL 0x3F0
83 #define B43_MMIO_CHANNEL_EXT 0x3F4 83 #define B43_MMIO_CHANNEL_EXT 0x3F4
84 #define B43_MMIO_RADIO_CONTROL 0x3F6 84 #define B43_MMIO_RADIO_CONTROL 0x3F6
85 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8 85 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
86 #define B43_MMIO_RADIO_DATA_LOW 0x3FA 86 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
87 #define B43_MMIO_PHY_CONTROL 0x3FC 87 #define B43_MMIO_PHY_CONTROL 0x3FC
88 #define B43_MMIO_PHY_DATA 0x3FE 88 #define B43_MMIO_PHY_DATA 0x3FE
89 #define B43_MMIO_MACFILTER_CONTROL 0x420 89 #define B43_MMIO_MACFILTER_CONTROL 0x420
90 #define B43_MMIO_MACFILTER_DATA 0x422 90 #define B43_MMIO_MACFILTER_DATA 0x422
91 #define B43_MMIO_RCMTA_COUNT 0x43C 91 #define B43_MMIO_RCMTA_COUNT 0x43C
92 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A 92 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
93 #define B43_MMIO_GPIO_CONTROL 0x49C 93 #define B43_MMIO_GPIO_CONTROL 0x49C
94 #define B43_MMIO_GPIO_MASK 0x49E 94 #define B43_MMIO_GPIO_MASK 0x49E
95 #define B43_MMIO_TSF_CFP_START_LOW 0x604 95 #define B43_MMIO_TSF_CFP_START_LOW 0x604
96 #define B43_MMIO_TSF_CFP_START_HIGH 0x606 96 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
97 #define B43_MMIO_TSF_0 0x632 97 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
98 #define B43_MMIO_TSF_1 0x634 98 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
99 #define B43_MMIO_TSF_2 0x636 99 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
100 #define B43_MMIO_TSF_3 0x638 100 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
101 #define B43_MMIO_RNG 0x65A 101 #define B43_MMIO_RNG 0x65A
102 #define B43_MMIO_POWERUP_DELAY 0x6A8 102 #define B43_MMIO_POWERUP_DELAY 0x6A8
103 103
104 /* SPROM boardflags_lo values */ 104 /* SPROM boardflags_lo values */
105 #define B43_BFL_BTCOEXIST 0x0001 105 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
106 #define B43_BFL_PACTRL 0x0002 106 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
107 #define B43_BFL_AIRLINEMODE 0x0004 107 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
108 #define B43_BFL_RSSI 0x0008 108 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
109 #define B43_BFL_ENETSPI 0x0010 109 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
110 #define B43_BFL_XTAL_NOSLOW 0x0020 110 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
111 #define B43_BFL_CCKHIPWR 0x0040 111 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
112 #define B43_BFL_ENETADM 0x0080 112 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
113 #define B43_BFL_ENETVLAN 0x0100 113 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
114 #define B43_BFL_AFTERBURNER 0x0200 114 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
115 #define B43_BFL_NOPCI 0x0400 115 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
116 #define B43_BFL_FEM 0x0800 116 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
117 #define B43_BFL_EXTLNA 0x1000 117 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
118 #define B43_BFL_HGPA 0x2000 118 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
119 #define B43_BFL_BTCMOD 0x4000 119 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
120 #define B43_BFL_ALTIQ 0x8000 120 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
121 121
122 /* GPIO register offset, in both ChipCommon an 122 /* GPIO register offset, in both ChipCommon and PCI core. */
123 #define B43_GPIO_CONTROL 0x6c 123 #define B43_GPIO_CONTROL 0x6c
124 124
125 /* SHM Routing */ 125 /* SHM Routing */
126 enum { 126 enum {
127 B43_SHM_UCODE, /* Microcode m 127 B43_SHM_UCODE, /* Microcode memory */
128 B43_SHM_SHARED, /* Shared memo 128 B43_SHM_SHARED, /* Shared memory */
129 B43_SHM_SCRATCH, /* Scratch mem 129 B43_SHM_SCRATCH, /* Scratch memory */
130 B43_SHM_HW, /* Internal ha 130 B43_SHM_HW, /* Internal hardware register */
131 B43_SHM_RCMTA, /* Receive mat 131 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
132 }; 132 };
133 /* SHM Routing modifiers */ 133 /* SHM Routing modifiers */
134 #define B43_SHM_AUTOINC_R 0x0200 134 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
135 #define B43_SHM_AUTOINC_W 0x0100 135 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
136 #define B43_SHM_AUTOINC_RW (B43_S 136 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
137 B43_S 137 B43_SHM_AUTOINC_W)
138 138
139 /* Misc SHM_SHARED offsets */ 139 /* Misc SHM_SHARED offsets */
140 #define B43_SHM_SH_WLCOREREV 0x0016 140 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
141 #define B43_SHM_SH_PCTLWDPOS 0x0008 141 #define B43_SHM_SH_PCTLWDPOS 0x0008
142 #define B43_SHM_SH_RXPADOFF 0x0034 142 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
143 #define B43_SHM_SH_PHYVER 0x0050 143 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
144 #define B43_SHM_SH_PHYTYPE 0x0052 144 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
145 #define B43_SHM_SH_ANTSWAP 0x005C 145 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
146 #define B43_SHM_SH_HOSTFLO 0x005E 146 #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
147 #define B43_SHM_SH_HOSTFHI 0x0060 147 #define B43_SHM_SH_HOSTFHI 0x0060 /* Hostflags for ucode options (high) */
148 #define B43_SHM_SH_RFATT 0x0064 148 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
149 #define B43_SHM_SH_RADAR 0x0066 149 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
150 #define B43_SHM_SH_PHYTXNOI 0x006E 150 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
151 #define B43_SHM_SH_RFRXSP1 0x0072 151 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
152 #define B43_SHM_SH_CHAN 0x00A0 152 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
153 #define B43_SHM_SH_CHAN_5GHZ 0x0100 153 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
154 #define B43_SHM_SH_BCMCFIFOID 0x0108 154 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
155 /* SHM_SHARED TX FIFO variables */ 155 /* SHM_SHARED TX FIFO variables */
156 #define B43_SHM_SH_SIZE01 0x0098 156 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
157 #define B43_SHM_SH_SIZE23 0x009A 157 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
158 #define B43_SHM_SH_SIZE45 0x009C 158 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
159 #define B43_SHM_SH_SIZE67 0x009E 159 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
160 /* SHM_SHARED background noise */ 160 /* SHM_SHARED background noise */
161 #define B43_SHM_SH_JSSI0 0x0088 161 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
162 #define B43_SHM_SH_JSSI1 0x008A 162 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
163 #define B43_SHM_SH_JSSIAUX 0x008C 163 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
164 /* SHM_SHARED crypto engine */ 164 /* SHM_SHARED crypto engine */
165 #define B43_SHM_SH_DEFAULTIV 0x003C 165 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
166 #define B43_SHM_SH_NRRXTRANS 0x003E 166 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
167 #define B43_SHM_SH_KTP 0x0056 167 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
168 #define B43_SHM_SH_TKIPTSCTTAK 0x0318 168 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
169 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 169 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
170 #define B43_SHM_SH_PSM 0x05F4 170 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
171 /* SHM_SHARED WME variables */ 171 /* SHM_SHARED WME variables */
172 #define B43_SHM_SH_EDCFSTAT 0x000E 172 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
173 #define B43_SHM_SH_TXFCUR 0x0030 173 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
174 #define B43_SHM_SH_EDCFQ 0x0240 174 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
175 /* SHM_SHARED powersave mode related */ 175 /* SHM_SHARED powersave mode related */
176 #define B43_SHM_SH_SLOTT 0x0010 176 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
177 #define B43_SHM_SH_DTIMPER 0x0012 177 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
178 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C 178 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
179 /* SHM_SHARED beacon/AP variables */ 179 /* SHM_SHARED beacon/AP variables */
180 #define B43_SHM_SH_BTL0 0x0018 180 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
181 #define B43_SHM_SH_BTL1 0x001A 181 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
182 #define B43_SHM_SH_BTSFOFF 0x001C 182 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
183 #define B43_SHM_SH_TIMBPOS 0x001E 183 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
184 #define B43_SHM_SH_DTIMP 0x0012 184 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
185 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 185 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
186 #define B43_SHM_SH_SFFBLIM 0x0044 186 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
187 #define B43_SHM_SH_LFFBLIM 0x0046 187 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
188 #define B43_SHM_SH_BEACPHYCTL 0x0054 188 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
189 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 189 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
190 /* SHM_SHARED ACK/CTS control */ 190 /* SHM_SHARED ACK/CTS control */
191 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 191 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
192 /* SHM_SHARED probe response variables */ 192 /* SHM_SHARED probe response variables */
193 #define B43_SHM_SH_PRSSID 0x0160 193 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
194 #define B43_SHM_SH_PRSSIDLEN 0x0048 194 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
195 #define B43_SHM_SH_PRTLEN 0x004A 195 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
196 #define B43_SHM_SH_PRMAXTIME 0x0074 196 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
197 #define B43_SHM_SH_PRPHYCTL 0x0188 197 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
198 /* SHM_SHARED rate tables */ 198 /* SHM_SHARED rate tables */
199 #define B43_SHM_SH_OFDMDIRECT 0x01C0 199 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
200 #define B43_SHM_SH_OFDMBASIC 0x01E0 200 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
201 #define B43_SHM_SH_CCKDIRECT 0x0200 201 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
202 #define B43_SHM_SH_CCKBASIC 0x0220 202 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
203 /* SHM_SHARED microcode soft registers */ 203 /* SHM_SHARED microcode soft registers */
204 #define B43_SHM_SH_UCODEREV 0x0000 204 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
205 #define B43_SHM_SH_UCODEPATCH 0x0002 205 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
206 #define B43_SHM_SH_UCODEDATE 0x0004 206 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
207 #define B43_SHM_SH_UCODETIME 0x0006 207 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
208 #define B43_SHM_SH_UCODESTAT 0x0040 208 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
209 #define B43_SHM_SH_UCODESTAT_INVALID 0 209 #define B43_SHM_SH_UCODESTAT_INVALID 0
210 #define B43_SHM_SH_UCODESTAT_INIT 1 210 #define B43_SHM_SH_UCODESTAT_INIT 1
211 #define B43_SHM_SH_UCODESTAT_ACTIVE 2 211 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
212 #define B43_SHM_SH_UCODESTAT_SUSP 3 212 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
213 #define B43_SHM_SH_UCODESTAT_SLEEP 4 213 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
214 #define B43_SHM_SH_MAXBFRAMES 0x0080 214 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
215 #define B43_SHM_SH_SPUWKUP 0x0094 215 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
216 #define B43_SHM_SH_PRETBTT 0x0096 216 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
217 217
218 /* SHM_SCRATCH offsets */ 218 /* SHM_SCRATCH offsets */
219 #define B43_SHM_SC_MINCONT 0x0003 219 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
220 #define B43_SHM_SC_MAXCONT 0x0004 220 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
221 #define B43_SHM_SC_CURCONT 0x0005 221 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
222 #define B43_SHM_SC_SRLIMIT 0x0006 222 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
223 #define B43_SHM_SC_LRLIMIT 0x0007 223 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
224 #define B43_SHM_SC_DTIMC 0x0008 224 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
225 #define B43_SHM_SC_BTL0LEN 0x0015 225 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
226 #define B43_SHM_SC_BTL1LEN 0x0016 226 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
227 #define B43_SHM_SC_SCFB 0x0017 227 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
228 #define B43_SHM_SC_LCFB 0x0018 228 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
229 229
230 /* Hardware Radio Enable masks */ 230 /* Hardware Radio Enable masks */
231 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 231 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
232 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 232 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
233 233
234 /* HostFlags. See b43_hf_read/write() */ 234 /* HostFlags. See b43_hf_read/write() */
235 #define B43_HF_ANTDIVHELP 0x0000 235 #define B43_HF_ANTDIVHELP 0x00000001 /* ucode antenna div helper */
236 #define B43_HF_SYMW 0x0000 236 #define B43_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
237 #define B43_HF_RXPULLW 0x0000 237 #define B43_HF_RXPULLW 0x00000004 /* RX pullup workaround */
238 #define B43_HF_CCKBOOST 0x0000 238 #define B43_HF_CCKBOOST 0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
239 #define B43_HF_BTCOEX 0x0000 239 #define B43_HF_BTCOEX 0x00000010 /* Bluetooth coexistance */
240 #define B43_HF_GDCW 0x0000 240 #define B43_HF_GDCW 0x00000020 /* G-PHY DV canceller filter bw workaround */
241 #define B43_HF_OFDMPABOOST 0x0000 241 #define B43_HF_OFDMPABOOST 0x00000040 /* Enable PA gain boost for OFDM */
242 #define B43_HF_ACPR 0x0000 242 #define B43_HF_ACPR 0x00000080 /* Disable for Japan, channel 14 */
243 #define B43_HF_EDCF 0x0000 243 #define B43_HF_EDCF 0x00000100 /* on if WME and MAC suspended */
244 #define B43_HF_TSSIRPSMW 0x0000 244 #define B43_HF_TSSIRPSMW 0x00000200 /* TSSI reset PSM ucode workaround */
245 #define B43_HF_DSCRQ 0x0000 245 #define B43_HF_DSCRQ 0x00000400 /* Disable slow clock request in ucode */
246 #define B43_HF_ACIW 0x0000 246 #define B43_HF_ACIW 0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
247 #define B43_HF_2060W 0x0000 247 #define B43_HF_2060W 0x00001000 /* 2060 radio workaround */
248 #define B43_HF_RADARW 0x0000 248 #define B43_HF_RADARW 0x00002000 /* Radar workaround */
249 #define B43_HF_USEDEFKEYS 0x0000 249 #define B43_HF_USEDEFKEYS 0x00004000 /* Enable use of default keys */
250 #define B43_HF_BT4PRIOCOEX 0x0001 250 #define B43_HF_BT4PRIOCOEX 0x00010000 /* Bluetooth 2-priority coexistance */
251 #define B43_HF_FWKUP 0x0002 251 #define B43_HF_FWKUP 0x00020000 /* Fast wake-up ucode */
252 #define B43_HF_VCORECALC 0x0004 252 #define B43_HF_VCORECALC 0x00040000 /* Force VCO recalculation when powering up synthpu */
253 #define B43_HF_PCISCW 0x0008 253 #define B43_HF_PCISCW 0x00080000 /* PCI slow clock workaround */
254 #define B43_HF_4318TSSI 0x0020 254 #define B43_HF_4318TSSI 0x00200000 /* 4318 TSSI */
255 #define B43_HF_FBCMCFIFO 0x0040 255 #define B43_HF_FBCMCFIFO 0x00400000 /* Flush bcast/mcast FIFO immediately */
256 #define B43_HF_HWPCTL 0x0080 256 #define B43_HF_HWPCTL 0x00800000 /* Enable hardwarre power control */
257 #define B43_HF_BTCOEXALT 0x0100 257 #define B43_HF_BTCOEXALT 0x01000000 /* Bluetooth coexistance in alternate pins */
258 #define B43_HF_TXBTCHECK 0x0200 258 #define B43_HF_TXBTCHECK 0x02000000 /* Bluetooth check during transmission */
259 #define B43_HF_SKCFPUP 0x0400 259 #define B43_HF_SKCFPUP 0x04000000 /* Skip CFP update */
260 260
261 /* MacFilter offsets. */ 261 /* MacFilter offsets. */
262 #define B43_MACFILTER_SELF 0x0000 262 #define B43_MACFILTER_SELF 0x0000
263 #define B43_MACFILTER_BSSID 0x0003 263 #define B43_MACFILTER_BSSID 0x0003
264 264
265 /* PowerControl */ 265 /* PowerControl */
266 #define B43_PCTL_IN 0xB0 266 #define B43_PCTL_IN 0xB0
267 #define B43_PCTL_OUT 0xB4 267 #define B43_PCTL_OUT 0xB4
268 #define B43_PCTL_OUTENABLE 0xB8 268 #define B43_PCTL_OUTENABLE 0xB8
269 #define B43_PCTL_XTAL_POWERUP 0x40 269 #define B43_PCTL_XTAL_POWERUP 0x40
270 #define B43_PCTL_PLL_POWERDOWN 0x80 270 #define B43_PCTL_PLL_POWERDOWN 0x80
271 271
272 /* PowerControl Clock Modes */ 272 /* PowerControl Clock Modes */
273 #define B43_PCTL_CLK_FAST 0x00 273 #define B43_PCTL_CLK_FAST 0x00
274 #define B43_PCTL_CLK_SLOW 0x01 274 #define B43_PCTL_CLK_SLOW 0x01
275 #define B43_PCTL_CLK_DYNAMIC 0x02 275 #define B43_PCTL_CLK_DYNAMIC 0x02
276 276
277 #define B43_PCTL_FORCE_SLOW 0x0800 277 #define B43_PCTL_FORCE_SLOW 0x0800
278 #define B43_PCTL_FORCE_PLL 0x1000 278 #define B43_PCTL_FORCE_PLL 0x1000
279 #define B43_PCTL_DYN_XTAL 0x2000 279 #define B43_PCTL_DYN_XTAL 0x2000
280 280
281 /* PHYVersioning */ 281 /* PHYVersioning */
282 #define B43_PHYTYPE_A 0x00 282 #define B43_PHYTYPE_A 0x00
283 #define B43_PHYTYPE_B 0x01 283 #define B43_PHYTYPE_B 0x01
284 #define B43_PHYTYPE_G 0x02 284 #define B43_PHYTYPE_G 0x02
285 #define B43_PHYTYPE_N 0x04 285 #define B43_PHYTYPE_N 0x04
286 #define B43_PHYTYPE_LP 0x05 286 #define B43_PHYTYPE_LP 0x05
287 287
288 /* PHYRegisters */ 288 /* PHYRegisters */
289 #define B43_PHY_ILT_A_CTRL 0x0072 289 #define B43_PHY_ILT_A_CTRL 0x0072
290 #define B43_PHY_ILT_A_DATA1 0x0073 290 #define B43_PHY_ILT_A_DATA1 0x0073
291 #define B43_PHY_ILT_A_DATA2 0x0074 291 #define B43_PHY_ILT_A_DATA2 0x0074
292 #define B43_PHY_G_LO_CONTROL 0x0810 292 #define B43_PHY_G_LO_CONTROL 0x0810
293 #define B43_PHY_ILT_G_CTRL 0x0472 293 #define B43_PHY_ILT_G_CTRL 0x0472
294 #define B43_PHY_ILT_G_DATA1 0x0473 294 #define B43_PHY_ILT_G_DATA1 0x0473
295 #define B43_PHY_ILT_G_DATA2 0x0474 295 #define B43_PHY_ILT_G_DATA2 0x0474
296 #define B43_PHY_A_PCTL 0x007B 296 #define B43_PHY_A_PCTL 0x007B
297 #define B43_PHY_G_PCTL 0x0029 297 #define B43_PHY_G_PCTL 0x0029
298 #define B43_PHY_A_CRS 0x0029 298 #define B43_PHY_A_CRS 0x0029
299 #define B43_PHY_RADIO_BITFIELD 0x0401 299 #define B43_PHY_RADIO_BITFIELD 0x0401
300 #define B43_PHY_G_CRS 0x0429 300 #define B43_PHY_G_CRS 0x0429
301 #define B43_PHY_NRSSILT_CTRL 0x0803 301 #define B43_PHY_NRSSILT_CTRL 0x0803
302 #define B43_PHY_NRSSILT_DATA 0x0804 302 #define B43_PHY_NRSSILT_DATA 0x0804
303 303
304 /* RadioRegisters */ 304 /* RadioRegisters */
305 #define B43_RADIOCTL_ID 0x01 305 #define B43_RADIOCTL_ID 0x01
306 306
307 /* MAC Control bitfield */ 307 /* MAC Control bitfield */
308 #define B43_MACCTL_ENABLED 0x0000 308 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
309 #define B43_MACCTL_PSM_RUN 0x0000 309 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
310 #define B43_MACCTL_PSM_JMP0 0x0000 310 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
311 #define B43_MACCTL_SHM_ENABLED 0x0000 311 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
312 #define B43_MACCTL_SHM_UPPER 0x0000 312 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
313 #define B43_MACCTL_IHR_ENABLED 0x0000 313 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
314 #define B43_MACCTL_PSM_DBG 0x0000 314 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
315 #define B43_MACCTL_GPOUTSMSK 0x0000 315 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
316 #define B43_MACCTL_BE 0x0001 316 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
317 #define B43_MACCTL_INFRA 0x0002 317 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
318 #define B43_MACCTL_AP 0x0004 318 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
319 #define B43_MACCTL_RADIOLOCK 0x0008 319 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
320 #define B43_MACCTL_BEACPROMISC 0x0010 320 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
321 #define B43_MACCTL_KEEP_BADPLCP 0x0020 321 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
322 #define B43_MACCTL_KEEP_CTL 0x0040 322 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
323 #define B43_MACCTL_KEEP_BAD 0x0080 323 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
324 #define B43_MACCTL_PROMISC 0x0100 324 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
325 #define B43_MACCTL_HWPS 0x0200 325 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
326 #define B43_MACCTL_AWAKE 0x0400 326 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
327 #define B43_MACCTL_CLOSEDNET 0x0800 327 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
328 #define B43_MACCTL_TBTTHOLD 0x1000 328 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
329 #define B43_MACCTL_DISCTXSTAT 0x2000 329 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
330 #define B43_MACCTL_DISCPMQ 0x4000 330 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
331 #define B43_MACCTL_GMODE 0x8000 331 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
332 332
333 /* MAC Command bitfield */ 333 /* MAC Command bitfield */
334 #define B43_MACCMD_BEACON0_VALID 0x0000 334 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
335 #define B43_MACCMD_BEACON1_VALID 0x0000 335 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
336 #define B43_MACCMD_DFQ_VALID 0x0000 336 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
337 #define B43_MACCMD_CCA 0x0000 337 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
338 #define B43_MACCMD_BGNOISE 0x0000 338 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
339 339
340 /* 802.11 core specific TM State Low (SSB_TMSL 340 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
341 #define B43_TMSLOW_GMODE 0x2000 341 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
342 #define B43_TMSLOW_PHYCLKSPEED 0x00C0 342 #define B43_TMSLOW_PHYCLKSPEED 0x00C00000 /* PHY clock speed mask (N-PHY only) */
343 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x0000 343 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000 /* 40 MHz PHY */
344 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x0040 344 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000 /* 80 MHz PHY */
345 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x0080 345 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000 /* 160 MHz PHY */
346 #define B43_TMSLOW_PLLREFSEL 0x0020 346 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
347 #define B43_TMSLOW_MACPHYCLKEN 0x0010 347 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
348 #define B43_TMSLOW_PHYRESET 0x0008 348 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
349 #define B43_TMSLOW_PHYCLKEN 0x0004 349 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
350 350
351 /* 802.11 core specific TM State High (SSB_TMS 351 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
352 #define B43_TMSHIGH_DUALBAND_PHY 0x0008 352 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
353 #define B43_TMSHIGH_FCLOCK 0x0004 353 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
354 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x0002 354 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
355 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x0001 355 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
356 356
357 /* Generic-Interrupt reasons. */ 357 /* Generic-Interrupt reasons. */
358 #define B43_IRQ_MAC_SUSPENDED 0x0000 358 #define B43_IRQ_MAC_SUSPENDED 0x00000001
359 #define B43_IRQ_BEACON 0x0000 359 #define B43_IRQ_BEACON 0x00000002
360 #define B43_IRQ_TBTT_INDI 0x0000 360 #define B43_IRQ_TBTT_INDI 0x00000004
361 #define B43_IRQ_BEACON_TX_OK 0x0000 361 #define B43_IRQ_BEACON_TX_OK 0x00000008
362 #define B43_IRQ_BEACON_CANCEL 0x0000 362 #define B43_IRQ_BEACON_CANCEL 0x00000010
363 #define B43_IRQ_ATIM_END 0x0000 363 #define B43_IRQ_ATIM_END 0x00000020
364 #define B43_IRQ_PMQ 0x0000 364 #define B43_IRQ_PMQ 0x00000040
365 #define B43_IRQ_PIO_WORKAROUND 0x0000 365 #define B43_IRQ_PIO_WORKAROUND 0x00000100
366 #define B43_IRQ_MAC_TXERR 0x0000 366 #define B43_IRQ_MAC_TXERR 0x00000200
367 #define B43_IRQ_PHY_TXERR 0x0000 367 #define B43_IRQ_PHY_TXERR 0x00000800
368 #define B43_IRQ_PMEVENT 0x0000 368 #define B43_IRQ_PMEVENT 0x00001000
369 #define B43_IRQ_TIMER0 0x0000 369 #define B43_IRQ_TIMER0 0x00002000
370 #define B43_IRQ_TIMER1 0x0000 370 #define B43_IRQ_TIMER1 0x00004000
371 #define B43_IRQ_DMA 0x0000 371 #define B43_IRQ_DMA 0x00008000
372 #define B43_IRQ_TXFIFO_FLUSH_OK 0x0001 372 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
373 #define B43_IRQ_CCA_MEASURE_OK 0x0002 373 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
374 #define B43_IRQ_NOISESAMPLE_OK 0x0004 374 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
375 #define B43_IRQ_UCODE_DEBUG 0x0800 375 #define B43_IRQ_UCODE_DEBUG 0x08000000
376 #define B43_IRQ_RFKILL 0x1000 376 #define B43_IRQ_RFKILL 0x10000000
377 #define B43_IRQ_TX_OK 0x2000 377 #define B43_IRQ_TX_OK 0x20000000
378 #define B43_IRQ_PHY_G_CHANGED 0x4000 378 #define B43_IRQ_PHY_G_CHANGED 0x40000000
379 #define B43_IRQ_TIMEOUT 0x8000 379 #define B43_IRQ_TIMEOUT 0x80000000
380 380
381 #define B43_IRQ_ALL 0xFFFF 381 #define B43_IRQ_ALL 0xFFFFFFFF
382 #define B43_IRQ_MASKTEMPLATE (B43_I 382 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_MAC_SUSPENDED | \
383 B43_I 383 B43_IRQ_BEACON | \
384 B43_I 384 B43_IRQ_TBTT_INDI | \
385 B43_I 385 B43_IRQ_ATIM_END | \
386 B43_I 386 B43_IRQ_PMQ | \
387 B43_I 387 B43_IRQ_MAC_TXERR | \
388 B43_I 388 B43_IRQ_PHY_TXERR | \
389 B43_I 389 B43_IRQ_DMA | \
390 B43_I 390 B43_IRQ_TXFIFO_FLUSH_OK | \
391 B43_I 391 B43_IRQ_NOISESAMPLE_OK | \
392 B43_I 392 B43_IRQ_UCODE_DEBUG | \
393 B43_I 393 B43_IRQ_RFKILL | \
394 B43_I 394 B43_IRQ_TX_OK)
395 395
396 /* Device specific rate values. 396 /* Device specific rate values.
397 * The actual values defined here are (rate_in 397 * The actual values defined here are (rate_in_mbps * 2).
398 * Some code depends on this. Don't change it. 398 * Some code depends on this. Don't change it. */
399 #define B43_CCK_RATE_1MB 0x02 399 #define B43_CCK_RATE_1MB 0x02
400 #define B43_CCK_RATE_2MB 0x04 400 #define B43_CCK_RATE_2MB 0x04
401 #define B43_CCK_RATE_5MB 0x0B 401 #define B43_CCK_RATE_5MB 0x0B
402 #define B43_CCK_RATE_11MB 0x16 402 #define B43_CCK_RATE_11MB 0x16
403 #define B43_OFDM_RATE_6MB 0x0C 403 #define B43_OFDM_RATE_6MB 0x0C
404 #define B43_OFDM_RATE_9MB 0x12 404 #define B43_OFDM_RATE_9MB 0x12
405 #define B43_OFDM_RATE_12MB 0x18 405 #define B43_OFDM_RATE_12MB 0x18
406 #define B43_OFDM_RATE_18MB 0x24 406 #define B43_OFDM_RATE_18MB 0x24
407 #define B43_OFDM_RATE_24MB 0x30 407 #define B43_OFDM_RATE_24MB 0x30
408 #define B43_OFDM_RATE_36MB 0x48 408 #define B43_OFDM_RATE_36MB 0x48
409 #define B43_OFDM_RATE_48MB 0x60 409 #define B43_OFDM_RATE_48MB 0x60
410 #define B43_OFDM_RATE_54MB 0x6C 410 #define B43_OFDM_RATE_54MB 0x6C
411 /* Convert a b43 rate value to a rate in 100kb 411 /* Convert a b43 rate value to a rate in 100kbps */
412 #define B43_RATE_TO_BASE100KBPS(rate) (((rat 412 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
413 413
414 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7 414 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
415 #define B43_DEFAULT_LONG_RETRY_LIMIT 4 415 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
416 416
417 #define B43_PHY_TX_BADNESS_LIMIT 1000 417 #define B43_PHY_TX_BADNESS_LIMIT 1000
418 418
419 /* Max size of a security key */ 419 /* Max size of a security key */
420 #define B43_SEC_KEYSIZE 16 420 #define B43_SEC_KEYSIZE 16
421 /* Security algorithms. */ 421 /* Security algorithms. */
422 enum { 422 enum {
423 B43_SEC_ALGO_NONE = 0, /* unencrypted 423 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
424 B43_SEC_ALGO_WEP40, 424 B43_SEC_ALGO_WEP40,
425 B43_SEC_ALGO_TKIP, 425 B43_SEC_ALGO_TKIP,
426 B43_SEC_ALGO_AES, 426 B43_SEC_ALGO_AES,
427 B43_SEC_ALGO_WEP104, 427 B43_SEC_ALGO_WEP104,
428 B43_SEC_ALGO_AES_LEGACY, 428 B43_SEC_ALGO_AES_LEGACY,
429 }; 429 };
430 430
431 struct b43_dmaring; 431 struct b43_dmaring;
432 struct b43_pioqueue; 432 struct b43_pioqueue;
433 433
434 /* The firmware file header */ 434 /* The firmware file header */
435 #define B43_FW_TYPE_UCODE 'u' 435 #define B43_FW_TYPE_UCODE 'u'
436 #define B43_FW_TYPE_PCM 'p' 436 #define B43_FW_TYPE_PCM 'p'
437 #define B43_FW_TYPE_IV 'i' 437 #define B43_FW_TYPE_IV 'i'
438 struct b43_fw_header { 438 struct b43_fw_header {
439 /* File type */ 439 /* File type */
440 u8 type; 440 u8 type;
441 /* File format version */ 441 /* File format version */
442 u8 ver; 442 u8 ver;
443 u8 __padding[2]; 443 u8 __padding[2];
444 /* Size of the data. For ucode and PCM 444 /* Size of the data. For ucode and PCM this is in bytes.
445 * For IV this is number-of-ivs. */ 445 * For IV this is number-of-ivs. */
446 __be32 size; 446 __be32 size;
447 } __attribute__((__packed__)); 447 } __attribute__((__packed__));
448 448
449 /* Initial Value file format */ 449 /* Initial Value file format */
450 #define B43_IV_OFFSET_MASK 0x7FFF 450 #define B43_IV_OFFSET_MASK 0x7FFF
451 #define B43_IV_32BIT 0x8000 451 #define B43_IV_32BIT 0x8000
452 struct b43_iv { 452 struct b43_iv {
453 __be16 offset_size; 453 __be16 offset_size;
454 union { 454 union {
455 __be16 d16; 455 __be16 d16;
456 __be32 d32; 456 __be32 d32;
457 } data __attribute__((__packed__)); 457 } data __attribute__((__packed__));
458 } __attribute__((__packed__)); 458 } __attribute__((__packed__));
459 459
460 460
461 #define B43_PHYMODE(phytype) (1 << 461 #define B43_PHYMODE(phytype) (1 << (phytype))
462 #define B43_PHYMODE_A B43_PH 462 #define B43_PHYMODE_A B43_PHYMODE(B43_PHYTYPE_A)
463 #define B43_PHYMODE_B B43_PH 463 #define B43_PHYMODE_B B43_PHYMODE(B43_PHYTYPE_B)
464 #define B43_PHYMODE_G B43_PH 464 #define B43_PHYMODE_G B43_PHYMODE(B43_PHYTYPE_G)
465 465
466 struct b43_phy { 466 struct b43_phy {
467 /* Possible PHYMODEs on this PHY */ 467 /* Possible PHYMODEs on this PHY */
468 u8 possible_phymodes; 468 u8 possible_phymodes;
469 /* GMODE bit enabled? */ 469 /* GMODE bit enabled? */
470 bool gmode; 470 bool gmode;
471 /* Possible ieee80211 subsystem hwmode 471 /* Possible ieee80211 subsystem hwmodes for this PHY.
472 * Which mode is selected, depends on 472 * Which mode is selected, depends on thr GMODE enabled bit */
473 #define B43_MAX_PHYHWMODES 2 473 #define B43_MAX_PHYHWMODES 2
474 struct ieee80211_hw_mode hwmodes[B43_M 474 struct ieee80211_hw_mode hwmodes[B43_MAX_PHYHWMODES];
475 475
476 /* Analog Type */ 476 /* Analog Type */
477 u8 analog; 477 u8 analog;
478 /* B43_PHYTYPE_ */ 478 /* B43_PHYTYPE_ */
479 u8 type; 479 u8 type;
480 /* PHY revision number. */ 480 /* PHY revision number. */
481 u8 rev; 481 u8 rev;
482 482
483 /* Radio versioning */ 483 /* Radio versioning */
484 u16 radio_manuf; /* Radio manuf 484 u16 radio_manuf; /* Radio manufacturer */
485 u16 radio_ver; /* Radio versi 485 u16 radio_ver; /* Radio version */
486 u8 radio_rev; /* Radio revis 486 u8 radio_rev; /* Radio revision */
487 487
488 bool dyn_tssi_tbl; /* tssi2dbm is 488 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
489 489
490 /* ACI (adjacent channel interference) 490 /* ACI (adjacent channel interference) flags. */
491 bool aci_enable; 491 bool aci_enable;
492 bool aci_wlan_automatic; 492 bool aci_wlan_automatic;
493 bool aci_hw_rssi; 493 bool aci_hw_rssi;
494 494
495 /* Radio switched on/off */ 495 /* Radio switched on/off */
496 bool radio_on; 496 bool radio_on;
497 struct { 497 struct {
498 /* Values saved when turning t 498 /* Values saved when turning the radio off.
499 * They are needed when turnin 499 * They are needed when turning it on again. */
500 bool valid; 500 bool valid;
501 u16 rfover; 501 u16 rfover;
502 u16 rfoverval; 502 u16 rfoverval;
503 } radio_off_context; 503 } radio_off_context;
504 504
505 u16 minlowsig[2]; 505 u16 minlowsig[2];
506 u16 minlowsigpos[2]; 506 u16 minlowsigpos[2];
507 507
508 /* TSSI to dBm table in use */ 508 /* TSSI to dBm table in use */
509 const s8 *tssi2dbm; 509 const s8 *tssi2dbm;
510 /* Target idle TSSI */ 510 /* Target idle TSSI */
511 int tgt_idle_tssi; 511 int tgt_idle_tssi;
512 /* Current idle TSSI */ 512 /* Current idle TSSI */
513 int cur_idle_tssi; 513 int cur_idle_tssi;
514 514
515 /* LocalOscillator control values. */ 515 /* LocalOscillator control values. */
516 struct b43_txpower_lo_control *lo_cont 516 struct b43_txpower_lo_control *lo_control;
517 /* Values from b43_calc_loopback_gain( 517 /* Values from b43_calc_loopback_gain() */
518 s16 max_lb_gain; /* Maximum Loo 518 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
519 s16 trsw_rx_gain; /* TRSW RX gai 519 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
520 s16 lna_lod_gain; /* LNA lod */ 520 s16 lna_lod_gain; /* LNA lod */
521 s16 lna_gain; /* LNA */ 521 s16 lna_gain; /* LNA */
522 s16 pga_gain; /* PGA */ 522 s16 pga_gain; /* PGA */
523 523
524 /* Desired TX power level (in dBm). 524 /* Desired TX power level (in dBm).
525 * This is set by the user and adjuste 525 * This is set by the user and adjusted in b43_phy_xmitpower(). */
526 u8 power_level; 526 u8 power_level;
527 /* A-PHY TX Power control value. */ 527 /* A-PHY TX Power control value. */
528 u16 txpwr_offset; 528 u16 txpwr_offset;
529 529
530 /* Current TX power level attenuation 530 /* Current TX power level attenuation control values */
531 struct b43_bbatt bbatt; 531 struct b43_bbatt bbatt;
532 struct b43_rfatt rfatt; 532 struct b43_rfatt rfatt;
533 u8 tx_control; /* B43_TXCTL_X 533 u8 tx_control; /* B43_TXCTL_XXX */
534 534
535 /* Hardware Power Control enabled? */ 535 /* Hardware Power Control enabled? */
536 bool hardware_power_control; 536 bool hardware_power_control;
537 537
538 /* Current Interference Mitigation mod 538 /* Current Interference Mitigation mode */
539 int interfmode; 539 int interfmode;
540 /* Stack of saved values from the Inte 540 /* Stack of saved values from the Interference Mitigation code.
541 * Each value in the stack is layed ou 541 * Each value in the stack is layed out as follows:
542 * bit 0-11: offset 542 * bit 0-11: offset
543 * bit 12-15: register ID 543 * bit 12-15: register ID
544 * bit 16-32: value 544 * bit 16-32: value
545 * register ID is: 0x1 PHY, 0x2 Radio, 545 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
546 */ 546 */
547 #define B43_INTERFSTACK_SIZE 26 547 #define B43_INTERFSTACK_SIZE 26
548 u32 interfstack[B43_INTERFSTACK_SIZE]; 548 u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
549 549
550 /* Saved values from the NRSSI Slope c 550 /* Saved values from the NRSSI Slope calculation */
551 s16 nrssi[2]; 551 s16 nrssi[2];
552 s32 nrssislope; 552 s32 nrssislope;
553 /* In memory nrssi lookup table. */ 553 /* In memory nrssi lookup table. */
554 s8 nrssi_lt[64]; 554 s8 nrssi_lt[64];
555 555
556 /* current channel */ 556 /* current channel */
557 u8 channel; 557 u8 channel;
558 558
559 u16 lofcal; 559 u16 lofcal;
560 560
561 u16 initval; //FIXME rename 561 u16 initval; //FIXME rename?
562 562
563 /* PHY TX errors counter. */ 563 /* PHY TX errors counter. */
564 atomic_t txerr_cnt; 564 atomic_t txerr_cnt;
565 565
566 /* The device does address auto increm 566 /* The device does address auto increment for the OFDM tables.
567 * We cache the previously used addres 567 * We cache the previously used address here and omit the address
568 * write on the next table access, if 568 * write on the next table access, if possible. */
569 u16 ofdmtab_addr; /* The address curre 569 u16 ofdmtab_addr; /* The address currently set in hardware. */
570 enum { /* The last data flow direction 570 enum { /* The last data flow direction. */
571 B43_OFDMTAB_DIRECTION_UNKNOWN 571 B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
572 B43_OFDMTAB_DIRECTION_READ, 572 B43_OFDMTAB_DIRECTION_READ,
573 B43_OFDMTAB_DIRECTION_WRITE, 573 B43_OFDMTAB_DIRECTION_WRITE,
574 } ofdmtab_addr_direction; 574 } ofdmtab_addr_direction;
575 575
576 #if B43_DEBUG 576 #if B43_DEBUG
577 /* Manual TX-power control enabled? */ 577 /* Manual TX-power control enabled? */
578 bool manual_txpower_control; 578 bool manual_txpower_control;
579 /* PHY registers locked by b43_phy_loc 579 /* PHY registers locked by b43_phy_lock()? */
580 bool phy_locked; 580 bool phy_locked;
581 #endif /* B43_DEBUG */ 581 #endif /* B43_DEBUG */
582 }; 582 };
583 583
584 /* Data structures for DMA transmission, per 8 584 /* Data structures for DMA transmission, per 80211 core. */
585 struct b43_dma { 585 struct b43_dma {
586 struct b43_dmaring *tx_ring0; 586 struct b43_dmaring *tx_ring0;
587 struct b43_dmaring *tx_ring1; 587 struct b43_dmaring *tx_ring1;
588 struct b43_dmaring *tx_ring2; 588 struct b43_dmaring *tx_ring2;
589 struct b43_dmaring *tx_ring3; 589 struct b43_dmaring *tx_ring3;
590 struct b43_dmaring *tx_ring4; 590 struct b43_dmaring *tx_ring4;
591 struct b43_dmaring *tx_ring5; 591 struct b43_dmaring *tx_ring5;
592 592
593 struct b43_dmaring *rx_ring0; 593 struct b43_dmaring *rx_ring0;
594 struct b43_dmaring *rx_ring3; /* onl 594 struct b43_dmaring *rx_ring3; /* only available on core.rev < 5 */
595 }; 595 };
596 596
597 /* Context information for a noise calculation 597 /* Context information for a noise calculation (Link Quality). */
598 struct b43_noise_calculation { 598 struct b43_noise_calculation {
599 u8 channel_at_start; <<
600 bool calculation_running; 599 bool calculation_running;
601 u8 nr_samples; 600 u8 nr_samples;
602 s8 samples[8][4]; 601 s8 samples[8][4];
603 }; 602 };
604 603
605 struct b43_stats { 604 struct b43_stats {
606 u8 link_noise; 605 u8 link_noise;
607 /* Store the last TX/RX times here for 606 /* Store the last TX/RX times here for updating the leds. */
608 unsigned long last_tx; 607 unsigned long last_tx;
609 unsigned long last_rx; 608 unsigned long last_rx;
610 }; 609 };
611 610
612 struct b43_key { 611 struct b43_key {
613 /* If keyconf is NULL, this key is dis 612 /* If keyconf is NULL, this key is disabled.
614 * keyconf is a cookie. Don't derefenr 613 * keyconf is a cookie. Don't derefenrence it outside of the set_key
615 * path, because b43 doesn't own it. * 614 * path, because b43 doesn't own it. */
616 struct ieee80211_key_conf *keyconf; 615 struct ieee80211_key_conf *keyconf;
617 u8 algorithm; 616 u8 algorithm;
618 }; 617 };
619 618
620 struct b43_wldev; 619 struct b43_wldev;
621 620
622 /* Data structure for the WLAN parts (802.11 c 621 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
623 struct b43_wl { 622 struct b43_wl {
624 /* Pointer to the active wireless devi 623 /* Pointer to the active wireless device on this chip */
625 struct b43_wldev *current_dev; 624 struct b43_wldev *current_dev;
626 /* Pointer to the ieee80211 hardware d 625 /* Pointer to the ieee80211 hardware data structure */
627 struct ieee80211_hw *hw; 626 struct ieee80211_hw *hw;
628 627
629 struct mutex mutex; 628 struct mutex mutex;
630 spinlock_t irq_lock; 629 spinlock_t irq_lock;
>> 630 /* R/W lock for data transmission.
>> 631 * Transmissions on 2+ queues can run concurrently, but somebody else
>> 632 * might sync with TX by write_lock_irqsave()'ing. */
>> 633 rwlock_t tx_lock;
631 /* Lock for LEDs access. */ 634 /* Lock for LEDs access. */
632 spinlock_t leds_lock; 635 spinlock_t leds_lock;
633 /* Lock for SHM access. */ 636 /* Lock for SHM access. */
634 spinlock_t shm_lock; 637 spinlock_t shm_lock;
635 638
636 /* We can only have one operating inte 639 /* We can only have one operating interface (802.11 core)
637 * at a time. General information abou 640 * at a time. General information about this interface follows.
638 */ 641 */
639 642
640 struct ieee80211_vif *vif; 643 struct ieee80211_vif *vif;
641 /* The MAC address of the operating in 644 /* The MAC address of the operating interface. */
642 u8 mac_addr[ETH_ALEN]; 645 u8 mac_addr[ETH_ALEN];
643 /* Current BSSID */ 646 /* Current BSSID */
644 u8 bssid[ETH_ALEN]; 647 u8 bssid[ETH_ALEN];
645 /* Interface type. (IEEE80211_IF_TYPE_ 648 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
646 int if_type; 649 int if_type;
647 /* Is the card operating in AP, STA or 650 /* Is the card operating in AP, STA or IBSS mode? */
648 bool operating; 651 bool operating;
649 /* filter flags */ 652 /* filter flags */
650 unsigned int filter_flags; 653 unsigned int filter_flags;
651 /* Stats about the wireless interface 654 /* Stats about the wireless interface */
652 struct ieee80211_low_level_stats ieee_ 655 struct ieee80211_low_level_stats ieee_stats;
653 656
654 struct hwrng rng; 657 struct hwrng rng;
655 u8 rng_initialized; 658 u8 rng_initialized;
656 char rng_name[30 + 1]; 659 char rng_name[30 + 1];
657 660
658 /* The RF-kill button */ 661 /* The RF-kill button */
659 struct b43_rfkill rfkill; 662 struct b43_rfkill rfkill;
660 663
661 /* List of all wireless devices on thi 664 /* List of all wireless devices on this chip */
662 struct list_head devlist; 665 struct list_head devlist;
663 u8 nr_devs; 666 u8 nr_devs;
664 667
665 bool radiotap_enabled; 668 bool radiotap_enabled;
666 669
667 /* The beacon we are currently using ( 670 /* The beacon we are currently using (AP or IBSS mode).
668 * This beacon stuff is protected by t 671 * This beacon stuff is protected by the irq_lock. */
669 struct sk_buff *current_beacon; 672 struct sk_buff *current_beacon;
670 bool beacon0_uploaded; 673 bool beacon0_uploaded;
671 bool beacon1_uploaded; 674 bool beacon1_uploaded;
672 }; 675 };
673 676
674 /* In-memory representation of a cached microc 677 /* In-memory representation of a cached microcode file. */
675 struct b43_firmware_file { 678 struct b43_firmware_file {
676 const char *filename; 679 const char *filename;
677 const struct firmware *data; 680 const struct firmware *data;
678 }; 681 };
679 682
680 /* Pointers to the firmware data and meta info 683 /* Pointers to the firmware data and meta information about it. */
681 struct b43_firmware { 684 struct b43_firmware {
682 /* Microcode */ 685 /* Microcode */
683 struct b43_firmware_file ucode; 686 struct b43_firmware_file ucode;
684 /* PCM code */ 687 /* PCM code */
685 struct b43_firmware_file pcm; 688 struct b43_firmware_file pcm;
686 /* Initial MMIO values for the firmwar 689 /* Initial MMIO values for the firmware */
687 struct b43_firmware_file initvals; 690 struct b43_firmware_file initvals;
688 /* Initial MMIO values for the firmwar 691 /* Initial MMIO values for the firmware, band-specific */
689 struct b43_firmware_file initvals_band 692 struct b43_firmware_file initvals_band;
690 693
691 /* Firmware revision */ 694 /* Firmware revision */
692 u16 rev; 695 u16 rev;
693 /* Firmware patchlevel */ 696 /* Firmware patchlevel */
694 u16 patch; 697 u16 patch;
695 }; 698 };
696 699
697 /* Device (802.11 core) initialization status. 700 /* Device (802.11 core) initialization status. */
698 enum { 701 enum {
699 B43_STAT_UNINIT = 0, /* Uninitializ 702 B43_STAT_UNINIT = 0, /* Uninitialized. */
700 B43_STAT_INITIALIZED = 1, /* Ini 703 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
701 B43_STAT_STARTED = 2, /* Up and runn 704 B43_STAT_STARTED = 2, /* Up and running. */
702 }; 705 };
703 #define b43_status(wldev) atomic 706 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
704 #define b43_set_status(wldev, stat) do { 707 #define b43_set_status(wldev, stat) do { \
705 atomic_set(&(wldev)->__init_st 708 atomic_set(&(wldev)->__init_status, (stat)); \
706 smp_wmb(); 709 smp_wmb(); \
707 } whil 710 } while (0)
708 711
709 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX 712 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX
710 * 713 *
711 * You should always acquire both, wl->mutex a 714 * You should always acquire both, wl->mutex and wl->irq_lock unless:
712 * - You don't need to acquire wl->irq_lock, i 715 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
713 * - You don't need to acquire wl->mutex in th 716 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
714 * and packet TX path (and _ONLY_ there.) 717 * and packet TX path (and _ONLY_ there.)
715 */ 718 */
716 719
717 /* Data structure for one wireless device (802 720 /* Data structure for one wireless device (802.11 core) */
718 struct b43_wldev { 721 struct b43_wldev {
719 struct ssb_device *dev; 722 struct ssb_device *dev;
720 struct b43_wl *wl; 723 struct b43_wl *wl;
721 724
722 /* The device initialization status. 725 /* The device initialization status.
723 * Use b43_status() to query. */ 726 * Use b43_status() to query. */
724 atomic_t __init_status; 727 atomic_t __init_status;
725 /* Saved init status for handling susp 728 /* Saved init status for handling suspend. */
726 int suspend_init_status; 729 int suspend_init_status;
727 730
728 bool bad_frames_preempt; /* Use 731 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
729 bool dfq_valid; /* Directed fr 732 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
730 bool short_preamble; /* TRUE, if sh 733 bool short_preamble; /* TRUE, if short preamble is enabled. */
731 bool short_slot; /* TRUE, if sh 734 bool short_slot; /* TRUE, if short slot timing is enabled. */
732 bool radio_hw_enable; /* saved state 735 bool radio_hw_enable; /* saved state of radio hardware enabled state */
733 bool suspend_in_progress; /* TRU 736 bool suspend_in_progress; /* TRUE, if we are in a suspend/resume cycle */
734 737
735 /* PHY/Radio device. */ 738 /* PHY/Radio device. */
736 struct b43_phy phy; 739 struct b43_phy phy;
737 740
738 /* DMA engines. */ 741 /* DMA engines. */
739 struct b43_dma dma; 742 struct b43_dma dma;
740 743
741 /* Various statistics about the physic 744 /* Various statistics about the physical device. */
742 struct b43_stats stats; 745 struct b43_stats stats;
743 746
744 /* The device LEDs. */ 747 /* The device LEDs. */
745 struct b43_led led_tx; 748 struct b43_led led_tx;
746 struct b43_led led_rx; 749 struct b43_led led_rx;
747 struct b43_led led_assoc; 750 struct b43_led led_assoc;
748 struct b43_led led_radio; 751 struct b43_led led_radio;
749 752
750 /* Reason code of the last interrupt. 753 /* Reason code of the last interrupt. */
751 u32 irq_reason; 754 u32 irq_reason;
752 u32 dma_reason[6]; 755 u32 dma_reason[6];
753 /* saved irq enable/disable state bitf 756 /* saved irq enable/disable state bitfield. */
754 u32 irq_savedstate; 757 u32 irq_savedstate;
755 /* Link Quality calculation context. * 758 /* Link Quality calculation context. */
756 struct b43_noise_calculation noisecalc 759 struct b43_noise_calculation noisecalc;
757 /* if > 0 MAC is suspended. if == 0 MA 760 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
758 int mac_suspended; 761 int mac_suspended;
759 762
760 /* Interrupt Service Routine tasklet ( 763 /* Interrupt Service Routine tasklet (bottom-half) */
761 struct tasklet_struct isr_tasklet; 764 struct tasklet_struct isr_tasklet;
762 765
763 /* Periodic tasks */ 766 /* Periodic tasks */
764 struct delayed_work periodic_work; 767 struct delayed_work periodic_work;
765 unsigned int periodic_state; 768 unsigned int periodic_state;
766 769
767 struct work_struct restart_work; 770 struct work_struct restart_work;
768 771
769 /* encryption/decryption */ 772 /* encryption/decryption */
770 u16 ktp; /* Key table p 773 u16 ktp; /* Key table pointer */
771 u8 max_nr_keys; 774 u8 max_nr_keys;
772 struct b43_key key[58]; 775 struct b43_key key[58];
773 776
774 /* Firmware data */ 777 /* Firmware data */
775 struct b43_firmware fw; 778 struct b43_firmware fw;
776 779
777 /* Devicelist in struct b43_wl (all 80 780 /* Devicelist in struct b43_wl (all 802.11 cores) */
778 struct list_head list; 781 struct list_head list;
779 782
780 /* Debugging stuff follows. */ 783 /* Debugging stuff follows. */
781 #ifdef CONFIG_B43_DEBUG 784 #ifdef CONFIG_B43_DEBUG
782 struct b43_dfsentry *dfsentry; 785 struct b43_dfsentry *dfsentry;
783 #endif 786 #endif
784 }; 787 };
785 788
786 static inline struct b43_wl *hw_to_b43_wl(stru 789 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
787 { 790 {
788 return hw->priv; 791 return hw->priv;
789 } 792 }
790 793
791 static inline struct b43_wldev *dev_to_b43_wld 794 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
792 { 795 {
793 struct ssb_device *ssb_dev = dev_to_ss 796 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
794 return ssb_get_drvdata(ssb_dev); 797 return ssb_get_drvdata(ssb_dev);
795 } 798 }
796 799
797 /* Is the device operating in a specified mode 800 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
798 static inline int b43_is_mode(struct b43_wl *w 801 static inline int b43_is_mode(struct b43_wl *wl, int type)
799 { 802 {
800 return (wl->operating && wl->if_type = 803 return (wl->operating && wl->if_type == type);
801 } 804 }
802 805
803 static inline u16 b43_read16(struct b43_wldev 806 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
804 { 807 {
805 return ssb_read16(dev->dev, offset); 808 return ssb_read16(dev->dev, offset);
806 } 809 }
807 810
808 static inline void b43_write16(struct b43_wlde 811 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
809 { 812 {
810 ssb_write16(dev->dev, offset, value); 813 ssb_write16(dev->dev, offset, value);
811 } 814 }
812 815
813 static inline u32 b43_read32(struct b43_wldev 816 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
814 { 817 {
815 return ssb_read32(dev->dev, offset); 818 return ssb_read32(dev->dev, offset);
816 } 819 }
817 820
818 static inline void b43_write32(struct b43_wlde 821 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
819 { 822 {
820 ssb_write32(dev->dev, offset, value); 823 ssb_write32(dev->dev, offset, value);
821 } 824 }
822 825
823 /* Message printing */ 826 /* Message printing */
824 void b43info(struct b43_wl *wl, const char *fm 827 void b43info(struct b43_wl *wl, const char *fmt, ...)
825 __attribute__ ((format(printf, 2, 3))); 828 __attribute__ ((format(printf, 2, 3)));
826 void b43err(struct b43_wl *wl, const char *fmt 829 void b43err(struct b43_wl *wl, const char *fmt, ...)
827 __attribute__ ((format(printf, 2, 3))); 830 __attribute__ ((format(printf, 2, 3)));
828 void b43warn(struct b43_wl *wl, const char *fm 831 void b43warn(struct b43_wl *wl, const char *fmt, ...)
829 __attribute__ ((format(printf, 2, 3))); 832 __attribute__ ((format(printf, 2, 3)));
830 #if B43_DEBUG 833 #if B43_DEBUG
831 void b43dbg(struct b43_wl *wl, const char *fmt 834 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
832 __attribute__ ((format(printf, 2, 3))); 835 __attribute__ ((format(printf, 2, 3)));
833 #else /* DEBUG */ 836 #else /* DEBUG */
834 # define b43dbg(wl, fmt...) do { /* nothing */ 837 # define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
835 #endif /* DEBUG */ 838 #endif /* DEBUG */
836 839
837 /* A WARN_ON variant that vanishes when b43 de 840 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
838 * This _also_ evaluates the arg with debuggin 841 * This _also_ evaluates the arg with debugging disabled. */
839 #if B43_DEBUG 842 #if B43_DEBUG
840 # define B43_WARN_ON(x) WARN_ON(x) 843 # define B43_WARN_ON(x) WARN_ON(x)
841 #else 844 #else
842 static inline bool __b43_warn_on_dummy(bool x) 845 static inline bool __b43_warn_on_dummy(bool x) { return x; }
843 # define B43_WARN_ON(x) __b43_warn_on_dummy(un 846 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
844 #endif 847 #endif
845 848
846 /** Limit a value between two limits */ 849 /** Limit a value between two limits */
847 #ifdef limit_value 850 #ifdef limit_value
848 # undef limit_value 851 # undef limit_value
849 #endif 852 #endif
850 #define limit_value(value, min, max) \ 853 #define limit_value(value, min, max) \
851 ({ 854 ({ \
852 typeof(value) __value = (value 855 typeof(value) __value = (value); \
853 typeof(value) __min = (min); 856 typeof(value) __min = (min); \
854 typeof(value) __max = (max); 857 typeof(value) __max = (max); \
855 if (__value < __min) 858 if (__value < __min) \
856 __value = __min; 859 __value = __min; \
857 else if (__value > __max) 860 else if (__value > __max) \
858 __value = __max; 861 __value = __max; \
859 __value; 862 __value; \
860 }) 863 })
861 864
862 /* Convert an integer to a Q5.2 value */ 865 /* Convert an integer to a Q5.2 value */
863 #define INT_TO_Q52(i) ((i) << 2) 866 #define INT_TO_Q52(i) ((i) << 2)
864 /* Convert a Q5.2 value to an integer (precisi 867 /* Convert a Q5.2 value to an integer (precision loss!) */
865 #define Q52_TO_INT(q52) ((q52) >> 2) 868 #define Q52_TO_INT(q52) ((q52) >> 2)
866 /* Macros for printing a value in Q5.2 format 869 /* Macros for printing a value in Q5.2 format */
867 #define Q52_FMT "%u.%u" 870 #define Q52_FMT "%u.%u"
868 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q 871 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
869 872
870 #endif /* B43_H_ */ 873 #endif /* B43_H_ */
871 874
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