Diff markup
1 #ifndef B43_H_ 1
2 #define B43_H_
3
4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h>
10
11 #include "debugfs.h"
12 #include "leds.h"
13 #include "rfkill.h"
14 #include "lo.h"
15 #include "phy.h"
16
17
18 /* The unique identifier of the firmware that'
19 * this driver version. */
20 #define B43_SUPPORTED_FIRMWARE_ID "FW13"
21
22
23 #ifdef CONFIG_B43_DEBUG
24 # define B43_DEBUG 1
25 #else
26 # define B43_DEBUG 0
27 #endif
28
29 #define B43_RX_MAX_SSI 60
30
31 /* MMIO offsets */
32 #define B43_MMIO_DMA0_REASON 0x20
33 #define B43_MMIO_DMA0_IRQ_MASK 0x24
34 #define B43_MMIO_DMA1_REASON 0x28
35 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
36 #define B43_MMIO_DMA2_REASON 0x30
37 #define B43_MMIO_DMA2_IRQ_MASK 0x34
38 #define B43_MMIO_DMA3_REASON 0x38
39 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
40 #define B43_MMIO_DMA4_REASON 0x40
41 #define B43_MMIO_DMA4_IRQ_MASK 0x44
42 #define B43_MMIO_DMA5_REASON 0x48
43 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
44 #define B43_MMIO_MACCTL 0x120
45 #define B43_MMIO_MACCMD 0x124
46 #define B43_MMIO_GEN_IRQ_REASON 0x128
47 #define B43_MMIO_GEN_IRQ_MASK 0x12C
48 #define B43_MMIO_RAM_CONTROL 0x130
49 #define B43_MMIO_RAM_DATA 0x134
50 #define B43_MMIO_PS_STATUS 0x140
51 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
52 #define B43_MMIO_SHM_CONTROL 0x160
53 #define B43_MMIO_SHM_DATA 0x164
54 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
55 #define B43_MMIO_XMITSTAT_0 0x170
56 #define B43_MMIO_XMITSTAT_1 0x174
57 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180
58 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184
59 #define B43_MMIO_TSF_CFP_REP 0x188
60 #define B43_MMIO_TSF_CFP_START 0x18C
61 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
62
63 /* 32-bit DMA */
64 #define B43_MMIO_DMA32_BASE0 0x200
65 #define B43_MMIO_DMA32_BASE1 0x220
66 #define B43_MMIO_DMA32_BASE2 0x240
67 #define B43_MMIO_DMA32_BASE3 0x260
68 #define B43_MMIO_DMA32_BASE4 0x280
69 #define B43_MMIO_DMA32_BASE5 0x2A0
70 /* 64-bit DMA */
71 #define B43_MMIO_DMA64_BASE0 0x200
72 #define B43_MMIO_DMA64_BASE1 0x240
73 #define B43_MMIO_DMA64_BASE2 0x280
74 #define B43_MMIO_DMA64_BASE3 0x2C0
75 #define B43_MMIO_DMA64_BASE4 0x300
76 #define B43_MMIO_DMA64_BASE5 0x340
77
78 #define B43_MMIO_PHY_VER 0x3E0
79 #define B43_MMIO_PHY_RADIO 0x3E2
80 #define B43_MMIO_PHY0 0x3E6
81 #define B43_MMIO_ANTENNA 0x3E8
82 #define B43_MMIO_CHANNEL 0x3F0
83 #define B43_MMIO_CHANNEL_EXT 0x3F4
84 #define B43_MMIO_RADIO_CONTROL 0x3F6
85 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
86 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
87 #define B43_MMIO_PHY_CONTROL 0x3FC
88 #define B43_MMIO_PHY_DATA 0x3FE
89 #define B43_MMIO_MACFILTER_CONTROL 0x420
90 #define B43_MMIO_MACFILTER_DATA 0x422
91 #define B43_MMIO_RCMTA_COUNT 0x43C
92 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
93 #define B43_MMIO_GPIO_CONTROL 0x49C
94 #define B43_MMIO_GPIO_MASK 0x49E
95 #define B43_MMIO_TSF_CFP_START_LOW 0x604
96 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
97 #define B43_MMIO_TSF_0 0x632
98 #define B43_MMIO_TSF_1 0x634
99 #define B43_MMIO_TSF_2 0x636
100 #define B43_MMIO_TSF_3 0x638
101 #define B43_MMIO_RNG 0x65A
102 #define B43_MMIO_POWERUP_DELAY 0x6A8
103
104 /* SPROM boardflags_lo values */
105 #define B43_BFL_BTCOEXIST 0x0001
106 #define B43_BFL_PACTRL 0x0002
107 #define B43_BFL_AIRLINEMODE 0x0004
108 #define B43_BFL_RSSI 0x0008
109 #define B43_BFL_ENETSPI 0x0010
110 #define B43_BFL_XTAL_NOSLOW 0x0020
111 #define B43_BFL_CCKHIPWR 0x0040
112 #define B43_BFL_ENETADM 0x0080
113 #define B43_BFL_ENETVLAN 0x0100
114 #define B43_BFL_AFTERBURNER 0x0200
115 #define B43_BFL_NOPCI 0x0400
116 #define B43_BFL_FEM 0x0800
117 #define B43_BFL_EXTLNA 0x1000
118 #define B43_BFL_HGPA 0x2000
119 #define B43_BFL_BTCMOD 0x4000
120 #define B43_BFL_ALTIQ 0x8000
121
122 /* GPIO register offset, in both ChipCommon an
123 #define B43_GPIO_CONTROL 0x6c
124
125 /* SHM Routing */
126 enum {
127 B43_SHM_UCODE, /* Microcode m
128 B43_SHM_SHARED, /* Shared memo
129 B43_SHM_SCRATCH, /* Scratch mem
130 B43_SHM_HW, /* Internal ha
131 B43_SHM_RCMTA, /* Receive mat
132 };
133 /* SHM Routing modifiers */
134 #define B43_SHM_AUTOINC_R 0x0200
135 #define B43_SHM_AUTOINC_W 0x0100
136 #define B43_SHM_AUTOINC_RW (B43_S
137 B43_S
138
139 /* Misc SHM_SHARED offsets */
140 #define B43_SHM_SH_WLCOREREV 0x0016
141 #define B43_SHM_SH_PCTLWDPOS 0x0008
142 #define B43_SHM_SH_RXPADOFF 0x0034
143 #define B43_SHM_SH_PHYVER 0x0050
144 #define B43_SHM_SH_PHYTYPE 0x0052
145 #define B43_SHM_SH_ANTSWAP 0x005C
146 #define B43_SHM_SH_HOSTFLO 0x005E
147 #define B43_SHM_SH_HOSTFHI 0x0060
148 #define B43_SHM_SH_RFATT 0x0064
149 #define B43_SHM_SH_RADAR 0x0066
150 #define B43_SHM_SH_PHYTXNOI 0x006E
151 #define B43_SHM_SH_RFRXSP1 0x0072
152 #define B43_SHM_SH_CHAN 0x00A0
153 #define B43_SHM_SH_CHAN_5GHZ 0x0100
154 #define B43_SHM_SH_BCMCFIFOID 0x0108
155 /* SHM_SHARED TX FIFO variables */
156 #define B43_SHM_SH_SIZE01 0x0098
157 #define B43_SHM_SH_SIZE23 0x009A
158 #define B43_SHM_SH_SIZE45 0x009C
159 #define B43_SHM_SH_SIZE67 0x009E
160 /* SHM_SHARED background noise */
161 #define B43_SHM_SH_JSSI0 0x0088
162 #define B43_SHM_SH_JSSI1 0x008A
163 #define B43_SHM_SH_JSSIAUX 0x008C
164 /* SHM_SHARED crypto engine */
165 #define B43_SHM_SH_DEFAULTIV 0x003C
166 #define B43_SHM_SH_NRRXTRANS 0x003E
167 #define B43_SHM_SH_KTP 0x0056
168 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
169 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4
170 #define B43_SHM_SH_PSM 0x05F4
171 /* SHM_SHARED WME variables */
172 #define B43_SHM_SH_EDCFSTAT 0x000E
173 #define B43_SHM_SH_TXFCUR 0x0030
174 #define B43_SHM_SH_EDCFQ 0x0240
175 /* SHM_SHARED powersave mode related */
176 #define B43_SHM_SH_SLOTT 0x0010
177 #define B43_SHM_SH_DTIMPER 0x0012
178 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C
179 /* SHM_SHARED beacon/AP variables */
180 #define B43_SHM_SH_BTL0 0x0018
181 #define B43_SHM_SH_BTL1 0x001A
182 #define B43_SHM_SH_BTSFOFF 0x001C
183 #define B43_SHM_SH_TIMBPOS 0x001E
184 #define B43_SHM_SH_DTIMP 0x0012
185 #define B43_SHM_SH_MCASTCOOKIE 0x00A8
186 #define B43_SHM_SH_SFFBLIM 0x0044
187 #define B43_SHM_SH_LFFBLIM 0x0046
188 #define B43_SHM_SH_BEACPHYCTL 0x0054
189 #define B43_SHM_SH_EXTNPHYCTL 0x00B0
190 /* SHM_SHARED ACK/CTS control */
191 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022
192 /* SHM_SHARED probe response variables */
193 #define B43_SHM_SH_PRSSID 0x0160
194 #define B43_SHM_SH_PRSSIDLEN 0x0048
195 #define B43_SHM_SH_PRTLEN 0x004A
196 #define B43_SHM_SH_PRMAXTIME 0x0074
197 #define B43_SHM_SH_PRPHYCTL 0x0188
198 /* SHM_SHARED rate tables */
199 #define B43_SHM_SH_OFDMDIRECT 0x01C0
200 #define B43_SHM_SH_OFDMBASIC 0x01E0
201 #define B43_SHM_SH_CCKDIRECT 0x0200
202 #define B43_SHM_SH_CCKBASIC 0x0220
203 /* SHM_SHARED microcode soft registers */
204 #define B43_SHM_SH_UCODEREV 0x0000
205 #define B43_SHM_SH_UCODEPATCH 0x0002
206 #define B43_SHM_SH_UCODEDATE 0x0004
207 #define B43_SHM_SH_UCODETIME 0x0006
208 #define B43_SHM_SH_UCODESTAT 0x0040
209 #define B43_SHM_SH_UCODESTAT_INVALID 0
210 #define B43_SHM_SH_UCODESTAT_INIT 1
211 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
212 #define B43_SHM_SH_UCODESTAT_SUSP 3
213 #define B43_SHM_SH_UCODESTAT_SLEEP 4
214 #define B43_SHM_SH_MAXBFRAMES 0x0080
215 #define B43_SHM_SH_SPUWKUP 0x0094
216 #define B43_SHM_SH_PRETBTT 0x0096
217
218 /* SHM_SCRATCH offsets */
219 #define B43_SHM_SC_MINCONT 0x0003
220 #define B43_SHM_SC_MAXCONT 0x0004
221 #define B43_SHM_SC_CURCONT 0x0005
222 #define B43_SHM_SC_SRLIMIT 0x0006
223 #define B43_SHM_SC_LRLIMIT 0x0007
224 #define B43_SHM_SC_DTIMC 0x0008
225 #define B43_SHM_SC_BTL0LEN 0x0015
226 #define B43_SHM_SC_BTL1LEN 0x0016
227 #define B43_SHM_SC_SCFB 0x0017
228 #define B43_SHM_SC_LCFB 0x0018
229
230 /* Hardware Radio Enable masks */
231 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 <<
232 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 <<
233
234 /* HostFlags. See b43_hf_read/write() */
235 #define B43_HF_ANTDIVHELP 0x0000
236 #define B43_HF_SYMW 0x0000
237 #define B43_HF_RXPULLW 0x0000
238 #define B43_HF_CCKBOOST 0x0000
239 #define B43_HF_BTCOEX 0x0000
240 #define B43_HF_GDCW 0x0000
241 #define B43_HF_OFDMPABOOST 0x0000
242 #define B43_HF_ACPR 0x0000
243 #define B43_HF_EDCF 0x0000
244 #define B43_HF_TSSIRPSMW 0x0000
245 #define B43_HF_DSCRQ 0x0000
246 #define B43_HF_ACIW 0x0000
247 #define B43_HF_2060W 0x0000
248 #define B43_HF_RADARW 0x0000
249 #define B43_HF_USEDEFKEYS 0x0000
250 #define B43_HF_BT4PRIOCOEX 0x0001
251 #define B43_HF_FWKUP 0x0002
252 #define B43_HF_VCORECALC 0x0004
253 #define B43_HF_PCISCW 0x0008
254 #define B43_HF_4318TSSI 0x0020
255 #define B43_HF_FBCMCFIFO 0x0040
256 #define B43_HF_HWPCTL 0x0080
257 #define B43_HF_BTCOEXALT 0x0100
258 #define B43_HF_TXBTCHECK 0x0200
259 #define B43_HF_SKCFPUP 0x0400
260
261 /* MacFilter offsets. */
262 #define B43_MACFILTER_SELF 0x0000
263 #define B43_MACFILTER_BSSID 0x0003
264
265 /* PowerControl */
266 #define B43_PCTL_IN 0xB0
267 #define B43_PCTL_OUT 0xB4
268 #define B43_PCTL_OUTENABLE 0xB8
269 #define B43_PCTL_XTAL_POWERUP 0x40
270 #define B43_PCTL_PLL_POWERDOWN 0x80
271
272 /* PowerControl Clock Modes */
273 #define B43_PCTL_CLK_FAST 0x00
274 #define B43_PCTL_CLK_SLOW 0x01
275 #define B43_PCTL_CLK_DYNAMIC 0x02
276
277 #define B43_PCTL_FORCE_SLOW 0x0800
278 #define B43_PCTL_FORCE_PLL 0x1000
279 #define B43_PCTL_DYN_XTAL 0x2000
280
281 /* PHYVersioning */
282 #define B43_PHYTYPE_A 0x00
283 #define B43_PHYTYPE_B 0x01
284 #define B43_PHYTYPE_G 0x02
285 #define B43_PHYTYPE_N 0x04
286 #define B43_PHYTYPE_LP 0x05
287
288 /* PHYRegisters */
289 #define B43_PHY_ILT_A_CTRL 0x0072
290 #define B43_PHY_ILT_A_DATA1 0x0073
291 #define B43_PHY_ILT_A_DATA2 0x0074
292 #define B43_PHY_G_LO_CONTROL 0x0810
293 #define B43_PHY_ILT_G_CTRL 0x0472
294 #define B43_PHY_ILT_G_DATA1 0x0473
295 #define B43_PHY_ILT_G_DATA2 0x0474
296 #define B43_PHY_A_PCTL 0x007B
297 #define B43_PHY_G_PCTL 0x0029
298 #define B43_PHY_A_CRS 0x0029
299 #define B43_PHY_RADIO_BITFIELD 0x0401
300 #define B43_PHY_G_CRS 0x0429
301 #define B43_PHY_NRSSILT_CTRL 0x0803
302 #define B43_PHY_NRSSILT_DATA 0x0804
303
304 /* RadioRegisters */
305 #define B43_RADIOCTL_ID 0x01
306
307 /* MAC Control bitfield */
308 #define B43_MACCTL_ENABLED 0x0000
309 #define B43_MACCTL_PSM_RUN 0x0000
310 #define B43_MACCTL_PSM_JMP0 0x0000
311 #define B43_MACCTL_SHM_ENABLED 0x0000
312 #define B43_MACCTL_SHM_UPPER 0x0000
313 #define B43_MACCTL_IHR_ENABLED 0x0000
314 #define B43_MACCTL_PSM_DBG 0x0000
315 #define B43_MACCTL_GPOUTSMSK 0x0000
316 #define B43_MACCTL_BE 0x0001
317 #define B43_MACCTL_INFRA 0x0002
318 #define B43_MACCTL_AP 0x0004
319 #define B43_MACCTL_RADIOLOCK 0x0008
320 #define B43_MACCTL_BEACPROMISC 0x0010
321 #define B43_MACCTL_KEEP_BADPLCP 0x0020
322 #define B43_MACCTL_KEEP_CTL 0x0040
323 #define B43_MACCTL_KEEP_BAD 0x0080
324 #define B43_MACCTL_PROMISC 0x0100
325 #define B43_MACCTL_HWPS 0x0200
326 #define B43_MACCTL_AWAKE 0x0400
327 #define B43_MACCTL_CLOSEDNET 0x0800
328 #define B43_MACCTL_TBTTHOLD 0x1000
329 #define B43_MACCTL_DISCTXSTAT 0x2000
330 #define B43_MACCTL_DISCPMQ 0x4000
331 #define B43_MACCTL_GMODE 0x8000
332
333 /* MAC Command bitfield */
334 #define B43_MACCMD_BEACON0_VALID 0x0000
335 #define B43_MACCMD_BEACON1_VALID 0x0000
336 #define B43_MACCMD_DFQ_VALID 0x0000
337 #define B43_MACCMD_CCA 0x0000
338 #define B43_MACCMD_BGNOISE 0x0000
339
340 /* 802.11 core specific TM State Low (SSB_TMSL
341 #define B43_TMSLOW_GMODE 0x2000
342 #define B43_TMSLOW_PHYCLKSPEED 0x00C0
343 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x0000
344 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x0040
345 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x0080
346 #define B43_TMSLOW_PLLREFSEL 0x0020
347 #define B43_TMSLOW_MACPHYCLKEN 0x0010
348 #define B43_TMSLOW_PHYRESET 0x0008
349 #define B43_TMSLOW_PHYCLKEN 0x0004
350
351 /* 802.11 core specific TM State High (SSB_TMS
352 #define B43_TMSHIGH_DUALBAND_PHY 0x0008
353 #define B43_TMSHIGH_FCLOCK 0x0004
354 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x0002
355 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x0001
356
357 /* Generic-Interrupt reasons. */
358 #define B43_IRQ_MAC_SUSPENDED 0x0000
359 #define B43_IRQ_BEACON 0x0000
360 #define B43_IRQ_TBTT_INDI 0x0000
361 #define B43_IRQ_BEACON_TX_OK 0x0000
362 #define B43_IRQ_BEACON_CANCEL 0x0000
363 #define B43_IRQ_ATIM_END 0x0000
364 #define B43_IRQ_PMQ 0x0000
365 #define B43_IRQ_PIO_WORKAROUND 0x0000
366 #define B43_IRQ_MAC_TXERR 0x0000
367 #define B43_IRQ_PHY_TXERR 0x0000
368 #define B43_IRQ_PMEVENT 0x0000
369 #define B43_IRQ_TIMER0 0x0000
370 #define B43_IRQ_TIMER1 0x0000
371 #define B43_IRQ_DMA 0x0000
372 #define B43_IRQ_TXFIFO_FLUSH_OK 0x0001
373 #define B43_IRQ_CCA_MEASURE_OK 0x0002
374 #define B43_IRQ_NOISESAMPLE_OK 0x0004
375 #define B43_IRQ_UCODE_DEBUG 0x0800
376 #define B43_IRQ_RFKILL 0x1000
377 #define B43_IRQ_TX_OK 0x2000
378 #define B43_IRQ_PHY_G_CHANGED 0x4000
379 #define B43_IRQ_TIMEOUT 0x8000
380
381 #define B43_IRQ_ALL 0xFFFF
382 #define B43_IRQ_MASKTEMPLATE (B43_I
383 B43_I
384 B43_I
385 B43_I
386 B43_I
387 B43_I
388 B43_I
389 B43_I
390 B43_I
391 B43_I
392 B43_I
393 B43_I
394 B43_I
395
396 /* Device specific rate values.
397 * The actual values defined here are (rate_in
398 * Some code depends on this. Don't change it.
399 #define B43_CCK_RATE_1MB 0x02
400 #define B43_CCK_RATE_2MB 0x04
401 #define B43_CCK_RATE_5MB 0x0B
402 #define B43_CCK_RATE_11MB 0x16
403 #define B43_OFDM_RATE_6MB 0x0C
404 #define B43_OFDM_RATE_9MB 0x12
405 #define B43_OFDM_RATE_12MB 0x18
406 #define B43_OFDM_RATE_18MB 0x24
407 #define B43_OFDM_RATE_24MB 0x30
408 #define B43_OFDM_RATE_36MB 0x48
409 #define B43_OFDM_RATE_48MB 0x60
410 #define B43_OFDM_RATE_54MB 0x6C
411 /* Convert a b43 rate value to a rate in 100kb
412 #define B43_RATE_TO_BASE100KBPS(rate) (((rat
413
414 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
415 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
416
417 #define B43_PHY_TX_BADNESS_LIMIT 1000
418
419 /* Max size of a security key */
420 #define B43_SEC_KEYSIZE 16
421 /* Security algorithms. */
422 enum {
423 B43_SEC_ALGO_NONE = 0, /* unencrypted
424 B43_SEC_ALGO_WEP40,
425 B43_SEC_ALGO_TKIP,
426 B43_SEC_ALGO_AES,
427 B43_SEC_ALGO_WEP104,
428 B43_SEC_ALGO_AES_LEGACY,
429 };
430
431 struct b43_dmaring;
432 struct b43_pioqueue;
433
434 /* The firmware file header */
435 #define B43_FW_TYPE_UCODE 'u'
436 #define B43_FW_TYPE_PCM 'p'
437 #define B43_FW_TYPE_IV 'i'
438 struct b43_fw_header {
439 /* File type */
440 u8 type;
441 /* File format version */
442 u8 ver;
443 u8 __padding[2];
444 /* Size of the data. For ucode and PCM
445 * For IV this is number-of-ivs. */
446 __be32 size;
447 } __attribute__((__packed__));
448
449 /* Initial Value file format */
450 #define B43_IV_OFFSET_MASK 0x7FFF
451 #define B43_IV_32BIT 0x8000
452 struct b43_iv {
453 __be16 offset_size;
454 union {
455 __be16 d16;
456 __be32 d32;
457 } data __attribute__((__packed__));
458 } __attribute__((__packed__));
459
460
461 #define B43_PHYMODE(phytype) (1 <<
462 #define B43_PHYMODE_A B43_PH
463 #define B43_PHYMODE_B B43_PH
464 #define B43_PHYMODE_G B43_PH
465
466 struct b43_phy {
467 /* Possible PHYMODEs on this PHY */
468 u8 possible_phymodes;
469 /* GMODE bit enabled? */
470 bool gmode;
471 /* Possible ieee80211 subsystem hwmode
472 * Which mode is selected, depends on
473 #define B43_MAX_PHYHWMODES 2
474 struct ieee80211_hw_mode hwmodes[B43_M
475
476 /* Analog Type */
477 u8 analog;
478 /* B43_PHYTYPE_ */
479 u8 type;
480 /* PHY revision number. */
481 u8 rev;
482
483 /* Radio versioning */
484 u16 radio_manuf; /* Radio manuf
485 u16 radio_ver; /* Radio versi
486 u8 radio_rev; /* Radio revis
487
488 bool dyn_tssi_tbl; /* tssi2dbm is
489
490 /* ACI (adjacent channel interference)
491 bool aci_enable;
492 bool aci_wlan_automatic;
493 bool aci_hw_rssi;
494
495 /* Radio switched on/off */
496 bool radio_on;
497 struct {
498 /* Values saved when turning t
499 * They are needed when turnin
500 bool valid;
501 u16 rfover;
502 u16 rfoverval;
503 } radio_off_context;
504
505 u16 minlowsig[2];
506 u16 minlowsigpos[2];
507
508 /* TSSI to dBm table in use */
509 const s8 *tssi2dbm;
510 /* Target idle TSSI */
511 int tgt_idle_tssi;
512 /* Current idle TSSI */
513 int cur_idle_tssi;
514
515 /* LocalOscillator control values. */
516 struct b43_txpower_lo_control *lo_cont
517 /* Values from b43_calc_loopback_gain(
518 s16 max_lb_gain; /* Maximum Loo
519 s16 trsw_rx_gain; /* TRSW RX gai
520 s16 lna_lod_gain; /* LNA lod */
521 s16 lna_gain; /* LNA */
522 s16 pga_gain; /* PGA */
523
524 /* Desired TX power level (in dBm).
525 * This is set by the user and adjuste
526 u8 power_level;
527 /* A-PHY TX Power control value. */
528 u16 txpwr_offset;
529
530 /* Current TX power level attenuation
531 struct b43_bbatt bbatt;
532 struct b43_rfatt rfatt;
533 u8 tx_control; /* B43_TXCTL_X
534
535 /* Hardware Power Control enabled? */
536 bool hardware_power_control;
537
538 /* Current Interference Mitigation mod
539 int interfmode;
540 /* Stack of saved values from the Inte
541 * Each value in the stack is layed ou
542 * bit 0-11: offset
543 * bit 12-15: register ID
544 * bit 16-32: value
545 * register ID is: 0x1 PHY, 0x2 Radio,
546 */
547 #define B43_INTERFSTACK_SIZE 26
548 u32 interfstack[B43_INTERFSTACK_SIZE];
549
550 /* Saved values from the NRSSI Slope c
551 s16 nrssi[2];
552 s32 nrssislope;
553 /* In memory nrssi lookup table. */
554 s8 nrssi_lt[64];
555
556 /* current channel */
557 u8 channel;
558
559 u16 lofcal;
560
561 u16 initval; //FIXME rename
562
563 /* PHY TX errors counter. */
564 atomic_t txerr_cnt;
565
566 /* The device does address auto increm
567 * We cache the previously used addres
568 * write on the next table access, if
569 u16 ofdmtab_addr; /* The address curre
570 enum { /* The last data flow direction
571 B43_OFDMTAB_DIRECTION_UNKNOWN
572 B43_OFDMTAB_DIRECTION_READ,
573 B43_OFDMTAB_DIRECTION_WRITE,
574 } ofdmtab_addr_direction;
575
576 #if B43_DEBUG
577 /* Manual TX-power control enabled? */
578 bool manual_txpower_control;
579 /* PHY registers locked by b43_phy_loc
580 bool phy_locked;
581 #endif /* B43_DEBUG */
582 };
583
584 /* Data structures for DMA transmission, per 8
585 struct b43_dma {
586 struct b43_dmaring *tx_ring0;
587 struct b43_dmaring *tx_ring1;
588 struct b43_dmaring *tx_ring2;
589 struct b43_dmaring *tx_ring3;
590 struct b43_dmaring *tx_ring4;
591 struct b43_dmaring *tx_ring5;
592
593 struct b43_dmaring *rx_ring0;
594 struct b43_dmaring *rx_ring3; /* onl
595 };
596
597 /* Context information for a noise calculation
598 struct b43_noise_calculation {
599 u8 channel_at_start;
600 bool calculation_running;
601 u8 nr_samples;
602 s8 samples[8][4];
603 };
604
605 struct b43_stats {
606 u8 link_noise;
607 /* Store the last TX/RX times here for
608 unsigned long last_tx;
609 unsigned long last_rx;
610 };
611
612 struct b43_key {
613 /* If keyconf is NULL, this key is dis
614 * keyconf is a cookie. Don't derefenr
615 * path, because b43 doesn't own it. *
616 struct ieee80211_key_conf *keyconf;
617 u8 algorithm;
618 };
619
620 struct b43_wldev;
621
622 /* Data structure for the WLAN parts (802.11 c
623 struct b43_wl {
624 /* Pointer to the active wireless devi
625 struct b43_wldev *current_dev;
626 /* Pointer to the ieee80211 hardware d
627 struct ieee80211_hw *hw;
628
629 struct mutex mutex;
630 spinlock_t irq_lock;
631 /* Lock for LEDs access. */
632 spinlock_t leds_lock;
633 /* Lock for SHM access. */
634 spinlock_t shm_lock;
635
636 /* We can only have one operating inte
637 * at a time. General information abou
638 */
639
640 struct ieee80211_vif *vif;
641 /* The MAC address of the operating in
642 u8 mac_addr[ETH_ALEN];
643 /* Current BSSID */
644 u8 bssid[ETH_ALEN];
645 /* Interface type. (IEEE80211_IF_TYPE_
646 int if_type;
647 /* Is the card operating in AP, STA or
648 bool operating;
649 /* filter flags */
650 unsigned int filter_flags;
651 /* Stats about the wireless interface
652 struct ieee80211_low_level_stats ieee_
653
654 struct hwrng rng;
655 u8 rng_initialized;
656 char rng_name[30 + 1];
657
658 /* The RF-kill button */
659 struct b43_rfkill rfkill;
660
661 /* List of all wireless devices on thi
662 struct list_head devlist;
663 u8 nr_devs;
664
665 bool radiotap_enabled;
666
667 /* The beacon we are currently using (
668 * This beacon stuff is protected by t
669 struct sk_buff *current_beacon;
670 bool beacon0_uploaded;
671 bool beacon1_uploaded;
672 };
673
674 /* In-memory representation of a cached microc
675 struct b43_firmware_file {
676 const char *filename;
677 const struct firmware *data;
678 };
679
680 /* Pointers to the firmware data and meta info
681 struct b43_firmware {
682 /* Microcode */
683 struct b43_firmware_file ucode;
684 /* PCM code */
685 struct b43_firmware_file pcm;
686 /* Initial MMIO values for the firmwar
687 struct b43_firmware_file initvals;
688 /* Initial MMIO values for the firmwar
689 struct b43_firmware_file initvals_band
690
691 /* Firmware revision */
692 u16 rev;
693 /* Firmware patchlevel */
694 u16 patch;
695 };
696
697 /* Device (802.11 core) initialization status.
698 enum {
699 B43_STAT_UNINIT = 0, /* Uninitializ
700 B43_STAT_INITIALIZED = 1, /* Ini
701 B43_STAT_STARTED = 2, /* Up and runn
702 };
703 #define b43_status(wldev) atomic
704 #define b43_set_status(wldev, stat) do {
705 atomic_set(&(wldev)->__init_st
706 smp_wmb();
707 } whil
708
709 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX
710 *
711 * You should always acquire both, wl->mutex a
712 * - You don't need to acquire wl->irq_lock, i
713 * - You don't need to acquire wl->mutex in th
714 * and packet TX path (and _ONLY_ there.)
715 */
716
717 /* Data structure for one wireless device (802
718 struct b43_wldev {
719 struct ssb_device *dev;
720 struct b43_wl *wl;
721
722 /* The device initialization status.
723 * Use b43_status() to query. */
724 atomic_t __init_status;
725 /* Saved init status for handling susp
726 int suspend_init_status;
727
728 bool bad_frames_preempt; /* Use
729 bool dfq_valid; /* Directed fr
730 bool short_preamble; /* TRUE, if sh
731 bool short_slot; /* TRUE, if sh
732 bool radio_hw_enable; /* saved state
733 bool suspend_in_progress; /* TRU
734
735 /* PHY/Radio device. */
736 struct b43_phy phy;
737
738 /* DMA engines. */
739 struct b43_dma dma;
740
741 /* Various statistics about the physic
742 struct b43_stats stats;
743
744 /* The device LEDs. */
745 struct b43_led led_tx;
746 struct b43_led led_rx;
747 struct b43_led led_assoc;
748 struct b43_led led_radio;
749
750 /* Reason code of the last interrupt.
751 u32 irq_reason;
752 u32 dma_reason[6];
753 /* saved irq enable/disable state bitf
754 u32 irq_savedstate;
755 /* Link Quality calculation context. *
756 struct b43_noise_calculation noisecalc
757 /* if > 0 MAC is suspended. if == 0 MA
758 int mac_suspended;
759
760 /* Interrupt Service Routine tasklet (
761 struct tasklet_struct isr_tasklet;
762
763 /* Periodic tasks */
764 struct delayed_work periodic_work;
765 unsigned int periodic_state;
766
767 struct work_struct restart_work;
768
769 /* encryption/decryption */
770 u16 ktp; /* Key table p
771 u8 max_nr_keys;
772 struct b43_key key[58];
773
774 /* Firmware data */
775 struct b43_firmware fw;
776
777 /* Devicelist in struct b43_wl (all 80
778 struct list_head list;
779
780 /* Debugging stuff follows. */
781 #ifdef CONFIG_B43_DEBUG
782 struct b43_dfsentry *dfsentry;
783 #endif
784 };
785
786 static inline struct b43_wl *hw_to_b43_wl(stru
787 {
788 return hw->priv;
789 }
790
791 static inline struct b43_wldev *dev_to_b43_wld
792 {
793 struct ssb_device *ssb_dev = dev_to_ss
794 return ssb_get_drvdata(ssb_dev);
795 }
796
797 /* Is the device operating in a specified mode
798 static inline int b43_is_mode(struct b43_wl *w
799 {
800 return (wl->operating && wl->if_type =
801 }
802
803 static inline u16 b43_read16(struct b43_wldev
804 {
805 return ssb_read16(dev->dev, offset);
806 }
807
808 static inline void b43_write16(struct b43_wlde
809 {
810 ssb_write16(dev->dev, offset, value);
811 }
812
813 static inline u32 b43_read32(struct b43_wldev
814 {
815 return ssb_read32(dev->dev, offset);
816 }
817
818 static inline void b43_write32(struct b43_wlde
819 {
820 ssb_write32(dev->dev, offset, value);
821 }
822
823 /* Message printing */
824 void b43info(struct b43_wl *wl, const char *fm
825 __attribute__ ((format(printf, 2, 3)));
826 void b43err(struct b43_wl *wl, const char *fmt
827 __attribute__ ((format(printf, 2, 3)));
828 void b43warn(struct b43_wl *wl, const char *fm
829 __attribute__ ((format(printf, 2, 3)));
830 #if B43_DEBUG
831 void b43dbg(struct b43_wl *wl, const char *fmt
832 __attribute__ ((format(printf, 2, 3)));
833 #else /* DEBUG */
834 # define b43dbg(wl, fmt...) do { /* nothing */
835 #endif /* DEBUG */
836
837 /* A WARN_ON variant that vanishes when b43 de
838 * This _also_ evaluates the arg with debuggin
839 #if B43_DEBUG
840 # define B43_WARN_ON(x) WARN_ON(x)
841 #else
842 static inline bool __b43_warn_on_dummy(bool x)
843 # define B43_WARN_ON(x) __b43_warn_on_dummy(un
844 #endif
845
846 /** Limit a value between two limits */
847 #ifdef limit_value
848 # undef limit_value
849 #endif
850 #define limit_value(value, min, max) \
851 ({
852 typeof(value) __value = (value
853 typeof(value) __min = (min);
854 typeof(value) __max = (max);
855 if (__value < __min)
856 __value = __min;
857 else if (__value > __max)
858 __value = __max;
859 __value;
860 })
861
862 /* Convert an integer to a Q5.2 value */
863 #define INT_TO_Q52(i) ((i) << 2)
864 /* Convert a Q5.2 value to an integer (precisi
865 #define Q52_TO_INT(q52) ((q52) >> 2)
866 /* Macros for printing a value in Q5.2 format
867 #define Q52_FMT "%u.%u"
868 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q
869
870 #endif /* B43_H_ */
871
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