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1 /* 1 /*
2 * 3c359.h (c) 2000 Mike Phillips (mikep@linu 2 * 3c359.h (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 * 3 *
4 * Linux driver for 3Com 3C359 Token Link PCI 4 * Linux driver for 3Com 3C359 Token Link PCI XL cards.
5 * 5 *
6 * This software may be used and distributed 6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License Version 7 * of the GNU General Public License Version 2 or (at your option)
8 * any later verion, incorporated herein by r 8 * any later verion, incorporated herein by reference.
9 */ 9 */
10 10
11 /* Memory Access Commands */ 11 /* Memory Access Commands */
12 #define IO_BYTE_READ 0x28 << 24 12 #define IO_BYTE_READ 0x28 << 24
13 #define IO_BYTE_WRITE 0x18 << 24 13 #define IO_BYTE_WRITE 0x18 << 24
14 #define IO_WORD_READ 0x20 << 24 14 #define IO_WORD_READ 0x20 << 24
15 #define IO_WORD_WRITE 0x10 << 24 15 #define IO_WORD_WRITE 0x10 << 24
16 #define MMIO_BYTE_READ 0x88 << 24 16 #define MMIO_BYTE_READ 0x88 << 24
17 #define MMIO_BYTE_WRITE 0x48 << 24 17 #define MMIO_BYTE_WRITE 0x48 << 24
18 #define MMIO_WORD_READ 0x80 << 24 18 #define MMIO_WORD_READ 0x80 << 24
19 #define MMIO_WORD_WRITE 0x40 << 24 19 #define MMIO_WORD_WRITE 0x40 << 24
20 #define MEM_BYTE_READ 0x8C << 24 20 #define MEM_BYTE_READ 0x8C << 24
21 #define MEM_BYTE_WRITE 0x4C << 24 21 #define MEM_BYTE_WRITE 0x4C << 24
22 #define MEM_WORD_READ 0x84 << 24 22 #define MEM_WORD_READ 0x84 << 24
23 #define MEM_WORD_WRITE 0x44 << 24 23 #define MEM_WORD_WRITE 0x44 << 24
24 24
25 #define PMBAR 0x1C80 25 #define PMBAR 0x1C80
26 #define PMB_CPHOLD (1<<10) 26 #define PMB_CPHOLD (1<<10)
27 27
28 #define CPATTENTION 0x180D 28 #define CPATTENTION 0x180D
29 #define CPA_PMBARVIS (1<<7) 29 #define CPA_PMBARVIS (1<<7)
30 #define CPA_MEMWREN (1<<6) 30 #define CPA_MEMWREN (1<<6)
31 31
32 #define SWITCHSETTINGS 0x1C88 32 #define SWITCHSETTINGS 0x1C88
33 #define EECONTROL 0x1C8A 33 #define EECONTROL 0x1C8A
34 #define EEDATA 0x1C8C 34 #define EEDATA 0x1C8C
35 #define EEREAD 0x0080 35 #define EEREAD 0x0080
36 #define EEWRITE 0x0040 36 #define EEWRITE 0x0040
37 #define EEERASE 0x0060 37 #define EEERASE 0x0060
38 #define EE_ENABLE_WRITE 0x0030 38 #define EE_ENABLE_WRITE 0x0030
39 #define EEBUSY (1<<15) 39 #define EEBUSY (1<<15)
40 40
41 #define WRBR 0xCDE02 41 #define WRBR 0xCDE02
42 #define WWOR 0xCDE04 42 #define WWOR 0xCDE04
43 #define WWCR 0xCDE06 43 #define WWCR 0xCDE06
44 #define MACSTATUS 0xCDE08 44 #define MACSTATUS 0xCDE08
45 #define MISR_RW 0xCDE0B 45 #define MISR_RW 0xCDE0B
46 #define MISR_AND 0xCDE2B 46 #define MISR_AND 0xCDE2B
47 #define MISR_SET 0xCDE4B 47 #define MISR_SET 0xCDE4B
48 #define RXBUFAREA 0xCDE10 48 #define RXBUFAREA 0xCDE10
49 #define RXEARLYTHRESH 0xCDE12 49 #define RXEARLYTHRESH 0xCDE12
50 #define TXSTARTTHRESH 0x58 50 #define TXSTARTTHRESH 0x58
51 #define DNPRIREQTHRESH 0x2C 51 #define DNPRIREQTHRESH 0x2C
52 52
53 #define MISR_CSRB (1<<5) 53 #define MISR_CSRB (1<<5)
54 #define MISR_RASB (1<<4) 54 #define MISR_RASB (1<<4)
55 #define MISR_SRBFR (1<<3) 55 #define MISR_SRBFR (1<<3)
56 #define MISR_ASBFR (1<<2) 56 #define MISR_ASBFR (1<<2)
57 #define MISR_ARBF (1<<1) 57 #define MISR_ARBF (1<<1)
58 58
59 /* MISR Flags memory locations */ 59 /* MISR Flags memory locations */
60 #define MF_SSBF 0xDFFE0 60 #define MF_SSBF 0xDFFE0
61 #define MF_ARBF 0xDFFE1 61 #define MF_ARBF 0xDFFE1
62 #define MF_ASBFR 0xDFFE2 62 #define MF_ASBFR 0xDFFE2
63 #define MF_SRBFR 0xDFFE3 63 #define MF_SRBFR 0xDFFE3
64 #define MF_RASB 0xDFFE4 64 #define MF_RASB 0xDFFE4
65 #define MF_CSRB 0xDFFE5 65 #define MF_CSRB 0xDFFE5
66 66
67 #define MMIO_MACDATA 0x10 67 #define MMIO_MACDATA 0x10
68 #define MMIO_MAC_ACCESS_CMD 0x14 68 #define MMIO_MAC_ACCESS_CMD 0x14
69 #define MMIO_TIMER 0x1A 69 #define MMIO_TIMER 0x1A
70 #define MMIO_DMA_CTRL 0x20 70 #define MMIO_DMA_CTRL 0x20
71 #define MMIO_DNLISTPTR 0x24 71 #define MMIO_DNLISTPTR 0x24
72 #define MMIO_HASHFILTER 0x28 72 #define MMIO_HASHFILTER 0x28
73 #define MMIO_CONFIG 0x29 73 #define MMIO_CONFIG 0x29
74 #define MMIO_DNPRIREQTHRESH 0x2C 74 #define MMIO_DNPRIREQTHRESH 0x2C
75 #define MMIO_DNPOLL 0x2D 75 #define MMIO_DNPOLL 0x2D
76 #define MMIO_UPPKTSTATUS 0x30 76 #define MMIO_UPPKTSTATUS 0x30
77 #define MMIO_FREETIMER 0x34 77 #define MMIO_FREETIMER 0x34
78 #define MMIO_COUNTDOWN 0x36 78 #define MMIO_COUNTDOWN 0x36
79 #define MMIO_UPLISTPTR 0x38 79 #define MMIO_UPLISTPTR 0x38
80 #define MMIO_UPPOLL 0x3C 80 #define MMIO_UPPOLL 0x3C
81 #define MMIO_UPBURSTTHRESH 0x40 81 #define MMIO_UPBURSTTHRESH 0x40
82 #define MMIO_DNBURSTTHRESH 0x41 82 #define MMIO_DNBURSTTHRESH 0x41
83 #define MMIO_INTSTATUS_AUTO 0x56 83 #define MMIO_INTSTATUS_AUTO 0x56
84 #define MMIO_TXSTARTTHRESH 0x58 84 #define MMIO_TXSTARTTHRESH 0x58
85 #define MMIO_INTERRUPTENABLE 0x5A 85 #define MMIO_INTERRUPTENABLE 0x5A
86 #define MMIO_INDICATIONENABLE 0x5C 86 #define MMIO_INDICATIONENABLE 0x5C
87 #define MMIO_COMMAND 0x5E /* These two are me 87 #define MMIO_COMMAND 0x5E /* These two are meant to be the same */
88 #define MMIO_INTSTATUS 0x5E /* Makes the code 88 #define MMIO_INTSTATUS 0x5E /* Makes the code more readable this way */
89 #define INTSTAT_CMD_IN_PROGRESS (1<<12) 89 #define INTSTAT_CMD_IN_PROGRESS (1<<12)
90 #define INTSTAT_SRB (1<<14) 90 #define INTSTAT_SRB (1<<14)
91 #define INTSTAT_INTLATCH (1<<0) 91 #define INTSTAT_INTLATCH (1<<0)
92 92
93 /* Indication / Interrupt Mask 93 /* Indication / Interrupt Mask
94 * Annoyingly the bits to be set in the indica 94 * Annoyingly the bits to be set in the indication and interrupt enable
95 * do not match with the actual bits received 95 * do not match with the actual bits received in the interrupt, although
96 * they are in the same order. 96 * they are in the same order.
97 * The mapping for the indication / interrupt 97 * The mapping for the indication / interrupt are:
98 * Bit Indication / Interrupt 98 * Bit Indication / Interrupt
99 * 0 HostError 99 * 0 HostError
100 * 1 txcomplete 100 * 1 txcomplete
101 * 2 updneeded 101 * 2 updneeded
102 * 3 rxcomplete 102 * 3 rxcomplete
103 * 4 intrequested 103 * 4 intrequested
104 * 5 macerror 104 * 5 macerror
105 * 6 dncomplete 105 * 6 dncomplete
106 * 7 upcomplete 106 * 7 upcomplete
107 * 8 txunderrun 107 * 8 txunderrun
108 * 9 asbf 108 * 9 asbf
109 * 10 srbr 109 * 10 srbr
110 * 11 arbc 110 * 11 arbc
111 * 111 *
112 * The only ones we don't want to receive are 112 * The only ones we don't want to receive are txcomplete and rxcomplete
113 * we use dncomplete and upcomplete instead. 113 * we use dncomplete and upcomplete instead.
114 */ 114 */
115 115
116 #define INT_MASK 0xFF5 116 #define INT_MASK 0xFF5
117 117
118 /* Note the subtle difference here, IND and IN 118 /* Note the subtle difference here, IND and INT */
119 119
120 #define SETINDENABLE (8<<12) 120 #define SETINDENABLE (8<<12)
121 #define SETINTENABLE (7<<12) 121 #define SETINTENABLE (7<<12)
122 #define SRBBIT (1<<10) 122 #define SRBBIT (1<<10)
123 #define ASBBIT (1<<9) 123 #define ASBBIT (1<<9)
124 #define ARBBIT (1<<11) 124 #define ARBBIT (1<<11)
125 125
126 #define SRB 0xDFE90 126 #define SRB 0xDFE90
127 #define ASB 0xDFED0 127 #define ASB 0xDFED0
128 #define ARB 0xD0000 128 #define ARB 0xD0000
129 #define SCRATCH 0xDFEF0 129 #define SCRATCH 0xDFEF0
130 130
131 #define INT_REQUEST 0x6000 /* (6 << 12) */ 131 #define INT_REQUEST 0x6000 /* (6 << 12) */
132 #define ACK_INTERRUPT 0x6800 /* (13 <<11) */ 132 #define ACK_INTERRUPT 0x6800 /* (13 <<11) */
133 #define GLOBAL_RESET 0x00 133 #define GLOBAL_RESET 0x00
134 #define DNDISABLE 0x5000 134 #define DNDISABLE 0x5000
135 #define DNENABLE 0x4800 135 #define DNENABLE 0x4800
136 #define DNSTALL 0x3002 136 #define DNSTALL 0x3002
137 #define DNRESET 0x5800 137 #define DNRESET 0x5800
138 #define DNUNSTALL 0x3003 138 #define DNUNSTALL 0x3003
139 #define UPRESET 0x2800 139 #define UPRESET 0x2800
140 #define UPSTALL 0x3000 140 #define UPSTALL 0x3000
141 #define UPUNSTALL 0x3001 141 #define UPUNSTALL 0x3001
142 #define SETCONFIG 0x4000 142 #define SETCONFIG 0x4000
143 #define SETTXSTARTTHRESH 0x9800 143 #define SETTXSTARTTHRESH 0x9800
144 144
145 /* Received Interrupts */ 145 /* Received Interrupts */
146 #define ASBFINT (1<<13) 146 #define ASBFINT (1<<13)
147 #define SRBRINT (1<<14) 147 #define SRBRINT (1<<14)
148 #define ARBCINT (1<<15) 148 #define ARBCINT (1<<15)
149 #define TXUNDERRUN (1<<11) 149 #define TXUNDERRUN (1<<11)
150 150
151 #define UPCOMPINT (1<<10) 151 #define UPCOMPINT (1<<10)
152 #define DNCOMPINT (1<<9) 152 #define DNCOMPINT (1<<9)
153 #define HARDERRINT (1<<7) 153 #define HARDERRINT (1<<7)
154 #define RXCOMPLETE (1<<4) 154 #define RXCOMPLETE (1<<4)
155 #define TXCOMPINT (1<<2) 155 #define TXCOMPINT (1<<2)
156 #define HOSTERRINT (1<<1) 156 #define HOSTERRINT (1<<1)
157 157
158 /* Receive descriptor bits */ 158 /* Receive descriptor bits */
159 #define RXOVERRUN cpu_to_le32(1<<19) 159 #define RXOVERRUN cpu_to_le32(1<<19)
160 #define RXFC cpu_to_le32(1<<21) 160 #define RXFC cpu_to_le32(1<<21)
161 #define RXAR cpu_to_le32(1<<22) 161 #define RXAR cpu_to_le32(1<<22)
162 #define RXUPDCOMPLETE cpu_to_le32(1<<23) 162 #define RXUPDCOMPLETE cpu_to_le32(1<<23)
163 #define RXUPDFULL cpu_to_le32(1<<24) 163 #define RXUPDFULL cpu_to_le32(1<<24)
164 #define RXUPLASTFRAG cpu_to_le32(1<<31) 164 #define RXUPLASTFRAG cpu_to_le32(1<<31)
165 165
166 /* Transmit descriptor bits */ 166 /* Transmit descriptor bits */
167 #define TXDNCOMPLETE cpu_to_le32(1<<16) 167 #define TXDNCOMPLETE cpu_to_le32(1<<16)
168 #define TXTXINDICATE cpu_to_le32(1<<27) 168 #define TXTXINDICATE cpu_to_le32(1<<27)
169 #define TXDPDEMPTY cpu_to_le32(1<<29) 169 #define TXDPDEMPTY cpu_to_le32(1<<29)
170 #define TXDNINDICATE cpu_to_le32(1<<31) 170 #define TXDNINDICATE cpu_to_le32(1<<31)
171 #define TXDNFRAGLAST cpu_to_le32(1<<31) 171 #define TXDNFRAGLAST cpu_to_le32(1<<31)
172 172
173 /* Interrupts to Acknowledge */ 173 /* Interrupts to Acknowledge */
174 #define LATCH_ACK 1 174 #define LATCH_ACK 1
175 #define TXCOMPACK (1<<1) 175 #define TXCOMPACK (1<<1)
176 #define INTREQACK (1<<2) 176 #define INTREQACK (1<<2)
177 #define DNCOMPACK (1<<3) 177 #define DNCOMPACK (1<<3)
178 #define UPCOMPACK (1<<4) 178 #define UPCOMPACK (1<<4)
179 #define ASBFACK (1<<5) 179 #define ASBFACK (1<<5)
180 #define SRBRACK (1<<6) 180 #define SRBRACK (1<<6)
181 #define ARBCACK (1<<7) 181 #define ARBCACK (1<<7)
182 182
183 #define XL_IO_SPACE 128 183 #define XL_IO_SPACE 128
184 #define SRB_COMMAND_SIZE 50 184 #define SRB_COMMAND_SIZE 50
185 185
186 /* Adapter Commands */ 186 /* Adapter Commands */
187 #define REQUEST_INT 0x00 187 #define REQUEST_INT 0x00
188 #define MODIFY_OPEN_PARMS 0x01 188 #define MODIFY_OPEN_PARMS 0x01
189 #define RESTORE_OPEN_PARMS 0x02 189 #define RESTORE_OPEN_PARMS 0x02
190 #define OPEN_NIC 0x03 190 #define OPEN_NIC 0x03
191 #define CLOSE_NIC 0x04 191 #define CLOSE_NIC 0x04
192 #define SET_SLEEP_MODE 0x05 192 #define SET_SLEEP_MODE 0x05
193 #define SET_GROUP_ADDRESS 0x06 193 #define SET_GROUP_ADDRESS 0x06
194 #define SET_FUNC_ADDRESS 0x07 194 #define SET_FUNC_ADDRESS 0x07
195 #define READ_LOG 0x08 195 #define READ_LOG 0x08
196 #define SET_MULTICAST_MODE 0x0C 196 #define SET_MULTICAST_MODE 0x0C
197 #define CHANGE_WAKEUP_PATTERN 0x0D 197 #define CHANGE_WAKEUP_PATTERN 0x0D
198 #define GET_STATISTICS 0x13 198 #define GET_STATISTICS 0x13
199 #define SET_RECEIVE_MODE 0x1F 199 #define SET_RECEIVE_MODE 0x1F
200 200
201 /* ARB Commands */ 201 /* ARB Commands */
202 #define RECEIVE_DATA 0x81 202 #define RECEIVE_DATA 0x81
203 #define RING_STATUS_CHANGE 0x84 203 #define RING_STATUS_CHANGE 0x84
204 204
205 /* ASB Commands */ 205 /* ASB Commands */
206 #define ASB_RECEIVE_DATE 0x81 206 #define ASB_RECEIVE_DATE 0x81
207 207
208 /* Defines for LAN STATUS CHANGE reports */ 208 /* Defines for LAN STATUS CHANGE reports */
209 #define LSC_SIG_LOSS 0x8000 209 #define LSC_SIG_LOSS 0x8000
210 #define LSC_HARD_ERR 0x4000 210 #define LSC_HARD_ERR 0x4000
211 #define LSC_SOFT_ERR 0x2000 211 #define LSC_SOFT_ERR 0x2000
212 #define LSC_TRAN_BCN 0x1000 212 #define LSC_TRAN_BCN 0x1000
213 #define LSC_LWF 0x0800 213 #define LSC_LWF 0x0800
214 #define LSC_ARW 0x0400 214 #define LSC_ARW 0x0400
215 #define LSC_FPE 0x0200 215 #define LSC_FPE 0x0200
216 #define LSC_RR 0x0100 216 #define LSC_RR 0x0100
217 #define LSC_CO 0x0080 217 #define LSC_CO 0x0080
218 #define LSC_SS 0x0040 218 #define LSC_SS 0x0040
219 #define LSC_RING_REC 0x0020 219 #define LSC_RING_REC 0x0020
220 #define LSC_SR_CO 0x0010 220 #define LSC_SR_CO 0x0010
221 #define LSC_FDX_MODE 0x0004 221 #define LSC_FDX_MODE 0x0004
222 222
223 #define XL_MAX_ADAPTERS 8 /* 0x08 __MODULE_STR 223 #define XL_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
224 224
225 /* 3c359 defaults for buffers */ 225 /* 3c359 defaults for buffers */
226 226
227 #define XL_RX_RING_SIZE 16 /* must be a power 227 #define XL_RX_RING_SIZE 16 /* must be a power of 2 */
228 #define XL_TX_RING_SIZE 16 /* must be a power 228 #define XL_TX_RING_SIZE 16 /* must be a power of 2 */
229 229
230 #define PKT_BUF_SZ 4096 /* Default packet size 230 #define PKT_BUF_SZ 4096 /* Default packet size */
231 231
232 /* 3c359 data structures */ 232 /* 3c359 data structures */
233 233
234 struct xl_tx_desc { 234 struct xl_tx_desc {
235 __le32 dnnextptr; 235 __le32 dnnextptr;
236 __le32 framestartheader; 236 __le32 framestartheader;
237 __le32 buffer; 237 __le32 buffer;
238 __le32 buffer_length; 238 __le32 buffer_length;
239 }; 239 };
240 240
241 struct xl_rx_desc { 241 struct xl_rx_desc {
242 __le32 upnextptr; 242 __le32 upnextptr;
243 __le32 framestatus; 243 __le32 framestatus;
244 __le32 upfragaddr; 244 __le32 upfragaddr;
245 __le32 upfraglen; 245 __le32 upfraglen;
246 }; 246 };
247 247
248 struct xl_private { 248 struct xl_private {
249 249
250 250
251 /* These two structures must be aligne 251 /* These two structures must be aligned on 8 byte boundaries */
252 252
253 /* struct xl_rx_desc xl_rx_ring[XL_RX_ 253 /* struct xl_rx_desc xl_rx_ring[XL_RX_RING_SIZE]; */
254 /* struct xl_tx_desc xl_tx_ring[XL_TX_ 254 /* struct xl_tx_desc xl_tx_ring[XL_TX_RING_SIZE]; */
255 struct xl_rx_desc *xl_rx_ring ; 255 struct xl_rx_desc *xl_rx_ring ;
256 struct xl_tx_desc *xl_tx_ring ; 256 struct xl_tx_desc *xl_tx_ring ;
257 struct sk_buff *tx_ring_skb[XL_TX_RING 257 struct sk_buff *tx_ring_skb[XL_TX_RING_SIZE], *rx_ring_skb[XL_RX_RING_SIZE];
258 int tx_ring_head, tx_ring_tail ; 258 int tx_ring_head, tx_ring_tail ;
259 int rx_ring_tail, rx_ring_no ; 259 int rx_ring_tail, rx_ring_no ;
260 int free_ring_entries ; 260 int free_ring_entries ;
261 261
262 u16 srb; 262 u16 srb;
263 u16 arb; 263 u16 arb;
264 u16 asb; 264 u16 asb;
265 265
266 u8 __iomem *xl_mmio; 266 u8 __iomem *xl_mmio;
267 char *xl_card_name; !! 267 const char *xl_card_name;
268 struct pci_dev *pdev ; 268 struct pci_dev *pdev ;
269 269
270 spinlock_t xl_lock ; 270 spinlock_t xl_lock ;
271 271
272 volatile int srb_queued; 272 volatile int srb_queued;
273 struct wait_queue *srb_wait; 273 struct wait_queue *srb_wait;
274 volatile int asb_queued; 274 volatile int asb_queued;
275 275
276 struct net_device_stats xl_stats ; <<
277 <<
278 u16 mac_buffer ; 276 u16 mac_buffer ;
279 u16 xl_lan_status ; 277 u16 xl_lan_status ;
280 u8 xl_ring_speed ; 278 u8 xl_ring_speed ;
281 u16 pkt_buf_sz ; 279 u16 pkt_buf_sz ;
282 u8 xl_message_level; 280 u8 xl_message_level;
283 u16 xl_copy_all_options ; 281 u16 xl_copy_all_options ;
284 unsigned char xl_functional_addr[4] ; 282 unsigned char xl_functional_addr[4] ;
285 u16 xl_addr_table_addr, xl_parms_addr 283 u16 xl_addr_table_addr, xl_parms_addr ;
286 u8 xl_laa[6] ; 284 u8 xl_laa[6] ;
287 u32 rx_ring_dma_addr ; 285 u32 rx_ring_dma_addr ;
288 u32 tx_ring_dma_addr ; 286 u32 tx_ring_dma_addr ;
>> 287
>> 288 /* firmware section */
>> 289 const struct firmware *fw;
289 }; 290 };
290 291
291 292
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