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1 /*-------------------------------------------- 1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx s 2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 . 3 .
4 . Copyright (C) 1996 by Erik Stahlman 4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Co 5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corp 6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, In 7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre 8 . Unified SMC91x driver by Nicolas Pitre
9 . 9 .
10 . This program is free software; you can redi 10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Publi 11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either versio 12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version. 13 . (at your option) any later version.
14 . 14 .
15 . This program is distributed in the hope tha 15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the 16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR 17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details 18 . GNU General Public License for more details.
19 . 19 .
20 . You should have received a copy of the GNU 20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to t 21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 33 22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 . 23 .
24 . Information contained in this file was obta 24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you rea 25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com. 26 . information under www.smsc.com.
27 . 27 .
28 . Authors 28 . Authors
29 . Erik Stahlman <erik@vt.edu> 29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.c 30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org> 31 . Nicolas Pitre <nico@cam.org>
32 . 32 .
33 --------------------------------------------- 33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_ 34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_ 35 #define _SMC91X_H_
36 36
37 #include <linux/smc91x.h> <<
38 37
39 /* 38 /*
40 * Define your architecture specific bus confi 39 * Define your architecture specific bus configuration parameters here.
41 */ 40 */
42 41
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\ !! 42 #if defined(CONFIG_ARCH_LUBBOCK)
44 defined(CONFIG_MACH_MAINSTONE) ||\ <<
45 defined(CONFIG_MACH_ZYLONITE) ||\ <<
46 defined(CONFIG_MACH_LITTLETON) ||\ <<
47 defined(CONFIG_MACH_ZYLONITE2) ||\ <<
48 defined(CONFIG_ARCH_VIPER) ||\ <<
49 defined(CONFIG_MACH_STARGATE2) <<
50 43
51 #include <asm/mach-types.h> !! 44 /* We can only do 16-bit reads and writes in the static memory space. */
52 !! 45 #define SMC_CAN_USE_8BIT 0
53 /* Now the bus width is specified in the platf <<
54 * pretend here to support all I/O access type <<
55 */ <<
56 #define SMC_CAN_USE_8BIT 1 <<
57 #define SMC_CAN_USE_16BIT 1 46 #define SMC_CAN_USE_16BIT 1
58 #define SMC_CAN_USE_32BIT 1 !! 47 #define SMC_CAN_USE_32BIT 0
59 #define SMC_NOWAIT 1 48 #define SMC_NOWAIT 1
60 49
61 #define SMC_IO_SHIFT (lp->io_shift) !! 50 /* The first two address lines aren't connected... */
>> 51 #define SMC_IO_SHIFT 2
62 52
63 #define SMC_inb(a, r) readb((a) + (r <<
64 #define SMC_inw(a, r) readw((a) + (r 53 #define SMC_inw(a, r) readw((a) + (r))
65 #define SMC_inl(a, r) readl((a) + (r !! 54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
66 #define SMC_outb(v, a, r) writeb(v, (a) <<
67 #define SMC_outl(v, a, r) writel(v, (a) <<
68 #define SMC_insw(a, r, p, l) readsw((a) + ( 55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
69 #define SMC_outsw(a, r, p, l) writesw((a) + 56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
70 #define SMC_insl(a, r, p, l) readsl((a) + ( <<
71 #define SMC_outsl(a, r, p, l) writesl((a) + <<
72 #define SMC_IRQ_FLAGS (-1) /* fro 57 #define SMC_IRQ_FLAGS (-1) /* from resource */
73 58
74 /* We actually can't write halfwords properly <<
75 static inline void SMC_outw(u16 val, void __io <<
76 { <<
77 if ((machine_is_mainstone() || machine <<
78 unsigned int v = val << 16; <<
79 v |= readl(ioaddr + (reg & ~2) <<
80 writel(v, ioaddr + (reg & ~2)) <<
81 } else { <<
82 writew(val, ioaddr + reg); <<
83 } <<
84 } <<
85 <<
86 #elif defined(CONFIG_BLACKFIN) 59 #elif defined(CONFIG_BLACKFIN)
87 60
88 #define SMC_IRQ_FLAGS IRQF_TRIGGER_H 61 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
89 #define RPC_LSA_DEFAULT RPC_LED_100_10 62 #define RPC_LSA_DEFAULT RPC_LED_100_10
90 #define RPC_LSB_DEFAULT RPC_LED_TX_RX 63 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
91 64
>> 65 # if defined (CONFIG_BFIN561_EZKIT)
92 #define SMC_CAN_USE_8BIT 0 66 #define SMC_CAN_USE_8BIT 0
93 #define SMC_CAN_USE_16BIT 1 67 #define SMC_CAN_USE_16BIT 1
94 # if defined(CONFIG_BF561) <<
95 #define SMC_CAN_USE_32BIT 1 68 #define SMC_CAN_USE_32BIT 1
>> 69 #define SMC_IO_SHIFT 0
>> 70 #define SMC_NOWAIT 1
>> 71 #define SMC_USE_BFIN_DMA 0
>> 72
>> 73
>> 74 #define SMC_inw(a, r) readw((a) + (r))
>> 75 #define SMC_outw(v, a, r) writew(v, (a) + (r))
>> 76 #define SMC_inl(a, r) readl((a) + (r))
>> 77 #define SMC_outl(v, a, r) writel(v, (a) + (r))
>> 78 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
>> 79 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
96 # else 80 # else
>> 81 #define SMC_CAN_USE_8BIT 0
>> 82 #define SMC_CAN_USE_16BIT 1
97 #define SMC_CAN_USE_32BIT 0 83 #define SMC_CAN_USE_32BIT 0
98 # endif <<
99 #define SMC_IO_SHIFT 0 84 #define SMC_IO_SHIFT 0
100 #define SMC_NOWAIT 1 85 #define SMC_NOWAIT 1
101 #define SMC_USE_BFIN_DMA 0 86 #define SMC_USE_BFIN_DMA 0
102 87
103 #define SMC_inw(a, r) readw((a) + (r <<
104 #define SMC_outw(v, a, r) writew(v, (a) <<
105 #define SMC_insw(a, r, p, l) readsw((a) + ( <<
106 #define SMC_outsw(a, r, p, l) writesw((a) + <<
107 # if SMC_CAN_USE_32BIT <<
108 #define SMC_inl(a, r) readl((a) + (r <<
109 #define SMC_outl(v, a, r) writel(v, (a) <<
110 #define SMC_insl(a, r, p, l) readsl((a) + ( <<
111 #define SMC_outsl(a, r, p, l) writesl((a) + <<
112 # endif <<
113 88
>> 89 #define SMC_inw(a, r) readw((a) + (r))
>> 90 #define SMC_outw(v, a, r) writew(v, (a) + (r))
>> 91 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
>> 92 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
>> 93 # endif
>> 94 /* check if the mac in reg is valid */
>> 95 #define SMC_GET_MAC_ADDR(addr) \
>> 96 do { \
>> 97 unsigned int __v; \
>> 98 __v = SMC_inw(ioaddr, ADDR0_REG); \
>> 99 addr[0] = __v; addr[1] = __v >> 8; \
>> 100 __v = SMC_inw(ioaddr, ADDR1_REG); \
>> 101 addr[2] = __v; addr[3] = __v >> 8; \
>> 102 __v = SMC_inw(ioaddr, ADDR2_REG); \
>> 103 addr[4] = __v; addr[5] = __v >> 8; \
>> 104 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
>> 105 random_ether_addr(addr); \
>> 106 } \
>> 107 } while (0)
114 #elif defined(CONFIG_REDWOOD_5) || defined(CON 108 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
115 109
116 /* We can only do 16-bit reads and writes in t 110 /* We can only do 16-bit reads and writes in the static memory space. */
117 #define SMC_CAN_USE_8BIT 0 111 #define SMC_CAN_USE_8BIT 0
118 #define SMC_CAN_USE_16BIT 1 112 #define SMC_CAN_USE_16BIT 1
119 #define SMC_CAN_USE_32BIT 0 113 #define SMC_CAN_USE_32BIT 0
120 #define SMC_NOWAIT 1 114 #define SMC_NOWAIT 1
121 115
122 #define SMC_IO_SHIFT 0 116 #define SMC_IO_SHIFT 0
123 117
124 #define SMC_inw(a, r) in_be16((volat 118 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
125 #define SMC_outw(v, a, r) out_be16((vola 119 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
126 #define SMC_insw(a, r, p, l) 120 #define SMC_insw(a, r, p, l) \
127 do { 121 do { \
128 unsigned long __port = (a) + ( 122 unsigned long __port = (a) + (r); \
129 u16 *__p = (u16 *)(p); 123 u16 *__p = (u16 *)(p); \
130 int __l = (l); 124 int __l = (l); \
131 insw(__port, __p, __l); 125 insw(__port, __p, __l); \
132 while (__l > 0) { 126 while (__l > 0) { \
133 *__p = swab16(*__p); 127 *__p = swab16(*__p); \
134 __p++; 128 __p++; \
135 __l--; 129 __l--; \
136 } 130 } \
137 } while (0) 131 } while (0)
138 #define SMC_outsw(a, r, p, l) 132 #define SMC_outsw(a, r, p, l) \
139 do { 133 do { \
140 unsigned long __port = (a) + ( 134 unsigned long __port = (a) + (r); \
141 u16 *__p = (u16 *)(p); 135 u16 *__p = (u16 *)(p); \
142 int __l = (l); 136 int __l = (l); \
143 while (__l > 0) { 137 while (__l > 0) { \
144 /* Believe it or not, 138 /* Believe it or not, the swab isn't needed. */ \
145 outw( /* swab16 */ (*_ 139 outw( /* swab16 */ (*__p++), __port); \
146 __l--; 140 __l--; \
147 } 141 } \
148 } while (0) 142 } while (0)
149 #define SMC_IRQ_FLAGS (0) 143 #define SMC_IRQ_FLAGS (0)
150 144
151 #elif defined(CONFIG_SA1100_PLEB) 145 #elif defined(CONFIG_SA1100_PLEB)
152 /* We can only do 16-bit reads and writes in t 146 /* We can only do 16-bit reads and writes in the static memory space. */
153 #define SMC_CAN_USE_8BIT 1 147 #define SMC_CAN_USE_8BIT 1
154 #define SMC_CAN_USE_16BIT 1 148 #define SMC_CAN_USE_16BIT 1
155 #define SMC_CAN_USE_32BIT 0 149 #define SMC_CAN_USE_32BIT 0
156 #define SMC_IO_SHIFT 0 150 #define SMC_IO_SHIFT 0
157 #define SMC_NOWAIT 1 151 #define SMC_NOWAIT 1
158 152
159 #define SMC_inb(a, r) readb((a) + (r 153 #define SMC_inb(a, r) readb((a) + (r))
160 #define SMC_insb(a, r, p, l) readsb((a) + ( 154 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
161 #define SMC_inw(a, r) readw((a) + (r 155 #define SMC_inw(a, r) readw((a) + (r))
162 #define SMC_insw(a, r, p, l) readsw((a) + ( 156 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
163 #define SMC_outb(v, a, r) writeb(v, (a) 157 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
164 #define SMC_outsb(a, r, p, l) writesb((a) + 158 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
165 #define SMC_outw(v, a, r) writew(v, (a) 159 #define SMC_outw(v, a, r) writew(v, (a) + (r))
166 #define SMC_outsw(a, r, p, l) writesw((a) + 160 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
167 161
168 #define SMC_IRQ_FLAGS (-1) 162 #define SMC_IRQ_FLAGS (-1)
169 163
170 #elif defined(CONFIG_SA1100_ASSABET) 164 #elif defined(CONFIG_SA1100_ASSABET)
171 165
172 #include <mach/neponset.h> !! 166 #include <asm/arch/neponset.h>
173 167
174 /* We can only do 8-bit reads and writes in th 168 /* We can only do 8-bit reads and writes in the static memory space. */
175 #define SMC_CAN_USE_8BIT 1 169 #define SMC_CAN_USE_8BIT 1
176 #define SMC_CAN_USE_16BIT 0 170 #define SMC_CAN_USE_16BIT 0
177 #define SMC_CAN_USE_32BIT 0 171 #define SMC_CAN_USE_32BIT 0
178 #define SMC_NOWAIT 1 172 #define SMC_NOWAIT 1
179 173
180 /* The first two address lines aren't connecte 174 /* The first two address lines aren't connected... */
181 #define SMC_IO_SHIFT 2 175 #define SMC_IO_SHIFT 2
182 176
183 #define SMC_inb(a, r) readb((a) + (r 177 #define SMC_inb(a, r) readb((a) + (r))
184 #define SMC_outb(v, a, r) writeb(v, (a) 178 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
185 #define SMC_insb(a, r, p, l) readsb((a) + ( 179 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
186 #define SMC_outsb(a, r, p, l) writesb((a) + 180 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
187 #define SMC_IRQ_FLAGS (-1) /* fro 181 #define SMC_IRQ_FLAGS (-1) /* from resource */
188 182
189 #elif defined(CONFIG_MACH_LOGICPD_PXA270) \ !! 183 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
190 || defined(CONFIG_MACH_NOMADIK_8815NHK <<
191 184
192 #define SMC_CAN_USE_8BIT 0 185 #define SMC_CAN_USE_8BIT 0
193 #define SMC_CAN_USE_16BIT 1 186 #define SMC_CAN_USE_16BIT 1
194 #define SMC_CAN_USE_32BIT 0 187 #define SMC_CAN_USE_32BIT 0
195 #define SMC_IO_SHIFT 0 188 #define SMC_IO_SHIFT 0
196 #define SMC_NOWAIT 1 189 #define SMC_NOWAIT 1
197 190
198 #define SMC_inw(a, r) readw((a) + (r 191 #define SMC_inw(a, r) readw((a) + (r))
199 #define SMC_outw(v, a, r) writew(v, (a) 192 #define SMC_outw(v, a, r) writew(v, (a) + (r))
200 #define SMC_insw(a, r, p, l) readsw((a) + ( 193 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
201 #define SMC_outsw(a, r, p, l) writesw((a) + 194 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
202 195
203 #elif defined(CONFIG_ARCH_INNOKOM) || \ 196 #elif defined(CONFIG_ARCH_INNOKOM) || \
>> 197 defined(CONFIG_MACH_MAINSTONE) || \
204 defined(CONFIG_ARCH_PXA_IDP) || \ 198 defined(CONFIG_ARCH_PXA_IDP) || \
205 defined(CONFIG_ARCH_RAMSES) || \ 199 defined(CONFIG_ARCH_RAMSES) || \
206 defined(CONFIG_ARCH_PCM027) 200 defined(CONFIG_ARCH_PCM027)
207 201
208 #define SMC_CAN_USE_8BIT 1 202 #define SMC_CAN_USE_8BIT 1
209 #define SMC_CAN_USE_16BIT 1 203 #define SMC_CAN_USE_16BIT 1
210 #define SMC_CAN_USE_32BIT 1 204 #define SMC_CAN_USE_32BIT 1
211 #define SMC_IO_SHIFT 0 205 #define SMC_IO_SHIFT 0
212 #define SMC_NOWAIT 1 206 #define SMC_NOWAIT 1
213 #define SMC_USE_PXA_DMA 1 207 #define SMC_USE_PXA_DMA 1
214 208
215 #define SMC_inb(a, r) readb((a) + (r 209 #define SMC_inb(a, r) readb((a) + (r))
216 #define SMC_inw(a, r) readw((a) + (r 210 #define SMC_inw(a, r) readw((a) + (r))
217 #define SMC_inl(a, r) readl((a) + (r 211 #define SMC_inl(a, r) readl((a) + (r))
218 #define SMC_outb(v, a, r) writeb(v, (a) 212 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
219 #define SMC_outl(v, a, r) writel(v, (a) 213 #define SMC_outl(v, a, r) writel(v, (a) + (r))
220 #define SMC_insl(a, r, p, l) readsl((a) + ( 214 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
221 #define SMC_outsl(a, r, p, l) writesl((a) + 215 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
222 #define SMC_IRQ_FLAGS (-1) /* fro 216 #define SMC_IRQ_FLAGS (-1) /* from resource */
223 217
224 /* We actually can't write halfwords properly 218 /* We actually can't write halfwords properly if not word aligned */
225 static inline void 219 static inline void
226 SMC_outw(u16 val, void __iomem *ioaddr, int re 220 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
227 { 221 {
228 if (reg & 2) { 222 if (reg & 2) {
229 unsigned int v = val << 16; 223 unsigned int v = val << 16;
230 v |= readl(ioaddr + (reg & ~2) 224 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
231 writel(v, ioaddr + (reg & ~2)) 225 writel(v, ioaddr + (reg & ~2));
232 } else { 226 } else {
233 writew(val, ioaddr + reg); 227 writew(val, ioaddr + reg);
234 } 228 }
235 } 229 }
236 230
>> 231 #elif defined(CONFIG_MACH_ZYLONITE)
>> 232
>> 233 #define SMC_CAN_USE_8BIT 1
>> 234 #define SMC_CAN_USE_16BIT 1
>> 235 #define SMC_CAN_USE_32BIT 0
>> 236 #define SMC_IO_SHIFT 0
>> 237 #define SMC_NOWAIT 1
>> 238 #define SMC_USE_PXA_DMA 1
>> 239 #define SMC_inb(a, r) readb((a) + (r))
>> 240 #define SMC_inw(a, r) readw((a) + (r))
>> 241 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
>> 242 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
>> 243 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
>> 244 #define SMC_outw(v, a, r) writew(v, (a) + (r))
>> 245 #define SMC_IRQ_FLAGS (-1) /* from resource */
>> 246
237 #elif defined(CONFIG_ARCH_OMAP) 247 #elif defined(CONFIG_ARCH_OMAP)
238 248
239 /* We can only do 16-bit reads and writes in t 249 /* We can only do 16-bit reads and writes in the static memory space. */
240 #define SMC_CAN_USE_8BIT 0 250 #define SMC_CAN_USE_8BIT 0
241 #define SMC_CAN_USE_16BIT 1 251 #define SMC_CAN_USE_16BIT 1
242 #define SMC_CAN_USE_32BIT 0 252 #define SMC_CAN_USE_32BIT 0
243 #define SMC_IO_SHIFT 0 253 #define SMC_IO_SHIFT 0
244 #define SMC_NOWAIT 1 254 #define SMC_NOWAIT 1
245 255
246 #define SMC_inw(a, r) readw((a) + (r 256 #define SMC_inw(a, r) readw((a) + (r))
247 #define SMC_outw(v, a, r) writew(v, (a) 257 #define SMC_outw(v, a, r) writew(v, (a) + (r))
248 #define SMC_insw(a, r, p, l) readsw((a) + ( 258 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
249 #define SMC_outsw(a, r, p, l) writesw((a) + 259 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
250 #define SMC_IRQ_FLAGS (-1) /* fro 260 #define SMC_IRQ_FLAGS (-1) /* from resource */
251 261
252 #elif defined(CONFIG_SH_SH4202_MICRODEV) 262 #elif defined(CONFIG_SH_SH4202_MICRODEV)
253 263
254 #define SMC_CAN_USE_8BIT 0 264 #define SMC_CAN_USE_8BIT 0
255 #define SMC_CAN_USE_16BIT 1 265 #define SMC_CAN_USE_16BIT 1
256 #define SMC_CAN_USE_32BIT 0 266 #define SMC_CAN_USE_32BIT 0
257 267
258 #define SMC_inb(a, r) inb((a) + (r) 268 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
259 #define SMC_inw(a, r) inw((a) + (r) 269 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
260 #define SMC_inl(a, r) inl((a) + (r) 270 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
261 #define SMC_outb(v, a, r) outb(v, (a) + 271 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
262 #define SMC_outw(v, a, r) outw(v, (a) + 272 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
263 #define SMC_outl(v, a, r) outl(v, (a) + 273 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
264 #define SMC_insl(a, r, p, l) insl((a) + (r) 274 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
265 #define SMC_outsl(a, r, p, l) outsl((a) + (r 275 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
266 #define SMC_insw(a, r, p, l) insw((a) + (r) 276 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
267 #define SMC_outsw(a, r, p, l) outsw((a) + (r 277 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
268 278
269 #define SMC_IRQ_FLAGS (0) 279 #define SMC_IRQ_FLAGS (0)
270 280
>> 281 #elif defined(CONFIG_ISA)
>> 282
>> 283 #define SMC_CAN_USE_8BIT 1
>> 284 #define SMC_CAN_USE_16BIT 1
>> 285 #define SMC_CAN_USE_32BIT 0
>> 286
>> 287 #define SMC_inb(a, r) inb((a) + (r))
>> 288 #define SMC_inw(a, r) inw((a) + (r))
>> 289 #define SMC_outb(v, a, r) outb(v, (a) + (r))
>> 290 #define SMC_outw(v, a, r) outw(v, (a) + (r))
>> 291 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
>> 292 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
>> 293
>> 294 #elif defined(CONFIG_SUPERH)
>> 295
>> 296 #ifdef CONFIG_SOLUTION_ENGINE
>> 297 #define SMC_IRQ_FLAGS (0)
>> 298 #define SMC_CAN_USE_8BIT 0
>> 299 #define SMC_CAN_USE_16BIT 1
>> 300 #define SMC_CAN_USE_32BIT 0
>> 301 #define SMC_IO_SHIFT 0
>> 302 #define SMC_NOWAIT 1
>> 303
>> 304 #define SMC_inw(a, r) inw((a) + (r))
>> 305 #define SMC_outw(v, a, r) outw(v, (a) + (r))
>> 306 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
>> 307 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
>> 308
>> 309 #else /* BOARDS */
>> 310
>> 311 #define SMC_CAN_USE_8BIT 1
>> 312 #define SMC_CAN_USE_16BIT 1
>> 313 #define SMC_CAN_USE_32BIT 0
>> 314
>> 315 #define SMC_inb(a, r) inb((a) + (r))
>> 316 #define SMC_inw(a, r) inw((a) + (r))
>> 317 #define SMC_outb(v, a, r) outb(v, (a) + (r))
>> 318 #define SMC_outw(v, a, r) outw(v, (a) + (r))
>> 319 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
>> 320 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
>> 321
>> 322 #endif /* BOARDS */
>> 323
271 #elif defined(CONFIG_M32R) 324 #elif defined(CONFIG_M32R)
272 325
273 #define SMC_CAN_USE_8BIT 0 326 #define SMC_CAN_USE_8BIT 0
274 #define SMC_CAN_USE_16BIT 1 327 #define SMC_CAN_USE_16BIT 1
275 #define SMC_CAN_USE_32BIT 0 328 #define SMC_CAN_USE_32BIT 0
276 329
277 #define SMC_inb(a, r) inb(((u32)a) + 330 #define SMC_inb(a, r) inb(((u32)a) + (r))
278 #define SMC_inw(a, r) inw(((u32)a) + 331 #define SMC_inw(a, r) inw(((u32)a) + (r))
279 #define SMC_outb(v, a, r) outb(v, ((u32) 332 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
280 #define SMC_outw(v, a, r) outw(v, ((u32) 333 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
281 #define SMC_insw(a, r, p, l) insw(((u32)a) 334 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
282 #define SMC_outsw(a, r, p, l) outsw(((u32)a) 335 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
283 336
284 #define SMC_IRQ_FLAGS (0) 337 #define SMC_IRQ_FLAGS (0)
285 338
286 #define RPC_LSA_DEFAULT RPC_LED_TX_RX 339 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
287 #define RPC_LSB_DEFAULT RPC_LED_100_10 340 #define RPC_LSB_DEFAULT RPC_LED_100_10
288 341
289 #elif defined(CONFIG_MACH_LPD79520) \ 342 #elif defined(CONFIG_MACH_LPD79520) \
290 || defined(CONFIG_MACH_LPD7A400) \ 343 || defined(CONFIG_MACH_LPD7A400) \
291 || defined(CONFIG_MACH_LPD7A404) 344 || defined(CONFIG_MACH_LPD7A404)
292 345
293 /* The LPD7X_IOBARRIER is necessary to overcom 346 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
294 * way that the CPU handles chip selects and t 347 * way that the CPU handles chip selects and the way that the SMC chip
295 * expects the chip select to operate. Refer 348 * expects the chip select to operate. Refer to
296 * Documentation/arm/Sharp-LH/IOBarrier for de 349 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
297 * IOBARRIER is a byte, in order that we read 350 * IOBARRIER is a byte, in order that we read the least-common
298 * denominator. It would be wasteful to read 351 * denominator. It would be wasteful to read 32 bits from an 8-bit
299 * accessible region. 352 * accessible region.
300 * 353 *
301 * There is no explicit protection against int 354 * There is no explicit protection against interrupts intervening
302 * between the writew and the IOBARRIER. In S 355 * between the writew and the IOBARRIER. In SMC ISR there is a
303 * preamble that performs an IOBARRIER in the 356 * preamble that performs an IOBARRIER in the extremely unlikely event
304 * that the driver interrupts itself between a 357 * that the driver interrupts itself between a writew to the chip an
305 * the IOBARRIER that follows *and* the cache 358 * the IOBARRIER that follows *and* the cache is large enough that the
306 * first off-chip access while handing the int 359 * first off-chip access while handing the interrupt is to the SMC
307 * chip. Other devices in the same address sp 360 * chip. Other devices in the same address space as the SMC chip must
308 * be aware of the potential for trouble and p 361 * be aware of the potential for trouble and perform a similar
309 * IOBARRIER on entry to their ISR. 362 * IOBARRIER on entry to their ISR.
310 */ 363 */
311 364
312 #include <mach/constants.h> /* IOBARRIER_V !! 365 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
313 366
314 #define SMC_CAN_USE_8BIT 0 367 #define SMC_CAN_USE_8BIT 0
315 #define SMC_CAN_USE_16BIT 1 368 #define SMC_CAN_USE_16BIT 1
316 #define SMC_CAN_USE_32BIT 0 369 #define SMC_CAN_USE_32BIT 0
317 #define SMC_NOWAIT 0 370 #define SMC_NOWAIT 0
318 #define LPD7X_IOBARRIER readb (IOBARRI 371 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
319 372
320 #define SMC_inw(a,r)\ 373 #define SMC_inw(a,r)\
321 ({ unsigned short v = readw ((void*) ((a) + 374 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
322 #define SMC_outw(v,a,r) ({ writew ((v), (a) 375 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
323 376
324 #define SMC_insw LPD7_SMC_insw 377 #define SMC_insw LPD7_SMC_insw
325 static inline void LPD7_SMC_insw (unsigned cha 378 static inline void LPD7_SMC_insw (unsigned char* a, int r,
326 unsigned cha 379 unsigned char* p, int l)
327 { 380 {
328 unsigned short* ps = (unsigned short*) 381 unsigned short* ps = (unsigned short*) p;
329 while (l-- > 0) { 382 while (l-- > 0) {
330 *ps++ = readw (a + r); 383 *ps++ = readw (a + r);
331 LPD7X_IOBARRIER; 384 LPD7X_IOBARRIER;
332 } 385 }
333 } 386 }
334 387
335 #define SMC_outsw LPD7_SMC_outsw 388 #define SMC_outsw LPD7_SMC_outsw
336 static inline void LPD7_SMC_outsw (unsigned ch 389 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
337 unsigned ch 390 unsigned char* p, int l)
338 { 391 {
339 unsigned short* ps = (unsigned short*) 392 unsigned short* ps = (unsigned short*) p;
340 while (l-- > 0) { 393 while (l-- > 0) {
341 writew (*ps++, a + r); 394 writew (*ps++, a + r);
342 LPD7X_IOBARRIER; 395 LPD7X_IOBARRIER;
343 } 396 }
344 } 397 }
345 398
346 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIE 399 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
347 400
348 #define RPC_LSA_DEFAULT RPC_LED_TX_RX 401 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
349 #define RPC_LSB_DEFAULT RPC_LED_100_10 402 #define RPC_LSB_DEFAULT RPC_LED_100_10
350 403
>> 404 #elif defined(CONFIG_SOC_AU1X00)
>> 405
>> 406 #include <au1xxx.h>
>> 407
>> 408 /* We can only do 16-bit reads and writes in the static memory space. */
>> 409 #define SMC_CAN_USE_8BIT 0
>> 410 #define SMC_CAN_USE_16BIT 1
>> 411 #define SMC_CAN_USE_32BIT 0
>> 412 #define SMC_IO_SHIFT 0
>> 413 #define SMC_NOWAIT 1
>> 414
>> 415 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
>> 416 #define SMC_insw(a, r, p, l) \
>> 417 do { \
>> 418 unsigned long _a = (unsigned long)((a) + (r)); \
>> 419 int _l = (l); \
>> 420 u16 *_p = (u16 *)(p); \
>> 421 while (_l-- > 0) \
>> 422 *_p++ = au_readw(_a); \
>> 423 } while(0)
>> 424 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
>> 425 #define SMC_outsw(a, r, p, l) \
>> 426 do { \
>> 427 unsigned long _a = (unsigned long)((a) + (r)); \
>> 428 int _l = (l); \
>> 429 const u16 *_p = (const u16 *)(p); \
>> 430 while (_l-- > 0) \
>> 431 au_writew(*_p++ , _a); \
>> 432 } while(0)
>> 433
>> 434 #define SMC_IRQ_FLAGS (0)
>> 435
351 #elif defined(CONFIG_ARCH_VERSATILE) 436 #elif defined(CONFIG_ARCH_VERSATILE)
352 437
353 #define SMC_CAN_USE_8BIT 1 438 #define SMC_CAN_USE_8BIT 1
354 #define SMC_CAN_USE_16BIT 1 439 #define SMC_CAN_USE_16BIT 1
355 #define SMC_CAN_USE_32BIT 1 440 #define SMC_CAN_USE_32BIT 1
356 #define SMC_NOWAIT 1 441 #define SMC_NOWAIT 1
357 442
358 #define SMC_inb(a, r) readb((a) + (r 443 #define SMC_inb(a, r) readb((a) + (r))
359 #define SMC_inw(a, r) readw((a) + (r 444 #define SMC_inw(a, r) readw((a) + (r))
360 #define SMC_inl(a, r) readl((a) + (r 445 #define SMC_inl(a, r) readl((a) + (r))
361 #define SMC_outb(v, a, r) writeb(v, (a) 446 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
362 #define SMC_outw(v, a, r) writew(v, (a) 447 #define SMC_outw(v, a, r) writew(v, (a) + (r))
363 #define SMC_outl(v, a, r) writel(v, (a) 448 #define SMC_outl(v, a, r) writel(v, (a) + (r))
364 #define SMC_insl(a, r, p, l) readsl((a) + ( 449 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
365 #define SMC_outsl(a, r, p, l) writesl((a) + 450 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
366 #define SMC_IRQ_FLAGS (-1) /* fro 451 #define SMC_IRQ_FLAGS (-1) /* from resource */
367 452
368 #elif defined(CONFIG_MN10300) 453 #elif defined(CONFIG_MN10300)
369 454
370 /* 455 /*
371 * MN10300/AM33 configuration 456 * MN10300/AM33 configuration
372 */ 457 */
373 458
374 #include <unit/smc91111.h> !! 459 #include <asm/unit/smc91111.h>
375 460
376 #else 461 #else
377 462
378 /* 463 /*
379 * Default configuration 464 * Default configuration
380 */ 465 */
381 466
382 #define SMC_CAN_USE_8BIT 1 467 #define SMC_CAN_USE_8BIT 1
383 #define SMC_CAN_USE_16BIT 1 468 #define SMC_CAN_USE_16BIT 1
384 #define SMC_CAN_USE_32BIT 1 469 #define SMC_CAN_USE_32BIT 1
385 #define SMC_NOWAIT 1 470 #define SMC_NOWAIT 1
386 471
387 #define SMC_IO_SHIFT (lp->io_shift) <<
388 <<
389 #define SMC_inb(a, r) readb((a) + (r 472 #define SMC_inb(a, r) readb((a) + (r))
390 #define SMC_inw(a, r) readw((a) + (r 473 #define SMC_inw(a, r) readw((a) + (r))
391 #define SMC_inl(a, r) readl((a) + (r 474 #define SMC_inl(a, r) readl((a) + (r))
392 #define SMC_outb(v, a, r) writeb(v, (a) 475 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
393 #define SMC_outw(v, a, r) writew(v, (a) 476 #define SMC_outw(v, a, r) writew(v, (a) + (r))
394 #define SMC_outl(v, a, r) writel(v, (a) 477 #define SMC_outl(v, a, r) writel(v, (a) + (r))
395 #define SMC_insw(a, r, p, l) readsw((a) + ( <<
396 #define SMC_outsw(a, r, p, l) writesw((a) + <<
397 #define SMC_insl(a, r, p, l) readsl((a) + ( 478 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
398 #define SMC_outsl(a, r, p, l) writesl((a) + 479 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
399 480
400 #define RPC_LSA_DEFAULT RPC_LED_100_10 481 #define RPC_LSA_DEFAULT RPC_LED_100_10
401 #define RPC_LSB_DEFAULT RPC_LED_TX_RX 482 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
402 483
403 #endif 484 #endif
404 485
405 486
406 /* store this information for the driver.. */ 487 /* store this information for the driver.. */
407 struct smc_local { 488 struct smc_local {
408 /* 489 /*
409 * If I have to wait until memory is a 490 * If I have to wait until memory is available to send a
410 * packet, I will store the skbuff her 491 * packet, I will store the skbuff here, until I get the
411 * desired memory. Then, I'll send it 492 * desired memory. Then, I'll send it out and free it.
412 */ 493 */
413 struct sk_buff *pending_tx_skb; 494 struct sk_buff *pending_tx_skb;
414 struct tasklet_struct tx_task; 495 struct tasklet_struct tx_task;
415 496
416 /* version/revision of the SMC91x chip 497 /* version/revision of the SMC91x chip */
417 int version; 498 int version;
418 499
419 /* Contains the current active transmi 500 /* Contains the current active transmission mode */
420 int tcr_cur_mode; 501 int tcr_cur_mode;
421 502
422 /* Contains the current active receive 503 /* Contains the current active receive mode */
423 int rcr_cur_mode; 504 int rcr_cur_mode;
424 505
425 /* Contains the current active receive 506 /* Contains the current active receive/phy mode */
426 int rpc_cur_mode; 507 int rpc_cur_mode;
427 int ctl_rfduplx; 508 int ctl_rfduplx;
428 int ctl_rspeed; 509 int ctl_rspeed;
429 510
430 u32 msg_enable; 511 u32 msg_enable;
431 u32 phy_type; 512 u32 phy_type;
432 struct mii_if_info mii; 513 struct mii_if_info mii;
433 514
434 /* work queue */ 515 /* work queue */
435 struct work_struct phy_configure; 516 struct work_struct phy_configure;
436 struct net_device *dev; 517 struct net_device *dev;
437 int work_pending; 518 int work_pending;
438 519
439 spinlock_t lock; 520 spinlock_t lock;
440 521
441 #ifdef CONFIG_ARCH_PXA !! 522 #ifdef SMC_USE_PXA_DMA
442 /* DMA needs the physical address of t 523 /* DMA needs the physical address of the chip */
443 u_long physaddr; 524 u_long physaddr;
444 struct device *device; 525 struct device *device;
445 #endif 526 #endif
446 void __iomem *base; 527 void __iomem *base;
447 void __iomem *datacs; 528 void __iomem *datacs;
448 <<
449 /* the low address lines on some platf <<
450 int io_shift; <<
451 <<
452 struct smc91x_platdata cfg; <<
453 }; 529 };
454 530
455 #define SMC_8BIT(p) ((p)->cfg.flags & SMC9 <<
456 #define SMC_16BIT(p) ((p)->cfg.flags & SMC9 <<
457 #define SMC_32BIT(p) ((p)->cfg.flags & SMC9 <<
458 531
459 #ifdef CONFIG_ARCH_PXA !! 532 #ifdef SMC_USE_PXA_DMA
460 /* 533 /*
461 * Let's use the DMA engine on the XScale PXA2 534 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
462 * always happening in irq context so no need 535 * always happening in irq context so no need to worry about races. TX is
463 * different and probably not worth it for tha 536 * different and probably not worth it for that reason, and not as critical
464 * as RX which can overrun memory and lose pac 537 * as RX which can overrun memory and lose packets.
465 */ 538 */
466 #include <linux/dma-mapping.h> 539 #include <linux/dma-mapping.h>
467 #include <mach/dma.h> !! 540 #include <asm/dma.h>
>> 541 #include <asm/arch/pxa-regs.h>
468 542
469 #ifdef SMC_insl 543 #ifdef SMC_insl
470 #undef SMC_insl 544 #undef SMC_insl
471 #define SMC_insl(a, r, p, l) \ 545 #define SMC_insl(a, r, p, l) \
472 smc_pxa_dma_insl(a, lp, r, dev->dma, p 546 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
473 static inline void 547 static inline void
474 smc_pxa_dma_insl(void __iomem *ioaddr, struct 548 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
475 u_char *buf, int len) 549 u_char *buf, int len)
476 { 550 {
477 u_long physaddr = lp->physaddr; 551 u_long physaddr = lp->physaddr;
478 dma_addr_t dmabuf; 552 dma_addr_t dmabuf;
479 553
480 /* fallback if no DMA available */ 554 /* fallback if no DMA available */
481 if (dma == (unsigned char)-1) { 555 if (dma == (unsigned char)-1) {
482 readsl(ioaddr + reg, buf, len) 556 readsl(ioaddr + reg, buf, len);
483 return; 557 return;
484 } 558 }
485 559
486 /* 64 bit alignment is required for me 560 /* 64 bit alignment is required for memory to memory DMA */
487 if ((long)buf & 4) { 561 if ((long)buf & 4) {
488 *((u32 *)buf) = SMC_inl(ioaddr 562 *((u32 *)buf) = SMC_inl(ioaddr, reg);
489 buf += 4; 563 buf += 4;
490 len--; 564 len--;
491 } 565 }
492 566
493 len *= 4; 567 len *= 4;
494 dmabuf = dma_map_single(lp->device, bu 568 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
495 DCSR(dma) = DCSR_NODESC; 569 DCSR(dma) = DCSR_NODESC;
496 DTADR(dma) = dmabuf; 570 DTADR(dma) = dmabuf;
497 DSADR(dma) = physaddr + reg; 571 DSADR(dma) = physaddr + reg;
498 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BU 572 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
499 DCMD_WIDTH4 | (DCMD_LENGT 573 DCMD_WIDTH4 | (DCMD_LENGTH & len));
500 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 574 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
501 while (!(DCSR(dma) & DCSR_STOPSTATE)) 575 while (!(DCSR(dma) & DCSR_STOPSTATE))
502 cpu_relax(); 576 cpu_relax();
503 DCSR(dma) = 0; 577 DCSR(dma) = 0;
504 dma_unmap_single(lp->device, dmabuf, l 578 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
505 } 579 }
506 #endif 580 #endif
507 581
508 #ifdef SMC_insw 582 #ifdef SMC_insw
509 #undef SMC_insw 583 #undef SMC_insw
510 #define SMC_insw(a, r, p, l) \ 584 #define SMC_insw(a, r, p, l) \
511 smc_pxa_dma_insw(a, lp, r, dev->dma, p 585 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
512 static inline void 586 static inline void
513 smc_pxa_dma_insw(void __iomem *ioaddr, struct 587 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
514 u_char *buf, int len) 588 u_char *buf, int len)
515 { 589 {
516 u_long physaddr = lp->physaddr; 590 u_long physaddr = lp->physaddr;
517 dma_addr_t dmabuf; 591 dma_addr_t dmabuf;
518 592
519 /* fallback if no DMA available */ 593 /* fallback if no DMA available */
520 if (dma == (unsigned char)-1) { 594 if (dma == (unsigned char)-1) {
521 readsw(ioaddr + reg, buf, len) 595 readsw(ioaddr + reg, buf, len);
522 return; 596 return;
523 } 597 }
524 598
525 /* 64 bit alignment is required for me 599 /* 64 bit alignment is required for memory to memory DMA */
526 while ((long)buf & 6) { 600 while ((long)buf & 6) {
527 *((u16 *)buf) = SMC_inw(ioaddr 601 *((u16 *)buf) = SMC_inw(ioaddr, reg);
528 buf += 2; 602 buf += 2;
529 len--; 603 len--;
530 } 604 }
531 605
532 len *= 2; 606 len *= 2;
533 dmabuf = dma_map_single(lp->device, bu 607 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
534 DCSR(dma) = DCSR_NODESC; 608 DCSR(dma) = DCSR_NODESC;
535 DTADR(dma) = dmabuf; 609 DTADR(dma) = dmabuf;
536 DSADR(dma) = physaddr + reg; 610 DSADR(dma) = physaddr + reg;
537 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BU 611 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
538 DCMD_WIDTH2 | (DCMD_LENGT 612 DCMD_WIDTH2 | (DCMD_LENGTH & len));
539 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 613 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
540 while (!(DCSR(dma) & DCSR_STOPSTATE)) 614 while (!(DCSR(dma) & DCSR_STOPSTATE))
541 cpu_relax(); 615 cpu_relax();
542 DCSR(dma) = 0; 616 DCSR(dma) = 0;
543 dma_unmap_single(lp->device, dmabuf, l 617 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
544 } 618 }
545 #endif 619 #endif
546 620
547 static void 621 static void
548 smc_pxa_dma_irq(int dma, void *dummy) 622 smc_pxa_dma_irq(int dma, void *dummy)
549 { 623 {
550 DCSR(dma) = 0; 624 DCSR(dma) = 0;
551 } 625 }
552 #endif /* CONFIG_ARCH_PXA */ !! 626 #endif /* SMC_USE_PXA_DMA */
553 627
554 628
555 /* 629 /*
556 * Everything a particular hardware setup need 630 * Everything a particular hardware setup needs should have been defined
557 * at this point. Add stubs for the undefined 631 * at this point. Add stubs for the undefined cases, mainly to avoid
558 * compilation warnings since they'll be optim 632 * compilation warnings since they'll be optimized away, or to prevent buggy
559 * use of them. 633 * use of them.
560 */ 634 */
561 635
562 #if ! SMC_CAN_USE_32BIT 636 #if ! SMC_CAN_USE_32BIT
563 #define SMC_inl(ioaddr, reg) ({ BUG 637 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
564 #define SMC_outl(x, ioaddr, reg) BUG() 638 #define SMC_outl(x, ioaddr, reg) BUG()
565 #define SMC_insl(a, r, p, l) BUG() 639 #define SMC_insl(a, r, p, l) BUG()
566 #define SMC_outsl(a, r, p, l) BUG() 640 #define SMC_outsl(a, r, p, l) BUG()
567 #endif 641 #endif
568 642
569 #if !defined(SMC_insl) || !defined(SMC_outsl) 643 #if !defined(SMC_insl) || !defined(SMC_outsl)
570 #define SMC_insl(a, r, p, l) BUG() 644 #define SMC_insl(a, r, p, l) BUG()
571 #define SMC_outsl(a, r, p, l) BUG() 645 #define SMC_outsl(a, r, p, l) BUG()
572 #endif 646 #endif
573 647
574 #if ! SMC_CAN_USE_16BIT 648 #if ! SMC_CAN_USE_16BIT
575 649
576 /* 650 /*
577 * Any 16-bit access is performed with two 8-b 651 * Any 16-bit access is performed with two 8-bit accesses if the hardware
578 * can't do it directly. Most registers are 16 652 * can't do it directly. Most registers are 16-bit so those are mandatory.
579 */ 653 */
580 #define SMC_outw(x, ioaddr, reg) 654 #define SMC_outw(x, ioaddr, reg) \
581 do { 655 do { \
582 unsigned int __val16 = (x); 656 unsigned int __val16 = (x); \
583 SMC_outb( __val16, ioaddr, reg 657 SMC_outb( __val16, ioaddr, reg ); \
584 SMC_outb( __val16 >> 8, ioaddr 658 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
585 } while (0) 659 } while (0)
586 #define SMC_inw(ioaddr, reg) 660 #define SMC_inw(ioaddr, reg) \
587 ({ 661 ({ \
588 unsigned int __val16; 662 unsigned int __val16; \
589 __val16 = SMC_inb( ioaddr, re 663 __val16 = SMC_inb( ioaddr, reg ); \
590 __val16 |= SMC_inb( ioaddr, re 664 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
591 __val16; 665 __val16; \
592 }) 666 })
593 667
594 #define SMC_insw(a, r, p, l) BUG() 668 #define SMC_insw(a, r, p, l) BUG()
595 #define SMC_outsw(a, r, p, l) BUG() 669 #define SMC_outsw(a, r, p, l) BUG()
596 670
597 #endif 671 #endif
598 672
599 #if !defined(SMC_insw) || !defined(SMC_outsw) 673 #if !defined(SMC_insw) || !defined(SMC_outsw)
600 #define SMC_insw(a, r, p, l) BUG() 674 #define SMC_insw(a, r, p, l) BUG()
601 #define SMC_outsw(a, r, p, l) BUG() 675 #define SMC_outsw(a, r, p, l) BUG()
602 #endif 676 #endif
603 677
604 #if ! SMC_CAN_USE_8BIT 678 #if ! SMC_CAN_USE_8BIT
605 #define SMC_inb(ioaddr, reg) ({ BUG 679 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
606 #define SMC_outb(x, ioaddr, reg) BUG() 680 #define SMC_outb(x, ioaddr, reg) BUG()
607 #define SMC_insb(a, r, p, l) BUG() 681 #define SMC_insb(a, r, p, l) BUG()
608 #define SMC_outsb(a, r, p, l) BUG() 682 #define SMC_outsb(a, r, p, l) BUG()
609 #endif 683 #endif
610 684
611 #if !defined(SMC_insb) || !defined(SMC_outsb) 685 #if !defined(SMC_insb) || !defined(SMC_outsb)
612 #define SMC_insb(a, r, p, l) BUG() 686 #define SMC_insb(a, r, p, l) BUG()
613 #define SMC_outsb(a, r, p, l) BUG() 687 #define SMC_outsb(a, r, p, l) BUG()
614 #endif 688 #endif
615 689
616 #ifndef SMC_CAN_USE_DATACS 690 #ifndef SMC_CAN_USE_DATACS
617 #define SMC_CAN_USE_DATACS 0 691 #define SMC_CAN_USE_DATACS 0
618 #endif 692 #endif
619 693
620 #ifndef SMC_IO_SHIFT 694 #ifndef SMC_IO_SHIFT
621 #define SMC_IO_SHIFT 0 695 #define SMC_IO_SHIFT 0
622 #endif 696 #endif
623 697
624 #ifndef SMC_IRQ_FLAGS 698 #ifndef SMC_IRQ_FLAGS
625 #define SMC_IRQ_FLAGS IRQF_TRIGGER_R 699 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
626 #endif 700 #endif
627 701
628 #ifndef SMC_INTERRUPT_PREAMBLE 702 #ifndef SMC_INTERRUPT_PREAMBLE
629 #define SMC_INTERRUPT_PREAMBLE 703 #define SMC_INTERRUPT_PREAMBLE
630 #endif 704 #endif
631 705
632 706
633 /* Because of bank switching, the LAN91x uses 707 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
634 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) 708 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
635 #define SMC_DATA_EXTENT (4) 709 #define SMC_DATA_EXTENT (4)
636 710
637 /* 711 /*
638 . Bank Select Register: 712 . Bank Select Register:
639 . 713 .
640 . yyyy yyyy 0000 00xx 714 . yyyy yyyy 0000 00xx
641 . xx = bank number 715 . xx = bank number
642 . yyyy yyyy = 0x33, for id 716 . yyyy yyyy = 0x33, for identification purposes.
643 */ 717 */
644 #define BANK_SELECT (14 << SMC_IO_ 718 #define BANK_SELECT (14 << SMC_IO_SHIFT)
645 719
646 720
647 // Transmit Control Register 721 // Transmit Control Register
648 /* BANK 0 */ 722 /* BANK 0 */
649 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) !! 723 #define TCR_REG SMC_REG(0x0000, 0)
650 #define TCR_ENABLE 0x0001 // When 1 we c 724 #define TCR_ENABLE 0x0001 // When 1 we can transmit
651 #define TCR_LOOP 0x0002 // Controls ou 725 #define TCR_LOOP 0x0002 // Controls output pin LBK
652 #define TCR_FORCOL 0x0004 // When 1 will 726 #define TCR_FORCOL 0x0004 // When 1 will force a collision
653 #define TCR_PAD_EN 0x0080 // When 1 will 727 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
654 #define TCR_NOCRC 0x0100 // When 1 will 728 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
655 #define TCR_MON_CSN 0x0400 // When 1 tx m 729 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
656 #define TCR_FDUPLX 0x0800 // When 1 enab 730 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
657 #define TCR_STP_SQET 0x1000 // When 1 stop 731 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
658 #define TCR_EPH_LOOP 0x2000 // When 1 enab 732 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
659 #define TCR_SWFDUP 0x8000 // When 1 enab 733 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
660 734
661 #define TCR_CLEAR 0 /* do NOTHING 735 #define TCR_CLEAR 0 /* do NOTHING */
662 /* the default settings for the TCR register : 736 /* the default settings for the TCR register : */
663 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_ 737 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
664 738
665 739
666 // EPH Status Register 740 // EPH Status Register
667 /* BANK 0 */ 741 /* BANK 0 */
668 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x !! 742 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
669 #define ES_TX_SUC 0x0001 // Last TX was 743 #define ES_TX_SUC 0x0001 // Last TX was successful
670 #define ES_SNGL_COL 0x0002 // Single coll 744 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
671 #define ES_MUL_COL 0x0004 // Multiple co 745 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
672 #define ES_LTX_MULT 0x0008 // Last tx was 746 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
673 #define ES_16COL 0x0010 // 16 Collisio 747 #define ES_16COL 0x0010 // 16 Collisions Reached
674 #define ES_SQET 0x0020 // Signal Qual 748 #define ES_SQET 0x0020 // Signal Quality Error Test
675 #define ES_LTXBRD 0x0040 // Last tx was 749 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
676 #define ES_TXDEFR 0x0080 // Transmit De 750 #define ES_TXDEFR 0x0080 // Transmit Deferred
677 #define ES_LATCOL 0x0200 // Late collis 751 #define ES_LATCOL 0x0200 // Late collision detected on last tx
678 #define ES_LOSTCARR 0x0400 // Lost Carrie 752 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
679 #define ES_EXC_DEF 0x0800 // Excessive D 753 #define ES_EXC_DEF 0x0800 // Excessive Deferral
680 #define ES_CTR_ROL 0x1000 // Counter Rol 754 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
681 #define ES_LINK_OK 0x4000 // Driven by i 755 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
682 #define ES_TXUNRN 0x8000 // Tx Underrun 756 #define ES_TXUNRN 0x8000 // Tx Underrun
683 757
684 758
685 // Receive Control Register 759 // Receive Control Register
686 /* BANK 0 */ 760 /* BANK 0 */
687 #define RCR_REG(lp) SMC_REG(lp, 0x !! 761 #define RCR_REG SMC_REG(0x0004, 0)
688 #define RCR_RX_ABORT 0x0001 // Set if a rx 762 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
689 #define RCR_PRMS 0x0002 // Enable prom 763 #define RCR_PRMS 0x0002 // Enable promiscuous mode
690 #define RCR_ALMUL 0x0004 // When set ac 764 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
691 #define RCR_RXEN 0x0100 // IFF this is 765 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
692 #define RCR_STRIP_CRC 0x0200 // When set st 766 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
693 #define RCR_ABORT_ENB 0x0200 // When set wi 767 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
694 #define RCR_FILT_CAR 0x0400 // When set fi 768 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
695 #define RCR_SOFTRST 0x8000 // resets the 769 #define RCR_SOFTRST 0x8000 // resets the chip
696 770
697 /* the normal settings for the RCR register : 771 /* the normal settings for the RCR register : */
698 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_R 772 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
699 #define RCR_CLEAR 0x0 // set it to a 773 #define RCR_CLEAR 0x0 // set it to a base state
700 774
701 775
702 // Counter Register 776 // Counter Register
703 /* BANK 0 */ 777 /* BANK 0 */
704 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) !! 778 #define COUNTER_REG SMC_REG(0x0006, 0)
705 779
706 780
707 // Memory Information Register 781 // Memory Information Register
708 /* BANK 0 */ 782 /* BANK 0 */
709 #define MIR_REG(lp) SMC_REG(lp, 0x !! 783 #define MIR_REG SMC_REG(0x0008, 0)
710 784
711 785
712 // Receive/Phy Control Register 786 // Receive/Phy Control Register
713 /* BANK 0 */ 787 /* BANK 0 */
714 #define RPC_REG(lp) SMC_REG(lp, 0x !! 788 #define RPC_REG SMC_REG(0x000A, 0)
715 #define RPC_SPEED 0x2000 // When 1 PHY 789 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
716 #define RPC_DPLX 0x1000 // When 1 PHY 790 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
717 #define RPC_ANEG 0x0800 // When 1 PHY 791 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
718 #define RPC_LSXA_SHFT 5 // Bits to shi 792 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
719 #define RPC_LSXB_SHFT 2 // Bits to get 793 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
>> 794 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
>> 795 #define RPC_LED_RES (0x01) // LED = Reserved
>> 796 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
>> 797 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
>> 798 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
>> 799 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
>> 800 #define RPC_LED_TX (0x06) // LED = TX packet occurred
>> 801 #define RPC_LED_RX (0x07) // LED = RX packet occurred
720 802
721 #ifndef RPC_LSA_DEFAULT 803 #ifndef RPC_LSA_DEFAULT
722 #define RPC_LSA_DEFAULT RPC_LED_100 804 #define RPC_LSA_DEFAULT RPC_LED_100
723 #endif 805 #endif
724 #ifndef RPC_LSB_DEFAULT 806 #ifndef RPC_LSB_DEFAULT
725 #define RPC_LSB_DEFAULT RPC_LED_FD 807 #define RPC_LSB_DEFAULT RPC_LED_FD
726 #endif 808 #endif
727 809
728 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RP !! 810 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
729 811
730 812
731 /* Bank 0 0x0C is reserved */ 813 /* Bank 0 0x0C is reserved */
732 814
733 // Bank Select Register 815 // Bank Select Register
734 /* All Banks */ 816 /* All Banks */
735 #define BSR_REG 0x000E 817 #define BSR_REG 0x000E
736 818
737 819
738 // Configuration Reg 820 // Configuration Reg
739 /* BANK 1 */ 821 /* BANK 1 */
740 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, !! 822 #define CONFIG_REG SMC_REG(0x0000, 1)
741 #define CONFIG_EXT_PHY 0x0200 // 1=external 823 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
742 #define CONFIG_GPCNTRL 0x0400 // Inverse val 824 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
743 #define CONFIG_NO_WAIT 0x1000 // When 1 no e 825 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
744 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 E 826 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
745 827
746 // Default is powered-up, Internal Phy, Wait S 828 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
747 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 829 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
748 830
749 831
750 // Base Address Register 832 // Base Address Register
751 /* BANK 1 */ 833 /* BANK 1 */
752 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) !! 834 #define BASE_REG SMC_REG(0x0002, 1)
753 835
754 836
755 // Individual Address Registers 837 // Individual Address Registers
756 /* BANK 1 */ 838 /* BANK 1 */
757 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) !! 839 #define ADDR0_REG SMC_REG(0x0004, 1)
758 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) !! 840 #define ADDR1_REG SMC_REG(0x0006, 1)
759 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) !! 841 #define ADDR2_REG SMC_REG(0x0008, 1)
760 842
761 843
762 // General Purpose Register 844 // General Purpose Register
763 /* BANK 1 */ 845 /* BANK 1 */
764 #define GP_REG(lp) SMC_REG(lp, 0x !! 846 #define GP_REG SMC_REG(0x000A, 1)
765 847
766 848
767 // Control Register 849 // Control Register
768 /* BANK 1 */ 850 /* BANK 1 */
769 #define CTL_REG(lp) SMC_REG(lp, 0x !! 851 #define CTL_REG SMC_REG(0x000C, 1)
770 #define CTL_RCV_BAD 0x4000 // When 1 bad C 852 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
771 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx p 853 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
772 #define CTL_LE_ENABLE 0x0080 // When 1 enabl 854 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
773 #define CTL_CR_ENABLE 0x0040 // When 1 enabl 855 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
774 #define CTL_TE_ENABLE 0x0020 // When 1 enabl 856 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
775 #define CTL_EEPROM_SELECT 0x0004 // Controls E 857 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
776 #define CTL_RELOAD 0x0002 // When set rea 858 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
777 #define CTL_STORE 0x0001 // When set sto 859 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
778 860
779 861
780 // MMU Command Register 862 // MMU Command Register
781 /* BANK 2 */ 863 /* BANK 2 */
782 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) !! 864 #define MMU_CMD_REG SMC_REG(0x0000, 2)
783 #define MC_BUSY 1 // When 1 the 865 #define MC_BUSY 1 // When 1 the last release has not completed
784 #define MC_NOP (0<<5) // No Op 866 #define MC_NOP (0<<5) // No Op
785 #define MC_ALLOC (1<<5) // OR with num 867 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
786 #define MC_RESET (2<<5) // Reset MMU t 868 #define MC_RESET (2<<5) // Reset MMU to initial state
787 #define MC_REMOVE (3<<5) // Remove the 869 #define MC_REMOVE (3<<5) // Remove the current rx packet
788 #define MC_RELEASE (4<<5) // Remove and 870 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
789 #define MC_FREEPKT (5<<5) // Release pac 871 #define MC_FREEPKT (5<<5) // Release packet in PNR register
790 #define MC_ENQUEUE (6<<5) // Enqueue the 872 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
791 #define MC_RSTTXFIFO (7<<5) // Reset the T 873 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
792 874
793 875
794 // Packet Number Register 876 // Packet Number Register
795 /* BANK 2 */ 877 /* BANK 2 */
796 #define PN_REG(lp) SMC_REG(lp, 0x !! 878 #define PN_REG SMC_REG(0x0002, 2)
797 879
798 880
799 // Allocation Result Register 881 // Allocation Result Register
800 /* BANK 2 */ 882 /* BANK 2 */
801 #define AR_REG(lp) SMC_REG(lp, 0x !! 883 #define AR_REG SMC_REG(0x0003, 2)
802 #define AR_FAILED 0x80 // Alocation F 884 #define AR_FAILED 0x80 // Alocation Failed
803 885
804 886
805 // TX FIFO Ports Register 887 // TX FIFO Ports Register
806 /* BANK 2 */ 888 /* BANK 2 */
807 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) !! 889 #define TXFIFO_REG SMC_REG(0x0004, 2)
808 #define TXFIFO_TEMPTY 0x80 // TX FIFO Emp 890 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
809 891
810 // RX FIFO Ports Register 892 // RX FIFO Ports Register
811 /* BANK 2 */ 893 /* BANK 2 */
812 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) !! 894 #define RXFIFO_REG SMC_REG(0x0005, 2)
813 #define RXFIFO_REMPTY 0x80 // RX FIFO Emp 895 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
814 896
815 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) !! 897 #define FIFO_REG SMC_REG(0x0004, 2)
816 898
817 // Pointer Register 899 // Pointer Register
818 /* BANK 2 */ 900 /* BANK 2 */
819 #define PTR_REG(lp) SMC_REG(lp, 0x !! 901 #define PTR_REG SMC_REG(0x0006, 2)
820 #define PTR_RCV 0x8000 // 1=Receive ar 902 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
821 #define PTR_AUTOINC 0x4000 // Auto increme 903 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
822 #define PTR_READ 0x2000 // When 1 the o 904 #define PTR_READ 0x2000 // When 1 the operation is a read
823 905
824 906
825 // Data Register 907 // Data Register
826 /* BANK 2 */ 908 /* BANK 2 */
827 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) !! 909 #define DATA_REG SMC_REG(0x0008, 2)
828 910
829 911
830 // Interrupt Status/Acknowledge Register 912 // Interrupt Status/Acknowledge Register
831 /* BANK 2 */ 913 /* BANK 2 */
832 #define INT_REG(lp) SMC_REG(lp, 0x !! 914 #define INT_REG SMC_REG(0x000C, 2)
833 915
834 916
835 // Interrupt Mask Register 917 // Interrupt Mask Register
836 /* BANK 2 */ 918 /* BANK 2 */
837 #define IM_REG(lp) SMC_REG(lp, 0x !! 919 #define IM_REG SMC_REG(0x000D, 2)
838 #define IM_MDINT 0x80 // PHY MI Registe 920 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
839 #define IM_ERCV_INT 0x40 // Early Receive 921 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
840 #define IM_EPH_INT 0x20 // Set by Etherne 922 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
841 #define IM_RX_OVRN_INT 0x10 // Set by Receive 923 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
842 #define IM_ALLOC_INT 0x08 // Set when alloc 924 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
843 #define IM_TX_EMPTY_INT 0x04 // Set if the TX 925 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
844 #define IM_TX_INT 0x02 // Transmit Inter 926 #define IM_TX_INT 0x02 // Transmit Interrupt
845 #define IM_RCV_INT 0x01 // Receive Interr 927 #define IM_RCV_INT 0x01 // Receive Interrupt
846 928
847 929
848 // Multicast Table Registers 930 // Multicast Table Registers
849 /* BANK 3 */ 931 /* BANK 3 */
850 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) !! 932 #define MCAST_REG1 SMC_REG(0x0000, 3)
851 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) !! 933 #define MCAST_REG2 SMC_REG(0x0002, 3)
852 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) !! 934 #define MCAST_REG3 SMC_REG(0x0004, 3)
853 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) !! 935 #define MCAST_REG4 SMC_REG(0x0006, 3)
854 936
855 937
856 // Management Interface Register (MII) 938 // Management Interface Register (MII)
857 /* BANK 3 */ 939 /* BANK 3 */
858 #define MII_REG(lp) SMC_REG(lp, 0x !! 940 #define MII_REG SMC_REG(0x0008, 3)
859 #define MII_MSK_CRS100 0x4000 // Disables CRS 941 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
860 #define MII_MDOE 0x0008 // MII Output E 942 #define MII_MDOE 0x0008 // MII Output Enable
861 #define MII_MCLK 0x0004 // MII Clock, p 943 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
862 #define MII_MDI 0x0002 // MII Input, p 944 #define MII_MDI 0x0002 // MII Input, pin MDI
863 #define MII_MDO 0x0001 // MII Output, 945 #define MII_MDO 0x0001 // MII Output, pin MDO
864 946
865 947
866 // Revision Register 948 // Revision Register
867 /* BANK 3 */ 949 /* BANK 3 */
868 /* ( hi: chip id low: rev # ) */ 950 /* ( hi: chip id low: rev # ) */
869 #define REV_REG(lp) SMC_REG(lp, 0x !! 951 #define REV_REG SMC_REG(0x000A, 3)
870 952
871 953
872 // Early RCV Register 954 // Early RCV Register
873 /* BANK 3 */ 955 /* BANK 3 */
874 /* this is NOT on SMC9192 */ 956 /* this is NOT on SMC9192 */
875 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) !! 957 #define ERCV_REG SMC_REG(0x000C, 3)
876 #define ERCV_RCV_DISCRD 0x0080 // When 1 disca 958 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
877 #define ERCV_THRESHOLD 0x001F // ERCV Thresho 959 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
878 960
879 961
880 // External Register 962 // External Register
881 /* BANK 7 */ 963 /* BANK 7 */
882 #define EXT_REG(lp) SMC_REG(lp, 0x !! 964 #define EXT_REG SMC_REG(0x0000, 7)
883 965
884 966
885 #define CHIP_9192 3 967 #define CHIP_9192 3
886 #define CHIP_9194 4 968 #define CHIP_9194 4
887 #define CHIP_9195 5 969 #define CHIP_9195 5
888 #define CHIP_9196 6 970 #define CHIP_9196 6
889 #define CHIP_91100 7 971 #define CHIP_91100 7
890 #define CHIP_91100FD 8 972 #define CHIP_91100FD 8
891 #define CHIP_91111FD 9 973 #define CHIP_91111FD 9
892 974
893 static const char * chip_ids[ 16 ] = { 975 static const char * chip_ids[ 16 ] = {
894 NULL, NULL, NULL, 976 NULL, NULL, NULL,
895 /* 3 */ "SMC91C90/91C92", 977 /* 3 */ "SMC91C90/91C92",
896 /* 4 */ "SMC91C94", 978 /* 4 */ "SMC91C94",
897 /* 5 */ "SMC91C95", 979 /* 5 */ "SMC91C95",
898 /* 6 */ "SMC91C96", 980 /* 6 */ "SMC91C96",
899 /* 7 */ "SMC91C100", 981 /* 7 */ "SMC91C100",
900 /* 8 */ "SMC91C100FD", 982 /* 8 */ "SMC91C100FD",
901 /* 9 */ "SMC91C11xFD", 983 /* 9 */ "SMC91C11xFD",
902 NULL, NULL, NULL, 984 NULL, NULL, NULL,
903 NULL, NULL, NULL}; 985 NULL, NULL, NULL};
904 986
905 987
906 /* 988 /*
907 . Receive status bits 989 . Receive status bits
908 */ 990 */
909 #define RS_ALGNERR 0x8000 991 #define RS_ALGNERR 0x8000
910 #define RS_BRODCAST 0x4000 992 #define RS_BRODCAST 0x4000
911 #define RS_BADCRC 0x2000 993 #define RS_BADCRC 0x2000
912 #define RS_ODDFRAME 0x1000 994 #define RS_ODDFRAME 0x1000
913 #define RS_TOOLONG 0x0800 995 #define RS_TOOLONG 0x0800
914 #define RS_TOOSHORT 0x0400 996 #define RS_TOOSHORT 0x0400
915 #define RS_MULTICAST 0x0001 997 #define RS_MULTICAST 0x0001
916 #define RS_ERRORS (RS_ALGNERR | RS_BADCR 998 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
917 999
918 1000
919 /* 1001 /*
920 * PHY IDs 1002 * PHY IDs
921 * LAN83C183 == LAN91C111 Internal PHY 1003 * LAN83C183 == LAN91C111 Internal PHY
922 */ 1004 */
923 #define PHY_LAN83C183 0x0016f840 1005 #define PHY_LAN83C183 0x0016f840
924 #define PHY_LAN83C180 0x02821c50 1006 #define PHY_LAN83C180 0x02821c50
925 1007
926 /* 1008 /*
927 * PHY Register Addresses (LAN91C111 Internal 1009 * PHY Register Addresses (LAN91C111 Internal PHY)
928 * 1010 *
929 * Generic PHY registers can be found in <linu 1011 * Generic PHY registers can be found in <linux/mii.h>
930 * 1012 *
931 * These phy registers are specific to our on- 1013 * These phy registers are specific to our on-board phy.
932 */ 1014 */
933 1015
934 // PHY Configuration Register 1 1016 // PHY Configuration Register 1
935 #define PHY_CFG1_REG 0x10 1017 #define PHY_CFG1_REG 0x10
936 #define PHY_CFG1_LNKDIS 0x8000 // 1=R 1018 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
937 #define PHY_CFG1_XMTDIS 0x4000 // 1=T 1019 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
938 #define PHY_CFG1_XMTPDN 0x2000 // 1=T 1020 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
939 #define PHY_CFG1_BYPSCR 0x0400 // 1=B 1021 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
940 #define PHY_CFG1_UNSCDS 0x0200 // 1=U 1022 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
941 #define PHY_CFG1_EQLZR 0x0100 // 1=R 1023 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
942 #define PHY_CFG1_CABLE 0x0080 // 1=S 1024 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
943 #define PHY_CFG1_RLVL0 0x0040 // 1=R 1025 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
944 #define PHY_CFG1_TLVL_SHIFT 2 // Tra 1026 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
945 #define PHY_CFG1_TLVL_MASK 0x003C 1027 #define PHY_CFG1_TLVL_MASK 0x003C
946 #define PHY_CFG1_TRF_MASK 0x0003 // Tra 1028 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
947 1029
948 1030
949 // PHY Configuration Register 2 1031 // PHY Configuration Register 2
950 #define PHY_CFG2_REG 0x11 1032 #define PHY_CFG2_REG 0x11
951 #define PHY_CFG2_APOLDIS 0x0020 // 1=A 1033 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
952 #define PHY_CFG2_JABDIS 0x0010 // 1=J 1034 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
953 #define PHY_CFG2_MREG 0x0008 // 1=M 1035 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
954 #define PHY_CFG2_INTMDIO 0x0004 // 1=I 1036 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
955 1037
956 // PHY Status Output (and Interrupt status) Re 1038 // PHY Status Output (and Interrupt status) Register
957 #define PHY_INT_REG 0x12 // Sta 1039 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
958 #define PHY_INT_INT 0x8000 // 1=b 1040 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
959 #define PHY_INT_LNKFAIL 0x4000 // 1=L 1041 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
960 #define PHY_INT_LOSSSYNC 0x2000 // 1=D 1042 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
961 #define PHY_INT_CWRD 0x1000 // 1=I 1043 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
962 #define PHY_INT_SSD 0x0800 // 1=N 1044 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
963 #define PHY_INT_ESD 0x0400 // 1=N 1045 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
964 #define PHY_INT_RPOL 0x0200 // 1=R 1046 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
965 #define PHY_INT_JAB 0x0100 // 1=J 1047 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
966 #define PHY_INT_SPDDET 0x0080 // 1=1 1048 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
967 #define PHY_INT_DPLXDET 0x0040 // 1=D 1049 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
968 1050
969 // PHY Interrupt/Status Mask Register 1051 // PHY Interrupt/Status Mask Register
970 #define PHY_MASK_REG 0x13 // Int 1052 #define PHY_MASK_REG 0x13 // Interrupt Mask
971 // Uses the same bit definitions as PHY_INT_RE 1053 // Uses the same bit definitions as PHY_INT_REG
972 1054
973 1055
974 /* 1056 /*
975 * SMC91C96 ethernet config and status registe 1057 * SMC91C96 ethernet config and status registers.
976 * These are in the "attribute" space. 1058 * These are in the "attribute" space.
977 */ 1059 */
978 #define ECOR 0x8000 1060 #define ECOR 0x8000
979 #define ECOR_RESET 0x80 1061 #define ECOR_RESET 0x80
980 #define ECOR_LEVEL_IRQ 0x40 1062 #define ECOR_LEVEL_IRQ 0x40
981 #define ECOR_WR_ATTRIB 0x04 1063 #define ECOR_WR_ATTRIB 0x04
982 #define ECOR_ENABLE 0x01 1064 #define ECOR_ENABLE 0x01
983 1065
984 #define ECSR 0x8002 1066 #define ECSR 0x8002
985 #define ECSR_IOIS8 0x20 1067 #define ECSR_IOIS8 0x20
986 #define ECSR_PWRDWN 0x04 1068 #define ECSR_PWRDWN 0x04
987 #define ECSR_INT 0x02 1069 #define ECSR_INT 0x02
988 1070
989 #define ATTRIB_SIZE ((64*1024) << 1071 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
990 1072
991 1073
992 /* 1074 /*
993 * Macros to abstract register access accordin 1075 * Macros to abstract register access according to the data bus
994 * capabilities. Please use those and not the 1076 * capabilities. Please use those and not the in/out primitives.
995 * Note: the following macros do *not* select 1077 * Note: the following macros do *not* select the bank -- this must
996 * be done separately as needed in the main co 1078 * be done separately as needed in the main code. The SMC_REG() macro
997 * only uses the bank argument for debugging p 1079 * only uses the bank argument for debugging purposes (when enabled).
998 * 1080 *
999 * Note: despite inline functions being safer, 1081 * Note: despite inline functions being safer, everything leading to this
1000 * should preferably be macros to let BUG() d 1082 * should preferably be macros to let BUG() display the line number in
1001 * the core source code since we're intereste 1083 * the core source code since we're interested in the top call site
1002 * not in any inline function location. 1084 * not in any inline function location.
1003 */ 1085 */
1004 1086
1005 #if SMC_DEBUG > 0 1087 #if SMC_DEBUG > 0
1006 #define SMC_REG(lp, reg, bank) !! 1088 #define SMC_REG(reg, bank) \
1007 ({ 1089 ({ \
1008 int __b = SMC_CURRENT_BANK(lp !! 1090 int __b = SMC_CURRENT_BANK(); \
1009 if (unlikely((__b & ~0xf0) != 1091 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1010 printk( "%s: bank reg 1092 printk( "%s: bank reg screwed (0x%04x)\n", \
1011 CARDNAME, __b 1093 CARDNAME, __b ); \
1012 BUG(); 1094 BUG(); \
1013 } 1095 } \
1014 reg<<SMC_IO_SHIFT; 1096 reg<<SMC_IO_SHIFT; \
1015 }) 1097 })
1016 #else 1098 #else
1017 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_ !! 1099 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1018 #endif 1100 #endif
1019 1101
1020 /* 1102 /*
1021 * Hack Alert: Some setups just can't write 8 1103 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1022 * aligned to a 32 bit boundary. I tell you 1104 * aligned to a 32 bit boundary. I tell you that does exist!
1023 * Fortunately the affected register accesses 1105 * Fortunately the affected register accesses can be easily worked around
1024 * since we can write zeroes to the preceedin 1106 * since we can write zeroes to the preceeding 16 bits without adverse
1025 * effects and use a 32-bit access. 1107 * effects and use a 32-bit access.
1026 * 1108 *
1027 * Enforce it on any 32-bit capable setup for 1109 * Enforce it on any 32-bit capable setup for now.
1028 */ 1110 */
1029 #define SMC_MUST_ALIGN_WRITE(lp) SMC_3 !! 1111 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1030 1112
1031 #define SMC_GET_PN(lp) !! 1113 #define SMC_GET_PN() \
1032 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN !! 1114 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1033 : (SMC_inw(io !! 1115 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1034 1116
1035 #define SMC_SET_PN(lp, x) !! 1117 #define SMC_SET_PN(x) \
1036 do { 1118 do { \
1037 if (SMC_MUST_ALIGN_WRITE(lp)) !! 1119 if (SMC_MUST_ALIGN_WRITE) \
1038 SMC_outl((x)<<16, ioa !! 1120 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1039 else if (SMC_8BIT(lp)) !! 1121 else if (SMC_CAN_USE_8BIT) \
1040 SMC_outb(x, ioaddr, P !! 1122 SMC_outb(x, ioaddr, PN_REG); \
1041 else 1123 else \
1042 SMC_outw(x, ioaddr, P !! 1124 SMC_outw(x, ioaddr, PN_REG); \
1043 } while (0) 1125 } while (0)
1044 1126
1045 #define SMC_GET_AR(lp) !! 1127 #define SMC_GET_AR() \
1046 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR !! 1128 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1047 : (SMC_inw(io !! 1129 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1048 !! 1130
1049 #define SMC_GET_TXFIFO(lp) !! 1131 #define SMC_GET_TXFIFO() \
1050 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TX !! 1132 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1051 : (SMC_inw(io !! 1133 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1052 !! 1134
1053 #define SMC_GET_RXFIFO(lp) !! 1135 #define SMC_GET_RXFIFO() \
1054 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RX !! 1136 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1055 : (SMC_inw(io !! 1137 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1056 !! 1138
1057 #define SMC_GET_INT(lp) !! 1139 #define SMC_GET_INT() \
1058 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IN !! 1140 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1059 : (SMC_inw(io !! 1141 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1060 1142
1061 #define SMC_ACK_INT(lp, x) !! 1143 #define SMC_ACK_INT(x) \
1062 do { 1144 do { \
1063 if (SMC_8BIT(lp)) !! 1145 if (SMC_CAN_USE_8BIT) \
1064 SMC_outb(x, ioaddr, I !! 1146 SMC_outb(x, ioaddr, INT_REG); \
1065 else { 1147 else { \
1066 unsigned long __flags 1148 unsigned long __flags; \
1067 int __mask; 1149 int __mask; \
1068 local_irq_save(__flag 1150 local_irq_save(__flags); \
1069 __mask = SMC_inw(ioad !! 1151 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1070 SMC_outw(__mask | (x) !! 1152 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1071 local_irq_restore(__f 1153 local_irq_restore(__flags); \
1072 } 1154 } \
1073 } while (0) 1155 } while (0)
1074 1156
1075 #define SMC_GET_INT_MASK(lp) !! 1157 #define SMC_GET_INT_MASK() \
1076 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM !! 1158 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1077 : (SMC_inw(io !! 1159 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1078 1160
1079 #define SMC_SET_INT_MASK(lp, x) !! 1161 #define SMC_SET_INT_MASK(x) \
1080 do { 1162 do { \
1081 if (SMC_8BIT(lp)) !! 1163 if (SMC_CAN_USE_8BIT) \
1082 SMC_outb(x, ioaddr, I !! 1164 SMC_outb(x, ioaddr, IM_REG); \
1083 else 1165 else \
1084 SMC_outw((x) << 8, io !! 1166 SMC_outw((x) << 8, ioaddr, INT_REG); \
1085 } while (0) 1167 } while (0)
1086 1168
1087 #define SMC_CURRENT_BANK(lp) SMC_inw(ioadd !! 1169 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1088 1170
1089 #define SMC_SELECT_BANK(lp, x) !! 1171 #define SMC_SELECT_BANK(x) \
1090 do { 1172 do { \
1091 if (SMC_MUST_ALIGN_WRITE(lp)) !! 1173 if (SMC_MUST_ALIGN_WRITE) \
1092 SMC_outl((x)<<16, ioa 1174 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1093 else 1175 else \
1094 SMC_outw(x, ioaddr, B 1176 SMC_outw(x, ioaddr, BANK_SELECT); \
1095 } while (0) 1177 } while (0)
1096 1178
1097 #define SMC_GET_BASE(lp) SMC_i !! 1179 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1098 1180
1099 #define SMC_SET_BASE(lp, x) SMC_o !! 1181 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1100 1182
1101 #define SMC_GET_CONFIG(lp) SMC_inw(ioadd !! 1183 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1102 1184
1103 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, i !! 1185 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1104 1186
1105 #define SMC_GET_COUNTER(lp) SMC_inw(ioadd !! 1187 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1106 1188
1107 #define SMC_GET_CTL(lp) SMC_inw(ioadd !! 1189 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1108 1190
1109 #define SMC_SET_CTL(lp, x) SMC_o !! 1191 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1110 1192
1111 #define SMC_GET_MII(lp) SMC_inw(ioadd !! 1193 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1112 <<
1113 #define SMC_GET_GP(lp) SMC_inw(ioadd <<
1114 <<
1115 #define SMC_SET_GP(lp, x) <<
1116 do { <<
1117 if (SMC_MUST_ALIGN_WRITE(lp)) <<
1118 SMC_outl((x)<<16, ioa <<
1119 else <<
1120 SMC_outw(x, ioaddr, G <<
1121 } while (0) <<
1122 1194
1123 #define SMC_SET_MII(lp, x) SMC_o !! 1195 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1124 1196
1125 #define SMC_GET_MIR(lp) SMC_inw(ioadd !! 1197 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1126 1198
1127 #define SMC_SET_MIR(lp, x) SMC_o !! 1199 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1128 1200
1129 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioadd !! 1201 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1130 1202
1131 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, i !! 1203 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1132 1204
1133 #define SMC_GET_FIFO(lp) SMC_i !! 1205 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1134 1206
1135 #define SMC_GET_PTR(lp) SMC_inw(ioadd !! 1207 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1136 1208
1137 #define SMC_SET_PTR(lp, x) !! 1209 #define SMC_SET_PTR(x) \
1138 do { 1210 do { \
1139 if (SMC_MUST_ALIGN_WRITE(lp)) !! 1211 if (SMC_MUST_ALIGN_WRITE) \
1140 SMC_outl((x)<<16, ioa !! 1212 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1141 else 1213 else \
1142 SMC_outw(x, ioaddr, P !! 1214 SMC_outw(x, ioaddr, PTR_REG); \
1143 } while (0) 1215 } while (0)
1144 1216
1145 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioadd !! 1217 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1146 1218
1147 #define SMC_GET_RCR(lp) SMC_inw(ioadd !! 1219 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1148 1220
1149 #define SMC_SET_RCR(lp, x) SMC_o !! 1221 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1150 1222
1151 #define SMC_GET_REV(lp) SMC_inw(ioadd !! 1223 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1152 1224
1153 #define SMC_GET_RPC(lp) SMC_inw(ioadd !! 1225 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1154 1226
1155 #define SMC_SET_RPC(lp, x) !! 1227 #define SMC_SET_RPC(x) \
1156 do { 1228 do { \
1157 if (SMC_MUST_ALIGN_WRITE(lp)) !! 1229 if (SMC_MUST_ALIGN_WRITE) \
1158 SMC_outl((x)<<16, ioa !! 1230 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1159 else 1231 else \
1160 SMC_outw(x, ioaddr, R !! 1232 SMC_outw(x, ioaddr, RPC_REG); \
1161 } while (0) 1233 } while (0)
1162 1234
1163 #define SMC_GET_TCR(lp) SMC_inw(ioadd !! 1235 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1164 1236
1165 #define SMC_SET_TCR(lp, x) SMC_o !! 1237 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1166 1238
1167 #ifndef SMC_GET_MAC_ADDR 1239 #ifndef SMC_GET_MAC_ADDR
1168 #define SMC_GET_MAC_ADDR(lp, addr) !! 1240 #define SMC_GET_MAC_ADDR(addr) \
1169 do { 1241 do { \
1170 unsigned int __v; 1242 unsigned int __v; \
1171 __v = SMC_inw(ioaddr, ADDR0_R !! 1243 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1172 addr[0] = __v; addr[1] = __v 1244 addr[0] = __v; addr[1] = __v >> 8; \
1173 __v = SMC_inw(ioaddr, ADDR1_R !! 1245 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1174 addr[2] = __v; addr[3] = __v 1246 addr[2] = __v; addr[3] = __v >> 8; \
1175 __v = SMC_inw(ioaddr, ADDR2_R !! 1247 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1176 addr[4] = __v; addr[5] = __v 1248 addr[4] = __v; addr[5] = __v >> 8; \
1177 } while (0) 1249 } while (0)
1178 #endif 1250 #endif
1179 1251
1180 #define SMC_SET_MAC_ADDR(lp, addr) !! 1252 #define SMC_SET_MAC_ADDR(addr) \
1181 do { 1253 do { \
1182 SMC_outw(addr[0]|(addr[1] << !! 1254 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1183 SMC_outw(addr[2]|(addr[3] << !! 1255 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1184 SMC_outw(addr[4]|(addr[5] << !! 1256 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1185 } while (0) 1257 } while (0)
1186 1258
1187 #define SMC_SET_MCAST(lp, x) !! 1259 #define SMC_SET_MCAST(x) \
1188 do { 1260 do { \
1189 const unsigned char *mt = (x) 1261 const unsigned char *mt = (x); \
1190 SMC_outw(mt[0] | (mt[1] << 8) !! 1262 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1191 SMC_outw(mt[2] | (mt[3] << 8) !! 1263 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1192 SMC_outw(mt[4] | (mt[5] << 8) !! 1264 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1193 SMC_outw(mt[6] | (mt[7] << 8) !! 1265 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1194 } while (0) 1266 } while (0)
1195 1267
1196 #define SMC_PUT_PKT_HDR(lp, status, length) !! 1268 #define SMC_PUT_PKT_HDR(status, length) \
1197 do { 1269 do { \
1198 if (SMC_32BIT(lp)) !! 1270 if (SMC_CAN_USE_32BIT) \
1199 SMC_outl((status) | ( !! 1271 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1200 DATA_REG(lp) <<
1201 else { 1272 else { \
1202 SMC_outw(status, ioad !! 1273 SMC_outw(status, ioaddr, DATA_REG); \
1203 SMC_outw(length, ioad !! 1274 SMC_outw(length, ioaddr, DATA_REG); \
1204 } 1275 } \
1205 } while (0) 1276 } while (0)
1206 1277
1207 #define SMC_GET_PKT_HDR(lp, status, length) !! 1278 #define SMC_GET_PKT_HDR(status, length) \
1208 do { 1279 do { \
1209 if (SMC_32BIT(lp)) { !! 1280 if (SMC_CAN_USE_32BIT) { \
1210 unsigned int __val = !! 1281 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1211 (status) = __val & 0x 1282 (status) = __val & 0xffff; \
1212 (length) = __val >> 1 1283 (length) = __val >> 16; \
1213 } else { 1284 } else { \
1214 (status) = SMC_inw(io !! 1285 (status) = SMC_inw(ioaddr, DATA_REG); \
1215 (length) = SMC_inw(io !! 1286 (length) = SMC_inw(ioaddr, DATA_REG); \
1216 } 1287 } \
1217 } while (0) 1288 } while (0)
1218 1289
1219 #define SMC_PUSH_DATA(lp, p, l) !! 1290 #define SMC_PUSH_DATA(p, l) \
1220 do { 1291 do { \
1221 if (SMC_32BIT(lp)) { !! 1292 if (SMC_CAN_USE_32BIT) { \
1222 void *__ptr = (p); 1293 void *__ptr = (p); \
1223 int __len = (l); 1294 int __len = (l); \
1224 void __iomem *__ioadd 1295 void __iomem *__ioaddr = ioaddr; \
1225 if (__len >= 2 && (un 1296 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1226 __len -= 2; 1297 __len -= 2; \
1227 SMC_outw(*(u1 !! 1298 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1228 DATA_ <<
1229 __ptr += 2; 1299 __ptr += 2; \
1230 } 1300 } \
1231 if (SMC_CAN_USE_DATAC 1301 if (SMC_CAN_USE_DATACS && lp->datacs) \
1232 __ioaddr = lp 1302 __ioaddr = lp->datacs; \
1233 SMC_outsl(__ioaddr, D !! 1303 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1234 if (__len & 2) { 1304 if (__len & 2) { \
1235 __ptr += (__l 1305 __ptr += (__len & ~3); \
1236 SMC_outw(*((u !! 1306 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1237 DATA <<
1238 } 1307 } \
1239 } else if (SMC_16BIT(lp)) !! 1308 } else if (SMC_CAN_USE_16BIT) \
1240 SMC_outsw(ioaddr, DAT !! 1309 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1241 else if (SMC_8BIT(lp)) !! 1310 else if (SMC_CAN_USE_8BIT) \
1242 SMC_outsb(ioaddr, DAT !! 1311 SMC_outsb(ioaddr, DATA_REG, p, l); \
1243 } while (0) 1312 } while (0)
1244 1313
1245 #define SMC_PULL_DATA(lp, p, l) !! 1314 #define SMC_PULL_DATA(p, l) \
1246 do { 1315 do { \
1247 if (SMC_32BIT(lp)) { !! 1316 if (SMC_CAN_USE_32BIT) { \
1248 void *__ptr = (p); 1317 void *__ptr = (p); \
1249 int __len = (l); 1318 int __len = (l); \
1250 void __iomem *__ioadd 1319 void __iomem *__ioaddr = ioaddr; \
1251 if ((unsigned long)__ 1320 if ((unsigned long)__ptr & 2) { \
1252 /* 1321 /* \
1253 * We want 32 1322 * We want 32bit alignment here. \
1254 * Since some 1323 * Since some buses perform a full \
1255 * 32bit fetc 1324 * 32bit fetch even for 16bit data \
1256 * we can't u 1325 * we can't use SMC_inw() here. \
1257 * Back both 1326 * Back both source (on-chip) and \
1258 * destinatio 1327 * destination pointers of 2 bytes. \
1259 * This is po 1328 * This is possible since the call to \
1260 * SMC_GET_PK 1329 * SMC_GET_PKT_HDR() already advanced \
1261 * the source 1330 * the source pointer of 4 bytes, and \
1262 * the skb_re 1331 * the skb_reserve(skb, 2) advanced \
1263 * the destin 1332 * the destination pointer of 2 bytes. \
1264 */ 1333 */ \
1265 __ptr -= 2; 1334 __ptr -= 2; \
1266 __len += 2; 1335 __len += 2; \
1267 SMC_SET_PTR(l !! 1336 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1268 2|PTR <<
1269 } 1337 } \
1270 if (SMC_CAN_USE_DATAC 1338 if (SMC_CAN_USE_DATACS && lp->datacs) \
1271 __ioaddr = lp 1339 __ioaddr = lp->datacs; \
1272 __len += 2; 1340 __len += 2; \
1273 SMC_insl(__ioaddr, DA !! 1341 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1274 } else if (SMC_16BIT(lp)) !! 1342 } else if (SMC_CAN_USE_16BIT) \
1275 SMC_insw(ioaddr, DATA !! 1343 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1276 else if (SMC_8BIT(lp)) !! 1344 else if (SMC_CAN_USE_8BIT) \
1277 SMC_insb(ioaddr, DATA !! 1345 SMC_insb(ioaddr, DATA_REG, p, l); \
1278 } while (0) 1346 } while (0)
1279 1347
1280 #endif /* _SMC91X_H_ */ 1348 #endif /* _SMC91X_H_ */
1281 1349
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