Diff markup
1 /*-------------------------------------------- 1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx s 2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 . 3 .
4 . Copyright (C) 1996 by Erik Stahlman 4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Co 5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corp 6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, In 7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre 8 . Unified SMC91x driver by Nicolas Pitre
9 . 9 .
10 . This program is free software; you can redi 10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Publi 11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either versio 12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version. 13 . (at your option) any later version.
14 . 14 .
15 . This program is distributed in the hope tha 15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the 16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR 17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details 18 . GNU General Public License for more details.
19 . 19 .
20 . You should have received a copy of the GNU 20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to t 21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 33 22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 . 23 .
24 . Information contained in this file was obta 24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you rea 25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com. 26 . information under www.smsc.com.
27 . 27 .
28 . Authors 28 . Authors
29 . Erik Stahlman <erik@vt.edu> 29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.c 30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org> 31 . Nicolas Pitre <nico@cam.org>
32 . 32 .
33 --------------------------------------------- 33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_ 34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_ 35 #define _SMC91X_H_
36 36
37 #include <linux/smc91x.h> <<
38 37
39 /* 38 /*
40 * Define your architecture specific bus confi 39 * Define your architecture specific bus configuration parameters here.
41 */ 40 */
42 41
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\ !! 42 #if defined(CONFIG_ARCH_LUBBOCK)
44 defined(CONFIG_MACH_MAINSTONE) ||\ <<
45 defined(CONFIG_MACH_ZYLONITE) ||\ <<
46 defined(CONFIG_MACH_LITTLETON) ||\ <<
47 defined(CONFIG_MACH_ZYLONITE2) ||\ <<
48 defined(CONFIG_ARCH_VIPER) ||\ <<
49 defined(CONFIG_MACH_STARGATE2) <<
50 <<
51 #include <asm/mach-types.h> <<
52 <<
53 /* Now the bus width is specified in the platf <<
54 * pretend here to support all I/O access type <<
55 */ <<
56 #define SMC_CAN_USE_8BIT 1 <<
57 #define SMC_CAN_USE_16BIT 1 <<
58 #define SMC_CAN_USE_32BIT 1 <<
59 #define SMC_NOWAIT 1 <<
60 <<
61 #define SMC_IO_SHIFT (lp->io_shift) <<
62 <<
63 #define SMC_inb(a, r) readb((a) + (r <<
64 #define SMC_inw(a, r) readw((a) + (r <<
65 #define SMC_inl(a, r) readl((a) + (r <<
66 #define SMC_outb(v, a, r) writeb(v, (a) <<
67 #define SMC_outl(v, a, r) writel(v, (a) <<
68 #define SMC_insw(a, r, p, l) readsw((a) + ( <<
69 #define SMC_outsw(a, r, p, l) writesw((a) + <<
70 #define SMC_insl(a, r, p, l) readsl((a) + ( <<
71 #define SMC_outsl(a, r, p, l) writesl((a) + <<
72 #define SMC_IRQ_FLAGS (-1) /* fro <<
73 <<
74 /* We actually can't write halfwords properly <<
75 static inline void SMC_outw(u16 val, void __io <<
76 { <<
77 if ((machine_is_mainstone() || machine <<
78 unsigned int v = val << 16; <<
79 v |= readl(ioaddr + (reg & ~2) <<
80 writel(v, ioaddr + (reg & ~2)) <<
81 } else { <<
82 writew(val, ioaddr + reg); <<
83 } <<
84 } <<
85 <<
86 #elif defined(CONFIG_BLACKFIN) <<
87 <<
88 #define SMC_IRQ_FLAGS IRQF_TRIGGER_H <<
89 #define RPC_LSA_DEFAULT RPC_LED_100_10 <<
90 #define RPC_LSB_DEFAULT RPC_LED_TX_RX <<
91 43
>> 44 /* We can only do 16-bit reads and writes in the static memory space. */
92 #define SMC_CAN_USE_8BIT 0 45 #define SMC_CAN_USE_8BIT 0
93 #define SMC_CAN_USE_16BIT 1 46 #define SMC_CAN_USE_16BIT 1
94 # if defined(CONFIG_BF561) <<
95 #define SMC_CAN_USE_32BIT 1 <<
96 # else <<
97 #define SMC_CAN_USE_32BIT 0 47 #define SMC_CAN_USE_32BIT 0
98 # endif !! 48 #define SMC_NOWAIT 1
99 #define SMC_IO_SHIFT 0 !! 49
100 #define SMC_NOWAIT 1 !! 50 /* The first two address lines aren't connected... */
101 #define SMC_USE_BFIN_DMA 0 !! 51 #define SMC_IO_SHIFT 2
102 52
103 #define SMC_inw(a, r) readw((a) + (r 53 #define SMC_inw(a, r) readw((a) + (r))
104 #define SMC_outw(v, a, r) writew(v, (a) 54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
105 #define SMC_insw(a, r, p, l) readsw((a) + ( 55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
106 #define SMC_outsw(a, r, p, l) writesw((a) + 56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
107 # if SMC_CAN_USE_32BIT <<
108 #define SMC_inl(a, r) readl((a) + (r <<
109 #define SMC_outl(v, a, r) writel(v, (a) <<
110 #define SMC_insl(a, r, p, l) readsl((a) + ( <<
111 #define SMC_outsl(a, r, p, l) writesl((a) + <<
112 # endif <<
113 57
114 #elif defined(CONFIG_REDWOOD_5) || defined(CON 58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
115 59
116 /* We can only do 16-bit reads and writes in t 60 /* We can only do 16-bit reads and writes in the static memory space. */
117 #define SMC_CAN_USE_8BIT 0 61 #define SMC_CAN_USE_8BIT 0
118 #define SMC_CAN_USE_16BIT 1 62 #define SMC_CAN_USE_16BIT 1
119 #define SMC_CAN_USE_32BIT 0 63 #define SMC_CAN_USE_32BIT 0
120 #define SMC_NOWAIT 1 64 #define SMC_NOWAIT 1
121 65
122 #define SMC_IO_SHIFT 0 66 #define SMC_IO_SHIFT 0
123 67
124 #define SMC_inw(a, r) in_be16((volat 68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
125 #define SMC_outw(v, a, r) out_be16((vola 69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
126 #define SMC_insw(a, r, p, l) 70 #define SMC_insw(a, r, p, l) \
127 do { 71 do { \
128 unsigned long __port = (a) + ( 72 unsigned long __port = (a) + (r); \
129 u16 *__p = (u16 *)(p); 73 u16 *__p = (u16 *)(p); \
130 int __l = (l); 74 int __l = (l); \
131 insw(__port, __p, __l); 75 insw(__port, __p, __l); \
132 while (__l > 0) { 76 while (__l > 0) { \
133 *__p = swab16(*__p); 77 *__p = swab16(*__p); \
134 __p++; 78 __p++; \
135 __l--; 79 __l--; \
136 } 80 } \
137 } while (0) 81 } while (0)
138 #define SMC_outsw(a, r, p, l) 82 #define SMC_outsw(a, r, p, l) \
139 do { 83 do { \
140 unsigned long __port = (a) + ( 84 unsigned long __port = (a) + (r); \
141 u16 *__p = (u16 *)(p); 85 u16 *__p = (u16 *)(p); \
142 int __l = (l); 86 int __l = (l); \
143 while (__l > 0) { 87 while (__l > 0) { \
144 /* Believe it or not, 88 /* Believe it or not, the swab isn't needed. */ \
145 outw( /* swab16 */ (*_ 89 outw( /* swab16 */ (*__p++), __port); \
146 __l--; 90 __l--; \
147 } 91 } \
148 } while (0) 92 } while (0)
149 #define SMC_IRQ_FLAGS (0) !! 93 #define set_irq_type(irq, type)
150 94
151 #elif defined(CONFIG_SA1100_PLEB) 95 #elif defined(CONFIG_SA1100_PLEB)
152 /* We can only do 16-bit reads and writes in t 96 /* We can only do 16-bit reads and writes in the static memory space. */
153 #define SMC_CAN_USE_8BIT 1 97 #define SMC_CAN_USE_8BIT 1
154 #define SMC_CAN_USE_16BIT 1 98 #define SMC_CAN_USE_16BIT 1
155 #define SMC_CAN_USE_32BIT 0 99 #define SMC_CAN_USE_32BIT 0
156 #define SMC_IO_SHIFT 0 100 #define SMC_IO_SHIFT 0
157 #define SMC_NOWAIT 1 101 #define SMC_NOWAIT 1
158 102
159 #define SMC_inb(a, r) readb((a) + (r !! 103 #define SMC_inb(a, r) inb((a) + (r))
160 #define SMC_insb(a, r, p, l) readsb((a) + ( !! 104 #define SMC_insb(a, r, p, l) insb((a) + (r), p, (l))
161 #define SMC_inw(a, r) readw((a) + (r !! 105 #define SMC_inw(a, r) inw((a) + (r))
162 #define SMC_insw(a, r, p, l) readsw((a) + ( !! 106 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
163 #define SMC_outb(v, a, r) writeb(v, (a) !! 107 #define SMC_outb(v, a, r) outb(v, (a) + (r))
164 #define SMC_outsb(a, r, p, l) writesb((a) + !! 108 #define SMC_outsb(a, r, p, l) outsb((a) + (r), p, (l))
165 #define SMC_outw(v, a, r) writew(v, (a) !! 109 #define SMC_outw(v, a, r) outw(v, (a) + (r))
166 #define SMC_outsw(a, r, p, l) writesw((a) + !! 110 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
167 111
168 #define SMC_IRQ_FLAGS (-1) !! 112 #define set_irq_type(irq, type) do {} while (0)
169 113
170 #elif defined(CONFIG_SA1100_ASSABET) 114 #elif defined(CONFIG_SA1100_ASSABET)
171 115
172 #include <mach/neponset.h> !! 116 #include <asm/arch/neponset.h>
173 117
174 /* We can only do 8-bit reads and writes in th 118 /* We can only do 8-bit reads and writes in the static memory space. */
175 #define SMC_CAN_USE_8BIT 1 119 #define SMC_CAN_USE_8BIT 1
176 #define SMC_CAN_USE_16BIT 0 120 #define SMC_CAN_USE_16BIT 0
177 #define SMC_CAN_USE_32BIT 0 121 #define SMC_CAN_USE_32BIT 0
178 #define SMC_NOWAIT 1 122 #define SMC_NOWAIT 1
179 123
180 /* The first two address lines aren't connecte 124 /* The first two address lines aren't connected... */
181 #define SMC_IO_SHIFT 2 125 #define SMC_IO_SHIFT 2
182 126
183 #define SMC_inb(a, r) readb((a) + (r 127 #define SMC_inb(a, r) readb((a) + (r))
184 #define SMC_outb(v, a, r) writeb(v, (a) 128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
185 #define SMC_insb(a, r, p, l) readsb((a) + ( 129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
186 #define SMC_outsb(a, r, p, l) writesb((a) + 130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
187 #define SMC_IRQ_FLAGS (-1) /* fro <<
188 <<
189 #elif defined(CONFIG_MACH_LOGICPD_PXA270) \ <<
190 || defined(CONFIG_MACH_NOMADIK_8815NHK <<
191 <<
192 #define SMC_CAN_USE_8BIT 0 <<
193 #define SMC_CAN_USE_16BIT 1 <<
194 #define SMC_CAN_USE_32BIT 0 <<
195 #define SMC_IO_SHIFT 0 <<
196 #define SMC_NOWAIT 1 <<
197 <<
198 #define SMC_inw(a, r) readw((a) + (r <<
199 #define SMC_outw(v, a, r) writew(v, (a) <<
200 #define SMC_insw(a, r, p, l) readsw((a) + ( <<
201 #define SMC_outsw(a, r, p, l) writesw((a) + <<
202 131
203 #elif defined(CONFIG_ARCH_INNOKOM) || \ 132 #elif defined(CONFIG_ARCH_INNOKOM) || \
>> 133 defined(CONFIG_MACH_MAINSTONE) || \
204 defined(CONFIG_ARCH_PXA_IDP) || \ 134 defined(CONFIG_ARCH_PXA_IDP) || \
205 defined(CONFIG_ARCH_RAMSES) || \ !! 135 defined(CONFIG_ARCH_RAMSES)
206 defined(CONFIG_ARCH_PCM027) <<
207 136
208 #define SMC_CAN_USE_8BIT 1 137 #define SMC_CAN_USE_8BIT 1
209 #define SMC_CAN_USE_16BIT 1 138 #define SMC_CAN_USE_16BIT 1
210 #define SMC_CAN_USE_32BIT 1 139 #define SMC_CAN_USE_32BIT 1
211 #define SMC_IO_SHIFT 0 140 #define SMC_IO_SHIFT 0
212 #define SMC_NOWAIT 1 141 #define SMC_NOWAIT 1
213 #define SMC_USE_PXA_DMA 1 142 #define SMC_USE_PXA_DMA 1
214 143
215 #define SMC_inb(a, r) readb((a) + (r 144 #define SMC_inb(a, r) readb((a) + (r))
216 #define SMC_inw(a, r) readw((a) + (r 145 #define SMC_inw(a, r) readw((a) + (r))
217 #define SMC_inl(a, r) readl((a) + (r 146 #define SMC_inl(a, r) readl((a) + (r))
218 #define SMC_outb(v, a, r) writeb(v, (a) 147 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
219 #define SMC_outl(v, a, r) writel(v, (a) 148 #define SMC_outl(v, a, r) writel(v, (a) + (r))
220 #define SMC_insl(a, r, p, l) readsl((a) + ( 149 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
221 #define SMC_outsl(a, r, p, l) writesl((a) + 150 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
222 #define SMC_IRQ_FLAGS (-1) /* fro <<
223 151
224 /* We actually can't write halfwords properly 152 /* We actually can't write halfwords properly if not word aligned */
225 static inline void 153 static inline void
226 SMC_outw(u16 val, void __iomem *ioaddr, int re !! 154 SMC_outw(u16 val, unsigned long ioaddr, int reg)
227 { 155 {
228 if (reg & 2) { 156 if (reg & 2) {
229 unsigned int v = val << 16; 157 unsigned int v = val << 16;
230 v |= readl(ioaddr + (reg & ~2) 158 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
231 writel(v, ioaddr + (reg & ~2)) 159 writel(v, ioaddr + (reg & ~2));
232 } else { 160 } else {
233 writew(val, ioaddr + reg); 161 writew(val, ioaddr + reg);
234 } 162 }
235 } 163 }
236 164
237 #elif defined(CONFIG_ARCH_OMAP) !! 165 #elif defined(CONFIG_ISA)
238 166
239 /* We can only do 16-bit reads and writes in t !! 167 #define SMC_CAN_USE_8BIT 1
240 #define SMC_CAN_USE_8BIT 0 <<
241 #define SMC_CAN_USE_16BIT 1 168 #define SMC_CAN_USE_16BIT 1
242 #define SMC_CAN_USE_32BIT 0 169 #define SMC_CAN_USE_32BIT 0
243 #define SMC_IO_SHIFT 0 <<
244 #define SMC_NOWAIT 1 <<
245 170
246 #define SMC_inw(a, r) readw((a) + (r !! 171 #define SMC_inb(a, r) inb((a) + (r))
247 #define SMC_outw(v, a, r) writew(v, (a) !! 172 #define SMC_inw(a, r) inw((a) + (r))
248 #define SMC_insw(a, r, p, l) readsw((a) + ( !! 173 #define SMC_outb(v, a, r) outb(v, (a) + (r))
249 #define SMC_outsw(a, r, p, l) writesw((a) + !! 174 #define SMC_outw(v, a, r) outw(v, (a) + (r))
250 #define SMC_IRQ_FLAGS (-1) /* fro !! 175 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
>> 176 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
251 177
252 #elif defined(CONFIG_SH_SH4202_MICRODEV) !! 178 #elif defined(CONFIG_M32R)
253 179
254 #define SMC_CAN_USE_8BIT 0 180 #define SMC_CAN_USE_8BIT 0
255 #define SMC_CAN_USE_16BIT 1 181 #define SMC_CAN_USE_16BIT 1
256 #define SMC_CAN_USE_32BIT 0 182 #define SMC_CAN_USE_32BIT 0
257 183
258 #define SMC_inb(a, r) inb((a) + (r) 184 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
259 #define SMC_inw(a, r) inw((a) + (r) 185 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
260 #define SMC_inl(a, r) inl((a) + (r) <<
261 #define SMC_outb(v, a, r) outb(v, (a) + 186 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
262 #define SMC_outw(v, a, r) outw(v, (a) + 187 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
263 #define SMC_outl(v, a, r) outl(v, (a) + <<
264 #define SMC_insl(a, r, p, l) insl((a) + (r) <<
265 #define SMC_outsl(a, r, p, l) outsl((a) + (r <<
266 #define SMC_insw(a, r, p, l) insw((a) + (r) 188 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
267 #define SMC_outsw(a, r, p, l) outsw((a) + (r 189 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
268 190
269 #define SMC_IRQ_FLAGS (0) !! 191 #define set_irq_type(irq, type) do {} while(0)
270 <<
271 #elif defined(CONFIG_M32R) <<
272 <<
273 #define SMC_CAN_USE_8BIT 0 <<
274 #define SMC_CAN_USE_16BIT 1 <<
275 #define SMC_CAN_USE_32BIT 0 <<
276 <<
277 #define SMC_inb(a, r) inb(((u32)a) + <<
278 #define SMC_inw(a, r) inw(((u32)a) + <<
279 #define SMC_outb(v, a, r) outb(v, ((u32) <<
280 #define SMC_outw(v, a, r) outw(v, ((u32) <<
281 #define SMC_insw(a, r, p, l) insw(((u32)a) <<
282 #define SMC_outsw(a, r, p, l) outsw(((u32)a) <<
283 <<
284 #define SMC_IRQ_FLAGS (0) <<
285 192
286 #define RPC_LSA_DEFAULT RPC_LED_TX_RX 193 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
287 #define RPC_LSB_DEFAULT RPC_LED_100_10 194 #define RPC_LSB_DEFAULT RPC_LED_100_10
288 195
289 #elif defined(CONFIG_MACH_LPD79520) \ !! 196 #elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404)
290 || defined(CONFIG_MACH_LPD7A400) \ !! 197
291 || defined(CONFIG_MACH_LPD7A404) !! 198 /* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between
292 !! 199 * the way that the CPU handles chip selects and the way that the SMC
293 /* The LPD7X_IOBARRIER is necessary to overcom !! 200 * chip expects the chip select to operate. Refer to
294 * way that the CPU handles chip selects and t <<
295 * expects the chip select to operate. Refer <<
296 * Documentation/arm/Sharp-LH/IOBarrier for de 201 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
297 * IOBARRIER is a byte, in order that we read !! 202 * IOBARRIER is a byte as a least-common denominator of possible
298 * denominator. It would be wasteful to read !! 203 * regions to use as the barrier. It would be wasteful to read 32
299 * accessible region. !! 204 * bits from a byte oriented region.
300 * 205 *
301 * There is no explicit protection against int 206 * There is no explicit protection against interrupts intervening
302 * between the writew and the IOBARRIER. In S 207 * between the writew and the IOBARRIER. In SMC ISR there is a
303 * preamble that performs an IOBARRIER in the 208 * preamble that performs an IOBARRIER in the extremely unlikely event
304 * that the driver interrupts itself between a 209 * that the driver interrupts itself between a writew to the chip an
305 * the IOBARRIER that follows *and* the cache 210 * the IOBARRIER that follows *and* the cache is large enough that the
306 * first off-chip access while handing the int 211 * first off-chip access while handing the interrupt is to the SMC
307 * chip. Other devices in the same address sp 212 * chip. Other devices in the same address space as the SMC chip must
308 * be aware of the potential for trouble and p 213 * be aware of the potential for trouble and perform a similar
309 * IOBARRIER on entry to their ISR. 214 * IOBARRIER on entry to their ISR.
310 */ 215 */
311 216
312 #include <mach/constants.h> /* IOBARRIER_V !! 217 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
313 218
314 #define SMC_CAN_USE_8BIT 0 219 #define SMC_CAN_USE_8BIT 0
315 #define SMC_CAN_USE_16BIT 1 220 #define SMC_CAN_USE_16BIT 1
316 #define SMC_CAN_USE_32BIT 0 221 #define SMC_CAN_USE_32BIT 0
317 #define SMC_NOWAIT 0 222 #define SMC_NOWAIT 0
318 #define LPD7X_IOBARRIER readb (IOBARRI !! 223 #define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT)
319 224
320 #define SMC_inw(a,r)\ !! 225 #define SMC_inw(a,r) readw ((void*) ((a) + (r)))
321 ({ unsigned short v = readw ((void*) ((a) + !! 226 #define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l)
322 #define SMC_outw(v,a,r) ({ writew ((v), (a) !! 227 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; })
323 <<
324 #define SMC_insw LPD7_SMC_insw <<
325 static inline void LPD7_SMC_insw (unsigned cha <<
326 unsigned cha <<
327 { <<
328 unsigned short* ps = (unsigned short*) <<
329 while (l-- > 0) { <<
330 *ps++ = readw (a + r); <<
331 LPD7X_IOBARRIER; <<
332 } <<
333 } <<
334 228
335 #define SMC_outsw LPD7_SMC_outsw !! 229 static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l)
336 static inline void LPD7_SMC_outsw (unsigned ch <<
337 unsigned ch <<
338 { 230 {
339 unsigned short* ps = (unsigned short*) 231 unsigned short* ps = (unsigned short*) p;
340 while (l-- > 0) { 232 while (l-- > 0) {
341 writew (*ps++, a + r); 233 writew (*ps++, a + r);
342 LPD7X_IOBARRIER; !! 234 LPD7A40X_IOBARRIER;
343 } 235 }
344 } 236 }
345 237
346 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIE !! 238 #define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER
347 239
348 #define RPC_LSA_DEFAULT RPC_LED_TX_RX 240 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
349 #define RPC_LSB_DEFAULT RPC_LED_100_10 241 #define RPC_LSB_DEFAULT RPC_LED_100_10
350 242
351 #elif defined(CONFIG_ARCH_VERSATILE) <<
352 <<
353 #define SMC_CAN_USE_8BIT 1 <<
354 #define SMC_CAN_USE_16BIT 1 <<
355 #define SMC_CAN_USE_32BIT 1 <<
356 #define SMC_NOWAIT 1 <<
357 <<
358 #define SMC_inb(a, r) readb((a) + (r <<
359 #define SMC_inw(a, r) readw((a) + (r <<
360 #define SMC_inl(a, r) readl((a) + (r <<
361 #define SMC_outb(v, a, r) writeb(v, (a) <<
362 #define SMC_outw(v, a, r) writew(v, (a) <<
363 #define SMC_outl(v, a, r) writel(v, (a) <<
364 #define SMC_insl(a, r, p, l) readsl((a) + ( <<
365 #define SMC_outsl(a, r, p, l) writesl((a) + <<
366 #define SMC_IRQ_FLAGS (-1) /* fro <<
367 <<
368 #elif defined(CONFIG_MN10300) <<
369 <<
370 /* <<
371 * MN10300/AM33 configuration <<
372 */ <<
373 <<
374 #include <unit/smc91111.h> <<
375 <<
376 #else 243 #else
377 244
378 /* <<
379 * Default configuration <<
380 */ <<
381 <<
382 #define SMC_CAN_USE_8BIT 1 245 #define SMC_CAN_USE_8BIT 1
383 #define SMC_CAN_USE_16BIT 1 246 #define SMC_CAN_USE_16BIT 1
384 #define SMC_CAN_USE_32BIT 1 247 #define SMC_CAN_USE_32BIT 1
385 #define SMC_NOWAIT 1 248 #define SMC_NOWAIT 1
386 249
387 #define SMC_IO_SHIFT (lp->io_shift) <<
388 <<
389 #define SMC_inb(a, r) readb((a) + (r 250 #define SMC_inb(a, r) readb((a) + (r))
390 #define SMC_inw(a, r) readw((a) + (r 251 #define SMC_inw(a, r) readw((a) + (r))
391 #define SMC_inl(a, r) readl((a) + (r 252 #define SMC_inl(a, r) readl((a) + (r))
392 #define SMC_outb(v, a, r) writeb(v, (a) 253 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
393 #define SMC_outw(v, a, r) writew(v, (a) 254 #define SMC_outw(v, a, r) writew(v, (a) + (r))
394 #define SMC_outl(v, a, r) writel(v, (a) 255 #define SMC_outl(v, a, r) writel(v, (a) + (r))
395 #define SMC_insw(a, r, p, l) readsw((a) + ( <<
396 #define SMC_outsw(a, r, p, l) writesw((a) + <<
397 #define SMC_insl(a, r, p, l) readsl((a) + ( 256 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
398 #define SMC_outsl(a, r, p, l) writesl((a) + 257 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
399 258
400 #define RPC_LSA_DEFAULT RPC_LED_100_10 259 #define RPC_LSA_DEFAULT RPC_LED_100_10
401 #define RPC_LSB_DEFAULT RPC_LED_TX_RX 260 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
402 261
403 #endif 262 #endif
404 263
405 264
406 /* store this information for the driver.. */ !! 265 #ifdef SMC_USE_PXA_DMA
407 struct smc_local { <<
408 /* <<
409 * If I have to wait until memory is a <<
410 * packet, I will store the skbuff her <<
411 * desired memory. Then, I'll send it <<
412 */ <<
413 struct sk_buff *pending_tx_skb; <<
414 struct tasklet_struct tx_task; <<
415 <<
416 /* version/revision of the SMC91x chip <<
417 int version; <<
418 <<
419 /* Contains the current active transmi <<
420 int tcr_cur_mode; <<
421 <<
422 /* Contains the current active receive <<
423 int rcr_cur_mode; <<
424 <<
425 /* Contains the current active receive <<
426 int rpc_cur_mode; <<
427 int ctl_rfduplx; <<
428 int ctl_rspeed; <<
429 <<
430 u32 msg_enable; <<
431 u32 phy_type; <<
432 struct mii_if_info mii; <<
433 <<
434 /* work queue */ <<
435 struct work_struct phy_configure; <<
436 struct net_device *dev; <<
437 int work_pending; <<
438 <<
439 spinlock_t lock; <<
440 <<
441 #ifdef CONFIG_ARCH_PXA <<
442 /* DMA needs the physical address of t <<
443 u_long physaddr; <<
444 struct device *device; <<
445 #endif <<
446 void __iomem *base; <<
447 void __iomem *datacs; <<
448 <<
449 /* the low address lines on some platf <<
450 int io_shift; <<
451 <<
452 struct smc91x_platdata cfg; <<
453 }; <<
454 <<
455 #define SMC_8BIT(p) ((p)->cfg.flags & SMC9 <<
456 #define SMC_16BIT(p) ((p)->cfg.flags & SMC9 <<
457 #define SMC_32BIT(p) ((p)->cfg.flags & SMC9 <<
458 <<
459 #ifdef CONFIG_ARCH_PXA <<
460 /* 266 /*
461 * Let's use the DMA engine on the XScale PXA2 267 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
462 * always happening in irq context so no need 268 * always happening in irq context so no need to worry about races. TX is
463 * different and probably not worth it for tha 269 * different and probably not worth it for that reason, and not as critical
464 * as RX which can overrun memory and lose pac 270 * as RX which can overrun memory and lose packets.
465 */ 271 */
466 #include <linux/dma-mapping.h> 272 #include <linux/dma-mapping.h>
467 #include <mach/dma.h> !! 273 #include <asm/dma.h>
>> 274 #include <asm/arch/pxa-regs.h>
468 275
469 #ifdef SMC_insl 276 #ifdef SMC_insl
470 #undef SMC_insl 277 #undef SMC_insl
471 #define SMC_insl(a, r, p, l) \ 278 #define SMC_insl(a, r, p, l) \
472 smc_pxa_dma_insl(a, lp, r, dev->dma, p !! 279 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
473 static inline void 280 static inline void
474 smc_pxa_dma_insl(void __iomem *ioaddr, struct !! 281 smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,
475 u_char *buf, int len) 282 u_char *buf, int len)
476 { 283 {
477 u_long physaddr = lp->physaddr; <<
478 dma_addr_t dmabuf; 284 dma_addr_t dmabuf;
479 285
480 /* fallback if no DMA available */ 286 /* fallback if no DMA available */
481 if (dma == (unsigned char)-1) { 287 if (dma == (unsigned char)-1) {
482 readsl(ioaddr + reg, buf, len) 288 readsl(ioaddr + reg, buf, len);
483 return; 289 return;
484 } 290 }
485 291
486 /* 64 bit alignment is required for me 292 /* 64 bit alignment is required for memory to memory DMA */
487 if ((long)buf & 4) { 293 if ((long)buf & 4) {
488 *((u32 *)buf) = SMC_inl(ioaddr 294 *((u32 *)buf) = SMC_inl(ioaddr, reg);
489 buf += 4; 295 buf += 4;
490 len--; 296 len--;
491 } 297 }
492 298
493 len *= 4; 299 len *= 4;
494 dmabuf = dma_map_single(lp->device, bu !! 300 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
495 DCSR(dma) = DCSR_NODESC; 301 DCSR(dma) = DCSR_NODESC;
496 DTADR(dma) = dmabuf; 302 DTADR(dma) = dmabuf;
497 DSADR(dma) = physaddr + reg; 303 DSADR(dma) = physaddr + reg;
498 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BU 304 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
499 DCMD_WIDTH4 | (DCMD_LENGT 305 DCMD_WIDTH4 | (DCMD_LENGTH & len));
500 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 306 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
501 while (!(DCSR(dma) & DCSR_STOPSTATE)) 307 while (!(DCSR(dma) & DCSR_STOPSTATE))
502 cpu_relax(); 308 cpu_relax();
503 DCSR(dma) = 0; 309 DCSR(dma) = 0;
504 dma_unmap_single(lp->device, dmabuf, l !! 310 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
505 } 311 }
506 #endif 312 #endif
507 313
508 #ifdef SMC_insw 314 #ifdef SMC_insw
509 #undef SMC_insw 315 #undef SMC_insw
510 #define SMC_insw(a, r, p, l) \ 316 #define SMC_insw(a, r, p, l) \
511 smc_pxa_dma_insw(a, lp, r, dev->dma, p !! 317 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
512 static inline void 318 static inline void
513 smc_pxa_dma_insw(void __iomem *ioaddr, struct !! 319 smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma,
514 u_char *buf, int len) 320 u_char *buf, int len)
515 { 321 {
516 u_long physaddr = lp->physaddr; <<
517 dma_addr_t dmabuf; 322 dma_addr_t dmabuf;
518 323
519 /* fallback if no DMA available */ 324 /* fallback if no DMA available */
520 if (dma == (unsigned char)-1) { 325 if (dma == (unsigned char)-1) {
521 readsw(ioaddr + reg, buf, len) 326 readsw(ioaddr + reg, buf, len);
522 return; 327 return;
523 } 328 }
524 329
525 /* 64 bit alignment is required for me 330 /* 64 bit alignment is required for memory to memory DMA */
526 while ((long)buf & 6) { 331 while ((long)buf & 6) {
527 *((u16 *)buf) = SMC_inw(ioaddr 332 *((u16 *)buf) = SMC_inw(ioaddr, reg);
528 buf += 2; 333 buf += 2;
529 len--; 334 len--;
530 } 335 }
531 336
532 len *= 2; 337 len *= 2;
533 dmabuf = dma_map_single(lp->device, bu !! 338 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
534 DCSR(dma) = DCSR_NODESC; 339 DCSR(dma) = DCSR_NODESC;
535 DTADR(dma) = dmabuf; 340 DTADR(dma) = dmabuf;
536 DSADR(dma) = physaddr + reg; 341 DSADR(dma) = physaddr + reg;
537 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BU 342 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
538 DCMD_WIDTH2 | (DCMD_LENGT 343 DCMD_WIDTH2 | (DCMD_LENGTH & len));
539 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 344 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
540 while (!(DCSR(dma) & DCSR_STOPSTATE)) 345 while (!(DCSR(dma) & DCSR_STOPSTATE))
541 cpu_relax(); 346 cpu_relax();
542 DCSR(dma) = 0; 347 DCSR(dma) = 0;
543 dma_unmap_single(lp->device, dmabuf, l !! 348 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
544 } 349 }
545 #endif 350 #endif
546 351
547 static void 352 static void
548 smc_pxa_dma_irq(int dma, void *dummy) !! 353 smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
549 { 354 {
550 DCSR(dma) = 0; 355 DCSR(dma) = 0;
551 } 356 }
552 #endif /* CONFIG_ARCH_PXA */ !! 357 #endif /* SMC_USE_PXA_DMA */
553 <<
554 358
555 /* <<
556 * Everything a particular hardware setup need <<
557 * at this point. Add stubs for the undefined <<
558 * compilation warnings since they'll be optim <<
559 * use of them. <<
560 */ <<
561 <<
562 #if ! SMC_CAN_USE_32BIT <<
563 #define SMC_inl(ioaddr, reg) ({ BUG <<
564 #define SMC_outl(x, ioaddr, reg) BUG() <<
565 #define SMC_insl(a, r, p, l) BUG() <<
566 #define SMC_outsl(a, r, p, l) BUG() <<
567 #endif <<
568 <<
569 #if !defined(SMC_insl) || !defined(SMC_outsl) <<
570 #define SMC_insl(a, r, p, l) BUG() <<
571 #define SMC_outsl(a, r, p, l) BUG() <<
572 #endif <<
573 <<
574 #if ! SMC_CAN_USE_16BIT <<
575 <<
576 /* <<
577 * Any 16-bit access is performed with two 8-b <<
578 * can't do it directly. Most registers are 16 <<
579 */ <<
580 #define SMC_outw(x, ioaddr, reg) <<
581 do { <<
582 unsigned int __val16 = (x); <<
583 SMC_outb( __val16, ioaddr, reg <<
584 SMC_outb( __val16 >> 8, ioaddr <<
585 } while (0) <<
586 #define SMC_inw(ioaddr, reg) <<
587 ({ <<
588 unsigned int __val16; <<
589 __val16 = SMC_inb( ioaddr, re <<
590 __val16 |= SMC_inb( ioaddr, re <<
591 __val16; <<
592 }) <<
593 <<
594 #define SMC_insw(a, r, p, l) BUG() <<
595 #define SMC_outsw(a, r, p, l) BUG() <<
596 <<
597 #endif <<
598 <<
599 #if !defined(SMC_insw) || !defined(SMC_outsw) <<
600 #define SMC_insw(a, r, p, l) BUG() <<
601 #define SMC_outsw(a, r, p, l) BUG() <<
602 #endif <<
603 <<
604 #if ! SMC_CAN_USE_8BIT <<
605 #define SMC_inb(ioaddr, reg) ({ BUG <<
606 #define SMC_outb(x, ioaddr, reg) BUG() <<
607 #define SMC_insb(a, r, p, l) BUG() <<
608 #define SMC_outsb(a, r, p, l) BUG() <<
609 #endif <<
610 <<
611 #if !defined(SMC_insb) || !defined(SMC_outsb) <<
612 #define SMC_insb(a, r, p, l) BUG() <<
613 #define SMC_outsb(a, r, p, l) BUG() <<
614 #endif <<
615 <<
616 #ifndef SMC_CAN_USE_DATACS <<
617 #define SMC_CAN_USE_DATACS 0 <<
618 #endif <<
619 359
>> 360 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
620 #ifndef SMC_IO_SHIFT 361 #ifndef SMC_IO_SHIFT
621 #define SMC_IO_SHIFT 0 362 #define SMC_IO_SHIFT 0
622 #endif 363 #endif
623 <<
624 #ifndef SMC_IRQ_FLAGS <<
625 #define SMC_IRQ_FLAGS IRQF_TRIGGER_R <<
626 #endif <<
627 <<
628 #ifndef SMC_INTERRUPT_PREAMBLE <<
629 #define SMC_INTERRUPT_PREAMBLE <<
630 #endif <<
631 <<
632 <<
633 /* Because of bank switching, the LAN91x uses <<
634 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) 364 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
635 #define SMC_DATA_EXTENT (4) !! 365
636 366
637 /* 367 /*
638 . Bank Select Register: 368 . Bank Select Register:
639 . 369 .
640 . yyyy yyyy 0000 00xx 370 . yyyy yyyy 0000 00xx
641 . xx = bank number 371 . xx = bank number
642 . yyyy yyyy = 0x33, for id 372 . yyyy yyyy = 0x33, for identification purposes.
643 */ 373 */
644 #define BANK_SELECT (14 << SMC_IO_ 374 #define BANK_SELECT (14 << SMC_IO_SHIFT)
645 375
646 376
647 // Transmit Control Register 377 // Transmit Control Register
648 /* BANK 0 */ 378 /* BANK 0 */
649 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) !! 379 #define TCR_REG SMC_REG(0x0000, 0)
650 #define TCR_ENABLE 0x0001 // When 1 we c 380 #define TCR_ENABLE 0x0001 // When 1 we can transmit
651 #define TCR_LOOP 0x0002 // Controls ou 381 #define TCR_LOOP 0x0002 // Controls output pin LBK
652 #define TCR_FORCOL 0x0004 // When 1 will 382 #define TCR_FORCOL 0x0004 // When 1 will force a collision
653 #define TCR_PAD_EN 0x0080 // When 1 will 383 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
654 #define TCR_NOCRC 0x0100 // When 1 will 384 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
655 #define TCR_MON_CSN 0x0400 // When 1 tx m 385 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
656 #define TCR_FDUPLX 0x0800 // When 1 enab 386 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
657 #define TCR_STP_SQET 0x1000 // When 1 stop 387 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
658 #define TCR_EPH_LOOP 0x2000 // When 1 enab 388 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
659 #define TCR_SWFDUP 0x8000 // When 1 enab 389 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
660 390
661 #define TCR_CLEAR 0 /* do NOTHING 391 #define TCR_CLEAR 0 /* do NOTHING */
662 /* the default settings for the TCR register : 392 /* the default settings for the TCR register : */
663 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_ 393 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
664 394
665 395
666 // EPH Status Register 396 // EPH Status Register
667 /* BANK 0 */ 397 /* BANK 0 */
668 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x !! 398 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
669 #define ES_TX_SUC 0x0001 // Last TX was 399 #define ES_TX_SUC 0x0001 // Last TX was successful
670 #define ES_SNGL_COL 0x0002 // Single coll 400 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
671 #define ES_MUL_COL 0x0004 // Multiple co 401 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
672 #define ES_LTX_MULT 0x0008 // Last tx was 402 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
673 #define ES_16COL 0x0010 // 16 Collisio 403 #define ES_16COL 0x0010 // 16 Collisions Reached
674 #define ES_SQET 0x0020 // Signal Qual 404 #define ES_SQET 0x0020 // Signal Quality Error Test
675 #define ES_LTXBRD 0x0040 // Last tx was 405 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
676 #define ES_TXDEFR 0x0080 // Transmit De 406 #define ES_TXDEFR 0x0080 // Transmit Deferred
677 #define ES_LATCOL 0x0200 // Late collis 407 #define ES_LATCOL 0x0200 // Late collision detected on last tx
678 #define ES_LOSTCARR 0x0400 // Lost Carrie 408 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
679 #define ES_EXC_DEF 0x0800 // Excessive D 409 #define ES_EXC_DEF 0x0800 // Excessive Deferral
680 #define ES_CTR_ROL 0x1000 // Counter Rol 410 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
681 #define ES_LINK_OK 0x4000 // Driven by i 411 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
682 #define ES_TXUNRN 0x8000 // Tx Underrun 412 #define ES_TXUNRN 0x8000 // Tx Underrun
683 413
684 414
685 // Receive Control Register 415 // Receive Control Register
686 /* BANK 0 */ 416 /* BANK 0 */
687 #define RCR_REG(lp) SMC_REG(lp, 0x !! 417 #define RCR_REG SMC_REG(0x0004, 0)
688 #define RCR_RX_ABORT 0x0001 // Set if a rx 418 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
689 #define RCR_PRMS 0x0002 // Enable prom 419 #define RCR_PRMS 0x0002 // Enable promiscuous mode
690 #define RCR_ALMUL 0x0004 // When set ac 420 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
691 #define RCR_RXEN 0x0100 // IFF this is 421 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
692 #define RCR_STRIP_CRC 0x0200 // When set st 422 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
693 #define RCR_ABORT_ENB 0x0200 // When set wi 423 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
694 #define RCR_FILT_CAR 0x0400 // When set fi 424 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
695 #define RCR_SOFTRST 0x8000 // resets the 425 #define RCR_SOFTRST 0x8000 // resets the chip
696 426
697 /* the normal settings for the RCR register : 427 /* the normal settings for the RCR register : */
698 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_R 428 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
699 #define RCR_CLEAR 0x0 // set it to a 429 #define RCR_CLEAR 0x0 // set it to a base state
700 430
701 431
702 // Counter Register 432 // Counter Register
703 /* BANK 0 */ 433 /* BANK 0 */
704 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) !! 434 #define COUNTER_REG SMC_REG(0x0006, 0)
705 435
706 436
707 // Memory Information Register 437 // Memory Information Register
708 /* BANK 0 */ 438 /* BANK 0 */
709 #define MIR_REG(lp) SMC_REG(lp, 0x !! 439 #define MIR_REG SMC_REG(0x0008, 0)
710 440
711 441
712 // Receive/Phy Control Register 442 // Receive/Phy Control Register
713 /* BANK 0 */ 443 /* BANK 0 */
714 #define RPC_REG(lp) SMC_REG(lp, 0x !! 444 #define RPC_REG SMC_REG(0x000A, 0)
715 #define RPC_SPEED 0x2000 // When 1 PHY 445 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
716 #define RPC_DPLX 0x1000 // When 1 PHY 446 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
717 #define RPC_ANEG 0x0800 // When 1 PHY 447 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
718 #define RPC_LSXA_SHFT 5 // Bits to shi 448 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
719 #define RPC_LSXB_SHFT 2 // Bits to get 449 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
>> 450 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
>> 451 #define RPC_LED_RES (0x01) // LED = Reserved
>> 452 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
>> 453 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
>> 454 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
>> 455 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
>> 456 #define RPC_LED_TX (0x06) // LED = TX packet occurred
>> 457 #define RPC_LED_RX (0x07) // LED = RX packet occurred
720 458
721 #ifndef RPC_LSA_DEFAULT 459 #ifndef RPC_LSA_DEFAULT
722 #define RPC_LSA_DEFAULT RPC_LED_100 460 #define RPC_LSA_DEFAULT RPC_LED_100
723 #endif 461 #endif
724 #ifndef RPC_LSB_DEFAULT 462 #ifndef RPC_LSB_DEFAULT
725 #define RPC_LSB_DEFAULT RPC_LED_FD 463 #define RPC_LSB_DEFAULT RPC_LED_FD
726 #endif 464 #endif
727 465
728 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RP !! 466 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
729 467
730 468
731 /* Bank 0 0x0C is reserved */ 469 /* Bank 0 0x0C is reserved */
732 470
733 // Bank Select Register 471 // Bank Select Register
734 /* All Banks */ 472 /* All Banks */
735 #define BSR_REG 0x000E 473 #define BSR_REG 0x000E
736 474
737 475
738 // Configuration Reg 476 // Configuration Reg
739 /* BANK 1 */ 477 /* BANK 1 */
740 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, !! 478 #define CONFIG_REG SMC_REG(0x0000, 1)
741 #define CONFIG_EXT_PHY 0x0200 // 1=external 479 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
742 #define CONFIG_GPCNTRL 0x0400 // Inverse val 480 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
743 #define CONFIG_NO_WAIT 0x1000 // When 1 no e 481 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
744 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 E 482 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
745 483
746 // Default is powered-up, Internal Phy, Wait S 484 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
747 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 485 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
748 486
749 487
750 // Base Address Register 488 // Base Address Register
751 /* BANK 1 */ 489 /* BANK 1 */
752 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) !! 490 #define BASE_REG SMC_REG(0x0002, 1)
753 491
754 492
755 // Individual Address Registers 493 // Individual Address Registers
756 /* BANK 1 */ 494 /* BANK 1 */
757 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) !! 495 #define ADDR0_REG SMC_REG(0x0004, 1)
758 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) !! 496 #define ADDR1_REG SMC_REG(0x0006, 1)
759 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) !! 497 #define ADDR2_REG SMC_REG(0x0008, 1)
760 498
761 499
762 // General Purpose Register 500 // General Purpose Register
763 /* BANK 1 */ 501 /* BANK 1 */
764 #define GP_REG(lp) SMC_REG(lp, 0x !! 502 #define GP_REG SMC_REG(0x000A, 1)
765 503
766 504
767 // Control Register 505 // Control Register
768 /* BANK 1 */ 506 /* BANK 1 */
769 #define CTL_REG(lp) SMC_REG(lp, 0x !! 507 #define CTL_REG SMC_REG(0x000C, 1)
770 #define CTL_RCV_BAD 0x4000 // When 1 bad C 508 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
771 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx p 509 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
772 #define CTL_LE_ENABLE 0x0080 // When 1 enabl 510 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
773 #define CTL_CR_ENABLE 0x0040 // When 1 enabl 511 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
774 #define CTL_TE_ENABLE 0x0020 // When 1 enabl 512 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
775 #define CTL_EEPROM_SELECT 0x0004 // Controls E 513 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
776 #define CTL_RELOAD 0x0002 // When set rea 514 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
777 #define CTL_STORE 0x0001 // When set sto 515 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
778 516
779 517
780 // MMU Command Register 518 // MMU Command Register
781 /* BANK 2 */ 519 /* BANK 2 */
782 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) !! 520 #define MMU_CMD_REG SMC_REG(0x0000, 2)
783 #define MC_BUSY 1 // When 1 the 521 #define MC_BUSY 1 // When 1 the last release has not completed
784 #define MC_NOP (0<<5) // No Op 522 #define MC_NOP (0<<5) // No Op
785 #define MC_ALLOC (1<<5) // OR with num 523 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
786 #define MC_RESET (2<<5) // Reset MMU t 524 #define MC_RESET (2<<5) // Reset MMU to initial state
787 #define MC_REMOVE (3<<5) // Remove the 525 #define MC_REMOVE (3<<5) // Remove the current rx packet
788 #define MC_RELEASE (4<<5) // Remove and 526 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
789 #define MC_FREEPKT (5<<5) // Release pac 527 #define MC_FREEPKT (5<<5) // Release packet in PNR register
790 #define MC_ENQUEUE (6<<5) // Enqueue the 528 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
791 #define MC_RSTTXFIFO (7<<5) // Reset the T 529 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
792 530
793 531
794 // Packet Number Register 532 // Packet Number Register
795 /* BANK 2 */ 533 /* BANK 2 */
796 #define PN_REG(lp) SMC_REG(lp, 0x !! 534 #define PN_REG SMC_REG(0x0002, 2)
797 535
798 536
799 // Allocation Result Register 537 // Allocation Result Register
800 /* BANK 2 */ 538 /* BANK 2 */
801 #define AR_REG(lp) SMC_REG(lp, 0x !! 539 #define AR_REG SMC_REG(0x0003, 2)
802 #define AR_FAILED 0x80 // Alocation F 540 #define AR_FAILED 0x80 // Alocation Failed
803 541
804 542
805 // TX FIFO Ports Register 543 // TX FIFO Ports Register
806 /* BANK 2 */ 544 /* BANK 2 */
807 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) !! 545 #define TXFIFO_REG SMC_REG(0x0004, 2)
808 #define TXFIFO_TEMPTY 0x80 // TX FIFO Emp 546 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
809 547
810 // RX FIFO Ports Register 548 // RX FIFO Ports Register
811 /* BANK 2 */ 549 /* BANK 2 */
812 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) !! 550 #define RXFIFO_REG SMC_REG(0x0005, 2)
813 #define RXFIFO_REMPTY 0x80 // RX FIFO Emp 551 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
814 552
815 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) !! 553 #define FIFO_REG SMC_REG(0x0004, 2)
816 554
817 // Pointer Register 555 // Pointer Register
818 /* BANK 2 */ 556 /* BANK 2 */
819 #define PTR_REG(lp) SMC_REG(lp, 0x !! 557 #define PTR_REG SMC_REG(0x0006, 2)
820 #define PTR_RCV 0x8000 // 1=Receive ar 558 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
821 #define PTR_AUTOINC 0x4000 // Auto increme 559 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
822 #define PTR_READ 0x2000 // When 1 the o 560 #define PTR_READ 0x2000 // When 1 the operation is a read
823 561
824 562
825 // Data Register 563 // Data Register
826 /* BANK 2 */ 564 /* BANK 2 */
827 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) !! 565 #define DATA_REG SMC_REG(0x0008, 2)
828 566
829 567
830 // Interrupt Status/Acknowledge Register 568 // Interrupt Status/Acknowledge Register
831 /* BANK 2 */ 569 /* BANK 2 */
832 #define INT_REG(lp) SMC_REG(lp, 0x !! 570 #define INT_REG SMC_REG(0x000C, 2)
833 571
834 572
835 // Interrupt Mask Register 573 // Interrupt Mask Register
836 /* BANK 2 */ 574 /* BANK 2 */
837 #define IM_REG(lp) SMC_REG(lp, 0x !! 575 #define IM_REG SMC_REG(0x000D, 2)
838 #define IM_MDINT 0x80 // PHY MI Registe 576 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
839 #define IM_ERCV_INT 0x40 // Early Receive 577 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
840 #define IM_EPH_INT 0x20 // Set by Etherne 578 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
841 #define IM_RX_OVRN_INT 0x10 // Set by Receive 579 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
842 #define IM_ALLOC_INT 0x08 // Set when alloc 580 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
843 #define IM_TX_EMPTY_INT 0x04 // Set if the TX 581 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
844 #define IM_TX_INT 0x02 // Transmit Inter 582 #define IM_TX_INT 0x02 // Transmit Interrupt
845 #define IM_RCV_INT 0x01 // Receive Interr 583 #define IM_RCV_INT 0x01 // Receive Interrupt
846 584
847 585
848 // Multicast Table Registers 586 // Multicast Table Registers
849 /* BANK 3 */ 587 /* BANK 3 */
850 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) !! 588 #define MCAST_REG1 SMC_REG(0x0000, 3)
851 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) !! 589 #define MCAST_REG2 SMC_REG(0x0002, 3)
852 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) !! 590 #define MCAST_REG3 SMC_REG(0x0004, 3)
853 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) !! 591 #define MCAST_REG4 SMC_REG(0x0006, 3)
854 592
855 593
856 // Management Interface Register (MII) 594 // Management Interface Register (MII)
857 /* BANK 3 */ 595 /* BANK 3 */
858 #define MII_REG(lp) SMC_REG(lp, 0x !! 596 #define MII_REG SMC_REG(0x0008, 3)
859 #define MII_MSK_CRS100 0x4000 // Disables CRS 597 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
860 #define MII_MDOE 0x0008 // MII Output E 598 #define MII_MDOE 0x0008 // MII Output Enable
861 #define MII_MCLK 0x0004 // MII Clock, p 599 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
862 #define MII_MDI 0x0002 // MII Input, p 600 #define MII_MDI 0x0002 // MII Input, pin MDI
863 #define MII_MDO 0x0001 // MII Output, 601 #define MII_MDO 0x0001 // MII Output, pin MDO
864 602
865 603
866 // Revision Register 604 // Revision Register
867 /* BANK 3 */ 605 /* BANK 3 */
868 /* ( hi: chip id low: rev # ) */ 606 /* ( hi: chip id low: rev # ) */
869 #define REV_REG(lp) SMC_REG(lp, 0x !! 607 #define REV_REG SMC_REG(0x000A, 3)
870 608
871 609
872 // Early RCV Register 610 // Early RCV Register
873 /* BANK 3 */ 611 /* BANK 3 */
874 /* this is NOT on SMC9192 */ 612 /* this is NOT on SMC9192 */
875 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) !! 613 #define ERCV_REG SMC_REG(0x000C, 3)
876 #define ERCV_RCV_DISCRD 0x0080 // When 1 disca 614 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
877 #define ERCV_THRESHOLD 0x001F // ERCV Thresho 615 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
878 616
879 617
880 // External Register 618 // External Register
881 /* BANK 7 */ 619 /* BANK 7 */
882 #define EXT_REG(lp) SMC_REG(lp, 0x !! 620 #define EXT_REG SMC_REG(0x0000, 7)
883 621
884 622
885 #define CHIP_9192 3 623 #define CHIP_9192 3
886 #define CHIP_9194 4 624 #define CHIP_9194 4
887 #define CHIP_9195 5 625 #define CHIP_9195 5
888 #define CHIP_9196 6 626 #define CHIP_9196 6
889 #define CHIP_91100 7 627 #define CHIP_91100 7
890 #define CHIP_91100FD 8 628 #define CHIP_91100FD 8
891 #define CHIP_91111FD 9 629 #define CHIP_91111FD 9
892 630
893 static const char * chip_ids[ 16 ] = { 631 static const char * chip_ids[ 16 ] = {
894 NULL, NULL, NULL, 632 NULL, NULL, NULL,
895 /* 3 */ "SMC91C90/91C92", 633 /* 3 */ "SMC91C90/91C92",
896 /* 4 */ "SMC91C94", 634 /* 4 */ "SMC91C94",
897 /* 5 */ "SMC91C95", 635 /* 5 */ "SMC91C95",
898 /* 6 */ "SMC91C96", 636 /* 6 */ "SMC91C96",
899 /* 7 */ "SMC91C100", 637 /* 7 */ "SMC91C100",
900 /* 8 */ "SMC91C100FD", 638 /* 8 */ "SMC91C100FD",
901 /* 9 */ "SMC91C11xFD", 639 /* 9 */ "SMC91C11xFD",
902 NULL, NULL, NULL, 640 NULL, NULL, NULL,
903 NULL, NULL, NULL}; 641 NULL, NULL, NULL};
904 642
905 643
906 /* 644 /*
>> 645 . Transmit status bits
>> 646 */
>> 647 #define TS_SUCCESS 0x0001
>> 648 #define TS_LOSTCAR 0x0400
>> 649 #define TS_LATCOL 0x0200
>> 650 #define TS_16COL 0x0010
>> 651
>> 652 /*
907 . Receive status bits 653 . Receive status bits
908 */ 654 */
909 #define RS_ALGNERR 0x8000 655 #define RS_ALGNERR 0x8000
910 #define RS_BRODCAST 0x4000 656 #define RS_BRODCAST 0x4000
911 #define RS_BADCRC 0x2000 657 #define RS_BADCRC 0x2000
912 #define RS_ODDFRAME 0x1000 658 #define RS_ODDFRAME 0x1000
913 #define RS_TOOLONG 0x0800 659 #define RS_TOOLONG 0x0800
914 #define RS_TOOSHORT 0x0400 660 #define RS_TOOSHORT 0x0400
915 #define RS_MULTICAST 0x0001 661 #define RS_MULTICAST 0x0001
916 #define RS_ERRORS (RS_ALGNERR | RS_BADCR 662 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
917 663
918 664
919 /* 665 /*
920 * PHY IDs 666 * PHY IDs
921 * LAN83C183 == LAN91C111 Internal PHY 667 * LAN83C183 == LAN91C111 Internal PHY
922 */ 668 */
923 #define PHY_LAN83C183 0x0016f840 669 #define PHY_LAN83C183 0x0016f840
924 #define PHY_LAN83C180 0x02821c50 670 #define PHY_LAN83C180 0x02821c50
925 671
926 /* 672 /*
927 * PHY Register Addresses (LAN91C111 Internal 673 * PHY Register Addresses (LAN91C111 Internal PHY)
928 * 674 *
929 * Generic PHY registers can be found in <linu 675 * Generic PHY registers can be found in <linux/mii.h>
930 * 676 *
931 * These phy registers are specific to our on- 677 * These phy registers are specific to our on-board phy.
932 */ 678 */
933 679
934 // PHY Configuration Register 1 680 // PHY Configuration Register 1
935 #define PHY_CFG1_REG 0x10 681 #define PHY_CFG1_REG 0x10
936 #define PHY_CFG1_LNKDIS 0x8000 // 1=R 682 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
937 #define PHY_CFG1_XMTDIS 0x4000 // 1=T 683 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
938 #define PHY_CFG1_XMTPDN 0x2000 // 1=T 684 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
939 #define PHY_CFG1_BYPSCR 0x0400 // 1=B 685 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
940 #define PHY_CFG1_UNSCDS 0x0200 // 1=U 686 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
941 #define PHY_CFG1_EQLZR 0x0100 // 1=R 687 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
942 #define PHY_CFG1_CABLE 0x0080 // 1=S 688 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
943 #define PHY_CFG1_RLVL0 0x0040 // 1=R 689 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
944 #define PHY_CFG1_TLVL_SHIFT 2 // Tra 690 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
945 #define PHY_CFG1_TLVL_MASK 0x003C 691 #define PHY_CFG1_TLVL_MASK 0x003C
946 #define PHY_CFG1_TRF_MASK 0x0003 // Tra 692 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
947 693
948 694
949 // PHY Configuration Register 2 695 // PHY Configuration Register 2
950 #define PHY_CFG2_REG 0x11 696 #define PHY_CFG2_REG 0x11
951 #define PHY_CFG2_APOLDIS 0x0020 // 1=A 697 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
952 #define PHY_CFG2_JABDIS 0x0010 // 1=J 698 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
953 #define PHY_CFG2_MREG 0x0008 // 1=M 699 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
954 #define PHY_CFG2_INTMDIO 0x0004 // 1=I 700 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
955 701
956 // PHY Status Output (and Interrupt status) Re 702 // PHY Status Output (and Interrupt status) Register
957 #define PHY_INT_REG 0x12 // Sta 703 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
958 #define PHY_INT_INT 0x8000 // 1=b 704 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
959 #define PHY_INT_LNKFAIL 0x4000 // 1=L 705 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
960 #define PHY_INT_LOSSSYNC 0x2000 // 1=D 706 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
961 #define PHY_INT_CWRD 0x1000 // 1=I 707 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
962 #define PHY_INT_SSD 0x0800 // 1=N 708 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
963 #define PHY_INT_ESD 0x0400 // 1=N 709 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
964 #define PHY_INT_RPOL 0x0200 // 1=R 710 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
965 #define PHY_INT_JAB 0x0100 // 1=J 711 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
966 #define PHY_INT_SPDDET 0x0080 // 1=1 712 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
967 #define PHY_INT_DPLXDET 0x0040 // 1=D 713 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
968 714
969 // PHY Interrupt/Status Mask Register 715 // PHY Interrupt/Status Mask Register
970 #define PHY_MASK_REG 0x13 // Int 716 #define PHY_MASK_REG 0x13 // Interrupt Mask
971 // Uses the same bit definitions as PHY_INT_RE 717 // Uses the same bit definitions as PHY_INT_REG
972 718
973 719
974 /* 720 /*
975 * SMC91C96 ethernet config and status registe 721 * SMC91C96 ethernet config and status registers.
976 * These are in the "attribute" space. 722 * These are in the "attribute" space.
977 */ 723 */
978 #define ECOR 0x8000 724 #define ECOR 0x8000
979 #define ECOR_RESET 0x80 725 #define ECOR_RESET 0x80
980 #define ECOR_LEVEL_IRQ 0x40 726 #define ECOR_LEVEL_IRQ 0x40
981 #define ECOR_WR_ATTRIB 0x04 727 #define ECOR_WR_ATTRIB 0x04
982 #define ECOR_ENABLE 0x01 728 #define ECOR_ENABLE 0x01
983 729
984 #define ECSR 0x8002 730 #define ECSR 0x8002
985 #define ECSR_IOIS8 0x20 731 #define ECSR_IOIS8 0x20
986 #define ECSR_PWRDWN 0x04 732 #define ECSR_PWRDWN 0x04
987 #define ECSR_INT 0x02 733 #define ECSR_INT 0x02
988 734
989 #define ATTRIB_SIZE ((64*1024) << 735 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
990 736
991 737
992 /* 738 /*
993 * Macros to abstract register access accordin 739 * Macros to abstract register access according to the data bus
994 * capabilities. Please use those and not the 740 * capabilities. Please use those and not the in/out primitives.
995 * Note: the following macros do *not* select 741 * Note: the following macros do *not* select the bank -- this must
996 * be done separately as needed in the main co 742 * be done separately as needed in the main code. The SMC_REG() macro
997 * only uses the bank argument for debugging p 743 * only uses the bank argument for debugging purposes (when enabled).
998 * <<
999 * Note: despite inline functions being safer, <<
1000 * should preferably be macros to let BUG() d <<
1001 * the core source code since we're intereste <<
1002 * not in any inline function location. <<
1003 */ 744 */
1004 745
1005 #if SMC_DEBUG > 0 746 #if SMC_DEBUG > 0
1006 #define SMC_REG(lp, reg, bank) !! 747 #define SMC_REG(reg, bank) \
1007 ({ 748 ({ \
1008 int __b = SMC_CURRENT_BANK(lp !! 749 int __b = SMC_CURRENT_BANK(); \
1009 if (unlikely((__b & ~0xf0) != 750 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1010 printk( "%s: bank reg 751 printk( "%s: bank reg screwed (0x%04x)\n", \
1011 CARDNAME, __b 752 CARDNAME, __b ); \
1012 BUG(); 753 BUG(); \
1013 } 754 } \
1014 reg<<SMC_IO_SHIFT; 755 reg<<SMC_IO_SHIFT; \
1015 }) 756 })
1016 #else 757 #else
1017 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_ !! 758 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1018 #endif 759 #endif
1019 760
1020 /* !! 761 #if SMC_CAN_USE_8BIT
1021 * Hack Alert: Some setups just can't write 8 !! 762 #define SMC_GET_PN() SMC_inb( ioaddr, PN_REG )
1022 * aligned to a 32 bit boundary. I tell you !! 763 #define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG )
1023 * Fortunately the affected register accesses !! 764 #define SMC_GET_AR() SMC_inb( ioaddr, AR_REG )
1024 * since we can write zeroes to the preceedin !! 765 #define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG )
1025 * effects and use a 32-bit access. !! 766 #define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG )
1026 * !! 767 #define SMC_GET_INT() SMC_inb( ioaddr, INT_REG )
1027 * Enforce it on any 32-bit capable setup for !! 768 #define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG )
1028 */ !! 769 #define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG )
1029 #define SMC_MUST_ALIGN_WRITE(lp) SMC_3 !! 770 #define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG )
1030 !! 771 #else
1031 #define SMC_GET_PN(lp) !! 772 #define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF)
1032 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN !! 773 #define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG )
1033 : (SMC_inw(io !! 774 #define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8)
1034 !! 775 #define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF)
1035 #define SMC_SET_PN(lp, x) !! 776 #define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8)
1036 do { !! 777 #define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF)
1037 if (SMC_MUST_ALIGN_WRITE(lp)) !! 778 #define SMC_ACK_INT(x) \
1038 SMC_outl((x)<<16, ioa !! 779 do { \
1039 else if (SMC_8BIT(lp)) !! 780 unsigned long __flags; \
1040 SMC_outb(x, ioaddr, P !! 781 int __mask; \
1041 else !! 782 local_irq_save(__flags); \
1042 SMC_outw(x, ioaddr, P !! 783 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1043 } while (0) !! 784 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1044 !! 785 local_irq_restore(__flags); \
1045 #define SMC_GET_AR(lp) !! 786 } while (0)
1046 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR !! 787 #define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8)
1047 : (SMC_inw(io !! 788 #define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG )
1048 !! 789 #endif
1049 #define SMC_GET_TXFIFO(lp) !! 790
1050 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TX !! 791 #define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT )
1051 : (SMC_inw(io !! 792 #define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT )
1052 !! 793 #define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG )
1053 #define SMC_GET_RXFIFO(lp) !! 794 #define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG )
1054 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RX !! 795 #define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG )
1055 : (SMC_inw(io !! 796 #define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG )
1056 !! 797 #define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG )
1057 #define SMC_GET_INT(lp) !! 798 #define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG )
1058 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IN !! 799 #define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG )
1059 : (SMC_inw(io !! 800 #define SMC_GET_MII() SMC_inw( ioaddr, MII_REG )
1060 !! 801 #define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG )
1061 #define SMC_ACK_INT(lp, x) !! 802 #define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG )
1062 do { !! 803 #define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG )
1063 if (SMC_8BIT(lp)) !! 804 #define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG )
1064 SMC_outb(x, ioaddr, I !! 805 #define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG )
1065 else { !! 806 #define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
1066 unsigned long __flags !! 807 #define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
1067 int __mask; !! 808 #define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
1068 local_irq_save(__flag !! 809 #define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
1069 __mask = SMC_inw(ioad !! 810 #define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
1070 SMC_outw(__mask | (x) !! 811 #define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
1071 local_irq_restore(__f !! 812 #define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG )
1072 } !! 813 #define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG )
1073 } while (0) !! 814 #define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG )
1074 !! 815 #define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG )
1075 #define SMC_GET_INT_MASK(lp) <<
1076 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM <<
1077 : (SMC_inw(io <<
1078 <<
1079 #define SMC_SET_INT_MASK(lp, x) <<
1080 do { <<
1081 if (SMC_8BIT(lp)) <<
1082 SMC_outb(x, ioaddr, I <<
1083 else <<
1084 SMC_outw((x) << 8, io <<
1085 } while (0) <<
1086 <<
1087 #define SMC_CURRENT_BANK(lp) SMC_inw(ioadd <<
1088 <<
1089 #define SMC_SELECT_BANK(lp, x) <<
1090 do { <<
1091 if (SMC_MUST_ALIGN_WRITE(lp)) <<
1092 SMC_outl((x)<<16, ioa <<
1093 else <<
1094 SMC_outw(x, ioaddr, B <<
1095 } while (0) <<
1096 <<
1097 #define SMC_GET_BASE(lp) SMC_i <<
1098 <<
1099 #define SMC_SET_BASE(lp, x) SMC_o <<
1100 <<
1101 #define SMC_GET_CONFIG(lp) SMC_inw(ioadd <<
1102 <<
1103 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, i <<
1104 <<
1105 #define SMC_GET_COUNTER(lp) SMC_inw(ioadd <<
1106 <<
1107 #define SMC_GET_CTL(lp) SMC_inw(ioadd <<
1108 <<
1109 #define SMC_SET_CTL(lp, x) SMC_o <<
1110 <<
1111 #define SMC_GET_MII(lp) SMC_inw(ioadd <<
1112 <<
1113 #define SMC_GET_GP(lp) SMC_inw(ioadd <<
1114 <<
1115 #define SMC_SET_GP(lp, x) <<
1116 do { <<
1117 if (SMC_MUST_ALIGN_WRITE(lp)) <<
1118 SMC_outl((x)<<16, ioa <<
1119 else <<
1120 SMC_outw(x, ioaddr, G <<
1121 } while (0) <<
1122 <<
1123 #define SMC_SET_MII(lp, x) SMC_o <<
1124 <<
1125 #define SMC_GET_MIR(lp) SMC_inw(ioadd <<
1126 <<
1127 #define SMC_SET_MIR(lp, x) SMC_o <<
1128 <<
1129 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioadd <<
1130 <<
1131 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, i <<
1132 <<
1133 #define SMC_GET_FIFO(lp) SMC_i <<
1134 <<
1135 #define SMC_GET_PTR(lp) SMC_inw(ioadd <<
1136 <<
1137 #define SMC_SET_PTR(lp, x) <<
1138 do { <<
1139 if (SMC_MUST_ALIGN_WRITE(lp)) <<
1140 SMC_outl((x)<<16, ioa <<
1141 else <<
1142 SMC_outw(x, ioaddr, P <<
1143 } while (0) <<
1144 <<
1145 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioadd <<
1146 <<
1147 #define SMC_GET_RCR(lp) SMC_inw(ioadd <<
1148 <<
1149 #define SMC_SET_RCR(lp, x) SMC_o <<
1150 <<
1151 #define SMC_GET_REV(lp) SMC_inw(ioadd <<
1152 <<
1153 #define SMC_GET_RPC(lp) SMC_inw(ioadd <<
1154 <<
1155 #define SMC_SET_RPC(lp, x) <<
1156 do { <<
1157 if (SMC_MUST_ALIGN_WRITE(lp)) <<
1158 SMC_outl((x)<<16, ioa <<
1159 else <<
1160 SMC_outw(x, ioaddr, R <<
1161 } while (0) <<
1162 <<
1163 #define SMC_GET_TCR(lp) SMC_inw(ioadd <<
1164 <<
1165 #define SMC_SET_TCR(lp, x) SMC_o <<
1166 816
1167 #ifndef SMC_GET_MAC_ADDR 817 #ifndef SMC_GET_MAC_ADDR
1168 #define SMC_GET_MAC_ADDR(lp, addr) !! 818 #define SMC_GET_MAC_ADDR(addr) \
1169 do { 819 do { \
1170 unsigned int __v; 820 unsigned int __v; \
1171 __v = SMC_inw(ioaddr, ADDR0_R !! 821 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1172 addr[0] = __v; addr[1] = __v 822 addr[0] = __v; addr[1] = __v >> 8; \
1173 __v = SMC_inw(ioaddr, ADDR1_R !! 823 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1174 addr[2] = __v; addr[3] = __v 824 addr[2] = __v; addr[3] = __v >> 8; \
1175 __v = SMC_inw(ioaddr, ADDR2_R !! 825 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1176 addr[4] = __v; addr[5] = __v 826 addr[4] = __v; addr[5] = __v >> 8; \
1177 } while (0) 827 } while (0)
1178 #endif 828 #endif
1179 829
1180 #define SMC_SET_MAC_ADDR(lp, addr) !! 830 #define SMC_SET_MAC_ADDR(addr) \
1181 do { 831 do { \
1182 SMC_outw(addr[0]|(addr[1] << !! 832 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1183 SMC_outw(addr[2]|(addr[3] << !! 833 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1184 SMC_outw(addr[4]|(addr[5] << !! 834 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1185 } while (0) 835 } while (0)
1186 836
1187 #define SMC_SET_MCAST(lp, x) !! 837 #define SMC_SET_MCAST(x) \
1188 do { 838 do { \
1189 const unsigned char *mt = (x) 839 const unsigned char *mt = (x); \
1190 SMC_outw(mt[0] | (mt[1] << 8) !! 840 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1191 SMC_outw(mt[2] | (mt[3] << 8) !! 841 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1192 SMC_outw(mt[4] | (mt[5] << 8) !! 842 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1193 SMC_outw(mt[6] | (mt[7] << 8) !! 843 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
>> 844 } while (0)
>> 845
>> 846 #if SMC_CAN_USE_32BIT
>> 847 /*
>> 848 * Some setups just can't write 8 or 16 bits reliably when not aligned
>> 849 * to a 32 bit boundary. I tell you that exists!
>> 850 * We re-do the ones here that can be easily worked around if they can have
>> 851 * their low parts written to 0 without adverse effects.
>> 852 */
>> 853 #undef SMC_SELECT_BANK
>> 854 #define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT )
>> 855 #undef SMC_SET_RPC
>> 856 #define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) )
>> 857 #undef SMC_SET_PN
>> 858 #define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) )
>> 859 #undef SMC_SET_PTR
>> 860 #define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) )
>> 861 #endif
>> 862
>> 863 #if SMC_CAN_USE_32BIT
>> 864 #define SMC_PUT_PKT_HDR(status, length) \
>> 865 SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG )
>> 866 #define SMC_GET_PKT_HDR(status, length) \
>> 867 do { \
>> 868 unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \
>> 869 (status) = __val & 0xffff; \
>> 870 (length) = __val >> 16; \
1194 } while (0) 871 } while (0)
1195 !! 872 #else
1196 #define SMC_PUT_PKT_HDR(lp, status, length) !! 873 #define SMC_PUT_PKT_HDR(status, length) \
1197 do { 874 do { \
1198 if (SMC_32BIT(lp)) !! 875 SMC_outw( status, ioaddr, DATA_REG ); \
1199 SMC_outl((status) | ( !! 876 SMC_outw( length, ioaddr, DATA_REG ); \
1200 DATA_REG(lp) !! 877 } while (0)
1201 else { !! 878 #define SMC_GET_PKT_HDR(status, length) \
1202 SMC_outw(status, ioad !! 879 do { \
1203 SMC_outw(length, ioad !! 880 (status) = SMC_inw( ioaddr, DATA_REG ); \
1204 } !! 881 (length) = SMC_inw( ioaddr, DATA_REG ); \
1205 } while (0) 882 } while (0)
>> 883 #endif
1206 884
1207 #define SMC_GET_PKT_HDR(lp, status, length) !! 885 #if SMC_CAN_USE_32BIT
>> 886 #define SMC_PUSH_DATA(p, l) \
1208 do { 887 do { \
1209 if (SMC_32BIT(lp)) { !! 888 char *__ptr = (p); \
1210 unsigned int __val = !! 889 int __len = (l); \
1211 (status) = __val & 0x !! 890 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1212 (length) = __val >> 1 !! 891 __len -= 2; \
1213 } else { !! 892 SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \
1214 (status) = SMC_inw(io !! 893 __ptr += 2; \
1215 (length) = SMC_inw(io !! 894 } \
>> 895 SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \
>> 896 if (__len & 2) { \
>> 897 __ptr += (__len & ~3); \
>> 898 SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
1216 } 899 } \
1217 } while (0) 900 } while (0)
1218 !! 901 #define SMC_PULL_DATA(p, l) \
1219 #define SMC_PUSH_DATA(lp, p, l) <<
1220 do { 902 do { \
1221 if (SMC_32BIT(lp)) { !! 903 char *__ptr = (p); \
1222 void *__ptr = (p); !! 904 int __len = (l); \
1223 int __len = (l); !! 905 if ((unsigned long)__ptr & 2) { \
1224 void __iomem *__ioadd !! 906 /* \
1225 if (__len >= 2 && (un !! 907 * We want 32bit alignment here. \
1226 __len -= 2; !! 908 * Since some buses perform a full 32bit \
1227 SMC_outw(*(u1 !! 909 * fetch even for 16bit data we can't use \
1228 DATA_ !! 910 * SMC_inw() here. Back both source (on chip \
1229 __ptr += 2; !! 911 * and destination) pointers of 2 bytes. \
1230 } !! 912 */ \
1231 if (SMC_CAN_USE_DATAC !! 913 __ptr -= 2; \
1232 __ioaddr = lp !! 914 __len += 2; \
1233 SMC_outsl(__ioaddr, D !! 915 SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \
1234 if (__len & 2) { !! 916 } \
1235 __ptr += (__l !! 917 __len += 2; \
1236 SMC_outw(*((u !! 918 SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \
1237 DATA <<
1238 } <<
1239 } else if (SMC_16BIT(lp)) <<
1240 SMC_outsw(ioaddr, DAT <<
1241 else if (SMC_8BIT(lp)) <<
1242 SMC_outsb(ioaddr, DAT <<
1243 } while (0) 919 } while (0)
>> 920 #elif SMC_CAN_USE_16BIT
>> 921 #define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 )
>> 922 #define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 )
>> 923 #elif SMC_CAN_USE_8BIT
>> 924 #define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l )
>> 925 #define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l )
>> 926 #endif
1244 927
1245 #define SMC_PULL_DATA(lp, p, l) !! 928 #if ! SMC_CAN_USE_16BIT
>> 929 #define SMC_outw(x, ioaddr, reg) \
1246 do { 930 do { \
1247 if (SMC_32BIT(lp)) { !! 931 unsigned int __val16 = (x); \
1248 void *__ptr = (p); !! 932 SMC_outb( __val16, ioaddr, reg ); \
1249 int __len = (l); !! 933 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
1250 void __iomem *__ioadd <<
1251 if ((unsigned long)__ <<
1252 /* <<
1253 * We want 32 <<
1254 * Since some <<
1255 * 32bit fetc <<
1256 * we can't u <<
1257 * Back both <<
1258 * destinatio <<
1259 * This is po <<
1260 * SMC_GET_PK <<
1261 * the source <<
1262 * the skb_re <<
1263 * the destin <<
1264 */ <<
1265 __ptr -= 2; <<
1266 __len += 2; <<
1267 SMC_SET_PTR(l <<
1268 2|PTR <<
1269 } <<
1270 if (SMC_CAN_USE_DATAC <<
1271 __ioaddr = lp <<
1272 __len += 2; <<
1273 SMC_insl(__ioaddr, DA <<
1274 } else if (SMC_16BIT(lp)) <<
1275 SMC_insw(ioaddr, DATA <<
1276 else if (SMC_8BIT(lp)) <<
1277 SMC_insb(ioaddr, DATA <<
1278 } while (0) 934 } while (0)
>> 935 #define SMC_inw(ioaddr, reg) \
>> 936 ({ \
>> 937 unsigned int __val16; \
>> 938 __val16 = SMC_inb( ioaddr, reg ); \
>> 939 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
>> 940 __val16; \
>> 941 })
>> 942 #endif
>> 943
>> 944 #if !defined (SMC_INTERRUPT_PREAMBLE)
>> 945 # define SMC_INTERRUPT_PREAMBLE
>> 946 #endif
1279 947
1280 #endif /* _SMC91X_H_ */ 948 #endif /* _SMC91X_H_ */
1281 949
|
This page was automatically generated by the
LXR engine.
|