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1 /* 1 /*
2 * Definitions for the new Marvell Yukon / Sys 2 * Definitions for the new Marvell Yukon / SysKonnect driver.
3 */ 3 */
4 #ifndef _SKGE_H 4 #ifndef _SKGE_H
5 #define _SKGE_H 5 #define _SKGE_H
6 6
7 /* PCI config registers */ 7 /* PCI config registers */
8 #define PCI_DEV_REG1 0x40 8 #define PCI_DEV_REG1 0x40
9 #define PCI_PHY_COMA 0x8000000 9 #define PCI_PHY_COMA 0x8000000
10 #define PCI_VIO 0x2000000 10 #define PCI_VIO 0x2000000
11 11
12 #define PCI_DEV_REG2 0x44 12 #define PCI_DEV_REG2 0x44
13 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM siz 13 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
14 #define PCI_REV_DESC 1<<2 /* Reverse Des 14 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
15 15
16 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETE 16 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
17 PCI_STATUS_SIG_ 17 PCI_STATUS_SIG_SYSTEM_ERROR | \
18 PCI_STATUS_REC_ 18 PCI_STATUS_REC_MASTER_ABORT | \
19 PCI_STATUS_REC_ 19 PCI_STATUS_REC_TARGET_ABORT | \
20 PCI_STATUS_PARI 20 PCI_STATUS_PARITY)
21 21
22 enum csr_regs { 22 enum csr_regs {
23 B0_RAP = 0x0000, 23 B0_RAP = 0x0000,
24 B0_CTST = 0x0004, 24 B0_CTST = 0x0004,
25 B0_LED = 0x0006, 25 B0_LED = 0x0006,
26 B0_POWER_CTRL = 0x0007, 26 B0_POWER_CTRL = 0x0007,
27 B0_ISRC = 0x0008, 27 B0_ISRC = 0x0008,
28 B0_IMSK = 0x000c, 28 B0_IMSK = 0x000c,
29 B0_HWE_ISRC = 0x0010, 29 B0_HWE_ISRC = 0x0010,
30 B0_HWE_IMSK = 0x0014, 30 B0_HWE_IMSK = 0x0014,
31 B0_SP_ISRC = 0x0018, 31 B0_SP_ISRC = 0x0018,
32 B0_XM1_IMSK = 0x0020, 32 B0_XM1_IMSK = 0x0020,
33 B0_XM1_ISRC = 0x0028, 33 B0_XM1_ISRC = 0x0028,
34 B0_XM1_PHY_ADDR = 0x0030, 34 B0_XM1_PHY_ADDR = 0x0030,
35 B0_XM1_PHY_DATA = 0x0034, 35 B0_XM1_PHY_DATA = 0x0034,
36 B0_XM2_IMSK = 0x0040, 36 B0_XM2_IMSK = 0x0040,
37 B0_XM2_ISRC = 0x0048, 37 B0_XM2_ISRC = 0x0048,
38 B0_XM2_PHY_ADDR = 0x0050, 38 B0_XM2_PHY_ADDR = 0x0050,
39 B0_XM2_PHY_DATA = 0x0054, 39 B0_XM2_PHY_DATA = 0x0054,
40 B0_R1_CSR = 0x0060, 40 B0_R1_CSR = 0x0060,
41 B0_R2_CSR = 0x0064, 41 B0_R2_CSR = 0x0064,
42 B0_XS1_CSR = 0x0068, 42 B0_XS1_CSR = 0x0068,
43 B0_XA1_CSR = 0x006c, 43 B0_XA1_CSR = 0x006c,
44 B0_XS2_CSR = 0x0070, 44 B0_XS2_CSR = 0x0070,
45 B0_XA2_CSR = 0x0074, 45 B0_XA2_CSR = 0x0074,
46 46
47 B2_MAC_1 = 0x0100, 47 B2_MAC_1 = 0x0100,
48 B2_MAC_2 = 0x0108, 48 B2_MAC_2 = 0x0108,
49 B2_MAC_3 = 0x0110, 49 B2_MAC_3 = 0x0110,
50 B2_CONN_TYP = 0x0118, 50 B2_CONN_TYP = 0x0118,
51 B2_PMD_TYP = 0x0119, 51 B2_PMD_TYP = 0x0119,
52 B2_MAC_CFG = 0x011a, 52 B2_MAC_CFG = 0x011a,
53 B2_CHIP_ID = 0x011b, 53 B2_CHIP_ID = 0x011b,
54 B2_E_0 = 0x011c, 54 B2_E_0 = 0x011c,
55 B2_E_1 = 0x011d, 55 B2_E_1 = 0x011d,
56 B2_E_2 = 0x011e, 56 B2_E_2 = 0x011e,
57 B2_E_3 = 0x011f, 57 B2_E_3 = 0x011f,
58 B2_FAR = 0x0120, 58 B2_FAR = 0x0120,
59 B2_FDP = 0x0124, 59 B2_FDP = 0x0124,
60 B2_LD_CTRL = 0x0128, 60 B2_LD_CTRL = 0x0128,
61 B2_LD_TEST = 0x0129, 61 B2_LD_TEST = 0x0129,
62 B2_TI_INI = 0x0130, 62 B2_TI_INI = 0x0130,
63 B2_TI_VAL = 0x0134, 63 B2_TI_VAL = 0x0134,
64 B2_TI_CTRL = 0x0138, 64 B2_TI_CTRL = 0x0138,
65 B2_TI_TEST = 0x0139, 65 B2_TI_TEST = 0x0139,
66 B2_IRQM_INI = 0x0140, 66 B2_IRQM_INI = 0x0140,
67 B2_IRQM_VAL = 0x0144, 67 B2_IRQM_VAL = 0x0144,
68 B2_IRQM_CTRL = 0x0148, 68 B2_IRQM_CTRL = 0x0148,
69 B2_IRQM_TEST = 0x0149, 69 B2_IRQM_TEST = 0x0149,
70 B2_IRQM_MSK = 0x014c, 70 B2_IRQM_MSK = 0x014c,
71 B2_IRQM_HWE_MSK = 0x0150, 71 B2_IRQM_HWE_MSK = 0x0150,
72 B2_TST_CTRL1 = 0x0158, 72 B2_TST_CTRL1 = 0x0158,
73 B2_TST_CTRL2 = 0x0159, 73 B2_TST_CTRL2 = 0x0159,
74 B2_GP_IO = 0x015c, 74 B2_GP_IO = 0x015c,
75 B2_I2C_CTRL = 0x0160, 75 B2_I2C_CTRL = 0x0160,
76 B2_I2C_DATA = 0x0164, 76 B2_I2C_DATA = 0x0164,
77 B2_I2C_IRQ = 0x0168, 77 B2_I2C_IRQ = 0x0168,
78 B2_I2C_SW = 0x016c, 78 B2_I2C_SW = 0x016c,
79 B2_BSC_INI = 0x0170, 79 B2_BSC_INI = 0x0170,
80 B2_BSC_VAL = 0x0174, 80 B2_BSC_VAL = 0x0174,
81 B2_BSC_CTRL = 0x0178, 81 B2_BSC_CTRL = 0x0178,
82 B2_BSC_STAT = 0x0179, 82 B2_BSC_STAT = 0x0179,
83 B2_BSC_TST = 0x017a, 83 B2_BSC_TST = 0x017a,
84 84
85 B3_RAM_ADDR = 0x0180, 85 B3_RAM_ADDR = 0x0180,
86 B3_RAM_DATA_LO = 0x0184, 86 B3_RAM_DATA_LO = 0x0184,
87 B3_RAM_DATA_HI = 0x0188, 87 B3_RAM_DATA_HI = 0x0188,
88 B3_RI_WTO_R1 = 0x0190, 88 B3_RI_WTO_R1 = 0x0190,
89 B3_RI_WTO_XA1 = 0x0191, 89 B3_RI_WTO_XA1 = 0x0191,
90 B3_RI_WTO_XS1 = 0x0192, 90 B3_RI_WTO_XS1 = 0x0192,
91 B3_RI_RTO_R1 = 0x0193, 91 B3_RI_RTO_R1 = 0x0193,
92 B3_RI_RTO_XA1 = 0x0194, 92 B3_RI_RTO_XA1 = 0x0194,
93 B3_RI_RTO_XS1 = 0x0195, 93 B3_RI_RTO_XS1 = 0x0195,
94 B3_RI_WTO_R2 = 0x0196, 94 B3_RI_WTO_R2 = 0x0196,
95 B3_RI_WTO_XA2 = 0x0197, 95 B3_RI_WTO_XA2 = 0x0197,
96 B3_RI_WTO_XS2 = 0x0198, 96 B3_RI_WTO_XS2 = 0x0198,
97 B3_RI_RTO_R2 = 0x0199, 97 B3_RI_RTO_R2 = 0x0199,
98 B3_RI_RTO_XA2 = 0x019a, 98 B3_RI_RTO_XA2 = 0x019a,
99 B3_RI_RTO_XS2 = 0x019b, 99 B3_RI_RTO_XS2 = 0x019b,
100 B3_RI_TO_VAL = 0x019c, 100 B3_RI_TO_VAL = 0x019c,
101 B3_RI_CTRL = 0x01a0, 101 B3_RI_CTRL = 0x01a0,
102 B3_RI_TEST = 0x01a2, 102 B3_RI_TEST = 0x01a2,
103 B3_MA_TOINI_RX1 = 0x01b0, 103 B3_MA_TOINI_RX1 = 0x01b0,
104 B3_MA_TOINI_RX2 = 0x01b1, 104 B3_MA_TOINI_RX2 = 0x01b1,
105 B3_MA_TOINI_TX1 = 0x01b2, 105 B3_MA_TOINI_TX1 = 0x01b2,
106 B3_MA_TOINI_TX2 = 0x01b3, 106 B3_MA_TOINI_TX2 = 0x01b3,
107 B3_MA_TOVAL_RX1 = 0x01b4, 107 B3_MA_TOVAL_RX1 = 0x01b4,
108 B3_MA_TOVAL_RX2 = 0x01b5, 108 B3_MA_TOVAL_RX2 = 0x01b5,
109 B3_MA_TOVAL_TX1 = 0x01b6, 109 B3_MA_TOVAL_TX1 = 0x01b6,
110 B3_MA_TOVAL_TX2 = 0x01b7, 110 B3_MA_TOVAL_TX2 = 0x01b7,
111 B3_MA_TO_CTRL = 0x01b8, 111 B3_MA_TO_CTRL = 0x01b8,
112 B3_MA_TO_TEST = 0x01ba, 112 B3_MA_TO_TEST = 0x01ba,
113 B3_MA_RCINI_RX1 = 0x01c0, 113 B3_MA_RCINI_RX1 = 0x01c0,
114 B3_MA_RCINI_RX2 = 0x01c1, 114 B3_MA_RCINI_RX2 = 0x01c1,
115 B3_MA_RCINI_TX1 = 0x01c2, 115 B3_MA_RCINI_TX1 = 0x01c2,
116 B3_MA_RCINI_TX2 = 0x01c3, 116 B3_MA_RCINI_TX2 = 0x01c3,
117 B3_MA_RCVAL_RX1 = 0x01c4, 117 B3_MA_RCVAL_RX1 = 0x01c4,
118 B3_MA_RCVAL_RX2 = 0x01c5, 118 B3_MA_RCVAL_RX2 = 0x01c5,
119 B3_MA_RCVAL_TX1 = 0x01c6, 119 B3_MA_RCVAL_TX1 = 0x01c6,
120 B3_MA_RCVAL_TX2 = 0x01c7, 120 B3_MA_RCVAL_TX2 = 0x01c7,
121 B3_MA_RC_CTRL = 0x01c8, 121 B3_MA_RC_CTRL = 0x01c8,
122 B3_MA_RC_TEST = 0x01ca, 122 B3_MA_RC_TEST = 0x01ca,
123 B3_PA_TOINI_RX1 = 0x01d0, 123 B3_PA_TOINI_RX1 = 0x01d0,
124 B3_PA_TOINI_RX2 = 0x01d4, 124 B3_PA_TOINI_RX2 = 0x01d4,
125 B3_PA_TOINI_TX1 = 0x01d8, 125 B3_PA_TOINI_TX1 = 0x01d8,
126 B3_PA_TOINI_TX2 = 0x01dc, 126 B3_PA_TOINI_TX2 = 0x01dc,
127 B3_PA_TOVAL_RX1 = 0x01e0, 127 B3_PA_TOVAL_RX1 = 0x01e0,
128 B3_PA_TOVAL_RX2 = 0x01e4, 128 B3_PA_TOVAL_RX2 = 0x01e4,
129 B3_PA_TOVAL_TX1 = 0x01e8, 129 B3_PA_TOVAL_TX1 = 0x01e8,
130 B3_PA_TOVAL_TX2 = 0x01ec, 130 B3_PA_TOVAL_TX2 = 0x01ec,
131 B3_PA_CTRL = 0x01f0, 131 B3_PA_CTRL = 0x01f0,
132 B3_PA_TEST = 0x01f2, 132 B3_PA_TEST = 0x01f2,
133 }; 133 };
134 134
135 /* B0_CTST 16 bit Contro 135 /* B0_CTST 16 bit Control/Status register */
136 enum { 136 enum {
137 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot 137 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
138 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN res 138 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
139 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN ena 139 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
140 CS_VAUX_AVAIL = 1<<10,/* VAUX availa 140 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
141 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0 141 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
142 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0 142 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
143 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW 143 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
144 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ S 144 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
145 CS_STOP_DONE = 1<<5, /* Stop Master 145 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
146 CS_STOP_MAST = 1<<4, /* Command Bit 146 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
147 CS_MRST_CLR = 1<<3, /* Clear Maste 147 CS_MRST_CLR = 1<<3, /* Clear Master reset */
148 CS_MRST_SET = 1<<2, /* Set Master 148 CS_MRST_SET = 1<<2, /* Set Master reset */
149 CS_RST_CLR = 1<<1, /* Clear Softw 149 CS_RST_CLR = 1<<1, /* Clear Software reset */
150 CS_RST_SET = 1, /* Set Softw 150 CS_RST_SET = 1, /* Set Software reset */
151 151
152 /* B0_LED 8 Bit LED re 152 /* B0_LED 8 Bit LED register */
153 /* Bit 7.. 2: reserved */ 153 /* Bit 7.. 2: reserved */
154 LED_STAT_ON = 1<<1, /* Status LED 154 LED_STAT_ON = 1<<1, /* Status LED on */
155 LED_STAT_OFF = 1, /* Sta 155 LED_STAT_OFF = 1, /* Status LED off */
156 156
157 /* B0_POWER_CTRL 8 Bit Power Control 157 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
158 PC_VAUX_ENA = 1<<7, /* Switch VAUX 158 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
159 PC_VAUX_DIS = 1<<6, /* Switch VAUX 159 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
160 PC_VCC_ENA = 1<<5, /* Switch VCC 160 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
161 PC_VCC_DIS = 1<<4, /* Switch VCC 161 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
162 PC_VAUX_ON = 1<<3, /* Switch VAUX 162 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
163 PC_VAUX_OFF = 1<<2, /* Switch VAUX 163 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
164 PC_VCC_ON = 1<<1, /* Switch VCC 164 PC_VCC_ON = 1<<1, /* Switch VCC On */
165 PC_VCC_OFF = 1<<0, /* Switch VCC 165 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
166 }; 166 };
167 167
168 /* B2_IRQM_MSK 32 bit IRQ Moderation 168 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
169 enum { 169 enum {
170 IS_ALL_MSK = 0xbffffffful, /* All 170 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
171 IS_HW_ERR = 1<<31, /* Int 171 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
172 /* Bit 172 /* Bit 30: reserved */
173 IS_PA_TO_RX1 = 1<<29, /* Pac 173 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
174 IS_PA_TO_RX2 = 1<<28, /* Pac 174 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
175 IS_PA_TO_TX1 = 1<<27, /* Pac 175 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
176 IS_PA_TO_TX2 = 1<<26, /* Pac 176 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
177 IS_I2C_READY = 1<<25, /* IRQ 177 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
178 IS_IRQ_SW = 1<<24, /* SW 178 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
179 IS_EXT_REG = 1<<23, /* IRQ 179 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
180 /* IRQ 180 /* IRQ from PHY (YUKON only) */
181 IS_TIMINT = 1<<22, /* IRQ 181 IS_TIMINT = 1<<22, /* IRQ from Timer */
182 IS_MAC1 = 1<<21, /* IRQ 182 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
183 IS_LNK_SYNC_M1 = 1<<20, /* Lin 183 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
184 IS_MAC2 = 1<<19, /* IRQ 184 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
185 IS_LNK_SYNC_M2 = 1<<18, /* Lin 185 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
186 /* Receive Queue 1 */ 186 /* Receive Queue 1 */
187 IS_R1_B = 1<<17, /* Q_R 187 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
188 IS_R1_F = 1<<16, /* Q_R 188 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
189 IS_R1_C = 1<<15, /* Q_R 189 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
190 /* Receive Queue 2 */ 190 /* Receive Queue 2 */
191 IS_R2_B = 1<<14, /* Q_R 191 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
192 IS_R2_F = 1<<13, /* Q_R 192 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
193 IS_R2_C = 1<<12, /* Q_R 193 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
194 /* Synchronous Transmit Queue 1 */ 194 /* Synchronous Transmit Queue 1 */
195 IS_XS1_B = 1<<11, /* Q_X 195 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
196 IS_XS1_F = 1<<10, /* Q_X 196 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
197 IS_XS1_C = 1<<9, /* Q_X 197 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
198 /* Asynchronous Transmit Queue 1 */ 198 /* Asynchronous Transmit Queue 1 */
199 IS_XA1_B = 1<<8, /* Q_X 199 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
200 IS_XA1_F = 1<<7, /* Q_X 200 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
201 IS_XA1_C = 1<<6, /* Q_X 201 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
202 /* Synchronous Transmit Queue 2 */ 202 /* Synchronous Transmit Queue 2 */
203 IS_XS2_B = 1<<5, /* Q_X 203 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
204 IS_XS2_F = 1<<4, /* Q_X 204 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
205 IS_XS2_C = 1<<3, /* Q_X 205 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
206 /* Asynchronous Transmit Queue 2 */ 206 /* Asynchronous Transmit Queue 2 */
207 IS_XA2_B = 1<<2, /* Q_X 207 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
208 IS_XA2_F = 1<<1, /* Q_X 208 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
209 IS_XA2_C = 1<<0, /* Q_X 209 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
210 210
211 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA 211 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
212 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA 212 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
213 213
214 IS_PORT_1 = IS_XA1_F| IS_R1_F | 214 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
215 IS_PORT_2 = IS_XA2_F| IS_R2_F | 215 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
216 }; 216 };
217 217
218 218
219 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation 219 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
220 enum { 220 enum {
221 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp 221 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
222 IS_IRQ_SENSOR = 1<<12, /* IRQ from S 222 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
223 IS_IRQ_MST_ERR = 1<<11, /* IRQ master 223 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
224 IS_IRQ_STAT = 1<<10, /* IRQ status 224 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
225 IS_NO_STAT_M1 = 1<<9, /* No Rx Statu 225 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
226 IS_NO_STAT_M2 = 1<<8, /* No Rx Statu 226 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
227 IS_NO_TIST_M1 = 1<<7, /* No Time Sta 227 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
228 IS_NO_TIST_M2 = 1<<6, /* No Time Sta 228 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
229 IS_RAM_RD_PAR = 1<<5, /* RAM Read P 229 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
230 IS_RAM_WR_PAR = 1<<4, /* RAM Write P 230 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
231 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parit 231 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
232 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parit 232 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
233 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Pa 233 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
234 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Pa 234 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
235 235
236 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_ 236 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
237 | IS_RAM_RD_PAR | IS_R 237 | IS_RAM_RD_PAR | IS_RAM_WR_PAR
238 | IS_M1_PAR_ERR | IS_M 238 | IS_M1_PAR_ERR | IS_M2_PAR_ERR
239 | IS_R1_PAR_ERR | IS_R 239 | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
240 }; 240 };
241 241
242 /* B2_TST_CTRL1 8 bit Test Control R 242 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
243 enum { 243 enum {
244 TST_FRC_DPERR_MR = 1<<7, /* force DATA 244 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
245 TST_FRC_DPERR_MW = 1<<6, /* force DATA 245 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
246 TST_FRC_DPERR_TR = 1<<5, /* force DATA 246 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
247 TST_FRC_DPERR_TW = 1<<4, /* force DATA 247 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
248 TST_FRC_APERR_M = 1<<3, /* force ADDR 248 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
249 TST_FRC_APERR_T = 1<<2, /* force ADDR 249 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
250 TST_CFG_WRITE_ON = 1<<1, /* Enable Co 250 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
251 TST_CFG_WRITE_OFF= 1<<0, /* Disable Co 251 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
252 }; 252 };
253 253
254 /* B2_MAC_CFG 8 bit MAC Co 254 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
255 enum { 255 enum {
256 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 256 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
257 /* Bit 257 /* Bit 3.. 2: reserved */
258 CFG_DIS_M2_CLK = 1<<1, /* Dis 258 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
259 CFG_SNG_MAC = 1<<0, /* MAC 259 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
260 }; 260 };
261 261
262 /* B2_CHIP_ID 8 bit Chip I 262 /* B2_CHIP_ID 8 bit Chip Identification Number */
263 enum { 263 enum {
264 CHIP_ID_GENESIS = 0x0a, /* Chip ID 264 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
265 CHIP_ID_YUKON = 0xb0, /* Chip ID 265 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
266 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID 266 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
267 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID 267 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
268 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID 268 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
269 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID 269 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
270 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID 270 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
271 271
272 CHIP_REV_YU_LITE_A1 = 3, /* Chi 272 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
273 CHIP_REV_YU_LITE_A3 = 7, /* Chi 273 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
274 }; 274 };
275 275
276 /* B2_TI_CTRL 8 bit Timer 276 /* B2_TI_CTRL 8 bit Timer control */
277 /* B2_IRQM_CTRL 8 bit IRQ Moderation 277 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
278 enum { 278 enum {
279 TIM_START = 1<<2, /* Start Timer 279 TIM_START = 1<<2, /* Start Timer */
280 TIM_STOP = 1<<1, /* Stop Timer 280 TIM_STOP = 1<<1, /* Stop Timer */
281 TIM_CLR_IRQ = 1<<0, /* Clear Timer 281 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
282 }; 282 };
283 283
284 /* B2_TI_TEST 8 Bit Timer 284 /* B2_TI_TEST 8 Bit Timer Test */
285 /* B2_IRQM_TEST 8 bit IRQ Moderation 285 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
286 /* B28_DPT_TST 8 bit Descri 286 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
287 enum { 287 enum {
288 TIM_T_ON = 1<<2, /* Test mode o 288 TIM_T_ON = 1<<2, /* Test mode on */
289 TIM_T_OFF = 1<<1, /* Test mode o 289 TIM_T_OFF = 1<<1, /* Test mode off */
290 TIM_T_STEP = 1<<0, /* Test step * 290 TIM_T_STEP = 1<<0, /* Test step */
291 }; 291 };
292 292
293 /* B2_GP_IO 32 bit Genera 293 /* B2_GP_IO 32 bit General Purpose I/O Register */
294 enum { 294 enum {
295 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In 295 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
296 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In 296 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
297 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In 297 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
298 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In 298 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
299 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In 299 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
300 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In 300 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
301 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In 301 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
302 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In 302 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
303 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In 303 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
304 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In 304 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
305 305
306 GP_IO_9 = 1<<9, /* IO_9 pin */ 306 GP_IO_9 = 1<<9, /* IO_9 pin */
307 GP_IO_8 = 1<<8, /* IO_8 pin */ 307 GP_IO_8 = 1<<8, /* IO_8 pin */
308 GP_IO_7 = 1<<7, /* IO_7 pin */ 308 GP_IO_7 = 1<<7, /* IO_7 pin */
309 GP_IO_6 = 1<<6, /* IO_6 pin */ 309 GP_IO_6 = 1<<6, /* IO_6 pin */
310 GP_IO_5 = 1<<5, /* IO_5 pin */ 310 GP_IO_5 = 1<<5, /* IO_5 pin */
311 GP_IO_4 = 1<<4, /* IO_4 pin */ 311 GP_IO_4 = 1<<4, /* IO_4 pin */
312 GP_IO_3 = 1<<3, /* IO_3 pin */ 312 GP_IO_3 = 1<<3, /* IO_3 pin */
313 GP_IO_2 = 1<<2, /* IO_2 pin */ 313 GP_IO_2 = 1<<2, /* IO_2 pin */
314 GP_IO_1 = 1<<1, /* IO_1 pin */ 314 GP_IO_1 = 1<<1, /* IO_1 pin */
315 GP_IO_0 = 1<<0, /* IO_0 pin */ 315 GP_IO_0 = 1<<0, /* IO_0 pin */
316 }; 316 };
317 317
318 /* Descriptor Bit Definition */ 318 /* Descriptor Bit Definition */
319 /* TxCtrl Transmit Buffer Contro 319 /* TxCtrl Transmit Buffer Control Field */
320 /* RxCtrl Receive Buffer Contro 320 /* RxCtrl Receive Buffer Control Field */
321 enum { 321 enum {
322 BMU_OWN = 1<<31, /* OWN bit: 0 322 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
323 BMU_STF = 1<<30, /* Start of F 323 BMU_STF = 1<<30, /* Start of Frame */
324 BMU_EOF = 1<<29, /* End of Fra 324 BMU_EOF = 1<<29, /* End of Frame */
325 BMU_IRQ_EOB = 1<<28, /* Req "End o 325 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
326 BMU_IRQ_EOF = 1<<27, /* Req "End o 326 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
327 /* TxCtrl spec 327 /* TxCtrl specific bits */
328 BMU_STFWD = 1<<26, /* (Tx) 328 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
329 BMU_NO_FCS = 1<<25, /* (Tx) Disab 329 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
330 BMU_SW = 1<<24, /* (Tx) 1 bit 330 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
331 /* RxCtrl spec 331 /* RxCtrl specific bits */
332 BMU_DEV_0 = 1<<26, /* (Rx) 332 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
333 BMU_STAT_VAL = 1<<25, /* (Rx) 333 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
334 BMU_TIST_VAL = 1<<24, /* (Rx) 334 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
335 /* Bit 23..16: BMU Ch 335 /* Bit 23..16: BMU Check Opcodes */
336 BMU_CHECK = 0x55<<16, /* Default 336 BMU_CHECK = 0x55<<16, /* Default BMU check */
337 BMU_TCP_CHECK = 0x56<<16, /* Descr w 337 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
338 BMU_UDP_CHECK = 0x57<<16, /* Descr w 338 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
339 BMU_BBC = 0xffffL, /* Bit 15.. 339 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
340 }; 340 };
341 341
342 /* B2_BSC_CTRL 8 bit Blink 342 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
343 enum { 343 enum {
344 BSC_START = 1<<1, /* Start Blink 344 BSC_START = 1<<1, /* Start Blink Source Counter */
345 BSC_STOP = 1<<0, /* Stop Blink 345 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
346 }; 346 };
347 347
348 /* B2_BSC_STAT 8 bit Blink 348 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
349 enum { 349 enum {
350 BSC_SRC = 1<<0, /* Blink Sourc 350 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
351 }; 351 };
352 352
353 /* B2_BSC_TST 16 bit Blink 353 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
354 enum { 354 enum {
355 BSC_T_ON = 1<<2, /* Test mode o 355 BSC_T_ON = 1<<2, /* Test mode on */
356 BSC_T_OFF = 1<<1, /* Test mode o 356 BSC_T_OFF = 1<<1, /* Test mode off */
357 BSC_T_STEP = 1<<0, /* Test step * 357 BSC_T_STEP = 1<<0, /* Test step */
358 }; 358 };
359 359
360 /* B3_RAM_ADDR 32 bit RAM Ad 360 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
361 /* Bit 361 /* Bit 31..19: reserved */
362 #define RAM_ADR_RAN 0x0007ffffL /* Bit 362 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
363 /* RAM Interface Registers */ 363 /* RAM Interface Registers */
364 364
365 /* B3_RI_CTRL 16 bit RAM If 365 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
366 enum { 366 enum {
367 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ R 367 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
368 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ R 368 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
369 369
370 RI_RST_CLR = 1<<1, /* Clear RAM I 370 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
371 RI_RST_SET = 1<<0, /* Set RAM I 371 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
372 }; 372 };
373 373
374 /* MAC Arbiter Registers */ 374 /* MAC Arbiter Registers */
375 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Ti 375 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
376 enum { 376 enum {
377 MA_FOE_ON = 1<<3, /* XMAC Fast O 377 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
378 MA_FOE_OFF = 1<<2, /* XMAC Fast O 378 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
379 MA_RST_CLR = 1<<1, /* Clear MAC A 379 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
380 MA_RST_SET = 1<<0, /* Set MAC A 380 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
381 381
382 }; 382 };
383 383
384 /* Timeout values */ 384 /* Timeout values */
385 #define SK_MAC_TO_53 72 /* MAC 385 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
386 #define SK_PKT_TO_53 0x2000 /* Pac 386 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
387 #define SK_PKT_TO_MAX 0xffff /* Max 387 #define SK_PKT_TO_MAX 0xffff /* Maximum value */
388 #define SK_RI_TO_53 36 /* RAM 388 #define SK_RI_TO_53 36 /* RAM interface timeout */
389 389
390 /* Packet Arbiter Registers */ 390 /* Packet Arbiter Registers */
391 /* B3_PA_CTRL 16 bit Packet 391 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
392 enum { 392 enum {
393 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ P 393 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
394 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ P 394 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
395 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ P 395 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
396 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ P 396 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
397 PA_ENA_TO_TX2 = 1<<9, /* Enable Tim 397 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
398 PA_DIS_TO_TX2 = 1<<8, /* Disable Tim 398 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
399 PA_ENA_TO_TX1 = 1<<7, /* Enable Tim 399 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
400 PA_DIS_TO_TX1 = 1<<6, /* Disable Tim 400 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
401 PA_ENA_TO_RX2 = 1<<5, /* Enable Tim 401 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
402 PA_DIS_TO_RX2 = 1<<4, /* Disable Tim 402 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
403 PA_ENA_TO_RX1 = 1<<3, /* Enable Tim 403 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
404 PA_DIS_TO_RX1 = 1<<2, /* Disable Tim 404 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
405 PA_RST_CLR = 1<<1, /* Clear MAC A 405 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
406 PA_RST_SET = 1<<0, /* Set MAC A 406 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
407 }; 407 };
408 408
409 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_EN 409 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
410 410 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
411 411
412 412
413 /* Transmit Arbiter Registers MAC 1 and 2, use 413 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
414 /* TXA_ITI_INI 32 bit Tx Arb 414 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
415 /* TXA_ITI_VAL 32 bit Tx Arb 415 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
416 /* TXA_LIM_INI 32 bit Tx Arb 416 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
417 /* TXA_LIM_VAL 32 bit Tx Arb 417 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
418 418
419 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 419 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
420 420
421 /* TXA_CTRL 8 bit Tx Arb 421 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
422 enum { 422 enum {
423 TXA_ENA_FSYNC = 1<<7, /* Enable for 423 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
424 TXA_DIS_FSYNC = 1<<6, /* Disable for 424 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
425 TXA_ENA_ALLOC = 1<<5, /* Enable all 425 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
426 TXA_DIS_ALLOC = 1<<4, /* Disable all 426 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
427 TXA_START_RC = 1<<3, /* Start sync 427 TXA_START_RC = 1<<3, /* Start sync Rate Control */
428 TXA_STOP_RC = 1<<2, /* Stop sync 428 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
429 TXA_ENA_ARB = 1<<1, /* Enable Tx 429 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
430 TXA_DIS_ARB = 1<<0, /* Disable Tx 430 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
431 }; 431 };
432 432
433 /* 433 /*
434 * Bank 4 - 5 434 * Bank 4 - 5
435 */ 435 */
436 /* Transmit Arbiter Registers MAC 1 and 2, use 436 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
437 enum { 437 enum {
438 TXA_ITI_INI = 0x0200,/* 32 bit 438 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
439 TXA_ITI_VAL = 0x0204,/* 32 bit 439 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
440 TXA_LIM_INI = 0x0208,/* 32 bit 440 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
441 TXA_LIM_VAL = 0x020c,/* 32 bit 441 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
442 TXA_CTRL = 0x0210,/* 8 bit 442 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
443 TXA_TEST = 0x0211,/* 8 bit 443 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
444 TXA_STAT = 0x0212,/* 8 bit 444 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
445 }; 445 };
446 446
447 447
448 enum { 448 enum {
449 B6_EXT_REG = 0x0300,/* External r 449 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
450 B7_CFG_SPC = 0x0380,/* copy of th 450 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
451 B8_RQ1_REGS = 0x0400,/* Receive Qu 451 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
452 B8_RQ2_REGS = 0x0480,/* Receive Qu 452 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
453 B8_TS1_REGS = 0x0600,/* Transmit s 453 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
454 B8_TA1_REGS = 0x0680,/* Transmit a 454 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
455 B8_TS2_REGS = 0x0700,/* Transmit s 455 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
456 B8_TA2_REGS = 0x0780,/* Transmit s 456 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
457 B16_RAM_REGS = 0x0800,/* RAM Buffer 457 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
458 }; 458 };
459 459
460 /* Queue Register Offsets, use Q_ADDR() to acc 460 /* Queue Register Offsets, use Q_ADDR() to access */
461 enum { 461 enum {
462 B8_Q_REGS = 0x0400, /* base of Queue r 462 B8_Q_REGS = 0x0400, /* base of Queue registers */
463 Q_D = 0x00, /* 8*32 bit Curren 463 Q_D = 0x00, /* 8*32 bit Current Descriptor */
464 Q_DA_L = 0x20, /* 32 bit Curren 464 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
465 Q_DA_H = 0x24, /* 32 bit Curren 465 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
466 Q_AC_L = 0x28, /* 32 bit Curren 466 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
467 Q_AC_H = 0x2c, /* 32 bit Curren 467 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
468 Q_BC = 0x30, /* 32 bit Curren 468 Q_BC = 0x30, /* 32 bit Current Byte Counter */
469 Q_CSR = 0x34, /* 32 bit BMU Co 469 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
470 Q_F = 0x38, /* 32 bit Flag R 470 Q_F = 0x38, /* 32 bit Flag Register */
471 Q_T1 = 0x3c, /* 32 bit Test R 471 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
472 Q_T1_TR = 0x3c, /* 8 bit Test R 472 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
473 Q_T1_WR = 0x3d, /* 8 bit Test R 473 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
474 Q_T1_RD = 0x3e, /* 8 bit Test R 474 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
475 Q_T1_SV = 0x3f, /* 8 bit Test R 475 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
476 Q_T2 = 0x40, /* 32 bit Test R 476 Q_T2 = 0x40, /* 32 bit Test Register 2 */
477 Q_T3 = 0x44, /* 32 bit Test R 477 Q_T3 = 0x44, /* 32 bit Test Register 3 */
478 478
479 }; 479 };
480 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + 480 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
481 481
482 /* RAM Buffer Register Offsets */ 482 /* RAM Buffer Register Offsets */
483 enum { 483 enum {
484 484
485 RB_START= 0x00,/* 32 bit RAM Bu 485 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
486 RB_END = 0x04,/* 32 bit RAM Bu 486 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
487 RB_WP = 0x08,/* 32 bit RAM Bu 487 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
488 RB_RP = 0x0c,/* 32 bit RAM Bu 488 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
489 RB_RX_UTPP= 0x10,/* 32 bit Rx Upp 489 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
490 RB_RX_LTPP= 0x14,/* 32 bit Rx Low 490 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
491 RB_RX_UTHP= 0x18,/* 32 bit Rx Upp 491 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
492 RB_RX_LTHP= 0x1c,/* 32 bit Rx Low 492 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
493 /* 0x10 - 0x1f: reserved at Tx RAM Buf 493 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
494 RB_PC = 0x20,/* 32 bit RAM Bu 494 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
495 RB_LEV = 0x24,/* 32 bit RAM Bu 495 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
496 RB_CTRL = 0x28,/* 32 bit RAM Bu 496 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
497 RB_TST1 = 0x29,/* 8 bit RAM Bu 497 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
498 RB_TST2 = 0x2a,/* 8 bit RAM Bu 498 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
499 }; 499 };
500 500
501 /* Receive and Transmit Queues */ 501 /* Receive and Transmit Queues */
502 enum { 502 enum {
503 Q_R1 = 0x0000, /* Receive Que 503 Q_R1 = 0x0000, /* Receive Queue 1 */
504 Q_R2 = 0x0080, /* Receive Que 504 Q_R2 = 0x0080, /* Receive Queue 2 */
505 Q_XS1 = 0x0200, /* Synchronous 505 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
506 Q_XA1 = 0x0280, /* Asynchronou 506 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
507 Q_XS2 = 0x0300, /* Synchronous 507 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
508 Q_XA2 = 0x0380, /* Asynchronou 508 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
509 }; 509 };
510 510
511 /* Different MAC Types */ 511 /* Different MAC Types */
512 enum { 512 enum {
513 SK_MAC_XMAC = 0, /* Xaqti XMAC 513 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
514 SK_MAC_GMAC = 1, /* Marvell GMA 514 SK_MAC_GMAC = 1, /* Marvell GMAC */
515 }; 515 };
516 516
517 /* Different PHY Types */ 517 /* Different PHY Types */
518 enum { 518 enum {
519 SK_PHY_XMAC = 0,/* integrated in X 519 SK_PHY_XMAC = 0,/* integrated in XMAC II */
520 SK_PHY_BCOM = 1,/* Broadcom BCM540 520 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
521 SK_PHY_LONE = 2,/* Level One LXT10 521 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
522 SK_PHY_NAT = 3,/* National DP8389 522 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
523 SK_PHY_MARV_COPPER= 4,/* Marvell 88E10 523 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
524 SK_PHY_MARV_FIBER = 5,/* Marvell 88E10 524 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
525 }; 525 };
526 526
527 /* PHY addresses (bits 12..8 of PHY address re 527 /* PHY addresses (bits 12..8 of PHY address reg) */
528 enum { 528 enum {
529 PHY_ADDR_XMAC = 0<<8, 529 PHY_ADDR_XMAC = 0<<8,
530 PHY_ADDR_BCOM = 1<<8, 530 PHY_ADDR_BCOM = 1<<8,
531 531
532 /* GPHY address (bits 15..11 of SMI control re 532 /* GPHY address (bits 15..11 of SMI control reg) */
533 PHY_ADDR_MARV = 0, 533 PHY_ADDR_MARV = 0,
534 }; 534 };
535 535
536 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REG 536 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
537 537
538 /* Receive MAC FIFO, Receive LED, and Link_Syn 538 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
539 enum { 539 enum {
540 RX_MFF_EA = 0x0c00,/* 32 bit 540 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
541 RX_MFF_WP = 0x0c04,/* 32 bit 541 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
542 542
543 RX_MFF_RP = 0x0c0c,/* 32 bit 543 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
544 RX_MFF_PC = 0x0c10,/* 32 bit 544 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
545 RX_MFF_LEV = 0x0c14,/* 32 bit 545 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
546 RX_MFF_CTRL1 = 0x0c18,/* 16 bit 546 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
547 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit 547 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
548 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit 548 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
549 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit 549 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
550 RX_MFF_TST1 = 0x0c1d,/* 8 bit 550 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
551 RX_MFF_TST2 = 0x0c1e,/* 8 bit 551 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
552 552
553 RX_LED_INI = 0x0c20,/* 32 bit 553 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
554 RX_LED_VAL = 0x0c24,/* 32 bit 554 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
555 RX_LED_CTRL = 0x0c28,/* 8 bit 555 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
556 RX_LED_TST = 0x0c29,/* 8 bit 556 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
557 557
558 LNK_SYNC_INI = 0x0c30,/* 32 bit 558 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
559 LNK_SYNC_VAL = 0x0c34,/* 32 bit 559 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
560 LNK_SYNC_CTRL = 0x0c38,/* 8 bit 560 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
561 LNK_SYNC_TST = 0x0c39,/* 8 bit 561 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
562 LNK_LED_REG = 0x0c3c,/* 8 bit 562 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
563 }; 563 };
564 564
565 /* Receive and Transmit MAC FIFO Registers (GE 565 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
566 /* RX_MFF_CTRL1 16 bit Receive MAC FI 566 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
567 enum { 567 enum {
568 MFF_ENA_RDY_PAT = 1<<13, /* Ena 568 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
569 MFF_DIS_RDY_PAT = 1<<12, /* Dis 569 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
570 MFF_ENA_TIM_PAT = 1<<11, /* Ena 570 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
571 MFF_DIS_TIM_PAT = 1<<10, /* Dis 571 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
572 MFF_ENA_ALM_FUL = 1<<9, /* Enable Alm 572 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
573 MFF_DIS_ALM_FUL = 1<<8, /* Disable Alm 573 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
574 MFF_ENA_PAUSE = 1<<7, /* Enable Pau 574 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
575 MFF_DIS_PAUSE = 1<<6, /* Disable Pau 575 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
576 MFF_ENA_FLUSH = 1<<5, /* Enable Fra 576 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
577 MFF_DIS_FLUSH = 1<<4, /* Disable Fra 577 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
578 MFF_ENA_TIST = 1<<3, /* Enable Tim 578 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
579 MFF_DIS_TIST = 1<<2, /* Disable Tim 579 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
580 MFF_CLR_INTIST = 1<<1, /* Clear IRQ N 580 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
581 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ N 581 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
582 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT, 582 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
583 }; 583 };
584 584
585 /* TX_MFF_CTRL1 16 bit Transmit MAC F 585 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
586 enum { 586 enum {
587 MFF_CLR_PERR = 1<<15, /* Clear Pari 587 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
588 588
589 MFF_ENA_PKT_REC = 1<<13, /* Enable Pa 589 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
590 MFF_DIS_PKT_REC = 1<<12, /* Disable Pa 590 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
591 591
592 MFF_ENA_W4E = 1<<7, /* Enable Wai 592 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
593 MFF_DIS_W4E = 1<<6, /* Disable Wai 593 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
594 594
595 MFF_ENA_LOOPB = 1<<3, /* Enable Loo 595 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
596 MFF_DIS_LOOPB = 1<<2, /* Disable Loo 596 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
597 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC 597 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
598 MFF_SET_MAC_RST = 1<<0, /* Set XMAC 598 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
599 599
600 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | ( 600 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
601 }; 601 };
602 602
603 603
604 /* RX_MFF_TST2 8 bit Receiv 604 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
605 /* TX_MFF_TST2 8 bit Transm 605 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
606 enum { 606 enum {
607 MFF_WSP_T_ON = 1<<6, /* Tx: Write S 607 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
608 MFF_WSP_T_OFF = 1<<5, /* Tx: Write S 608 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
609 MFF_WSP_INC = 1<<4, /* Tx: Write S 609 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
610 MFF_PC_DEC = 1<<3, /* Packet Coun 610 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
611 MFF_PC_T_ON = 1<<2, /* Packet Coun 611 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
612 MFF_PC_T_OFF = 1<<1, /* Packet Coun 612 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
613 MFF_PC_INC = 1<<0, /* Packet Coun 613 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
614 }; 614 };
615 615
616 /* RX_MFF_TST1 8 bit Receiv 616 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
617 /* TX_MFF_TST1 8 bit Transm 617 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
618 enum { 618 enum {
619 MFF_WP_T_ON = 1<<6, /* Write Point 619 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
620 MFF_WP_T_OFF = 1<<5, /* Write Point 620 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
621 MFF_WP_INC = 1<<4, /* Write Point 621 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
622 622
623 MFF_RP_T_ON = 1<<2, /* Read Pointe 623 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
624 MFF_RP_T_OFF = 1<<1, /* Read Pointe 624 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
625 MFF_RP_DEC = 1<<0, /* Read Pointe 625 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
626 }; 626 };
627 627
628 /* RX_MFF_CTRL2 8 bit Receive MAC FI 628 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
629 /* TX_MFF_CTRL2 8 bit Transmit MAC F 629 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
630 enum { 630 enum {
631 MFF_ENA_OP_MD = 1<<3, /* Enable Ope 631 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
632 MFF_DIS_OP_MD = 1<<2, /* Disable Ope 632 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
633 MFF_RST_CLR = 1<<1, /* Clear MAC F 633 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
634 MFF_RST_SET = 1<<0, /* Set MAC F 634 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
635 }; 635 };
636 636
637 637
638 /* Link LED Counter Registers (GENESIS on 638 /* Link LED Counter Registers (GENESIS only) */
639 639
640 /* RX_LED_CTRL 8 bit Receiv 640 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
641 /* TX_LED_CTRL 8 bit Transm 641 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
642 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt 642 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
643 enum { 643 enum {
644 LED_START = 1<<2, /* Start Timer 644 LED_START = 1<<2, /* Start Timer */
645 LED_STOP = 1<<1, /* Stop Timer 645 LED_STOP = 1<<1, /* Stop Timer */
646 LED_STATE = 1<<0, /* Rx/Tx: LED 646 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
647 }; 647 };
648 648
649 /* RX_LED_TST 8 bit Receiv 649 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
650 /* TX_LED_TST 8 bit Transm 650 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
651 /* LNK_SYNC_TST 8 bit Link Sync Cnt 651 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
652 enum { 652 enum {
653 LED_T_ON = 1<<2, /* LED Counter 653 LED_T_ON = 1<<2, /* LED Counter Test mode On */
654 LED_T_OFF = 1<<1, /* LED Counter 654 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
655 LED_T_STEP = 1<<0, /* LED Counter 655 LED_T_STEP = 1<<0, /* LED Counter Step */
656 }; 656 };
657 657
658 /* LNK_LED_REG 8 bit Link L 658 /* LNK_LED_REG 8 bit Link LED Register */
659 enum { 659 enum {
660 LED_BLK_ON = 1<<5, /* Link LED Bl 660 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
661 LED_BLK_OFF = 1<<4, /* Link LED Bl 661 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
662 LED_SYNC_ON = 1<<3, /* Use Sync Wi 662 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
663 LED_SYNC_OFF = 1<<2, /* Disable Syn 663 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
664 LED_ON = 1<<1, /* switch LED on */ 664 LED_ON = 1<<1, /* switch LED on */
665 LED_OFF = 1<<0, /* switch LED off */ 665 LED_OFF = 1<<0, /* switch LED off */
666 }; 666 };
667 667
668 /* Receive GMAC FIFO (YUKON) */ 668 /* Receive GMAC FIFO (YUKON) */
669 enum { 669 enum {
670 RX_GMF_EA = 0x0c40,/* 32 bit 670 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
671 RX_GMF_AF_THR = 0x0c44,/* 32 bit 671 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
672 RX_GMF_CTRL_T = 0x0c48,/* 32 bit 672 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
673 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit 673 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
674 RX_GMF_FL_THR = 0x0c50,/* 32 bit 674 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
675 RX_GMF_WP = 0x0c60,/* 32 bit 675 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
676 RX_GMF_WLEV = 0x0c68,/* 32 bit 676 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
677 RX_GMF_RP = 0x0c70,/* 32 bit 677 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
678 RX_GMF_RLEV = 0x0c78,/* 32 bit 678 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
679 }; 679 };
680 680
681 681
682 /* TXA_TEST 8 bit Tx Arb 682 /* TXA_TEST 8 bit Tx Arbiter Test Register */
683 enum { 683 enum {
684 TXA_INT_T_ON = 1<<5, /* Tx Arb Inte 684 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
685 TXA_INT_T_OFF = 1<<4, /* Tx Arb Inte 685 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
686 TXA_INT_T_STEP = 1<<3, /* Tx Arb Inte 686 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
687 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limi 687 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
688 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limi 688 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
689 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limi 689 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
690 }; 690 };
691 691
692 /* TXA_STAT 8 bit Tx Arb 692 /* TXA_STAT 8 bit Tx Arbiter Status Register */
693 enum { 693 enum {
694 TXA_PRIO_XS = 1<<0, /* sync queue 694 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
695 }; 695 };
696 696
697 697
698 /* Q_BC 32 bit Curren 698 /* Q_BC 32 bit Current Byte Counter */
699 699
700 /* BMU Control Status Registers */ 700 /* BMU Control Status Registers */
701 /* B0_R1_CSR 32 bit BMU Ct 701 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
702 /* B0_R2_CSR 32 bit BMU Ct 702 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
703 /* B0_XA1_CSR 32 bit BMU Ct 703 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
704 /* B0_XS1_CSR 32 bit BMU Ct 704 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
705 /* B0_XA2_CSR 32 bit BMU Ct 705 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
706 /* B0_XS2_CSR 32 bit BMU Ct 706 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
707 /* Q_CSR 32 bit BMU Co 707 /* Q_CSR 32 bit BMU Control/Status Register */
708 708
709 enum { 709 enum {
710 CSR_SV_IDLE = 1<<24, /* BMU 710 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
711 711
712 CSR_DESC_CLR = 1<<21, /* Cle 712 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
713 CSR_DESC_SET = 1<<20, /* Set 713 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
714 CSR_FIFO_CLR = 1<<19, /* Cle 714 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
715 CSR_FIFO_SET = 1<<18, /* Set 715 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
716 CSR_HPI_RUN = 1<<17, /* Rel 716 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
717 CSR_HPI_RST = 1<<16, /* Res 717 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
718 CSR_SV_RUN = 1<<15, /* Rel 718 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
719 CSR_SV_RST = 1<<14, /* Res 719 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
720 CSR_DREAD_RUN = 1<<13, /* Rel 720 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
721 CSR_DREAD_RST = 1<<12, /* Res 721 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
722 CSR_DWRITE_RUN = 1<<11, /* Rel 722 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
723 CSR_DWRITE_RST = 1<<10, /* Res 723 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
724 CSR_TRANS_RUN = 1<<9, /* Rel 724 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
725 CSR_TRANS_RST = 1<<8, /* Res 725 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
726 CSR_ENA_POL = 1<<7, /* Ena 726 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
727 CSR_DIS_POL = 1<<6, /* Dis 727 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
728 CSR_STOP = 1<<5, /* Sto 728 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
729 CSR_START = 1<<4, /* Sta 729 CSR_START = 1<<4, /* Start Rx/Tx Queue */
730 CSR_IRQ_CL_P = 1<<3, /* (Rx 730 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
731 CSR_IRQ_CL_B = 1<<2, /* Cle 731 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
732 CSR_IRQ_CL_F = 1<<1, /* Cle 732 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
733 CSR_IRQ_CL_C = 1<<0, /* Cle 733 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
734 }; 734 };
735 735
736 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FI 736 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
737 CSR_SV_RST | CSR_DREAD 737 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
738 CSR_TRANS_RST) 738 CSR_TRANS_RST)
739 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FI 739 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
740 CSR_SV_RUN | CSR_DREAD 740 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
741 CSR_TRANS_RUN) 741 CSR_TRANS_RUN)
742 742
743 /* Q_F 32 bit 743 /* Q_F 32 bit Flag Register */
744 enum { 744 enum {
745 F_ALM_FULL = 1<<27, /* Rx 745 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
746 F_EMPTY = 1<<27, /* Tx 746 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
747 F_FIFO_EOF = 1<<26, /* Tag 747 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
748 F_WM_REACHED = 1<<25, /* Wat 748 F_WM_REACHED = 1<<25, /* Watermark reached */
749 749
750 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 750 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
751 F_WATER_MARK = 0x0007ffL, /* Bit 751 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
752 }; 752 };
753 753
754 /* RAM Buffer Register Offsets, use RB_ADDR(Qu 754 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
755 /* RB_START 32 bit RAM Bu 755 /* RB_START 32 bit RAM Buffer Start Address */
756 /* RB_END 32 bit RAM Bu 756 /* RB_END 32 bit RAM Buffer End Address */
757 /* RB_WP 32 bit RAM Bu 757 /* RB_WP 32 bit RAM Buffer Write Pointer */
758 /* RB_RP 32 bit RAM Bu 758 /* RB_RP 32 bit RAM Buffer Read Pointer */
759 /* RB_RX_UTPP 32 bit Rx Upp 759 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
760 /* RB_RX_LTPP 32 bit Rx Low 760 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
761 /* RB_RX_UTHP 32 bit Rx Upp 761 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
762 /* RB_RX_LTHP 32 bit Rx Low 762 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
763 /* RB_PC 32 bit RAM Bu 763 /* RB_PC 32 bit RAM Buffer Packet Counter */
764 /* RB_LEV 32 bit RAM Bu 764 /* RB_LEV 32 bit RAM Buffer Level Register */
765 765
766 #define RB_MSK 0x0007ffff /* Bit 18.. 0: 766 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
767 /* RB_TST2 8 bit RAM Bu 767 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
768 /* RB_TST1 8 bit RAM Bu 768 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
769 769
770 /* RB_CTRL 8 bit RAM Bu 770 /* RB_CTRL 8 bit RAM Buffer Control Register */
771 enum { 771 enum {
772 RB_ENA_STFWD = 1<<5, /* Enable Sto 772 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
773 RB_DIS_STFWD = 1<<4, /* Disable Sto 773 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
774 RB_ENA_OP_MD = 1<<3, /* Enable Ope 774 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
775 RB_DIS_OP_MD = 1<<2, /* Disable Ope 775 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
776 RB_RST_CLR = 1<<1, /* Clear RAM B 776 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
777 RB_RST_SET = 1<<0, /* Set RAM B 777 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
778 }; 778 };
779 779
780 /* Transmit MAC FIFO and Transmit LED Register 780 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
781 enum { 781 enum {
782 TX_MFF_EA = 0x0d00,/* 32 bit 782 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
783 TX_MFF_WP = 0x0d04,/* 32 bit 783 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
784 TX_MFF_WSP = 0x0d08,/* 32 bit 784 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
785 TX_MFF_RP = 0x0d0c,/* 32 bit 785 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
786 TX_MFF_PC = 0x0d10,/* 32 bit 786 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
787 TX_MFF_LEV = 0x0d14,/* 32 bit 787 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
788 TX_MFF_CTRL1 = 0x0d18,/* 16 bit 788 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
789 TX_MFF_WAF = 0x0d1a,/* 8 bit 789 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
790 790
791 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit 791 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
792 TX_MFF_TST1 = 0x0d1d,/* 8 bit 792 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
793 TX_MFF_TST2 = 0x0d1e,/* 8 bit 793 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
794 794
795 TX_LED_INI = 0x0d20,/* 32 bit 795 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
796 TX_LED_VAL = 0x0d24,/* 32 bit 796 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
797 TX_LED_CTRL = 0x0d28,/* 8 bit 797 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
798 TX_LED_TST = 0x0d29,/* 8 bit 798 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
799 }; 799 };
800 800
801 /* Counter and Timer constants, for a host clo 801 /* Counter and Timer constants, for a host clock of 62.5 MHz */
802 #define SK_XMIT_DUR 0x002faf08UL 802 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
803 #define SK_BLK_DUR 0x01dcd650UL 803 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
804 804
805 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 805 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
806 806
807 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 807 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
808 /* 215 808 /* 215 ms at 78.12 MHz */
809 809
810 #define SK_FACT_62 100 /* is 810 #define SK_FACT_62 100 /* is given in percent */
811 #define SK_FACT_53 85 /* on 811 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
812 #define SK_FACT_78 125 /* on 812 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
813 813
814 814
815 /* Transmit GMAC FIFO (YUKON only) */ 815 /* Transmit GMAC FIFO (YUKON only) */
816 enum { 816 enum {
817 TX_GMF_EA = 0x0d40,/* 32 bit 817 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
818 TX_GMF_AE_THR = 0x0d44,/* 32 bit 818 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
819 TX_GMF_CTRL_T = 0x0d48,/* 32 bit 819 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
820 820
821 TX_GMF_WP = 0x0d60,/* 32 bit 821 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
822 TX_GMF_WSP = 0x0d64,/* 32 bit 822 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
823 TX_GMF_WLEV = 0x0d68,/* 32 bit 823 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
824 824
825 TX_GMF_RP = 0x0d70,/* 32 bit 825 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
826 TX_GMF_RSTP = 0x0d74,/* 32 bit 826 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
827 TX_GMF_RLEV = 0x0d78,/* 32 bit 827 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
828 828
829 /* Descriptor Poll Timer Registers */ 829 /* Descriptor Poll Timer Registers */
830 B28_DPT_INI = 0x0e00,/* 24 bit 830 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
831 B28_DPT_VAL = 0x0e04,/* 24 bit 831 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
832 B28_DPT_CTRL = 0x0e08,/* 8 bit 832 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
833 833
834 B28_DPT_TST = 0x0e0a,/* 8 bit 834 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
835 835
836 /* Time Stamp Timer Registers (YUKON o 836 /* Time Stamp Timer Registers (YUKON only) */
837 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit 837 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
838 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit 838 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
839 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit 839 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
840 }; 840 };
841 841
842 842
843 enum { 843 enum {
844 LINKLED_OFF = 0x01, 844 LINKLED_OFF = 0x01,
845 LINKLED_ON = 0x02, 845 LINKLED_ON = 0x02,
846 LINKLED_LINKSYNC_OFF = 0x04, 846 LINKLED_LINKSYNC_OFF = 0x04,
847 LINKLED_LINKSYNC_ON = 0x08, 847 LINKLED_LINKSYNC_ON = 0x08,
848 LINKLED_BLINK_OFF = 0x10, 848 LINKLED_BLINK_OFF = 0x10,
849 LINKLED_BLINK_ON = 0x20, 849 LINKLED_BLINK_ON = 0x20,
850 }; 850 };
851 851
852 /* GMAC and GPHY Control Registers (YUKON only 852 /* GMAC and GPHY Control Registers (YUKON only) */
853 enum { 853 enum {
854 GMAC_CTRL = 0x0f00,/* 32 bit 854 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
855 GPHY_CTRL = 0x0f04,/* 32 bit 855 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
856 GMAC_IRQ_SRC = 0x0f08,/* 8 bit 856 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
857 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit 857 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
858 GMAC_LINK_CTRL = 0x0f10,/* 16 bit 858 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
859 859
860 /* Wake-up Frame Pattern Match Control Registe 860 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
861 861
862 WOL_REG_OFFS = 0x20,/* HW-Bug: Addr 862 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
863 863
864 WOL_CTRL_STAT = 0x0f20,/* 16 bit 864 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
865 WOL_MATCH_CTL = 0x0f22,/* 8 bit 865 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
866 WOL_MATCH_RES = 0x0f23,/* 8 bit 866 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
867 WOL_MAC_ADDR = 0x0f24,/* 32 bit 867 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
868 WOL_PATT_RPTR = 0x0f2c,/* 8 bit 868 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
869 869
870 /* WOL Pattern Length Registers (YUKON only) * 870 /* WOL Pattern Length Registers (YUKON only) */
871 871
872 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit 872 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
873 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit 873 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
874 874
875 /* WOL Pattern Counter Registers (YUKON only) 875 /* WOL Pattern Counter Registers (YUKON only) */
876 876
877 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit 877 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
878 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit 878 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
879 }; 879 };
880 #define WOL_REGS(port, x) (x + (port)*0x 880 #define WOL_REGS(port, x) (x + (port)*0x80)
881 881
882 enum { 882 enum {
883 WOL_PATT_RAM_1 = 0x1000,/* WOL Patte 883 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
884 WOL_PATT_RAM_2 = 0x1400,/* WOL Patte 884 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
885 }; 885 };
886 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_ 886 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
887 887
888 enum { 888 enum {
889 BASE_XMAC_1 = 0x2000,/* XMAC 1 reg 889 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
890 BASE_GMAC_1 = 0x2800,/* GMAC 1 reg 890 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
891 BASE_XMAC_2 = 0x3000,/* XMAC 2 reg 891 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
892 BASE_GMAC_2 = 0x3800,/* GMAC 2 reg 892 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
893 }; 893 };
894 894
895 /* 895 /*
896 * Receive Frame Status Encoding 896 * Receive Frame Status Encoding
897 */ 897 */
898 enum { 898 enum {
899 XMR_FS_LEN = 0x3fff<<18, /* Bit 899 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
900 XMR_FS_LEN_SHIFT = 18, 900 XMR_FS_LEN_SHIFT = 18,
901 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: 901 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
902 XMR_FS_1_VLAN = 1<<16, /* Bit 16: 902 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
903 XMR_FS_BC = 1<<15, /* Bit 15: 903 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
904 XMR_FS_MC = 1<<14, /* Bit 14: 904 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
905 XMR_FS_UC = 1<<13, /* Bit 13: 905 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
906 906
907 XMR_FS_BURST = 1<<11, /* Bit 11: 907 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
908 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: 908 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
909 XMR_FS_802_3 = 1<<9, /* Bit 9: 909 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
910 XMR_FS_COL_ERR = 1<<8, /* Bit 8: 910 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
911 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: 911 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
912 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: 912 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
913 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: 913 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
914 XMR_FS_RUNT = 1<<4, /* Bit 4: 914 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
915 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: 915 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
916 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: 916 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
917 XMR_FS_ERR = 1<<1, /* Bit 1: 917 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
918 XMR_FS_MCTRL = 1<<0, /* Bit 0: 918 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
919 919
920 /* 920 /*
921 * XMR_FS_ERR will be set if 921 * XMR_FS_ERR will be set if
922 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS 922 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
923 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR 923 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
924 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR w 924 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
925 * XMR_FS_ERR unless the corresponding bit in 925 * XMR_FS_ERR unless the corresponding bit in the Receive Command
926 * Register is set. 926 * Register is set.
927 */ 927 */
928 }; 928 };
929 929
930 /* 930 /*
931 ,* XMAC-PHY Registers, indirect addressed over 931 ,* XMAC-PHY Registers, indirect addressed over the XMAC
932 */ 932 */
933 enum { 933 enum {
934 PHY_XMAC_CTRL = 0x00,/* 16 b 934 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
935 PHY_XMAC_STAT = 0x01,/* 16 b 935 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
936 PHY_XMAC_ID0 = 0x02,/* 16 b 936 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
937 PHY_XMAC_ID1 = 0x03,/* 16 b 937 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
938 PHY_XMAC_AUNE_ADV = 0x04,/* 16 b 938 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
939 PHY_XMAC_AUNE_LP = 0x05,/* 16 b 939 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
940 PHY_XMAC_AUNE_EXP = 0x06,/* 16 b 940 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
941 PHY_XMAC_NEPG = 0x07,/* 16 b 941 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
942 PHY_XMAC_NEPG_LP = 0x08,/* 16 b 942 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
943 943
944 PHY_XMAC_EXT_STAT = 0x0f,/* 16 b 944 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
945 PHY_XMAC_RES_ABI = 0x10,/* 16 b 945 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
946 }; 946 };
947 /* 947 /*
948 * Broadcom-PHY Registers, indirect addressed 948 * Broadcom-PHY Registers, indirect addressed over XMAC
949 */ 949 */
950 enum { 950 enum {
951 PHY_BCOM_CTRL = 0x00,/* 16 b 951 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
952 PHY_BCOM_STAT = 0x01,/* 16 b 952 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
953 PHY_BCOM_ID0 = 0x02,/* 16 b 953 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
954 PHY_BCOM_ID1 = 0x03,/* 16 b 954 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
955 PHY_BCOM_AUNE_ADV = 0x04,/* 16 b 955 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
956 PHY_BCOM_AUNE_LP = 0x05,/* 16 b 956 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
957 PHY_BCOM_AUNE_EXP = 0x06,/* 16 b 957 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
958 PHY_BCOM_NEPG = 0x07,/* 16 b 958 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
959 PHY_BCOM_NEPG_LP = 0x08,/* 16 b 959 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
960 /* Broadcom-specific registers */ 960 /* Broadcom-specific registers */
961 PHY_BCOM_1000T_CTRL = 0x09,/* 16 b 961 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
962 PHY_BCOM_1000T_STAT = 0x0a,/* 16 b 962 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
963 PHY_BCOM_EXT_STAT = 0x0f,/* 16 b 963 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
964 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 b 964 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
965 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 b 965 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
966 PHY_BCOM_RE_CTR = 0x12,/* 16 b 966 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
967 PHY_BCOM_FC_CTR = 0x13,/* 16 b 967 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
968 PHY_BCOM_RNO_CTR = 0x14,/* 16 b 968 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
969 969
970 PHY_BCOM_AUX_CTRL = 0x18,/* 16 b 970 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
971 PHY_BCOM_AUX_STAT = 0x19,/* 16 b 971 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
972 PHY_BCOM_INT_STAT = 0x1a,/* 16 b 972 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
973 PHY_BCOM_INT_MASK = 0x1b,/* 16 b 973 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
974 }; 974 };
975 975
976 /* 976 /*
977 * Marvel-PHY Registers, indirect addressed ov 977 * Marvel-PHY Registers, indirect addressed over GMAC
978 */ 978 */
979 enum { 979 enum {
980 PHY_MARV_CTRL = 0x00,/* 16 b 980 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
981 PHY_MARV_STAT = 0x01,/* 16 b 981 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
982 PHY_MARV_ID0 = 0x02,/* 16 b 982 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
983 PHY_MARV_ID1 = 0x03,/* 16 b 983 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
984 PHY_MARV_AUNE_ADV = 0x04,/* 16 b 984 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
985 PHY_MARV_AUNE_LP = 0x05,/* 16 b 985 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
986 PHY_MARV_AUNE_EXP = 0x06,/* 16 b 986 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
987 PHY_MARV_NEPG = 0x07,/* 16 b 987 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
988 PHY_MARV_NEPG_LP = 0x08,/* 16 b 988 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
989 /* Marvel-specific registers */ 989 /* Marvel-specific registers */
990 PHY_MARV_1000T_CTRL = 0x09,/* 16 b 990 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
991 PHY_MARV_1000T_STAT = 0x0a,/* 16 b 991 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
992 PHY_MARV_EXT_STAT = 0x0f,/* 16 b 992 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
993 PHY_MARV_PHY_CTRL = 0x10,/* 16 b 993 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
994 PHY_MARV_PHY_STAT = 0x11,/* 16 b 994 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
995 PHY_MARV_INT_MASK = 0x12,/* 16 b 995 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
996 PHY_MARV_INT_STAT = 0x13,/* 16 b 996 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
997 PHY_MARV_EXT_CTRL = 0x14,/* 16 b 997 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
998 PHY_MARV_RXE_CNT = 0x15,/* 16 b 998 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
999 PHY_MARV_EXT_ADR = 0x16,/* 16 b 999 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1000 PHY_MARV_PORT_IRQ = 0x17,/* 16 1000 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1001 PHY_MARV_LED_CTRL = 0x18,/* 16 1001 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1002 PHY_MARV_LED_OVER = 0x19,/* 16 1002 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1003 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 1003 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1004 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 1004 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1005 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 1005 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1006 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 1006 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1007 PHY_MARV_PAGE_DATA = 0x1e,/* 16 1007 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1008 1008
1009 /* for 10/100 Fast Ethernet PHY (88E3082 only 1009 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1010 PHY_MARV_FE_LED_PAR = 0x16,/* 16 1010 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1011 PHY_MARV_FE_LED_SER = 0x17,/* 16 1011 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1012 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 1012 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1013 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 1013 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1014 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 1014 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1015 }; 1015 };
1016 1016
1017 enum { 1017 enum {
1018 PHY_CT_RESET = 1<<15, /* Bit 15: ( 1018 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1019 PHY_CT_LOOP = 1<<14, /* Bit 14: 1019 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1020 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: 1020 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1021 PHY_CT_ANE = 1<<12, /* Bit 12: 1021 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1022 PHY_CT_PDOWN = 1<<11, /* Bit 11: 1022 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1023 PHY_CT_ISOL = 1<<10, /* Bit 10: 1023 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1024 PHY_CT_RE_CFG = 1<<9, /* Bit 9: 1024 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1025 PHY_CT_DUP_MD = 1<<8, /* Bit 8: 1025 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1026 PHY_CT_COL_TST = 1<<7, /* Bit 7: 1026 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1027 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: 1027 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1028 }; 1028 };
1029 1029
1030 enum { 1030 enum {
1031 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* 1031 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1032 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* 1032 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1033 PHY_CT_SP10 = 0, /* 1033 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1034 }; 1034 };
1035 1035
1036 enum { 1036 enum {
1037 PHY_ST_EXT_ST = 1<<8, /* Bit 8: 1037 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1038 1038
1039 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: 1039 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1040 PHY_ST_AN_OVER = 1<<5, /* Bit 5: 1040 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1041 PHY_ST_REM_FLT = 1<<4, /* Bit 4: 1041 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1042 PHY_ST_AN_CAP = 1<<3, /* Bit 3: 1042 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1043 PHY_ST_LSYNC = 1<<2, /* Bit 2: 1043 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1044 PHY_ST_JAB_DET = 1<<1, /* Bit 1: 1044 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1045 PHY_ST_EXT_REG = 1<<0, /* Bit 0: 1045 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1046 }; 1046 };
1047 1047
1048 enum { 1048 enum {
1049 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15 1049 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1050 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9. 1050 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1051 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: 1051 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1052 }; 1052 };
1053 1053
1054 /* different Broadcom PHY Ids */ 1054 /* different Broadcom PHY Ids */
1055 enum { 1055 enum {
1056 PHY_BCOM_ID1_A1 = 0x6041, 1056 PHY_BCOM_ID1_A1 = 0x6041,
1057 PHY_BCOM_ID1_B2 = 0x6043, 1057 PHY_BCOM_ID1_B2 = 0x6043,
1058 PHY_BCOM_ID1_C0 = 0x6044, 1058 PHY_BCOM_ID1_C0 = 0x6044,
1059 PHY_BCOM_ID1_C5 = 0x6047, 1059 PHY_BCOM_ID1_C5 = 0x6047,
1060 }; 1060 };
1061 1061
1062 /* different Marvell PHY Ids */ 1062 /* different Marvell PHY Ids */
1063 enum { 1063 enum {
1064 PHY_MARV_ID0_VAL= 0x0141, /* Marvell 1064 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1065 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (P 1065 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1066 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Pl 1066 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1067 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC 1067 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1068 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 1068 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1069 }; 1069 };
1070 1070
1071 /* Advertisement register bits */ 1071 /* Advertisement register bits */
1072 enum { 1072 enum {
1073 PHY_AN_NXT_PG = 1<<15, /* Bit 15: 1073 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1074 PHY_AN_ACK = 1<<14, /* Bit 14: 1074 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1075 PHY_AN_RF = 1<<13, /* Bit 13: 1075 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1076 1076
1077 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: 1077 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1078 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: 1078 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1079 PHY_AN_100BASE4 = 1<<9, /* Bit 9: 1079 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1080 PHY_AN_100FULL = 1<<8, /* Bit 8: 1080 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1081 PHY_AN_100HALF = 1<<7, /* Bit 7: 1081 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1082 PHY_AN_10FULL = 1<<6, /* Bit 6: 1082 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1083 PHY_AN_10HALF = 1<<5, /* Bit 5: 1083 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1084 PHY_AN_CSMA = 1<<0, /* Bit 0: 1084 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1085 PHY_AN_SEL = 0x1f, /* Bit 4..0: 1085 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1086 PHY_AN_FULL = PHY_AN_100FULL | PH 1086 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1087 PHY_AN_ALL = PHY_AN_10HALF | PHY 1087 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1088 PHY_AN_100HALF | PH 1088 PHY_AN_100HALF | PHY_AN_100FULL,
1089 }; 1089 };
1090 1090
1091 /* Xmac Specific */ 1091 /* Xmac Specific */
1092 enum { 1092 enum {
1093 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: 1093 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1094 PHY_X_AN_ACK = 1<<14, /* Bit 14: 1094 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1095 PHY_X_AN_RFB = 3<<12,/* Bit 13..12 1095 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1096 1096
1097 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: 1097 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1098 PHY_X_AN_HD = 1<<6, /* Bit 6: 1098 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1099 PHY_X_AN_FD = 1<<5, /* Bit 5: 1099 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1100 }; 1100 };
1101 1101
1102 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PA 1102 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1103 enum { 1103 enum {
1104 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: 1104 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1105 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: 1105 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1106 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: 1106 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1107 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: 1107 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1108 }; 1108 };
1109 1109
1110 1110
1111 /***** PHY_XMAC_EXT_STAT 16 bit r/w 1111 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1112 enum { 1112 enum {
1113 PHY_X_EX_FD = 1<<15, /* Bit 15: 1113 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1114 PHY_X_EX_HD = 1<<14, /* Bit 14: 1114 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1115 }; 1115 };
1116 1116
1117 /***** PHY_XMAC_RES_ABI 16 bit r/o 1117 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1118 enum { 1118 enum {
1119 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: 1119 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1120 PHY_X_RS_HD = 1<<6, /* Bit 6: 1120 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1121 PHY_X_RS_FD = 1<<5, /* Bit 5: 1121 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1122 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: 1122 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1123 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: 1123 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1124 }; 1124 };
1125 1125
1126 /* Remote Fault Bits (PHY_X_AN_RFB) encoding 1126 /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
1127 enum { 1127 enum {
1128 X_RFB_OK = 0<<12,/* Bit 13..12 1128 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1129 X_RFB_LF = 1<<12,/* Bit 13..12 1129 X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
1130 X_RFB_OFF = 2<<12,/* Bit 13..12 1130 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1131 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 1131 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1132 }; 1132 };
1133 1133
1134 /* Broadcom-Specific */ 1134 /* Broadcom-Specific */
1135 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1135 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1136 enum { 1136 enum {
1137 PHY_B_1000C_TEST = 7<<13,/* Bi 1137 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1138 PHY_B_1000C_MSE = 1<<12, /* Bit 12: 1138 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1139 PHY_B_1000C_MSC = 1<<11, /* Bit 11: 1139 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1140 PHY_B_1000C_RD = 1<<10, /* Bit 10: 1140 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1141 PHY_B_1000C_AFD = 1<<9, /* Bit 9: 1141 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1142 PHY_B_1000C_AHD = 1<<8, /* Bit 8: 1142 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1143 }; 1143 };
1144 1144
1145 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1145 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1146 /***** PHY_MARV_1000T_STAT 16 bit r/o 1146 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1147 enum { 1147 enum {
1148 PHY_B_1000S_MSF = 1<<15, /* Bit 15: 1148 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1149 PHY_B_1000S_MSR = 1<<14, /* Bit 14: 1149 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1150 PHY_B_1000S_LRS = 1<<13, /* Bit 13: 1150 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1151 PHY_B_1000S_RRS = 1<<12, /* Bit 12: 1151 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1152 PHY_B_1000S_LP_FD = 1<<11, /* B 1152 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1153 PHY_B_1000S_LP_HD = 1<<10, /* B 1153 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1154 1154 /* Bit 9..8: reserved */
1155 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: 1155 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1156 }; 1156 };
1157 1157
1158 /***** PHY_BCOM_EXT_STAT 16 bit r/o 1158 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1159 enum { 1159 enum {
1160 PHY_B_ES_X_FD_CAP = 1<<15, /* B 1160 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1161 PHY_B_ES_X_HD_CAP = 1<<14, /* B 1161 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1162 PHY_B_ES_T_FD_CAP = 1<<13, /* B 1162 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1163 PHY_B_ES_T_HD_CAP = 1<<12, /* B 1163 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1164 }; 1164 };
1165 1165
1166 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w 1166 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1167 enum { 1167 enum {
1168 PHY_B_PEC_MAC_PHY = 1<<15, /* B 1168 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1169 PHY_B_PEC_DIS_CROSS = 1<<14, /* B 1169 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1170 PHY_B_PEC_TX_DIS = 1<<13, /* B 1170 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1171 PHY_B_PEC_INT_DIS = 1<<12, /* B 1171 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1172 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: 1172 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1173 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: 1173 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1174 PHY_B_PEC_BY_SCR = 1<<9, /* Bi 1174 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1175 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bi 1175 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1176 PHY_B_PEC_BY_RXA = 1<<7, /* Bi 1176 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1177 PHY_B_PEC_RES_SCR = 1<<6, /* Bi 1177 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1178 PHY_B_PEC_EN_LTR = 1<<5, /* Bi 1178 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1179 PHY_B_PEC_LED_ON = 1<<4, /* Bi 1179 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1180 PHY_B_PEC_LED_OFF = 1<<3, /* Bi 1180 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1181 PHY_B_PEC_EX_IPG = 1<<2, /* Bi 1181 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1182 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: 1182 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1183 PHY_B_PEC_HIGH_LA = 1<<0, /* Bi 1183 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1184 }; 1184 };
1185 1185
1186 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o 1186 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1187 enum { 1187 enum {
1188 PHY_B_PES_CROSS_STAT = 1<<13, /* B 1188 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1189 PHY_B_PES_INT_STAT = 1<<12, /* B 1189 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1190 PHY_B_PES_RRS = 1<<11, /* Bit 11: 1190 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1191 PHY_B_PES_LRS = 1<<10, /* Bit 10: 1191 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1192 PHY_B_PES_LOCKED = 1<<9, /* Bi 1192 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1193 PHY_B_PES_LS = 1<<8, /* Bit 8: 1193 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1194 PHY_B_PES_RF = 1<<7, /* Bit 7: 1194 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1195 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: 1195 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1196 PHY_B_PES_BAD_SSD = 1<<5, /* Bi 1196 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1197 PHY_B_PES_BAD_ESD = 1<<4, /* Bi 1197 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1198 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: 1198 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1199 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: 1199 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1200 PHY_B_PES_LOCK_ER = 1<<1, /* Bi 1200 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1201 PHY_B_PES_MLT3_ER = 1<<0, /* Bi 1201 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1202 }; 1202 };
1203 1203
1204 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto- 1204 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1205 /* PHY_BCOM_AUNE_LP 16 bit r/o Link 1205 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1206 enum { 1206 enum {
1207 PHY_B_AN_RF = 1<<13, /* Bit 13: 1207 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1208 1208
1209 PHY_B_AN_ASP = 1<<11, /* Bit 11: 1209 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1210 PHY_B_AN_PC = 1<<10, /* Bit 10: 1210 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1211 }; 1211 };
1212 1212
1213 1213
1214 /***** PHY_BCOM_FC_CTR 16 bit r/w 1214 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1215 enum { 1215 enum {
1216 PHY_B_FC_CTR = 0xff, /* Bit 7..0: 1216 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1217 1217
1218 /***** PHY_BCOM_RNO_CTR 16 bit r/w 1218 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1219 PHY_B_RC_LOC_MSK = 0xff00, /* 1219 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1220 PHY_B_RC_REM_MSK = 0x00ff, /* 1220 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1221 1221
1222 /***** PHY_BCOM_AUX_CTRL 16 bit r/w 1222 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1223 PHY_B_AC_L_SQE = 1<<15, /* B 1223 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1224 PHY_B_AC_LONG_PACK = 1<<14, /* B 1224 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1225 PHY_B_AC_ER_CTRL = 3<<12,/* Bi 1225 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1226 1226 /* Bit 11: reserved */
1227 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: 1227 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1228 1228 /* Bit 9.. 8: reserved */
1229 PHY_B_AC_DIS_PRF = 1<<7, /* Bi 1229 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1230 1230 /* Bit 6: reserved */
1231 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: 1231 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1232 1232 /* Bit 4: reserved */
1233 PHY_B_AC_DIAG = 1<<3, /* Bit 3: 1233 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1234 }; 1234 };
1235 1235
1236 /***** PHY_BCOM_AUX_STAT 16 bit r/o 1236 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1237 enum { 1237 enum {
1238 PHY_B_AS_AN_C = 1<<15, /* Bit 15: 1238 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1239 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: 1239 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1240 PHY_B_AS_ANACK_D = 1<<13, /* B 1240 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1241 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: 1241 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1242 PHY_B_AS_NPW = 1<<11, /* Bit 11: 1242 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1243 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 1243 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1244 PHY_B_AS_PDF = 1<<7, /* Bit 7: 1244 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1245 PHY_B_AS_RF = 1<<6, /* Bit 6: 1245 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1246 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: 1246 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1247 PHY_B_AS_LP_ANAB = 1<<4, /* Bi 1247 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1248 PHY_B_AS_LP_NPAB = 1<<3, /* Bi 1248 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1249 PHY_B_AS_LS = 1<<2, /* Bit 2: 1249 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1250 PHY_B_AS_PRR = 1<<1, /* Bit 1: 1250 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1251 PHY_B_AS_PRT = 1<<0, /* Bit 0: 1251 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1252 }; 1252 };
1253 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR 1253 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1254 1254
1255 /***** PHY_BCOM_INT_STAT 16 bit r/o 1255 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1256 /***** PHY_BCOM_INT_MASK 16 bit r/w 1256 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1257 enum { 1257 enum {
1258 PHY_B_IS_PSE = 1<<14, /* Bit 14: 1258 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1259 PHY_B_IS_MDXI_SC = 1<<13, /* B 1259 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1260 PHY_B_IS_HCT = 1<<12, /* Bit 12: 1260 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1261 PHY_B_IS_LCT = 1<<11, /* Bit 11: 1261 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1262 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: 1262 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1263 PHY_B_IS_NO_HDCL = 1<<9, /* Bi 1263 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1264 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: 1264 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1265 PHY_B_IS_NEG_USHDC = 1<<7, /* Bi 1265 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1266 PHY_B_IS_SCR_S_ER = 1<<6, /* Bi 1266 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1267 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bi 1267 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1268 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bi 1268 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1269 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bi 1269 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1270 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bi 1270 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1271 PHY_B_IS_LST_CHANGE = 1<<1, /* Bi 1271 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1272 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: 1272 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1273 }; 1273 };
1274 #define PHY_B_DEF_MSK \ 1274 #define PHY_B_DEF_MSK \
1275 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PH 1275 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1276 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LS 1276 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1277 1277
1278 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) 1278 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1279 enum { 1279 enum {
1280 PHY_B_P_NO_PAUSE = 0<<10,/* Bi 1280 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1281 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..1 1281 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1282 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10 1282 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1283 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10 1283 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1284 }; 1284 };
1285 /* 1285 /*
1286 * Resolved Duplex mode and Capabilities (Aux 1286 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1287 */ 1287 */
1288 enum { 1288 enum {
1289 PHY_B_RES_1000FD = 7<<8,/* Bit 1289 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1290 PHY_B_RES_1000HD = 6<<8,/* Bit 1290 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1291 }; 1291 };
1292 1292
1293 /** Marvell-Specific */ 1293 /** Marvell-Specific */
1294 enum { 1294 enum {
1295 PHY_M_AN_NXT_PG = 1<<15, /* Request N 1295 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1296 PHY_M_AN_ACK = 1<<14, /* (ro) 1296 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1297 PHY_M_AN_RF = 1<<13, /* Remote Fa 1297 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1298 1298
1299 PHY_M_AN_ASP = 1<<11, /* Asymmetri 1299 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1300 PHY_M_AN_PC = 1<<10, /* MAC Pause 1300 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1301 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 1 1301 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1302 PHY_M_AN_100_FD = 1<<8, /* Advertise 1302 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1303 PHY_M_AN_100_HD = 1<<7, /* Advertise 1303 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1304 PHY_M_AN_10_FD = 1<<6, /* Advertise 1304 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1305 PHY_M_AN_10_HD = 1<<5, /* Advertise 1305 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1306 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bi 1306 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1307 }; 1307 };
1308 1308
1309 /* special defines for FIBER (88E1011S only) 1309 /* special defines for FIBER (88E1011S only) */
1310 enum { 1310 enum {
1311 PHY_M_AN_ASP_X = 1<<8, /* As 1311 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1312 PHY_M_AN_PC_X = 1<<7, /* MA 1312 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1313 PHY_M_AN_1000X_AHD = 1<<6, /* Ad 1313 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1314 PHY_M_AN_1000X_AFD = 1<<5, /* Ad 1314 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1315 }; 1315 };
1316 1316
1317 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC 1317 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1318 enum { 1318 enum {
1319 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 1319 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1320 PHY_M_P_SYM_MD_X = 1<<7, /* Bi 1320 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1321 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 1321 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1322 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 1322 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1323 }; 1323 };
1324 1324
1325 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1325 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1326 enum { 1326 enum {
1327 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13 1327 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1328 PHY_M_1000C_MSE = 1<<12, /* Manual Ma 1328 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1329 PHY_M_1000C_MSC = 1<<11, /* M/S Confi 1329 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1330 PHY_M_1000C_MPD = 1<<10, /* Multi-Por 1330 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1331 PHY_M_1000C_AFD = 1<<9, /* Advertise 1331 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1332 PHY_M_1000C_AHD = 1<<8, /* Advertise 1332 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1333 }; 1333 };
1334 1334
1335 /***** PHY_MARV_PHY_CTRL 16 bit r/w 1335 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1336 enum { 1336 enum {
1337 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bi 1337 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1338 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bi 1338 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1339 PHY_M_PC_ASS_CRS_TX = 1<<11, /* A 1339 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1340 PHY_M_PC_FL_GOOD = 1<<10, /* F 1340 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1341 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 1341 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1342 PHY_M_PC_ENA_EXT_D = 1<<7, /* En 1342 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1343 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 1343 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1344 PHY_M_PC_DIS_125CLK = 1<<4, /* Di 1344 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1345 PHY_M_PC_MAC_POW_UP = 1<<3, /* MA 1345 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1346 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQ 1346 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1347 PHY_M_PC_POL_R_DIS = 1<<1, /* Po 1347 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1348 PHY_M_PC_DIS_JABBER = 1<<0, /* Di 1348 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1349 }; 1349 };
1350 1350
1351 enum { 1351 enum {
1352 PHY_M_PC_EN_DET = 2<<8, /* En 1352 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1353 PHY_M_PC_EN_DET_PLUS = 3<<8, /* En 1353 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1354 }; 1354 };
1355 1355
1356 enum { 1356 enum {
1357 PHY_M_PC_MAN_MDI = 0, /* 00 = 1357 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1358 PHY_M_PC_MAN_MDIX = 1, /* 01 = 1358 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1359 PHY_M_PC_ENA_AUTO = 3, /* 11 = 1359 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1360 }; 1360 };
1361 1361
1362 /* for 10/100 Fast Ethernet PHY (88E3082 only 1362 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1363 enum { 1363 enum {
1364 PHY_M_PC_ENA_DTE_DT = 1<<15, /* E 1364 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1365 PHY_M_PC_ENA_ENE_DT = 1<<14, /* E 1365 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1366 PHY_M_PC_DIS_NLP_CK = 1<<13, /* D 1366 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1367 PHY_M_PC_ENA_LIP_NP = 1<<12, /* E 1367 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1368 PHY_M_PC_DIS_NLP_GN = 1<<11, /* D 1368 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1369 1369
1370 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Di 1370 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1371 PHY_M_PC_DIS_FEFI = 1<<8, /* Di 1371 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1372 1372
1373 PHY_M_PC_SH_TP_SEL = 1<<6, /* Sh 1373 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1374 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 1374 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1375 }; 1375 };
1376 1376
1377 /***** PHY_MARV_PHY_STAT 16 bit r/o 1377 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1378 enum { 1378 enum {
1379 PHY_M_PS_SPEED_MSK = 3<<14, /* B 1379 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1380 PHY_M_PS_SPEED_1000 = 1<<15, /* 1380 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1381 PHY_M_PS_SPEED_100 = 1<<14, /* 1381 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1382 PHY_M_PS_SPEED_10 = 0, /* 1382 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1383 PHY_M_PS_FULL_DUP = 1<<13, /* F 1383 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1384 PHY_M_PS_PAGE_REC = 1<<12, /* P 1384 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1385 PHY_M_PS_SPDUP_RES = 1<<11, /* S 1385 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1386 PHY_M_PS_LINK_UP = 1<<10, /* L 1386 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1387 PHY_M_PS_CABLE_MSK = 7<<7, /* B 1387 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1388 PHY_M_PS_MDI_X_STAT = 1<<6, /* M 1388 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1389 PHY_M_PS_DOWNS_STAT = 1<<5, /* D 1389 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1390 PHY_M_PS_ENDET_STAT = 1<<4, /* E 1390 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1391 PHY_M_PS_TX_P_EN = 1<<3, /* T 1391 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1392 PHY_M_PS_RX_P_EN = 1<<2, /* R 1392 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1393 PHY_M_PS_POL_REV = 1<<1, /* P 1393 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1394 PHY_M_PS_JABBER = 1<<0, /* J 1394 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1395 }; 1395 };
1396 1396
1397 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_ 1397 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1398 1398
1399 /* for 10/100 Fast Ethernet PHY (88E3082 only 1399 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1400 enum { 1400 enum {
1401 PHY_M_PS_DTE_DETECT = 1<<15, /* D 1401 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1402 PHY_M_PS_RES_SPEED = 1<<14, /* R 1402 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1403 }; 1403 };
1404 1404
1405 enum { 1405 enum {
1406 PHY_M_IS_AN_ERROR = 1<<15, /* A 1406 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1407 PHY_M_IS_LSP_CHANGE = 1<<14, /* L 1407 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1408 PHY_M_IS_DUP_CHANGE = 1<<13, /* D 1408 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1409 PHY_M_IS_AN_PR = 1<<12, /* P 1409 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1410 PHY_M_IS_AN_COMPL = 1<<11, /* A 1410 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1411 PHY_M_IS_LST_CHANGE = 1<<10, /* L 1411 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1412 PHY_M_IS_SYMB_ERROR = 1<<9, /* Sy 1412 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1413 PHY_M_IS_FALSE_CARR = 1<<8, /* Fa 1413 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1414 PHY_M_IS_FIFO_ERROR = 1<<7, /* FI 1414 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1415 PHY_M_IS_MDI_CHANGE = 1<<6, /* MD 1415 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1416 PHY_M_IS_DOWNSH_DET = 1<<5, /* Do 1416 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1417 PHY_M_IS_END_CHANGE = 1<<4, /* En 1417 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1418 1418
1419 PHY_M_IS_DTE_CHANGE = 1<<2, /* DT 1419 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1420 PHY_M_IS_POL_CHANGE = 1<<1, /* Po 1420 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1421 PHY_M_IS_JABBER = 1<<0, /* Ja 1421 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1422 1422
1423 PHY_M_IS_DEF_MSK = PHY_M_IS_AN 1423 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1424 PHY_M_IS_LS 1424 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1425 1425
1426 PHY_M_IS_AN_MSK = PHY_M_IS_AN 1426 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1427 }; 1427 };
1428 1428
1429 /***** PHY_MARV_EXT_CTRL 16 bit r/w 1429 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1430 enum { 1430 enum {
1431 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enabl 1431 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1432 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enabl 1432 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1433 1433
1434 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disab 1434 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1435 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 1 1435 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1436 /* (8 1436 /* (88E1011 only) */
1437 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 1437 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
1438 /* (88 1438 /* (88E1011 only) */
1439 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 1 1439 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1440 /* (8 1440 /* (88E1111 only) */
1441 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downs 1441 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1442 /* !! 1442 /* !!! Errata in spec. (1 = disable) */
1443 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII 1443 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1444 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 1444 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1445 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber 1445 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1446 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE D 1446 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1447 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII 1447 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1448 PHY_M_EC_TRANS_DIS = 1<<0, /* Trans 1448 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1449 1449
1450 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 1450 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1451 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) 1451 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1452 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) 1452 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1453 1453
1454 #define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) 1454 #define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1455 1455 /* 100=5x; 101=6x; 110=7x; 111=8x */
1456 enum { 1456 enum {
1457 MAC_TX_CLK_0_MHZ = 2, 1457 MAC_TX_CLK_0_MHZ = 2,
1458 MAC_TX_CLK_2_5_MHZ = 6, 1458 MAC_TX_CLK_2_5_MHZ = 6,
1459 MAC_TX_CLK_25_MHZ = 7, 1459 MAC_TX_CLK_25_MHZ = 7,
1460 }; 1460 };
1461 1461
1462 /***** PHY_MARV_LED_CTRL 16 bit r/w 1462 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1463 enum { 1463 enum {
1464 PHY_M_LEDC_DIS_LED = 1<<15, /* D 1464 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1465 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bi 1465 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1466 PHY_M_LEDC_F_INT = 1<<11, /* F 1466 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1467 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 1467 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1468 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Du 1468 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1469 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx 1469 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1470 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 1470 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1471 /* (8 1471 /* (88E1111 only) */
1472 }; 1472 };
1473 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<1 1473 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1474 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8 1474 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1475 1475
1476 enum { 1476 enum {
1477 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bi 1477 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
1478 /* (8 1478 /* (88E1011 only) */
1479 PHY_M_LEDC_DP_CTRL = 1<<2, /* Du 1479 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1480 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Du 1480 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1481 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx 1481 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1482 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx 1482 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1483 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx 1483 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1484 }; 1484 };
1485 1485
1486 enum { 1486 enum {
1487 PULS_NO_STR = 0, /* no pulse stre 1487 PULS_NO_STR = 0, /* no pulse stretching */
1488 PULS_21MS = 1, /* 21 ms to 42 m 1488 PULS_21MS = 1, /* 21 ms to 42 ms */
1489 PULS_42MS = 2, /* 42 ms to 84 m 1489 PULS_42MS = 2, /* 42 ms to 84 ms */
1490 PULS_84MS = 3, /* 84 ms to 170 1490 PULS_84MS = 3, /* 84 ms to 170 ms */
1491 PULS_170MS = 4, /* 170 ms to 340 1491 PULS_170MS = 4, /* 170 ms to 340 ms */
1492 PULS_340MS = 5, /* 340 ms to 670 1492 PULS_340MS = 5, /* 340 ms to 670 ms */
1493 PULS_670MS = 6, /* 670 ms to 1.3 1493 PULS_670MS = 6, /* 670 ms to 1.3 s */
1494 PULS_1300MS = 7, /* 1.3 s to 2.7 1494 PULS_1300MS = 7, /* 1.3 s to 2.7 s */
1495 }; 1495 };
1496 1496
1497 1497
1498 enum { 1498 enum {
1499 BLINK_42MS = 0, /* 42 ms */ 1499 BLINK_42MS = 0, /* 42 ms */
1500 BLINK_84MS = 1, /* 84 ms */ 1500 BLINK_84MS = 1, /* 84 ms */
1501 BLINK_170MS = 2, /* 170 ms */ 1501 BLINK_170MS = 2, /* 170 ms */
1502 BLINK_340MS = 3, /* 340 ms */ 1502 BLINK_340MS = 3, /* 340 ms */
1503 BLINK_670MS = 4, /* 670 ms */ 1503 BLINK_670MS = 4, /* 670 ms */
1504 }; 1504 };
1505 1505
1506 /***** PHY_MARV_LED_OVER 16 bit r/w 1506 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1507 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* 1507 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1508 1508 /* Bit 13..12: reserved */
1509 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* 1509 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1510 #define PHY_M_LED_MO_10(x) ((x)<<8) /* B 1510 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1511 #define PHY_M_LED_MO_100(x) ((x)<<6) /* B 1511 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1512 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* B 1512 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1513 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* B 1513 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1514 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* B 1514 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1515 1515
1516 enum { 1516 enum {
1517 MO_LED_NORM = 0, 1517 MO_LED_NORM = 0,
1518 MO_LED_BLINK = 1, 1518 MO_LED_BLINK = 1,
1519 MO_LED_OFF = 2, 1519 MO_LED_OFF = 2,
1520 MO_LED_ON = 3, 1520 MO_LED_ON = 3,
1521 }; 1521 };
1522 1522
1523 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w 1523 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1524 enum { 1524 enum {
1525 PHY_M_EC2_FI_IMPED = 1<<6, /* Fi 1525 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1526 PHY_M_EC2_FO_IMPED = 1<<5, /* Fi 1526 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1527 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fi 1527 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1528 PHY_M_EC2_FO_BOOST = 1<<3, /* Fi 1528 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1529 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 1529 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
1530 }; 1530 };
1531 1531
1532 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. 1532 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1533 enum { 1533 enum {
1534 PHY_M_FC_AUTO_SEL = 1<<15, /* F 1534 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1535 PHY_M_FC_AN_REG_ACC = 1<<14, /* F 1535 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1536 PHY_M_FC_RESOLUTION = 1<<13, /* F 1536 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1537 PHY_M_SER_IF_AN_BP = 1<<12, /* S 1537 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1538 PHY_M_SER_IF_BP_ST = 1<<11, /* S 1538 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1539 PHY_M_IRQ_POLARITY = 1<<10, /* I 1539 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1540 PHY_M_DIS_AUT_MED = 1<<9, /* Di 1540 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1541 1541 /* (88E1111 only) */
1542 1542 /* Bit 9.. 4: reserved (88E1011 only) */
1543 PHY_M_UNDOC1 = 1<<7, /* undocument 1543 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1544 PHY_M_DTE_POW_STAT = 1<<4, /* DT 1544 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1545 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: 1545 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1546 }; 1546 };
1547 1547
1548 /***** PHY_MARV_CABLE_DIAG 16 bit r/o 1548 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1549 enum { 1549 enum {
1550 PHY_M_CABD_ENA_TEST = 1<<15, /* E 1550 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1551 PHY_M_CABD_DIS_WAIT = 1<<15, /* D 1551 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1552 /* (8 1552 /* (88E1111 only) */
1553 PHY_M_CABD_STAT_MSK = 3<<13, /* B 1553 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1554 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* 1554 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1555 /* (8 1555 /* (88E1111 only) */
1556 PHY_M_CABD_DIST_MSK = 0xff, /* Bi 1556 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1557 }; 1557 };
1558 1558
1559 /* values for Cable Diagnostic Status (11=fai 1559 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1560 enum { 1560 enum {
1561 CABD_STAT_NORMAL= 0, 1561 CABD_STAT_NORMAL= 0,
1562 CABD_STAT_SHORT = 1, 1562 CABD_STAT_SHORT = 1,
1563 CABD_STAT_OPEN = 2, 1563 CABD_STAT_OPEN = 2,
1564 CABD_STAT_FAIL = 3, 1564 CABD_STAT_FAIL = 3,
1565 }; 1565 };
1566 1566
1567 /* for 10/100 Fast Ethernet PHY (88E3082 only 1567 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1568 /***** PHY_MARV_FE_LED_PAR 16 bi 1568 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1569 1569 /* Bit 15..12: reserved (used internally) */
1570 enum { 1570 enum {
1571 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bi 1571 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1572 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bi 1572 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1573 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3. 1573 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1574 }; 1574 };
1575 1575
1576 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & P 1576 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1577 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & P 1577 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1578 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & P 1578 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1579 1579
1580 enum { 1580 enum {
1581 LED_PAR_CTRL_COLX = 0x00, 1581 LED_PAR_CTRL_COLX = 0x00,
1582 LED_PAR_CTRL_ERROR = 0x01, 1582 LED_PAR_CTRL_ERROR = 0x01,
1583 LED_PAR_CTRL_DUPLEX = 0x02, 1583 LED_PAR_CTRL_DUPLEX = 0x02,
1584 LED_PAR_CTRL_DP_COL = 0x03, 1584 LED_PAR_CTRL_DP_COL = 0x03,
1585 LED_PAR_CTRL_SPEED = 0x04, 1585 LED_PAR_CTRL_SPEED = 0x04,
1586 LED_PAR_CTRL_LINK = 0x05, 1586 LED_PAR_CTRL_LINK = 0x05,
1587 LED_PAR_CTRL_TX = 0x06, 1587 LED_PAR_CTRL_TX = 0x06,
1588 LED_PAR_CTRL_RX = 0x07, 1588 LED_PAR_CTRL_RX = 0x07,
1589 LED_PAR_CTRL_ACT = 0x08, 1589 LED_PAR_CTRL_ACT = 0x08,
1590 LED_PAR_CTRL_LNK_RX = 0x09, 1590 LED_PAR_CTRL_LNK_RX = 0x09,
1591 LED_PAR_CTRL_LNK_AC = 0x0a, 1591 LED_PAR_CTRL_LNK_AC = 0x0a,
1592 LED_PAR_CTRL_ACT_BL = 0x0b, 1592 LED_PAR_CTRL_ACT_BL = 0x0b,
1593 LED_PAR_CTRL_TX_BL = 0x0c, 1593 LED_PAR_CTRL_TX_BL = 0x0c,
1594 LED_PAR_CTRL_RX_BL = 0x0d, 1594 LED_PAR_CTRL_RX_BL = 0x0d,
1595 LED_PAR_CTRL_COL_BL = 0x0e, 1595 LED_PAR_CTRL_COL_BL = 0x0e,
1596 LED_PAR_CTRL_INACT = 0x0f 1596 LED_PAR_CTRL_INACT = 0x0f
1597 }; 1597 };
1598 1598
1599 /*****,PHY_MARV_FE_SPEC_2 16 bi 1599 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1600 enum { 1600 enum {
1601 PHY_M_FESC_DIS_WAIT = 1<<2, /* Di 1601 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1602 PHY_M_FESC_ENA_MCLK = 1<<1, /* En 1602 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1603 PHY_M_FESC_SEL_CL_A = 1<<0, /* Se 1603 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1604 }; 1604 };
1605 1605
1606 1606
1607 /***** PHY_MARV_PHY_CTRL (page 3) 1607 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1608 enum { 1608 enum {
1609 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* 1609 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1610 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* 1610 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1611 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* 1611 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1612 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 1612 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1613 }; 1613 };
1614 1614
1615 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & 1615 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1616 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & P 1616 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1617 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & P 1617 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1618 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & P 1618 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1619 1619
1620 /* GMAC registers */ 1620 /* GMAC registers */
1621 /* Port Registers */ 1621 /* Port Registers */
1622 enum { 1622 enum {
1623 GM_GP_STAT = 0x0000, /* 16 1623 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1624 GM_GP_CTRL = 0x0004, /* 16 1624 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1625 GM_TX_CTRL = 0x0008, /* 16 1625 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1626 GM_RX_CTRL = 0x000c, /* 16 1626 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1627 GM_TX_FLOW_CTRL = 0x0010, /* 16 1627 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1628 GM_TX_PARAM = 0x0014, /* 16 1628 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1629 GM_SERIAL_MODE = 0x0018, /* 16 1629 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1630 /* Source Address Registers */ 1630 /* Source Address Registers */
1631 GM_SRC_ADDR_1L = 0x001c, /* 16 1631 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1632 GM_SRC_ADDR_1M = 0x0020, /* 16 1632 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1633 GM_SRC_ADDR_1H = 0x0024, /* 16 1633 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1634 GM_SRC_ADDR_2L = 0x0028, /* 16 1634 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1635 GM_SRC_ADDR_2M = 0x002c, /* 16 1635 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1636 GM_SRC_ADDR_2H = 0x0030, /* 16 1636 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1637 1637
1638 /* Multicast Address Hash Registers */ 1638 /* Multicast Address Hash Registers */
1639 GM_MC_ADDR_H1 = 0x0034, /* 16 1639 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1640 GM_MC_ADDR_H2 = 0x0038, /* 16 1640 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1641 GM_MC_ADDR_H3 = 0x003c, /* 16 1641 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1642 GM_MC_ADDR_H4 = 0x0040, /* 16 1642 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1643 1643
1644 /* Interrupt Source Registers */ 1644 /* Interrupt Source Registers */
1645 GM_TX_IRQ_SRC = 0x0044, /* 16 1645 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1646 GM_RX_IRQ_SRC = 0x0048, /* 16 1646 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1647 GM_TR_IRQ_SRC = 0x004c, /* 16 1647 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1648 1648
1649 /* Interrupt Mask Registers */ 1649 /* Interrupt Mask Registers */
1650 GM_TX_IRQ_MSK = 0x0050, /* 16 1650 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1651 GM_RX_IRQ_MSK = 0x0054, /* 16 1651 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1652 GM_TR_IRQ_MSK = 0x0058, /* 16 1652 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1653 1653
1654 /* Serial Management Interface (SMI) Register 1654 /* Serial Management Interface (SMI) Registers */
1655 GM_SMI_CTRL = 0x0080, /* 16 1655 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1656 GM_SMI_DATA = 0x0084, /* 16 1656 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1657 GM_PHY_ADDR = 0x0088, /* 16 1657 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1658 }; 1658 };
1659 1659
1660 /* MIB Counters */ 1660 /* MIB Counters */
1661 #define GM_MIB_CNT_BASE 0x0100 /* Ba 1661 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1662 #define GM_MIB_CNT_SIZE 44 /* Nu 1662 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1663 1663
1664 /* 1664 /*
1665 * MIB Counters base address definitions (low 1665 * MIB Counters base address definitions (low word) -
1666 * use offset 4 for access to high word (32 b 1666 * use offset 4 for access to high word (32 bit r/o)
1667 */ 1667 */
1668 enum { 1668 enum {
1669 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, 1669 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1670 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8 1670 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1671 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 1 1671 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1672 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 2 1672 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1673 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 3 1673 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1674 /* GM_MIB_CNT_BASE + 40: reser 1674 /* GM_MIB_CNT_BASE + 40: reserved */
1675 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 4 1675 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1676 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 5 1676 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1677 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 6 1677 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1678 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 7 1678 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1679 GM_RXF_SHT = GM_MIB_CNT_BASE + 8 1679 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1680 GM_RXE_FRAG = GM_MIB_CNT_BASE + 8 1680 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1681 GM_RXF_64B = GM_MIB_CNT_BASE + 9 1681 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1682 GM_RXF_127B = GM_MIB_CNT_BASE + 1 1682 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1683 GM_RXF_255B = GM_MIB_CNT_BASE + 1 1683 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1684 GM_RXF_511B = GM_MIB_CNT_BASE + 1 1684 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1685 GM_RXF_1023B = GM_MIB_CNT_BASE + 1 1685 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1686 GM_RXF_1518B = GM_MIB_CNT_BASE + 1 1686 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1687 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 1 1687 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1688 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 1 1688 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1689 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 1 1689 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1690 /* GM_MIB_CNT_BASE + 168: reser 1690 /* GM_MIB_CNT_BASE + 168: reserved */
1691 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 1 1691 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1692 /* GM_MIB_CNT_BASE + 184: reser 1692 /* GM_MIB_CNT_BASE + 184: reserved */
1693 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 1 1693 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1694 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 2 1694 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1695 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 2 1695 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1696 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 2 1696 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1697 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 2 1697 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1698 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 2 1698 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1699 GM_TXF_64B = GM_MIB_CNT_BASE + 2 1699 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1700 GM_TXF_127B = GM_MIB_CNT_BASE + 2 1700 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1701 GM_TXF_255B = GM_MIB_CNT_BASE + 2 1701 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1702 GM_TXF_511B = GM_MIB_CNT_BASE + 2 1702 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1703 GM_TXF_1023B = GM_MIB_CNT_BASE + 2 1703 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1704 GM_TXF_1518B = GM_MIB_CNT_BASE + 2 1704 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1705 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 2 1705 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1706 1706
1707 GM_TXF_COL = GM_MIB_CNT_BASE + 3 1707 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1708 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 3 1708 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1709 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 3 1709 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1710 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 3 1710 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1711 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 3 1711 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1712 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 3 1712 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1713 }; 1713 };
1714 1714
1715 /* GMAC Bit Definitions */ 1715 /* GMAC Bit Definitions */
1716 /* GM_GP_STAT 16 bit r/o Gener 1716 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1717 enum { 1717 enum {
1718 GM_GPSR_SPEED = 1<<15, /* B 1718 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1719 GM_GPSR_DUPLEX = 1<<14, /* B 1719 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1720 GM_GPSR_FC_TX_DIS = 1<<13, /* B 1720 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1721 GM_GPSR_LINK_UP = 1<<12, /* B 1721 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1722 GM_GPSR_PAUSE = 1<<11, /* B 1722 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1723 GM_GPSR_TX_ACTIVE = 1<<10, /* B 1723 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1724 GM_GPSR_EXC_COL = 1<<9, /* Bi 1724 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1725 GM_GPSR_LAT_COL = 1<<8, /* Bi 1725 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1726 1726
1727 GM_GPSR_PHY_ST_CH = 1<<5, /* Bi 1727 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1728 GM_GPSR_GIG_SPEED = 1<<4, /* Bi 1728 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1729 GM_GPSR_PART_MODE = 1<<3, /* Bi 1729 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1730 GM_GPSR_FC_RX_DIS = 1<<2, /* Bi 1730 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1731 GM_GPSR_PROM_EN = 1<<1, /* Bi 1731 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1732 }; 1732 };
1733 1733
1734 /* GM_GP_CTRL 16 bit r/w Gener 1734 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1735 enum { 1735 enum {
1736 GM_GPCR_PROM_ENA = 1<<14, 1736 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1737 GM_GPCR_FC_TX_DIS = 1<<13, /* B 1737 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1738 GM_GPCR_TX_ENA = 1<<12, /* B 1738 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1739 GM_GPCR_RX_ENA = 1<<11, /* B 1739 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1740 GM_GPCR_BURST_ENA = 1<<10, /* B 1740 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1741 GM_GPCR_LOOP_ENA = 1<<9, /* Bi 1741 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1742 GM_GPCR_PART_ENA = 1<<8, /* Bi 1742 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1743 GM_GPCR_GIGS_ENA = 1<<7, /* Bi 1743 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1744 GM_GPCR_FL_PASS = 1<<6, /* Bi 1744 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1745 GM_GPCR_DUP_FULL = 1<<5, /* Bi 1745 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1746 GM_GPCR_FC_RX_DIS = 1<<4, /* Bi 1746 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1747 GM_GPCR_SPEED_100 = 1<<3, /* 1747 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1748 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bi 1748 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1749 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bi 1749 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1750 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bi 1750 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1751 }; 1751 };
1752 1752
1753 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS 1753 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1754 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_D 1754 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1755 1755
1756 /* GM_TX_CTRL 16 bi 1756 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1757 enum { 1757 enum {
1758 GM_TXCR_FORCE_JAM = 1<<15, /* B 1758 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1759 GM_TXCR_CRC_DIS = 1<<14, /* B 1759 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1760 GM_TXCR_PAD_DIS = 1<<13, /* B 1760 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1761 GM_TXCR_COL_THR_MSK = 7<<10, /* B 1761 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1762 }; 1762 };
1763 1763
1764 #define TX_COL_THR(x) (((x)<<10) & 1764 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1765 #define TX_COL_DEF 0x04 /* la 1765 #define TX_COL_DEF 0x04 /* late collision after 64 byte */
1766 1766
1767 /* GM_RX_CTRL 16 bi 1767 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1768 enum { 1768 enum {
1769 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: 1769 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1770 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: 1770 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1771 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: 1771 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1772 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: 1772 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1773 }; 1773 };
1774 1774
1775 /* GM_TX_PARAM 16 bit r/w 1775 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1776 enum { 1776 enum {
1777 GM_TXPA_JAMLEN_MSK = 0x03<<14, 1777 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1778 GM_TXPA_JAMIPG_MSK = 0x1f<<9, 1778 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1779 GM_TXPA_JAMDAT_MSK = 0x1f<<4, 1779 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1780 1780
1781 TX_JAM_LEN_DEF = 0x03, 1781 TX_JAM_LEN_DEF = 0x03,
1782 TX_JAM_IPG_DEF = 0x0b, 1782 TX_JAM_IPG_DEF = 0x0b,
1783 TX_IPG_JAM_DEF = 0x1c, 1783 TX_IPG_JAM_DEF = 0x1c,
1784 }; 1784 };
1785 1785
1786 #define TX_JAM_LEN_VAL(x) (((x)<<14) & 1786 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1787 #define TX_JAM_IPG_VAL(x) (((x)<<9) & 1787 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1788 #define TX_IPG_JAM_DATA(x) (((x)<<4) & 1788 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1789 1789
1790 1790
1791 /* GM_SERIAL_MODE 16 bi 1791 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1792 enum { 1792 enum {
1793 GM_SMOD_DATABL_MSK = 0x1f<<11, / 1793 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1794 GM_SMOD_LIMIT_4 = 1<<10, /* B 1794 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1795 GM_SMOD_VLAN_ENA = 1<<9, /* Bi 1795 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1796 GM_SMOD_JUMBO_ENA = 1<<8, /* Bi 1796 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1797 GM_SMOD_IPG_MSK = 0x1f /* Bi 1797 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1798 }; 1798 };
1799 1799
1800 #define DATA_BLIND_VAL(x) (((x)<<11) & 1800 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1801 #define DATA_BLIND_DEF 0x04 1801 #define DATA_BLIND_DEF 0x04
1802 1802
1803 #define IPG_DATA_VAL(x) (x & GM_SMOD_ 1803 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1804 #define IPG_DATA_DEF 0x1e 1804 #define IPG_DATA_DEF 0x1e
1805 1805
1806 /* GM_SMI_CTRL 16 bi 1806 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1807 enum { 1807 enum {
1808 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, / 1808 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1809 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* 1809 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1810 GM_SMI_CT_OP_RD = 1<<5, /* Bi 1810 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1811 GM_SMI_CT_RD_VAL = 1<<4, /* Bi 1811 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1812 GM_SMI_CT_BUSY = 1<<3, /* Bi 1812 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1813 }; 1813 };
1814 1814
1815 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & 1815 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1816 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & G 1816 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1817 1817
1818 /* GM_PHY_ADDR 1818 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1819 enum { 1819 enum {
1820 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: 1820 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1821 GM_PAR_MIB_TST = 1<<4, /* Bit 4: 1821 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1822 }; 1822 };
1823 1823
1824 /* Receive Frame Status Encoding */ 1824 /* Receive Frame Status Encoding */
1825 enum { 1825 enum {
1826 GMR_FS_LEN = 0xffff<<16, /* Bit 1826 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1827 GMR_FS_LEN_SHIFT = 16, 1827 GMR_FS_LEN_SHIFT = 16,
1828 GMR_FS_VLAN = 1<<13, /* Bit 13: 1828 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1829 GMR_FS_JABBER = 1<<12, /* Bit 12: 1829 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1830 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: 1830 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1831 GMR_FS_MC = 1<<10, /* Bit 10: 1831 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1832 GMR_FS_BC = 1<<9, /* Bit 9: 1832 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1833 GMR_FS_RX_OK = 1<<8, /* Bit 8: 1833 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1834 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: 1834 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1835 GMR_FS_BAD_FC = 1<<6, /* Bit 6: 1835 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1836 GMR_FS_MII_ERR = 1<<5, /* Bit 5: 1836 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1837 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: 1837 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1838 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: 1838 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1839 1839
1840 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: 1840 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1841 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: 1841 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1842 1842
1843 /* 1843 /*
1844 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ER 1844 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1845 */ 1845 */
1846 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GM 1846 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1847 GMR_FS_MII_ERR | GM 1847 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1848 GMR_FS_JABBER, 1848 GMR_FS_JABBER,
1849 /* Rx GMAC FIFO Flush Mask (default) */ 1849 /* Rx GMAC FIFO Flush Mask (default) */
1850 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | G 1850 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1851 GMR_FS_BAD_FC | G 1851 GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
1852 }; 1852 };
1853 1853
1854 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO 1854 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1855 enum { 1855 enum {
1856 GMF_WP_TST_ON = 1<<14, /* Wr 1856 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1857 GMF_WP_TST_OFF = 1<<13, /* Wr 1857 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1858 GMF_WP_STEP = 1<<12, /* Wr 1858 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1859 1859
1860 GMF_RP_TST_ON = 1<<10, /* Re 1860 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1861 GMF_RP_TST_OFF = 1<<9, /* Re 1861 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1862 GMF_RP_STEP = 1<<8, /* Re 1862 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1863 GMF_RX_F_FL_ON = 1<<7, /* Rx 1863 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1864 GMF_RX_F_FL_OFF = 1<<6, /* Rx 1864 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1865 GMF_CLI_RX_FO = 1<<5, /* Cl 1865 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1866 GMF_CLI_RX_FC = 1<<4, /* Cl 1866 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1867 GMF_OPER_ON = 1<<3, /* Op 1867 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1868 GMF_OPER_OFF = 1<<2, /* Op 1868 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1869 GMF_RST_CLR = 1<<1, /* Cl 1869 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1870 GMF_RST_SET = 1<<0, /* Se 1870 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1871 1871
1872 RX_GMF_FL_THR_DEF = 0xa, /* fl 1872 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1873 }; 1873 };
1874 1874
1875 1875
1876 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO 1876 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1877 enum { 1877 enum {
1878 GMF_WSP_TST_ON = 1<<18, /* Write Sha 1878 GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
1879 GMF_WSP_TST_OFF = 1<<17, /* Write Sha 1879 GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
1880 GMF_WSP_STEP = 1<<16, /* Write Sha 1880 GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
1881 1881
1882 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ 1882 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1883 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ 1883 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1884 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ 1884 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1885 }; 1885 };
1886 1886
1887 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Ti 1887 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1888 enum { 1888 enum {
1889 GMT_ST_START = 1<<2, /* Start Time 1889 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1890 GMT_ST_STOP = 1<<1, /* Stop Time 1890 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1891 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time 1891 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1892 }; 1892 };
1893 1893
1894 /* GMAC_CTRL 32 bit GMAC 1894 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1895 enum { 1895 enum {
1896 GMC_H_BURST_ON = 1<<7, /* Half Duple 1896 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1897 GMC_H_BURST_OFF = 1<<6, /* Half Duple 1897 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1898 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopb 1898 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1899 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopb 1899 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1900 GMC_PAUSE_ON = 1<<3, /* Pause On * 1900 GMC_PAUSE_ON = 1<<3, /* Pause On */
1901 GMC_PAUSE_OFF = 1<<2, /* Pause Off 1901 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1902 GMC_RST_CLR = 1<<1, /* Clear GMAC 1902 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1903 GMC_RST_SET = 1<<0, /* Set GMAC 1903 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1904 }; 1904 };
1905 1905
1906 /* GPHY_CTRL 32 bit GPHY 1906 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1907 enum { 1907 enum {
1908 GPC_SEL_BDT = 1<<28, /* Select Bi 1908 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1909 GPC_INT_POL_HI = 1<<27, /* IRQ Polar 1909 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1910 GPC_75_OHM = 1<<26, /* Use 75 Oh 1910 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1911 GPC_DIS_FC = 1<<25, /* Disable A 1911 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1912 GPC_DIS_SLEEP = 1<<24, /* Disable E 1912 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1913 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MOD 1913 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1914 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MOD 1914 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1915 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MOD 1915 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1916 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MOD 1916 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1917 GPC_ANEG_0 = 1<<19, /* ANEG[0] * 1917 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1918 GPC_ENA_XC = 1<<18, /* Enable MD 1918 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1919 GPC_DIS_125 = 1<<17, /* Disable 1 1919 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1920 GPC_ANEG_3 = 1<<16, /* ANEG[3] * 1920 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1921 GPC_ANEG_2 = 1<<15, /* ANEG[2] * 1921 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1922 GPC_ANEG_1 = 1<<14, /* ANEG[1] * 1922 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1923 GPC_ENA_PAUSE = 1<<13, /* Enable Pa 1923 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1924 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of 1924 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1925 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of 1925 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1926 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of 1926 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1927 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of 1927 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1928 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of 1928 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1929 1929 /* Bits 7..2: reserved */
1930 GPC_RST_CLR = 1<<1, /* Clear GPHY 1930 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1931 GPC_RST_SET = 1<<0, /* Set GPHY 1931 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1932 }; 1932 };
1933 1933
1934 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC 1934 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1935 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | G 1935 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1936 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC 1936 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1937 1937
1938 /* forced speed and duplex mode (don't mix wi 1938 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1939 #define GPC_FRC10MBIT_HALF 0 1939 #define GPC_FRC10MBIT_HALF 0
1940 #define GPC_FRC10MBIT_FULL GPC_ANEG_0 1940 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
1941 #define GPC_FRC100MBIT_HALF GPC_ANEG_1 1941 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
1942 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | 1942 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1943 1943
1944 /* auto-negotiation with limited advertised s 1944 /* auto-negotiation with limited advertised speeds */
1945 /* mix only with master/slave settings (for c 1945 /* mix only with master/slave settings (for copper) */
1946 #define GPC_ADV_1000_HALF GPC_ANEG_2 1946 #define GPC_ADV_1000_HALF GPC_ANEG_2
1947 #define GPC_ADV_1000_FULL GPC_ANEG_3 1947 #define GPC_ADV_1000_FULL GPC_ANEG_3
1948 #define GPC_ADV_ALL (GPC_ANEG_2 | 1948 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
1949 1949
1950 /* master/slave settings */ 1950 /* master/slave settings */
1951 /* only for copper with 1000 Mbps */ 1951 /* only for copper with 1000 Mbps */
1952 #define GPC_FORCE_MASTER 0 1952 #define GPC_FORCE_MASTER 0
1953 #define GPC_FORCE_SLAVE GPC_ANEG_0 1953 #define GPC_FORCE_SLAVE GPC_ANEG_0
1954 #define GPC_PREF_MASTER GPC_ANEG_1 1954 #define GPC_PREF_MASTER GPC_ANEG_1
1955 #define GPC_PREF_SLAVE (GPC_ANEG_1 | 1955 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
1956 1956
1957 /* GMAC_IRQ_SRC 8 bit GMAC Interrup 1957 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1958 /* GMAC_IRQ_MSK 8 bit GMAC Interrup 1958 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1959 enum { 1959 enum {
1960 GM_IS_TX_CO_OV = 1<<5, /* Transmit C 1960 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1961 GM_IS_RX_CO_OV = 1<<4, /* Receive Co 1961 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1962 GM_IS_TX_FF_UR = 1<<3, /* Transmit F 1962 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1963 GM_IS_TX_COMPL = 1<<2, /* Frame Tran 1963 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1964 GM_IS_RX_FF_OR = 1<<1, /* Receive FI 1964 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1965 GM_IS_RX_COMPL = 1<<0, /* Frame Rece 1965 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1966 1966
1967 #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_ 1967 #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
1968 1968
1969 /* GMAC_LINK_CTRL 16 bit GMAC Link Con 1969 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1970 1970 /* Bits 15.. 2: reserved */
1971 GMLC_RST_CLR = 1<<1, /* Clear GMAC 1971 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1972 GMLC_RST_SET = 1<<0, /* Set GMAC 1972 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1973 1973
1974 1974
1975 /* WOL_CTRL_STAT 16 bit WOL Control/S 1975 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1976 WOL_CTL_LINK_CHG_OCC = 1<< 1976 WOL_CTL_LINK_CHG_OCC = 1<<15,
1977 WOL_CTL_MAGIC_PKT_OCC = 1<< 1977 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1978 WOL_CTL_PATTERN_OCC = 1<< 1978 WOL_CTL_PATTERN_OCC = 1<<13,
1979 WOL_CTL_CLEAR_RESULT = 1<< 1979 WOL_CTL_CLEAR_RESULT = 1<<12,
1980 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<< 1980 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1981 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<< 1981 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1982 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<< 1982 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1983 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<< 1983 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1984 WOL_CTL_ENA_PME_ON_PATTERN = 1<< 1984 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1985 WOL_CTL_DIS_PME_ON_PATTERN = 1<< 1985 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1986 WOL_CTL_ENA_LINK_CHG_UNIT = 1<< 1986 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1987 WOL_CTL_DIS_LINK_CHG_UNIT = 1<< 1987 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1988 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<< 1988 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1989 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<< 1989 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1990 WOL_CTL_ENA_PATTERN_UNIT = 1<< 1990 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1991 WOL_CTL_DIS_PATTERN_UNIT = 1<< 1991 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1992 }; 1992 };
1993 1993
1994 #define WOL_CTL_DEFAULT 1994 #define WOL_CTL_DEFAULT \
1995 (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1995 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1996 WOL_CTL_DIS_PME_ON_PATTERN | \ 1996 WOL_CTL_DIS_PME_ON_PATTERN | \
1997 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1997 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1998 WOL_CTL_DIS_LINK_CHG_UNIT | 1998 WOL_CTL_DIS_LINK_CHG_UNIT | \
1999 WOL_CTL_DIS_PATTERN_UNIT | 1999 WOL_CTL_DIS_PATTERN_UNIT | \
2000 WOL_CTL_DIS_MAGIC_PKT_UNIT) 2000 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2001 2001
2002 /* WOL_MATCH_CTL 8 bit WOL Match Con 2002 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2003 #define WOL_CTL_PATT_ENA(x) (1 << (x)) 2003 #define WOL_CTL_PATT_ENA(x) (1 << (x))
2004 2004
2005 2005
2006 /* XMAC II registers 2006 /* XMAC II registers */
2007 enum { 2007 enum {
2008 XM_MMU_CMD = 0x0000, /* 16 bit r 2008 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2009 XM_POFF = 0x0008, /* 32 bit r 2009 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2010 XM_BURST = 0x000c, /* 32 bit r 2010 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2011 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r 2011 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2012 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r 2012 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2013 XM_TX_CMD = 0x0020, /* 16 bit r 2013 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2014 XM_TX_RT_LIM = 0x0024, /* 16 bit r 2014 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2015 XM_TX_STIME = 0x0028, /* 16 bit r 2015 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2016 XM_TX_IPG = 0x002c, /* 16 bit r 2016 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2017 XM_RX_CMD = 0x0030, /* 16 bit r 2017 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2018 XM_PHY_ADDR = 0x0034, /* 16 bit r 2018 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2019 XM_PHY_DATA = 0x0038, /* 16 bit r 2019 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2020 XM_GP_PORT = 0x0040, /* 32 bit r 2020 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2021 XM_IMSK = 0x0044, /* 16 bit r 2021 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2022 XM_ISRC = 0x0048, /* 16 bit r 2022 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2023 XM_HW_CFG = 0x004c, /* 16 bit r 2023 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2024 XM_TX_LO_WM = 0x0060, /* 16 bit r 2024 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2025 XM_TX_HI_WM = 0x0062, /* 16 bit r 2025 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2026 XM_TX_THR = 0x0064, /* 16 bit r 2026 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2027 XM_HT_THR = 0x0066, /* 16 bit r 2027 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2028 XM_PAUSE_DA = 0x0068, /* NA reg r 2028 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2029 XM_CTL_PARA = 0x0070, /* 32 bit r 2029 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2030 XM_MAC_OPCODE = 0x0074, /* 16 bit r 2030 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2031 XM_MAC_PTIME = 0x0076, /* 16 bit r 2031 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2032 XM_TX_STAT = 0x0078, /* 32 bit r 2032 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2033 2033
2034 XM_EXM_START = 0x0080, /* r/w 2034 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2035 #define XM_EXM(reg) (XM_EXM_START + ((reg 2035 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2036 }; 2036 };
2037 2037
2038 enum { 2038 enum {
2039 XM_SRC_CHK = 0x0100, /* NA reg r 2039 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2040 XM_SA = 0x0108, /* NA reg r 2040 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2041 XM_HSM = 0x0110, /* 64 bit r 2041 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2042 XM_RX_LO_WM = 0x0118, /* 16 bit r 2042 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2043 XM_RX_HI_WM = 0x011a, /* 16 bit r 2043 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2044 XM_RX_THR = 0x011c, /* 32 bit r 2044 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2045 XM_DEV_ID = 0x0120, /* 32 bit r 2045 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2046 XM_MODE = 0x0124, /* 32 bit r 2046 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2047 XM_LSA = 0x0128, /* NA reg r 2047 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2048 XM_TS_READ = 0x0130, /* 32 bit r 2048 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2049 XM_TS_LOAD = 0x0134, /* 32 bit r 2049 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2050 XM_STAT_CMD = 0x0200, /* 16 bit r 2050 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2051 XM_RX_CNT_EV = 0x0204, /* 32 bit r 2051 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2052 XM_TX_CNT_EV = 0x0208, /* 32 bit r 2052 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2053 XM_RX_EV_MSK = 0x020c, /* 32 bit r 2053 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2054 XM_TX_EV_MSK = 0x0210, /* 32 bit r 2054 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2055 XM_TXF_OK = 0x0280, /* 32 bit r 2055 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2056 XM_TXO_OK_HI = 0x0284, /* 32 bit r 2056 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2057 XM_TXO_OK_LO = 0x0288, /* 32 bit r 2057 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2058 XM_TXF_BC_OK = 0x028c, /* 32 bit r 2058 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2059 XM_TXF_MC_OK = 0x0290, /* 32 bit r 2059 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2060 XM_TXF_UC_OK = 0x0294, /* 32 bit r 2060 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2061 XM_TXF_LONG = 0x0298, /* 32 bit r 2061 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2062 XM_TXE_BURST = 0x029c, /* 32 bit r 2062 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2063 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r 2063 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2064 XM_TXF_MCTRL = 0x02a4, /* 32 bit r 2064 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2065 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r 2065 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2066 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r 2066 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2067 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r 2067 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2068 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r 2068 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2069 XM_TXF_DEF = 0x02b8, /* 32 bit r 2069 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2070 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r 2070 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2071 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r 2071 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2072 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r 2072 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2073 XM_TXP_UTIL = 0x02c8, /* 32 bit r 2073 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2074 XM_TXF_64B = 0x02d0, /* 32 bit r 2074 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2075 XM_TXF_127B = 0x02d4, /* 32 bit r 2075 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2076 XM_TXF_255B = 0x02d8, /* 32 bit r 2076 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2077 XM_TXF_511B = 0x02dc, /* 32 bit r 2077 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2078 XM_TXF_1023B = 0x02e0, /* 32 bit r 2078 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2079 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r 2079 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2080 XM_RXF_OK = 0x0300, /* 32 bit r 2080 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2081 XM_RXO_OK_HI = 0x0304, /* 32 bit r 2081 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2082 XM_RXO_OK_LO = 0x0308, /* 32 bit r 2082 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2083 XM_RXF_BC_OK = 0x030c, /* 32 bit r 2083 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2084 XM_RXF_MC_OK = 0x0310, /* 32 bit r 2084 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2085 XM_RXF_UC_OK = 0x0314, /* 32 bit r 2085 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2086 XM_RXF_MPAUSE = 0x0318, /* 32 bit r 2086 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2087 XM_RXF_MCTRL = 0x031c, /* 32 bit r 2087 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2088 XM_RXF_INV_MP = 0x0320, /* 32 bit r 2088 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2089 XM_RXF_INV_MOC = 0x0324, /* 32 bit r 2089 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2090 XM_RXE_BURST = 0x0328, /* 32 bit r 2090 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2091 XM_RXE_FMISS = 0x032c, /* 32 bit r 2091 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2092 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r 2092 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2093 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r 2093 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2094 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r 2094 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2095 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r 2095 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2096 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r 2096 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2097 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r 2097 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2098 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r 2098 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2099 XM_RXE_RUNT = 0x034c, /* 32 bit r 2099 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2100 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r 2100 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2101 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r 2101 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2102 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r 2102 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2103 XM_RXP_UTIL = 0x0360, /* 32 bit r 2103 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2104 XM_RXF_64B = 0x0368, /* 32 bit r 2104 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2105 XM_RXF_127B = 0x036c, /* 32 bit r 2105 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2106 XM_RXF_255B = 0x0370, /* 32 bit r 2106 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2107 XM_RXF_511B = 0x0374, /* 32 bit r 2107 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2108 XM_RXF_1023B = 0x0378, /* 32 bit r 2108 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2109 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r 2109 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2110 }; 2110 };
2111 2111
2112 /* XM_MMU_CMD 16 bit r/w MMU C 2112 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2113 enum { 2113 enum {
2114 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: 2114 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2115 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: 2115 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2116 XM_MMU_IGN_PF = 1<<10, /* Bit 10: 2116 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2117 XM_MMU_MAC_LB = 1<<9, /* Bit 9: 2117 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2118 XM_MMU_FRC_COL = 1<<7, /* Bit 7: 2118 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2119 XM_MMU_SIM_COL = 1<<6, /* Bit 6: 2119 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2120 XM_MMU_NO_PRE = 1<<5, /* Bit 5: 2120 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2121 XM_MMU_GMII_FD = 1<<4, /* Bit 4: 2121 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2122 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: 2122 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2123 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: 2123 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2124 XM_MMU_ENA_RX = 1<<1, /* Bit 1: 2124 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2125 XM_MMU_ENA_TX = 1<<0, /* Bit 0: 2125 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2126 }; 2126 };
2127 2127
2128 2128
2129 /* XM_TX_CMD 16 bit r/w Trans 2129 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2130 enum { 2130 enum {
2131 XM_TX_BK2BK = 1<<6, /* Bit 6: 2131 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2132 XM_TX_ENC_BYP = 1<<5, /* Bit 5: 2132 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2133 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (s 2133 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2134 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: 2134 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2135 XM_TX_NO_PRE = 1<<2, /* Bit 2: 2135 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2136 XM_TX_NO_CRC = 1<<1, /* Bit 1: 2136 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2137 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: 2137 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2138 }; 2138 };
2139 2139
2140 /* XM_TX_RT_LIM 16 bit r/w Trans 2140 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2141 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: 2141 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2142 2142
2143 2143
2144 /* XM_TX_STIME 16 bit r/w Trans 2144 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2145 #define XM_STIME_MSK 0x7f /* Bit 6..0: 2145 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2146 2146
2147 2147
2148 /* XM_TX_IPG 16 bit r/w Trans 2148 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2149 #define XM_IPG_MSK 0xff /* Bi 2149 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2150 2150
2151 2151
2152 /* XM_RX_CMD 16 bit r/w Recei 2152 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2153 enum { 2153 enum {
2154 XM_RX_LENERR_OK = 1<<8, /* Bit 8 2154 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2155 /* 2155 /* inrange error packets */
2156 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 2156 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2157 /* 2157 /* jumbo packets */
2158 XM_RX_IPG_CAP = 1<<6, /* Bit 6 2158 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2159 XM_RX_TP_MD = 1<<5, /* Bit 5: 2159 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2160 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: 2160 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2161 XM_RX_SELF_RX = 1<<3, /* Bit 3: 2161 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2162 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (s 2162 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2163 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: 2163 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2164 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: 2164 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2165 }; 2165 };
2166 2166
2167 2167
2168 /* XM_GP_PORT 32 bit r/w Gener 2168 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2169 enum { 2169 enum {
2170 XM_GP_ANIP = 1<<6, /* Bit 6: (r 2170 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2171 XM_GP_FRC_INT = 1<<5, /* Bit 5: (s 2171 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2172 XM_GP_RES_MAC = 1<<3, /* Bit 3: (s 2172 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2173 XM_GP_RES_STAT = 1<<2, /* Bit 2: (s 2173 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2174 XM_GP_INP_ASS = 1<<0, /* Bit 0: (r 2174 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2175 }; 2175 };
2176 2176
2177 2177
2178 /* XM_IMSK 16 bit r/w Inter 2178 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2179 /* XM_ISRC 16 bit r/o Inter 2179 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2180 enum { 2180 enum {
2181 XM_IS_LNK_AE = 1<<14, /* Bit 14: 2181 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2182 XM_IS_TX_ABORT = 1<<13, /* Bit 13: 2182 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2183 XM_IS_FRC_INT = 1<<12, /* Bit 12: 2183 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2184 XM_IS_INP_ASS = 1<<11, /* Bit 11: 2184 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2185 XM_IS_LIPA_RC = 1<<10, /* Bit 10: 2185 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2186 XM_IS_RX_PAGE = 1<<9, /* Bit 9: 2186 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2187 XM_IS_TX_PAGE = 1<<8, /* Bit 8: 2187 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2188 XM_IS_AND = 1<<7, /* Bit 7: 2188 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2189 XM_IS_TSC_OV = 1<<6, /* Bit 6: 2189 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2190 XM_IS_RXC_OV = 1<<5, /* Bit 5: 2190 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2191 XM_IS_TXC_OV = 1<<4, /* Bit 4: 2191 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2192 XM_IS_RXF_OV = 1<<3, /* Bit 3: 2192 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2193 XM_IS_TXF_UR = 1<<2, /* Bit 2: 2193 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2194 XM_IS_TX_COMP = 1<<1, /* Bit 1: 2194 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2195 XM_IS_RX_COMP = 1<<0, /* Bit 0: 2195 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2196 2196
2197 XM_IMSK_DISABLE = 0xffff, 2197 XM_IMSK_DISABLE = 0xffff,
2198 }; 2198 };
2199 2199
2200 /* XM_HW_CFG 16 bit r/w Hardw 2200 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2201 enum { 2201 enum {
2202 XM_HW_GEN_EOP = 1<<3, /* Bit 3: 2202 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2203 XM_HW_COM4SIG = 1<<2, /* Bit 2: 2203 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2204 XM_HW_GMII_MD = 1<<0, /* Bit 0: 2204 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2205 }; 2205 };
2206 2206
2207 2207
2208 /* XM_TX_LO_WM 16 bit r/w Tx FI 2208 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2209 /* XM_TX_HI_WM 16 bit r/w Tx FI 2209 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2210 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 2210 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2211 2211
2212 /* XM_TX_THR 16 bit r/w Tx Re 2212 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2213 /* XM_HT_THR 16 bit r/w Host 2213 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2214 /* XM_RX_THR 16 bit r/w Rx Re 2214 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2215 #define XM_THR_MSK 0x03ff /* Bi 2215 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2216 2216
2217 2217
2218 /* XM_TX_STAT 32 bit r/o Tx St 2218 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2219 enum { 2219 enum {
2220 XM_ST_VALID = (1UL<<31), /* Bi 2220 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2221 XM_ST_BYTE_CNT = (0x3fffL<<17), 2221 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2222 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bi 2222 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2223 XM_ST_EX_COL = 1<<11, /* Bi 2223 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2224 XM_ST_EX_DEF = 1<<10, /* Bi 2224 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2225 XM_ST_BURST = 1<<9, /* Bi 2225 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2226 XM_ST_DEFER = 1<<8, /* Bi 2226 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2227 XM_ST_BC = 1<<7, /* Bi 2227 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2228 XM_ST_MC = 1<<6, /* Bi 2228 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2229 XM_ST_UC = 1<<5, /* Bi 2229 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2230 XM_ST_TX_UR = 1<<4, /* Bi 2230 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
2231 XM_ST_CS_ERR = 1<<3, /* Bi 2231 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2232 XM_ST_LAT_COL = 1<<2, /* Bi 2232 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2233 XM_ST_MUL_COL = 1<<1, /* Bi 2233 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2234 XM_ST_SGN_COL = 1<<0, /* Bi 2234 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2235 }; 2235 };
2236 2236
2237 /* XM_RX_LO_WM 16 bit r/w Recei 2237 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2238 /* XM_RX_HI_WM 16 bit r/w Recei 2238 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2239 #define XM_RX_WM_MSK 0x03ff /* Bi 2239 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2240 2240
2241 2241
2242 /* XM_DEV_ID 32 bit r/o Devic 2242 /* XM_DEV_ID 32 bit r/o Device ID Register */
2243 #define XM_DEV_OUI (0x00ffffffUL<<8) 2243 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2244 #define XM_DEV_REV (0x07L << 5) 2244 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2245 2245
2246 2246
2247 /* XM_MODE 32 bit r/w Mode 2247 /* XM_MODE 32 bit r/w Mode Register */
2248 enum { 2248 enum {
2249 XM_MD_ENA_REJ = 1<<26, /* Bit 26: 2249 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2250 XM_MD_SPOE_E = 1<<25, /* Bit 25: 2250 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2251 2251 /* extern generated */
2252 XM_MD_TX_REP = 1<<24, /* Bit 24: 2252 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2253 XM_MD_SPOFF_I = 1<<23, /* Bit 23: 2253 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2254 2254 /* intern generated */
2255 XM_MD_LE_STW = 1<<22, /* Bit 22: 2255 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2256 XM_MD_TX_CONT = 1<<21, /* Bit 21: 2256 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2257 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: ( 2257 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2258 XM_MD_ATS = 1<<19, /* Bit 19: 2258 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2259 XM_MD_SPOL_I = 1<<18, /* Bit 18: 2259 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2260 2260 /* intern generated */
2261 XM_MD_SPOH_I = 1<<17, /* Bit 17: 2261 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2262 2262 /* intern generated */
2263 XM_MD_CAP = 1<<16, /* Bit 16: 2263 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2264 XM_MD_ENA_HASH = 1<<15, /* Bit 15: 2264 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2265 XM_MD_CSA = 1<<14, /* Bit 14: 2265 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2266 XM_MD_CAA = 1<<13, /* Bit 13: 2266 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2267 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: 2267 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2268 XM_MD_RX_RUNT = 1<<11, /* Bit 11: 2268 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2269 XM_MD_RX_IRLE = 1<<10, /* Bit 10: 2269 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2270 XM_MD_RX_LONG = 1<<9, /* Bit 9: 2270 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2271 XM_MD_RX_CRCE = 1<<8, /* Bit 8: 2271 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2272 XM_MD_RX_ERR = 1<<7, /* Bit 7: 2272 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2273 XM_MD_DIS_UC = 1<<6, /* Bit 6: 2273 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2274 XM_MD_DIS_MC = 1<<5, /* Bit 5: 2274 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2275 XM_MD_DIS_BC = 1<<4, /* Bit 4: 2275 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2276 XM_MD_ENA_PROM = 1<<3, /* Bit 3: 2276 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2277 XM_MD_ENA_BE = 1<<2, /* Bit 2: 2277 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2278 XM_MD_FTF = 1<<1, /* Bit 1: ( 2278 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2279 XM_MD_FRF = 1<<0, /* Bit 0: ( 2279 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2280 }; 2280 };
2281 2281
2282 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD 2282 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2283 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_M 2283 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2284 XM_MD_RX_CRCE | XM_M 2284 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2285 2285
2286 /* XM_STAT_CMD 16 bit r/w Stati 2286 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2287 enum { 2287 enum {
2288 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (s 2288 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2289 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (s 2289 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2290 XM_SC_CP_RXC = 1<<3, /* Bit 3: 2290 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2291 XM_SC_CP_TXC = 1<<2, /* Bit 2: 2291 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2292 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (s 2292 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2293 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (s 2293 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2294 }; 2294 };
2295 2295
2296 2296
2297 /* XM_RX_CNT_EV 32 bit r/o Rx Co 2297 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2298 /* XM_RX_EV_MSK 32 bit r/w Rx Co 2298 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2299 enum { 2299 enum {
2300 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 2300 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2301 XMR_1023B_OV = 1<<30, /* Bit 30: 2301 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2302 XMR_511B_OV = 1<<29, /* Bit 29: 2302 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2303 XMR_255B_OV = 1<<28, /* Bit 28: 2303 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2304 XMR_127B_OV = 1<<27, /* Bit 27: 2304 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2305 XMR_64B_OV = 1<<26, /* Bit 26: 2305 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2306 XMR_UTIL_OV = 1<<25, /* Bit 25: 2306 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2307 XMR_UTIL_UR = 1<<24, /* Bit 24: 2307 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2308 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: 2308 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2309 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: 2309 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2310 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: 2310 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2311 XMR_RUNT_OV = 1<<19, /* Bit 19: 2311 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2312 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: 2312 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2313 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: 2313 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2314 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: 2314 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2315 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: 2315 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2316 XMR_FIFO_OV = 1<<13, /* Bit 13: 2316 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2317 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: 2317 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2318 XMR_FMISS_OV = 1<<11, /* Bit 11: 2318 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2319 XMR_BURST = 1<<10, /* Bit 10: 2319 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2320 XMR_INV_MOC = 1<<9, /* Bit 9: 2320 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2321 XMR_INV_MP = 1<<8, /* Bit 8: 2321 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2322 XMR_MCTRL_OV = 1<<7, /* Bit 7: 2322 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2323 XMR_MPAUSE_OV = 1<<6, /* Bit 6: 2323 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2324 XMR_UC_OK_OV = 1<<5, /* Bit 5: 2324 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2325 XMR_MC_OK_OV = 1<<4, /* Bit 4: 2325 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2326 XMR_BC_OK_OV = 1<<3, /* Bit 3: 2326 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2327 XMR_OK_LO_OV = 1<<2, /* Bit 2: 2327 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2328 XMR_OK_HI_OV = 1<<1, /* Bit 1: 2328 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2329 XMR_OK_OV = 1<<0, /* Bit 0: 2329 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2330 }; 2330 };
2331 2331
2332 #define XMR_DEF_MSK (XMR_OK_LO_OV 2332 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2333 2333
2334 /* XM_TX_CNT_EV 32 bit r/o Tx Co 2334 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2335 /* XM_TX_EV_MSK 32 bit r/w Tx Co 2335 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2336 enum { 2336 enum {
2337 XMT_MAX_SZ_OV = 1<<25, /* Bi 2337 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2338 XMT_1023B_OV = 1<<24, /* Bi 2338 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2339 XMT_511B_OV = 1<<23, /* Bi 2339 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2340 XMT_255B_OV = 1<<22, /* Bi 2340 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2341 XMT_127B_OV = 1<<21, /* Bi 2341 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2342 XMT_64B_OV = 1<<20, /* Bi 2342 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2343 XMT_UTIL_OV = 1<<19, /* Bi 2343 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2344 XMT_UTIL_UR = 1<<18, /* Bi 2344 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2345 XMT_CS_ERR_OV = 1<<17, /* Bi 2345 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2346 XMT_FIFO_UR_OV = 1<<16, /* Bi 2346 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2347 XMT_EX_DEF_OV = 1<<15, /* Bi 2347 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2348 XMT_DEF = 1<<14, /* Bit 14: 2348 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2349 XMT_LAT_COL_OV = 1<<13, /* Bi 2349 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2350 XMT_ABO_COL_OV = 1<<12, /* Bi 2350 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2351 XMT_MUL_COL_OV = 1<<11, /* Bi 2351 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2352 XMT_SNG_COL = 1<<10, /* Bi 2352 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2353 XMT_MCTRL_OV = 1<<9, /* Bi 2353 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2354 XMT_MPAUSE = 1<<8, /* Bi 2354 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2355 XMT_BURST = 1<<7, /* Bi 2355 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2356 XMT_LONG = 1<<6, /* Bi 2356 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2357 XMT_UC_OK_OV = 1<<5, /* Bi 2357 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2358 XMT_MC_OK_OV = 1<<4, /* Bi 2358 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2359 XMT_BC_OK_OV = 1<<3, /* Bi 2359 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2360 XMT_OK_LO_OV = 1<<2, /* Bi 2360 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2361 XMT_OK_HI_OV = 1<<1, /* Bi 2361 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2362 XMT_OK_OV = 1<<0, /* Bi 2362 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2363 }; 2363 };
2364 2364
2365 #define XMT_DEF_MSK (XMT_OK_LO_OV 2365 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2366 2366
2367 struct skge_rx_desc { 2367 struct skge_rx_desc {
2368 u32 control; 2368 u32 control;
2369 u32 next_offset; 2369 u32 next_offset;
2370 u32 dma_lo; 2370 u32 dma_lo;
2371 u32 dma_hi; 2371 u32 dma_hi;
2372 u32 status; 2372 u32 status;
2373 u32 timestamp; 2373 u32 timestamp;
2374 u16 csum2; 2374 u16 csum2;
2375 u16 csum1; 2375 u16 csum1;
2376 u16 csum2_start; 2376 u16 csum2_start;
2377 u16 csum1_start; 2377 u16 csum1_start;
2378 }; 2378 };
2379 2379
2380 struct skge_tx_desc { 2380 struct skge_tx_desc {
2381 u32 control; 2381 u32 control;
2382 u32 next_offset; 2382 u32 next_offset;
2383 u32 dma_lo; 2383 u32 dma_lo;
2384 u32 dma_hi; 2384 u32 dma_hi;
2385 u32 status; 2385 u32 status;
2386 u32 csum_offs; 2386 u32 csum_offs;
2387 u16 csum_write; 2387 u16 csum_write;
2388 u16 csum_start; 2388 u16 csum_start;
2389 u32 rsvd; 2389 u32 rsvd;
2390 }; 2390 };
2391 2391
2392 struct skge_element { 2392 struct skge_element {
2393 struct skge_element *next; 2393 struct skge_element *next;
2394 void *desc; 2394 void *desc;
2395 struct sk_buff *skb; 2395 struct sk_buff *skb;
2396 DECLARE_PCI_UNMAP_ADDR(mapaddr); 2396 DECLARE_PCI_UNMAP_ADDR(mapaddr);
2397 DECLARE_PCI_UNMAP_LEN(maplen); 2397 DECLARE_PCI_UNMAP_LEN(maplen);
2398 }; 2398 };
2399 2399
2400 struct skge_ring { 2400 struct skge_ring {
2401 struct skge_element *to_clean; 2401 struct skge_element *to_clean;
2402 struct skge_element *to_use; 2402 struct skge_element *to_use;
2403 struct skge_element *start; 2403 struct skge_element *start;
2404 unsigned long count; 2404 unsigned long count;
2405 }; 2405 };
2406 2406
2407 2407
2408 struct skge_hw { 2408 struct skge_hw {
2409 void __iomem *regs; 2409 void __iomem *regs;
2410 struct pci_dev *pdev; 2410 struct pci_dev *pdev;
2411 spinlock_t hw_lock; 2411 spinlock_t hw_lock;
2412 u32 intr_mask; 2412 u32 intr_mask;
2413 struct net_device *dev[2]; 2413 struct net_device *dev[2];
2414 2414
2415 u8 chip_id; 2415 u8 chip_id;
2416 u8 chip_rev; 2416 u8 chip_rev;
2417 u8 copper; 2417 u8 copper;
2418 u8 ports; 2418 u8 ports;
2419 u8 phy_type; 2419 u8 phy_type;
2420 2420
2421 u32 ram_size; 2421 u32 ram_size;
2422 u32 ram_offset; 2422 u32 ram_offset;
2423 u16 phy_addr; 2423 u16 phy_addr;
2424 spinlock_t phy_lock; 2424 spinlock_t phy_lock;
2425 struct tasklet_struct phy_task; 2425 struct tasklet_struct phy_task;
2426 }; 2426 };
2427 2427
2428 enum pause_control { 2428 enum pause_control {
2429 FLOW_MODE_NONE = 1, /* No Fl 2429 FLOW_MODE_NONE = 1, /* No Flow-Control */
2430 FLOW_MODE_LOC_SEND = 2, /* Local 2430 FLOW_MODE_LOC_SEND = 2, /* Local station sends PAUSE */
2431 FLOW_MODE_SYMMETRIC = 3, /* Both 2431 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2432 FLOW_MODE_SYM_OR_REM = 4, /* Both 2432 FLOW_MODE_SYM_OR_REM = 4, /* Both stations may send PAUSE or
2433 * just 2433 * just the remote station may send PAUSE
2434 */ 2434 */
2435 }; 2435 };
2436 2436
2437 enum pause_status { 2437 enum pause_status {
2438 FLOW_STAT_INDETERMINATED=0, /* in 2438 FLOW_STAT_INDETERMINATED=0, /* indeterminated */
2439 FLOW_STAT_NONE, /* No 2439 FLOW_STAT_NONE, /* No Flow Control */
2440 FLOW_STAT_REM_SEND, /* Re 2440 FLOW_STAT_REM_SEND, /* Remote Station sends PAUSE */
2441 FLOW_STAT_LOC_SEND, /* Lo 2441 FLOW_STAT_LOC_SEND, /* Local station sends PAUSE */
2442 FLOW_STAT_SYMMETRIC, /* Bo 2442 FLOW_STAT_SYMMETRIC, /* Both station may send PAUSE */
2443 }; 2443 };
2444 2444
2445 2445
2446 struct skge_port { 2446 struct skge_port {
2447 struct skge_hw *hw; 2447 struct skge_hw *hw;
2448 struct net_device *netdev; 2448 struct net_device *netdev;
2449 struct napi_struct napi; 2449 struct napi_struct napi;
2450 int port; 2450 int port;
2451 u32 msg_enable; 2451 u32 msg_enable;
2452 2452
2453 struct skge_ring tx_ring; 2453 struct skge_ring tx_ring;
2454 2454
2455 struct skge_ring rx_ring ____cach 2455 struct skge_ring rx_ring ____cacheline_aligned_in_smp;
2456 unsigned int rx_buf_size; 2456 unsigned int rx_buf_size;
2457 2457
2458 struct timer_list link_timer; 2458 struct timer_list link_timer;
2459 enum pause_control flow_control; 2459 enum pause_control flow_control;
2460 enum pause_status flow_status; 2460 enum pause_status flow_status;
2461 u8 rx_csum; 2461 u8 rx_csum;
2462 u8 blink_on; 2462 u8 blink_on;
2463 u8 wol; 2463 u8 wol;
2464 u8 autoneg; /* AU 2464 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2465 u8 duplex; /* DU 2465 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2466 u16 speed; /* SP 2466 u16 speed; /* SPEED_1000, SPEED_100, ... */
2467 u32 advertising; 2467 u32 advertising;
2468 2468
2469 void *mem; /* PC 2469 void *mem; /* PCI memory for rings */
2470 dma_addr_t dma; 2470 dma_addr_t dma;
2471 unsigned long mem_size; 2471 unsigned long mem_size;
2472 #ifdef CONFIG_SKGE_DEBUG 2472 #ifdef CONFIG_SKGE_DEBUG
2473 struct dentry *debugfs; 2473 struct dentry *debugfs;
2474 #endif 2474 #endif
2475 }; 2475 };
2476 2476
2477 2477
2478 /* Register accessor for memory mapped device 2478 /* Register accessor for memory mapped device */
2479 static inline u32 skge_read32(const struct sk 2479 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2480 { 2480 {
2481 return readl(hw->regs + reg); 2481 return readl(hw->regs + reg);
2482 } 2482 }
2483 2483
2484 static inline u16 skge_read16(const struct sk 2484 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2485 { 2485 {
2486 return readw(hw->regs + reg); 2486 return readw(hw->regs + reg);
2487 } 2487 }
2488 2488
2489 static inline u8 skge_read8(const struct skge 2489 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2490 { 2490 {
2491 return readb(hw->regs + reg); 2491 return readb(hw->regs + reg);
2492 } 2492 }
2493 2493
2494 static inline void skge_write32(const struct 2494 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2495 { 2495 {
2496 writel(val, hw->regs + reg); 2496 writel(val, hw->regs + reg);
2497 } 2497 }
2498 2498
2499 static inline void skge_write16(const struct 2499 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2500 { 2500 {
2501 writew(val, hw->regs + reg); 2501 writew(val, hw->regs + reg);
2502 } 2502 }
2503 2503
2504 static inline void skge_write8(const struct s 2504 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2505 { 2505 {
2506 writeb(val, hw->regs + reg); 2506 writeb(val, hw->regs + reg);
2507 } 2507 }
2508 2508
2509 /* MAC Related Registers inside the device. * 2509 /* MAC Related Registers inside the device. */
2510 #define SK_REG(port,reg) (((port)<<7)+ 2510 #define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2511 #define SK_XMAC_REG(port, reg) \ 2511 #define SK_XMAC_REG(port, reg) \
2512 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 2512 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2513 2513
2514 static inline u32 xm_read32(const struct skge 2514 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2515 { 2515 {
2516 u32 v; 2516 u32 v;
2517 v = skge_read16(hw, SK_XMAC_REG(port, 2517 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2518 v |= (u32)skge_read16(hw, SK_XMAC_REG 2518 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2519 return v; 2519 return v;
2520 } 2520 }
2521 2521
2522 static inline u16 xm_read16(const struct skge 2522 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2523 { 2523 {
2524 return skge_read16(hw, SK_XMAC_REG(po 2524 return skge_read16(hw, SK_XMAC_REG(port,reg));
2525 } 2525 }
2526 2526
2527 static inline void xm_write32(const struct sk 2527 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2528 { 2528 {
2529 skge_write16(hw, SK_XMAC_REG(port,r), 2529 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2530 skge_write16(hw, SK_XMAC_REG(port,r+2 2530 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2531 } 2531 }
2532 2532
2533 static inline void xm_write16(const struct sk 2533 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2534 { 2534 {
2535 skge_write16(hw, SK_XMAC_REG(port,r), 2535 skge_write16(hw, SK_XMAC_REG(port,r), v);
2536 } 2536 }
2537 2537
2538 static inline void xm_outhash(const struct sk 2538 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2539 const u8 * 2539 const u8 *hash)
2540 { 2540 {
2541 xm_write16(hw, port, reg, (u16)hash 2541 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2542 xm_write16(hw, port, reg+2, (u16)hash 2542 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2543 xm_write16(hw, port, reg+4, (u16)hash 2543 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2544 xm_write16(hw, port, reg+6, (u16)hash 2544 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2545 } 2545 }
2546 2546
2547 static inline void xm_outaddr(const struct sk 2547 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2548 const u8 * 2548 const u8 *addr)
2549 { 2549 {
2550 xm_write16(hw, port, reg, (u16)addr 2550 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2551 xm_write16(hw, port, reg+2, (u16)addr 2551 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2552 xm_write16(hw, port, reg+4, (u16)addr 2552 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2553 } 2553 }
2554 2554
2555 #define SK_GMAC_REG(port,reg) \ 2555 #define SK_GMAC_REG(port,reg) \
2556 (BASE_GMAC_1 + (port) * (BASE_GMAC_2- 2556 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2557 2557
2558 static inline u16 gma_read16(const struct skg 2558 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2559 { 2559 {
2560 return skge_read16(hw, SK_GMAC_REG(po 2560 return skge_read16(hw, SK_GMAC_REG(port,reg));
2561 } 2561 }
2562 2562
2563 static inline u32 gma_read32(const struct skg 2563 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2564 { 2564 {
2565 return (u32) skge_read16(hw, SK_GMAC_ 2565 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2566 | ((u32)skge_read16(hw, SK_GM 2566 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2567 } 2567 }
2568 2568
2569 static inline void gma_write16(const struct s 2569 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2570 { 2570 {
2571 skge_write16(hw, SK_GMAC_REG(port,r), 2571 skge_write16(hw, SK_GMAC_REG(port,r), v);
2572 } 2572 }
2573 2573
2574 static inline void gma_set_addr(struct skge_h 2574 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2575 const u8 2575 const u8 *addr)
2576 { 2576 {
2577 gma_write16(hw, port, reg, (u16) add 2577 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2578 gma_write16(hw, port, reg+4,(u16) add 2578 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2579 gma_write16(hw, port, reg+8,(u16) add 2579 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2580 } 2580 }
2581 2581
2582 #endif 2582 #endif
2583 2583
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