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1 /********************************************* 1 /******************************************************************************
2 * 2 *
3 * (C)Copyright 1998,1999 SysKonnect, 3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & 4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 * 5 *
6 * See the file "skfddi.c" for further in 6 * See the file "skfddi.c" for further information.
7 * 7 *
8 * This program is free software; you can 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either v 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * The information in this file is provid 13 * The information in this file is provided "AS IS" without warranty.
14 * 14 *
15 ********************************************* 15 ******************************************************************************/
16 16
17 #ifndef lint 17 #ifndef lint
18 static char const ID_sccs[] = "@(#)hwmtm.c 18 static char const ID_sccs[] = "@(#)hwmtm.c 1.40 99/05/31 (C) SK" ;
19 #endif 19 #endif
20 20
21 #define HWMTM 21 #define HWMTM
22 22
23 #ifndef FDDI 23 #ifndef FDDI
24 #define FDDI 24 #define FDDI
25 #endif 25 #endif
26 26
27 #include "h/types.h" 27 #include "h/types.h"
28 #include "h/fddi.h" 28 #include "h/fddi.h"
29 #include "h/smc.h" 29 #include "h/smc.h"
30 #include "h/supern_2.h" 30 #include "h/supern_2.h"
31 #include "h/skfbiinc.h" 31 #include "h/skfbiinc.h"
32 32
33 /* 33 /*
34 -------------------------------------- 34 -------------------------------------------------------------
35 DOCUMENTATION 35 DOCUMENTATION
36 -------------------------------------- 36 -------------------------------------------------------------
37 BEGIN_MANUAL_ENTRY(DOCUMENTATION) 37 BEGIN_MANUAL_ENTRY(DOCUMENTATION)
38 38
39 T B D 39 T B D
40 40
41 END_MANUAL_ENTRY 41 END_MANUAL_ENTRY
42 */ 42 */
43 /* 43 /*
44 -------------------------------------- 44 -------------------------------------------------------------
45 LOCAL VARIABLES: 45 LOCAL VARIABLES:
46 -------------------------------------- 46 -------------------------------------------------------------
47 */ 47 */
48 #ifdef COMMON_MB_POOL 48 #ifdef COMMON_MB_POOL
49 static SMbuf *mb_start = 0 ; 49 static SMbuf *mb_start = 0 ;
50 static SMbuf *mb_free = 0 ; 50 static SMbuf *mb_free = 0 ;
51 static int mb_init = FALSE ; 51 static int mb_init = FALSE ;
52 static int call_count = 0 ; 52 static int call_count = 0 ;
53 #endif 53 #endif
54 54
55 /* 55 /*
56 -------------------------------------- 56 -------------------------------------------------------------
57 EXTERNE VARIABLES: 57 EXTERNE VARIABLES:
58 -------------------------------------- 58 -------------------------------------------------------------
59 */ 59 */
60 60
61 #ifdef DEBUG 61 #ifdef DEBUG
62 #ifndef DEBUG_BRD 62 #ifndef DEBUG_BRD
63 extern struct smt_debug debug ; 63 extern struct smt_debug debug ;
64 #endif 64 #endif
65 #endif 65 #endif
66 66
67 #ifdef NDIS_OS2 67 #ifdef NDIS_OS2
68 extern u_char offDepth ; 68 extern u_char offDepth ;
69 extern u_char force_irq_pending ; 69 extern u_char force_irq_pending ;
70 #endif 70 #endif
71 71
72 /* 72 /*
73 -------------------------------------- 73 -------------------------------------------------------------
74 LOCAL FUNCTIONS: 74 LOCAL FUNCTIONS:
75 -------------------------------------- 75 -------------------------------------------------------------
76 */ 76 */
77 77
78 static void queue_llc_rx(struct s_smc *smc, SM 78 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb);
79 static void smt_to_llc(struct s_smc *smc, SMbu 79 static void smt_to_llc(struct s_smc *smc, SMbuf *mb);
80 static void init_txd_ring(struct s_smc *smc); 80 static void init_txd_ring(struct s_smc *smc);
81 static void init_rxd_ring(struct s_smc *smc); 81 static void init_rxd_ring(struct s_smc *smc);
82 static void queue_txd_mb(struct s_smc *smc, SM 82 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb);
83 static u_long init_descr_ring(struct s_smc *sm 83 static u_long init_descr_ring(struct s_smc *smc, union s_fp_descr volatile *start,
84 int count); 84 int count);
85 static u_long repair_txd_ring(struct s_smc *sm 85 static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue);
86 static u_long repair_rxd_ring(struct s_smc *sm 86 static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue);
87 static SMbuf* get_llc_rx(struct s_smc *smc); 87 static SMbuf* get_llc_rx(struct s_smc *smc);
88 static SMbuf* get_txd_mb(struct s_smc *smc); 88 static SMbuf* get_txd_mb(struct s_smc *smc);
>> 89 static void mac_drv_clear_txd(struct s_smc *smc);
89 90
90 /* 91 /*
91 -------------------------------------- 92 -------------------------------------------------------------
92 EXTERNAL FUNCTIONS: 93 EXTERNAL FUNCTIONS:
93 -------------------------------------- 94 -------------------------------------------------------------
94 */ 95 */
95 /* The external SMT functions are listed 96 /* The external SMT functions are listed in cmtdef.h */
96 97
97 extern void* mac_drv_get_space(struct s_smc *s 98 extern void* mac_drv_get_space(struct s_smc *smc, unsigned int size);
98 extern void* mac_drv_get_desc_mem(struct s_smc 99 extern void* mac_drv_get_desc_mem(struct s_smc *smc, unsigned int size);
99 extern void init_board(struct s_smc *smc, u_ch <<
100 extern void mac_drv_fill_rxd(struct s_smc *smc 100 extern void mac_drv_fill_rxd(struct s_smc *smc);
101 extern void plc1_irq(struct s_smc *smc); <<
102 extern void mac_drv_tx_complete(struct s_smc * 101 extern void mac_drv_tx_complete(struct s_smc *smc,
103 volatile struc 102 volatile struct s_smt_fp_txd *txd);
104 extern void plc2_irq(struct s_smc *smc); <<
105 extern void mac1_irq(struct s_smc *smc, u_shor <<
106 extern void mac2_irq(struct s_smc *smc, u_shor <<
107 extern void mac3_irq(struct s_smc *smc, u_shor <<
108 extern void timer_irq(struct s_smc *smc); <<
109 extern void mac_drv_rx_complete(struct s_smc * 103 extern void mac_drv_rx_complete(struct s_smc *smc,
110 volatile struc 104 volatile struct s_smt_fp_rxd *rxd,
111 int frag_count 105 int frag_count, int len);
112 extern void mac_drv_requeue_rxd(struct s_smc * 106 extern void mac_drv_requeue_rxd(struct s_smc *smc,
113 volatile struc 107 volatile struct s_smt_fp_rxd *rxd,
114 int frag_count 108 int frag_count);
115 extern void init_plc(struct s_smc *smc); <<
116 extern void mac_drv_clear_rxd(struct s_smc *sm 109 extern void mac_drv_clear_rxd(struct s_smc *smc,
117 volatile struct 110 volatile struct s_smt_fp_rxd *rxd, int frag_count);
118 111
119 #ifdef USE_OS_CPY 112 #ifdef USE_OS_CPY
120 extern void hwm_cpy_rxd2mb(void); 113 extern void hwm_cpy_rxd2mb(void);
121 extern void hwm_cpy_txd2mb(void); 114 extern void hwm_cpy_txd2mb(void);
122 #endif 115 #endif
123 116
124 #ifdef ALL_RX_COMPLETE 117 #ifdef ALL_RX_COMPLETE
125 extern void mac_drv_all_receives_complete(void 118 extern void mac_drv_all_receives_complete(void);
126 #endif 119 #endif
127 120
128 extern u_long mac_drv_virt2phys(struct s_smc * 121 extern u_long mac_drv_virt2phys(struct s_smc *smc, void *virt);
129 extern u_long dma_master(struct s_smc *smc, vo 122 extern u_long dma_master(struct s_smc *smc, void *virt, int len, int flag);
130 123
131 #ifdef NDIS_OS2 124 #ifdef NDIS_OS2
132 extern void post_proc(void); 125 extern void post_proc(void);
133 #else 126 #else
134 extern void dma_complete(struct s_smc *smc, vo 127 extern void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr,
135 int flag); 128 int flag);
136 #endif 129 #endif
137 130
138 extern int init_fplus(struct s_smc *smc); <<
139 extern int mac_drv_rx_init(struct s_smc *smc, 131 extern int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
140 int la_len); 132 int la_len);
141 133
142 /* 134 /*
143 -------------------------------------- 135 -------------------------------------------------------------
144 PUBLIC FUNCTIONS: 136 PUBLIC FUNCTIONS:
145 -------------------------------------- 137 -------------------------------------------------------------
146 */ 138 */
147 void process_receive(struct s_smc *smc); 139 void process_receive(struct s_smc *smc);
148 void fddi_isr(struct s_smc *smc); 140 void fddi_isr(struct s_smc *smc);
149 void mac_drv_clear_txd(struct s_smc *smc); <<
150 void smt_free_mbuf(struct s_smc *smc, SMbuf *m 141 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
151 void init_driver_fplus(struct s_smc *smc); 142 void init_driver_fplus(struct s_smc *smc);
152 void mac_drv_rx_mode(struct s_smc *smc, int mo 143 void mac_drv_rx_mode(struct s_smc *smc, int mode);
153 void init_fddi_driver(struct s_smc *smc, u_cha 144 void init_fddi_driver(struct s_smc *smc, u_char *mac_addr);
154 void mac_drv_clear_tx_queue(struct s_smc *smc) 145 void mac_drv_clear_tx_queue(struct s_smc *smc);
155 void mac_drv_clear_rx_queue(struct s_smc *smc) 146 void mac_drv_clear_rx_queue(struct s_smc *smc);
156 void hwm_tx_frag(struct s_smc *smc, char far * 147 void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
157 int frame_status); 148 int frame_status);
158 void hwm_rx_frag(struct s_smc *smc, char far * 149 void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
159 int frame_status); 150 int frame_status);
160 151
161 int mac_drv_rx_frag(struct s_smc *smc, void fa <<
162 int mac_drv_init(struct s_smc *smc); 152 int mac_drv_init(struct s_smc *smc);
163 int hwm_tx_init(struct s_smc *smc, u_char fc, 153 int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
164 int frame_status); 154 int frame_status);
165 155
166 u_int mac_drv_check_space(void); 156 u_int mac_drv_check_space(void);
167 157
168 SMbuf* smt_get_mbuf(struct s_smc *smc); 158 SMbuf* smt_get_mbuf(struct s_smc *smc);
169 159
170 #ifdef DEBUG 160 #ifdef DEBUG
171 void mac_drv_debug_lev(void); 161 void mac_drv_debug_lev(void);
172 #endif 162 #endif
173 163
174 /* 164 /*
175 -------------------------------------- 165 -------------------------------------------------------------
176 MACROS: 166 MACROS:
177 -------------------------------------- 167 -------------------------------------------------------------
178 */ 168 */
179 #ifndef UNUSED 169 #ifndef UNUSED
180 #ifdef lint 170 #ifdef lint
181 #define UNUSED(x) (x) = (x) 171 #define UNUSED(x) (x) = (x)
182 #else 172 #else
183 #define UNUSED(x) 173 #define UNUSED(x)
184 #endif 174 #endif
185 #endif 175 #endif
186 176
187 #ifdef USE_CAN_ADDR 177 #ifdef USE_CAN_ADDR
188 #define MA smc->hw.fddi_canon_add 178 #define MA smc->hw.fddi_canon_addr.a
189 #define GROUP_ADDR_BIT 0x01 179 #define GROUP_ADDR_BIT 0x01
190 #else 180 #else
191 #define MA smc->hw.fddi_home_addr 181 #define MA smc->hw.fddi_home_addr.a
192 #define GROUP_ADDR_BIT 0x80 182 #define GROUP_ADDR_BIT 0x80
193 #endif 183 #endif
194 184
195 #define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+H 185 #define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+HWM_SYNC_TXD_COUNT+\
196 SMT_R1_RXD_COUNT+SMT_R 186 SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT)
197 187
198 #ifdef MB_OUTSIDE_SMC 188 #ifdef MB_OUTSIDE_SMC
199 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*siz 189 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd) +\
200 MAX_MBUF*sizeof(SMbuf) 190 MAX_MBUF*sizeof(SMbuf))
201 #define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*siz 191 #define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
202 #else 192 #else
203 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*siz 193 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
204 #endif 194 #endif
205 195
206 /* 196 /*
207 * define critical read for 16 Bit dri 197 * define critical read for 16 Bit drivers
208 */ 198 */
209 #if defined(NDIS_OS2) || defined(ODI2) 199 #if defined(NDIS_OS2) || defined(ODI2)
210 #define CR_READ(var) ((var) & 0xffff0000 | 200 #define CR_READ(var) ((var) & 0xffff0000 | ((var) & 0xffff))
211 #else 201 #else
212 #define CR_READ(var) (u_long)(var) !! 202 #define CR_READ(var) (__le32)(var)
213 #endif 203 #endif
214 204
215 #define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 205 #define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
216 IS_MINTR1 | IS_MINTR2 206 IS_MINTR1 | IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
217 IS_R1_C | IS_XA_C | I 207 IS_R1_C | IS_XA_C | IS_XS_C)
218 208
219 /* 209 /*
220 -------------------------------------- 210 -------------------------------------------------------------
221 INIT- AND SMT FUNCTIONS: 211 INIT- AND SMT FUNCTIONS:
222 -------------------------------------- 212 -------------------------------------------------------------
223 */ 213 */
224 214
225 215
226 /* 216 /*
227 * BEGIN_MANUAL_ENTRY(mac_drv_check_space 217 * BEGIN_MANUAL_ENTRY(mac_drv_check_space)
228 * u_int mac_drv_check_space() 218 * u_int mac_drv_check_space()
229 * 219 *
230 * function DOWNCALL (drvsr 220 * function DOWNCALL (drvsr.c)
231 * This function calculat 221 * This function calculates the needed non virtual
232 * memory for MBufs, RxD 222 * memory for MBufs, RxD and TxD descriptors etc.
233 * needed by the driver. 223 * needed by the driver.
234 * 224 *
235 * return u_int memory in byte 225 * return u_int memory in bytes
236 * 226 *
237 * END_MANUAL_ENTRY 227 * END_MANUAL_ENTRY
238 */ 228 */
239 u_int mac_drv_check_space(void) 229 u_int mac_drv_check_space(void)
240 { 230 {
241 #ifdef MB_OUTSIDE_SMC 231 #ifdef MB_OUTSIDE_SMC
242 #ifdef COMMON_MB_POOL 232 #ifdef COMMON_MB_POOL
243 call_count++ ; 233 call_count++ ;
244 if (call_count == 1) { 234 if (call_count == 1) {
245 return(EXT_VIRT_MEM) ; 235 return(EXT_VIRT_MEM) ;
246 } 236 }
247 else { 237 else {
248 return(EXT_VIRT_MEM_2) ; 238 return(EXT_VIRT_MEM_2) ;
249 } 239 }
250 #else 240 #else
251 return (EXT_VIRT_MEM) ; 241 return (EXT_VIRT_MEM) ;
252 #endif 242 #endif
253 #else 243 #else
254 return (0) ; 244 return (0) ;
255 #endif 245 #endif
256 } 246 }
257 247
258 /* 248 /*
259 * BEGIN_MANUAL_ENTRY(mac_drv_init) 249 * BEGIN_MANUAL_ENTRY(mac_drv_init)
260 * void mac_drv_init(smc) 250 * void mac_drv_init(smc)
261 * 251 *
262 * function DOWNCALL (drvsr 252 * function DOWNCALL (drvsr.c)
263 * In this function the h 253 * In this function the hardware module allocates it's
264 * memory. 254 * memory.
265 * The operating system d 255 * The operating system dependent module should call
266 * mac_drv_init once, aft 256 * mac_drv_init once, after the adatper is detected.
267 * END_MANUAL_ENTRY 257 * END_MANUAL_ENTRY
268 */ 258 */
269 int mac_drv_init(struct s_smc *smc) 259 int mac_drv_init(struct s_smc *smc)
270 { 260 {
271 if (sizeof(struct s_smt_fp_rxd) % 16) 261 if (sizeof(struct s_smt_fp_rxd) % 16) {
272 SMT_PANIC(smc,HWM_E0001,HWM_E0 262 SMT_PANIC(smc,HWM_E0001,HWM_E0001_MSG) ;
273 } 263 }
274 if (sizeof(struct s_smt_fp_txd) % 16) 264 if (sizeof(struct s_smt_fp_txd) % 16) {
275 SMT_PANIC(smc,HWM_E0002,HWM_E0 265 SMT_PANIC(smc,HWM_E0002,HWM_E0002_MSG) ;
276 } 266 }
277 267
278 /* 268 /*
279 * get the required memory for the RxD 269 * get the required memory for the RxDs and TxDs
280 */ 270 */
281 if (!(smc->os.hwm.descr_p = (union s_f 271 if (!(smc->os.hwm.descr_p = (union s_fp_descr volatile *)
282 mac_drv_get_desc_mem(smc,(u_in 272 mac_drv_get_desc_mem(smc,(u_int)
283 (RXD_TXD_COUNT+1)*sizeof(struc 273 (RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd)))) {
284 return(1) ; /* no space th 274 return(1) ; /* no space the hwm modul can't work */
285 } 275 }
286 276
287 /* 277 /*
288 * get the memory for the SMT MBufs 278 * get the memory for the SMT MBufs
289 */ 279 */
290 #ifndef MB_OUTSIDE_SMC 280 #ifndef MB_OUTSIDE_SMC
291 smc->os.hwm.mbuf_pool.mb_start=(SMbuf 281 smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
292 #else 282 #else
293 #ifndef COMMON_MB_POOL 283 #ifndef COMMON_MB_POOL
294 if (!(smc->os.hwm.mbuf_pool.mb_start = 284 if (!(smc->os.hwm.mbuf_pool.mb_start = (SMbuf *) mac_drv_get_space(smc,
295 MAX_MBUF*sizeof(SMbuf)))) { 285 MAX_MBUF*sizeof(SMbuf)))) {
296 return(1) ; /* no space th 286 return(1) ; /* no space the hwm modul can't work */
297 } 287 }
298 #else 288 #else
299 if (!mb_start) { 289 if (!mb_start) {
300 if (!(mb_start = (SMbuf *) mac 290 if (!(mb_start = (SMbuf *) mac_drv_get_space(smc,
301 MAX_MBUF*sizeof(SMbuf) 291 MAX_MBUF*sizeof(SMbuf)))) {
302 return(1) ; /* no 292 return(1) ; /* no space the hwm modul can't work */
303 } 293 }
304 } 294 }
305 #endif 295 #endif
306 #endif 296 #endif
307 return (0) ; 297 return (0) ;
308 } 298 }
309 299
310 /* 300 /*
311 * BEGIN_MANUAL_ENTRY(init_driver_fplus) 301 * BEGIN_MANUAL_ENTRY(init_driver_fplus)
312 * init_driver_fplus(smc) 302 * init_driver_fplus(smc)
313 * 303 *
314 * Sets hardware modul specific values for the 304 * Sets hardware modul specific values for the mode register 2
315 * (e.g. the byte alignment for the received f 305 * (e.g. the byte alignment for the received frames, the position of the
316 * least significant byte etc.) 306 * least significant byte etc.)
317 * END_MANUAL_ENTRY 307 * END_MANUAL_ENTRY
318 */ 308 */
319 void init_driver_fplus(struct s_smc *smc) 309 void init_driver_fplus(struct s_smc *smc)
320 { 310 {
321 smc->hw.fp.mdr2init = FM_LSB | FM_BMMO 311 smc->hw.fp.mdr2init = FM_LSB | FM_BMMODE | FM_ENNPRQ | FM_ENHSRQ | 3 ;
322 312
323 #ifdef PCI 313 #ifdef PCI
324 smc->hw.fp.mdr2init |= FM_CHKPAR | FM_ 314 smc->hw.fp.mdr2init |= FM_CHKPAR | FM_PARITY ;
325 #endif 315 #endif
326 smc->hw.fp.mdr3init = FM_MENRQAUNLCK | 316 smc->hw.fp.mdr3init = FM_MENRQAUNLCK | FM_MENRS ;
327 317
328 #ifdef USE_CAN_ADDR 318 #ifdef USE_CAN_ADDR
329 /* enable address bit swapping */ 319 /* enable address bit swapping */
330 smc->hw.fp.frselreg_init = FM_ENXMTADS 320 smc->hw.fp.frselreg_init = FM_ENXMTADSWAP | FM_ENRCVADSWAP ;
331 #endif 321 #endif
332 } 322 }
333 323
334 static u_long init_descr_ring(struct s_smc *sm 324 static u_long init_descr_ring(struct s_smc *smc,
335 union s_fp_descr 325 union s_fp_descr volatile *start,
336 int count) 326 int count)
337 { 327 {
338 int i ; 328 int i ;
339 union s_fp_descr volatile *d1 ; 329 union s_fp_descr volatile *d1 ;
340 union s_fp_descr volatile *d2 ; 330 union s_fp_descr volatile *d2 ;
341 u_long phys ; 331 u_long phys ;
342 332
343 DB_GEN("descr ring starts at = %x ",(v 333 DB_GEN("descr ring starts at = %x ",(void *)start,0,3) ;
344 for (i=count-1, d1=start; i ; i--) { 334 for (i=count-1, d1=start; i ; i--) {
345 d2 = d1 ; 335 d2 = d1 ;
346 d1++ ; /* descr is ow 336 d1++ ; /* descr is owned by the host */
347 d2->r.rxd_rbctrl = AIX_REVERSE !! 337 d2->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
348 d2->r.rxd_next = &d1->r ; 338 d2->r.rxd_next = &d1->r ;
349 phys = mac_drv_virt2phys(smc,( 339 phys = mac_drv_virt2phys(smc,(void *)d1) ;
350 d2->r.rxd_nrdadr = AIX_REVERSE !! 340 d2->r.rxd_nrdadr = cpu_to_le32(phys) ;
351 } 341 }
352 DB_GEN("descr ring ends at = %x ",(voi 342 DB_GEN("descr ring ends at = %x ",(void *)d1,0,3) ;
353 d1->r.rxd_rbctrl = AIX_REVERSE(BMU_CHE !! 343 d1->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
354 d1->r.rxd_next = &start->r ; 344 d1->r.rxd_next = &start->r ;
355 phys = mac_drv_virt2phys(smc,(void *)s 345 phys = mac_drv_virt2phys(smc,(void *)start) ;
356 d1->r.rxd_nrdadr = AIX_REVERSE(phys) ; !! 346 d1->r.rxd_nrdadr = cpu_to_le32(phys) ;
357 347
358 for (i=count, d1=start; i ; i--) { 348 for (i=count, d1=start; i ; i--) {
359 DRV_BUF_FLUSH(&d1->r,DDI_DMA_S 349 DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
360 d1++; 350 d1++;
361 } 351 }
362 return(phys) ; 352 return(phys) ;
363 } 353 }
364 354
365 static void init_txd_ring(struct s_smc *smc) 355 static void init_txd_ring(struct s_smc *smc)
366 { 356 {
367 struct s_smt_fp_txd volatile *ds ; 357 struct s_smt_fp_txd volatile *ds ;
368 struct s_smt_tx_queue *queue ; 358 struct s_smt_tx_queue *queue ;
369 u_long phys ; 359 u_long phys ;
370 360
371 /* 361 /*
372 * initialize the transmit descriptors 362 * initialize the transmit descriptors
373 */ 363 */
374 ds = (struct s_smt_fp_txd volatile *) 364 ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
375 SMT_R1_RXD_COUNT*sizeof(struct 365 SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
376 queue = smc->hw.fp.tx[QUEUE_A0] ; 366 queue = smc->hw.fp.tx[QUEUE_A0] ;
377 DB_GEN("Init async TxD ring, %d TxDs " 367 DB_GEN("Init async TxD ring, %d TxDs ",HWM_ASYNC_TXD_COUNT,0,3) ;
378 (void)init_descr_ring(smc,(union s_fp_ 368 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
379 HWM_ASYNC_TXD_COUNT) ; 369 HWM_ASYNC_TXD_COUNT) ;
380 phys = AIX_REVERSE(ds->txd_ntdadr) ; !! 370 phys = le32_to_cpu(ds->txd_ntdadr) ;
381 ds++ ; 371 ds++ ;
382 queue->tx_curr_put = queue->tx_curr_ge 372 queue->tx_curr_put = queue->tx_curr_get = ds ;
383 ds-- ; 373 ds-- ;
384 queue->tx_free = HWM_ASYNC_TXD_COUNT ; 374 queue->tx_free = HWM_ASYNC_TXD_COUNT ;
385 queue->tx_used = 0 ; 375 queue->tx_used = 0 ;
386 outpd(ADDR(B5_XA_DA),phys) ; 376 outpd(ADDR(B5_XA_DA),phys) ;
387 377
388 ds = (struct s_smt_fp_txd volatile *) 378 ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
389 HWM_ASYNC_TXD_COUNT*sizeof(str 379 HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
390 queue = smc->hw.fp.tx[QUEUE_S] ; 380 queue = smc->hw.fp.tx[QUEUE_S] ;
391 DB_GEN("Init sync TxD ring, %d TxDs ", 381 DB_GEN("Init sync TxD ring, %d TxDs ",HWM_SYNC_TXD_COUNT,0,3) ;
392 (void)init_descr_ring(smc,(union s_fp_ 382 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
393 HWM_SYNC_TXD_COUNT) ; 383 HWM_SYNC_TXD_COUNT) ;
394 phys = AIX_REVERSE(ds->txd_ntdadr) ; !! 384 phys = le32_to_cpu(ds->txd_ntdadr) ;
395 ds++ ; 385 ds++ ;
396 queue->tx_curr_put = queue->tx_curr_ge 386 queue->tx_curr_put = queue->tx_curr_get = ds ;
397 queue->tx_free = HWM_SYNC_TXD_COUNT ; 387 queue->tx_free = HWM_SYNC_TXD_COUNT ;
398 queue->tx_used = 0 ; 388 queue->tx_used = 0 ;
399 outpd(ADDR(B5_XS_DA),phys) ; 389 outpd(ADDR(B5_XS_DA),phys) ;
400 } 390 }
401 391
402 static void init_rxd_ring(struct s_smc *smc) 392 static void init_rxd_ring(struct s_smc *smc)
403 { 393 {
404 struct s_smt_fp_rxd volatile *ds ; 394 struct s_smt_fp_rxd volatile *ds ;
405 struct s_smt_rx_queue *queue ; 395 struct s_smt_rx_queue *queue ;
406 u_long phys ; 396 u_long phys ;
407 397
408 /* 398 /*
409 * initialize the receive descriptors 399 * initialize the receive descriptors
410 */ 400 */
411 ds = (struct s_smt_fp_rxd volatile *) 401 ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
412 queue = smc->hw.fp.rx[QUEUE_R1] ; 402 queue = smc->hw.fp.rx[QUEUE_R1] ;
413 DB_GEN("Init RxD ring, %d RxDs ",SMT_R 403 DB_GEN("Init RxD ring, %d RxDs ",SMT_R1_RXD_COUNT,0,3) ;
414 (void)init_descr_ring(smc,(union s_fp_ 404 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
415 SMT_R1_RXD_COUNT) ; 405 SMT_R1_RXD_COUNT) ;
416 phys = AIX_REVERSE(ds->rxd_nrdadr) ; !! 406 phys = le32_to_cpu(ds->rxd_nrdadr) ;
417 ds++ ; 407 ds++ ;
418 queue->rx_curr_put = queue->rx_curr_ge 408 queue->rx_curr_put = queue->rx_curr_get = ds ;
419 queue->rx_free = SMT_R1_RXD_COUNT ; 409 queue->rx_free = SMT_R1_RXD_COUNT ;
420 queue->rx_used = 0 ; 410 queue->rx_used = 0 ;
421 outpd(ADDR(B4_R1_DA),phys) ; 411 outpd(ADDR(B4_R1_DA),phys) ;
422 } 412 }
423 413
424 /* 414 /*
425 * BEGIN_MANUAL_ENTRY(init_fddi_driver) 415 * BEGIN_MANUAL_ENTRY(init_fddi_driver)
426 * void init_fddi_driver(smc,mac_addr) 416 * void init_fddi_driver(smc,mac_addr)
427 * 417 *
428 * initializes the driver and it's variables 418 * initializes the driver and it's variables
429 * 419 *
430 * END_MANUAL_ENTRY 420 * END_MANUAL_ENTRY
431 */ 421 */
432 void init_fddi_driver(struct s_smc *smc, u_cha 422 void init_fddi_driver(struct s_smc *smc, u_char *mac_addr)
433 { 423 {
434 SMbuf *mb ; 424 SMbuf *mb ;
435 int i ; 425 int i ;
436 426
437 init_board(smc,mac_addr) ; 427 init_board(smc,mac_addr) ;
438 (void)init_fplus(smc) ; 428 (void)init_fplus(smc) ;
439 429
440 /* 430 /*
441 * initialize the SMbufs for the SMT 431 * initialize the SMbufs for the SMT
442 */ 432 */
443 #ifndef COMMON_MB_POOL 433 #ifndef COMMON_MB_POOL
444 mb = smc->os.hwm.mbuf_pool.mb_start ; 434 mb = smc->os.hwm.mbuf_pool.mb_start ;
445 smc->os.hwm.mbuf_pool.mb_free = (SMbuf 435 smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
446 for (i = 0; i < MAX_MBUF; i++) { 436 for (i = 0; i < MAX_MBUF; i++) {
447 mb->sm_use_count = 1 ; 437 mb->sm_use_count = 1 ;
448 smt_free_mbuf(smc,mb) ; 438 smt_free_mbuf(smc,mb) ;
449 mb++ ; 439 mb++ ;
450 } 440 }
451 #else 441 #else
452 mb = mb_start ; 442 mb = mb_start ;
453 if (!mb_init) { 443 if (!mb_init) {
454 mb_free = 0 ; 444 mb_free = 0 ;
455 for (i = 0; i < MAX_MBUF; i++) 445 for (i = 0; i < MAX_MBUF; i++) {
456 mb->sm_use_count = 1 ; 446 mb->sm_use_count = 1 ;
457 smt_free_mbuf(smc,mb) 447 smt_free_mbuf(smc,mb) ;
458 mb++ ; 448 mb++ ;
459 } 449 }
460 mb_init = TRUE ; 450 mb_init = TRUE ;
461 } 451 }
462 #endif 452 #endif
463 453
464 /* 454 /*
465 * initialize the other variables 455 * initialize the other variables
466 */ 456 */
467 smc->os.hwm.llc_rx_pipe = smc->os.hwm. 457 smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
468 smc->os.hwm.txd_tx_pipe = smc->os.hwm. 458 smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
469 smc->os.hwm.pass_SMT = smc->os.hwm.pas 459 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
470 smc->os.hwm.pass_llc_promisc = TRUE ; 460 smc->os.hwm.pass_llc_promisc = TRUE ;
471 smc->os.hwm.queued_rx_frames = smc->os 461 smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
472 smc->os.hwm.detec_count = 0 ; 462 smc->os.hwm.detec_count = 0 ;
473 smc->os.hwm.rx_break = 0 ; 463 smc->os.hwm.rx_break = 0 ;
474 smc->os.hwm.rx_len_error = 0 ; 464 smc->os.hwm.rx_len_error = 0 ;
475 smc->os.hwm.isr_flag = FALSE ; 465 smc->os.hwm.isr_flag = FALSE ;
476 466
477 /* 467 /*
478 * make sure that the start pointer is 468 * make sure that the start pointer is 16 byte aligned
479 */ 469 */
480 i = 16 - ((long)smc->os.hwm.descr_p & 470 i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
481 if (i != 16) { 471 if (i != 16) {
482 DB_GEN("i = %d",i,0,3) ; 472 DB_GEN("i = %d",i,0,3) ;
483 smc->os.hwm.descr_p = (union s 473 smc->os.hwm.descr_p = (union s_fp_descr volatile *)
484 ((char *)smc->os.hwm.d 474 ((char *)smc->os.hwm.descr_p+i) ;
485 } 475 }
486 DB_GEN("pt to descr area = %x",(void * 476 DB_GEN("pt to descr area = %x",(void *)smc->os.hwm.descr_p,0,3) ;
487 477
488 init_txd_ring(smc) ; 478 init_txd_ring(smc) ;
489 init_rxd_ring(smc) ; 479 init_rxd_ring(smc) ;
490 mac_drv_fill_rxd(smc) ; 480 mac_drv_fill_rxd(smc) ;
491 481
492 init_plc(smc) ; 482 init_plc(smc) ;
493 } 483 }
494 484
495 485
496 SMbuf *smt_get_mbuf(struct s_smc *smc) 486 SMbuf *smt_get_mbuf(struct s_smc *smc)
497 { 487 {
498 register SMbuf *mb ; 488 register SMbuf *mb ;
499 489
500 #ifndef COMMON_MB_POOL 490 #ifndef COMMON_MB_POOL
501 mb = smc->os.hwm.mbuf_pool.mb_free ; 491 mb = smc->os.hwm.mbuf_pool.mb_free ;
502 #else 492 #else
503 mb = mb_free ; 493 mb = mb_free ;
504 #endif 494 #endif
505 if (mb) { 495 if (mb) {
506 #ifndef COMMON_MB_POOL 496 #ifndef COMMON_MB_POOL
507 smc->os.hwm.mbuf_pool.mb_free 497 smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
508 #else 498 #else
509 mb_free = mb->sm_next ; 499 mb_free = mb->sm_next ;
510 #endif 500 #endif
511 mb->sm_off = 8 ; 501 mb->sm_off = 8 ;
512 mb->sm_use_count = 1 ; 502 mb->sm_use_count = 1 ;
513 } 503 }
514 DB_GEN("get SMbuf: mb = %x",(void *)mb 504 DB_GEN("get SMbuf: mb = %x",(void *)mb,0,3) ;
515 return (mb) ; /* May be NULL */ 505 return (mb) ; /* May be NULL */
516 } 506 }
517 507
518 void smt_free_mbuf(struct s_smc *smc, SMbuf *m 508 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb)
519 { 509 {
520 510
521 if (mb) { 511 if (mb) {
522 mb->sm_use_count-- ; 512 mb->sm_use_count-- ;
523 DB_GEN("free_mbuf: sm_use_coun 513 DB_GEN("free_mbuf: sm_use_count = %d",mb->sm_use_count,0,3) ;
524 /* 514 /*
525 * If the use_count is != zero 515 * If the use_count is != zero the MBuf is queued
526 * more than once and must not 516 * more than once and must not queued into the
527 * free MBuf queue 517 * free MBuf queue
528 */ 518 */
529 if (!mb->sm_use_count) { 519 if (!mb->sm_use_count) {
530 DB_GEN("free SMbuf: mb 520 DB_GEN("free SMbuf: mb = %x",(void *)mb,0,3) ;
531 #ifndef COMMON_MB_POOL 521 #ifndef COMMON_MB_POOL
532 mb->sm_next = smc->os. 522 mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
533 smc->os.hwm.mbuf_pool. 523 smc->os.hwm.mbuf_pool.mb_free = mb ;
534 #else 524 #else
535 mb->sm_next = mb_free 525 mb->sm_next = mb_free ;
536 mb_free = mb ; 526 mb_free = mb ;
537 #endif 527 #endif
538 } 528 }
539 } 529 }
540 else 530 else
541 SMT_PANIC(smc,HWM_E0003,HWM_E0 531 SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
542 } 532 }
543 533
544 534
545 /* 535 /*
546 * BEGIN_MANUAL_ENTRY(mac_drv_repair_desc 536 * BEGIN_MANUAL_ENTRY(mac_drv_repair_descr)
547 * void mac_drv_repair_descr(smc) 537 * void mac_drv_repair_descr(smc)
548 * 538 *
549 * function called from SMT (HWM / hwmtm.c 539 * function called from SMT (HWM / hwmtm.c)
550 * The BMU is idle when this func 540 * The BMU is idle when this function is called.
551 * Mac_drv_repair_descr sets up t 541 * Mac_drv_repair_descr sets up the physical address
552 * for all receive and transmit q 542 * for all receive and transmit queues where the BMU
553 * should continue. 543 * should continue.
554 * It may be that the BMU was res 544 * It may be that the BMU was reseted during a fragmented
555 * transfer. In this case there a 545 * transfer. In this case there are some fragments which will
556 * never completed by the BMU. Th 546 * never completed by the BMU. The OWN bit of this fragments
557 * must be switched to be owned b 547 * must be switched to be owned by the host.
558 * 548 *
559 * Give a start command to the re 549 * Give a start command to the receive BMU.
560 * Start the transmit BMUs if tra 550 * Start the transmit BMUs if transmit frames pending.
561 * 551 *
562 * END_MANUAL_ENTRY 552 * END_MANUAL_ENTRY
563 */ 553 */
564 void mac_drv_repair_descr(struct s_smc *smc) 554 void mac_drv_repair_descr(struct s_smc *smc)
565 { 555 {
566 u_long phys ; 556 u_long phys ;
567 557
568 if (smc->hw.hw_state != STOPPED) { 558 if (smc->hw.hw_state != STOPPED) {
569 SK_BREAK() ; 559 SK_BREAK() ;
570 SMT_PANIC(smc,HWM_E0013,HWM_E0 560 SMT_PANIC(smc,HWM_E0013,HWM_E0013_MSG) ;
571 return ; 561 return ;
572 } 562 }
573 563
574 /* 564 /*
575 * repair tx queues: don't start 565 * repair tx queues: don't start
576 */ 566 */
577 phys = repair_txd_ring(smc,smc->hw.fp. 567 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_A0]) ;
578 outpd(ADDR(B5_XA_DA),phys) ; 568 outpd(ADDR(B5_XA_DA),phys) ;
579 if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) 569 if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) {
580 outpd(ADDR(B0_XA_CSR),CSR_STAR 570 outpd(ADDR(B0_XA_CSR),CSR_START) ;
581 } 571 }
582 phys = repair_txd_ring(smc,smc->hw.fp. 572 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_S]) ;
583 outpd(ADDR(B5_XS_DA),phys) ; 573 outpd(ADDR(B5_XS_DA),phys) ;
584 if (smc->hw.fp.tx_q[QUEUE_S].tx_used) 574 if (smc->hw.fp.tx_q[QUEUE_S].tx_used) {
585 outpd(ADDR(B0_XS_CSR),CSR_STAR 575 outpd(ADDR(B0_XS_CSR),CSR_START) ;
586 } 576 }
587 577
588 /* 578 /*
589 * repair rx queues 579 * repair rx queues
590 */ 580 */
591 phys = repair_rxd_ring(smc,smc->hw.fp. 581 phys = repair_rxd_ring(smc,smc->hw.fp.rx[QUEUE_R1]) ;
592 outpd(ADDR(B4_R1_DA),phys) ; 582 outpd(ADDR(B4_R1_DA),phys) ;
593 outpd(ADDR(B0_R1_CSR),CSR_START) ; 583 outpd(ADDR(B0_R1_CSR),CSR_START) ;
594 } 584 }
595 585
596 static u_long repair_txd_ring(struct s_smc *sm 586 static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue)
597 { 587 {
598 int i ; 588 int i ;
599 int tx_used ; 589 int tx_used ;
600 u_long phys ; 590 u_long phys ;
601 u_long tbctrl ; 591 u_long tbctrl ;
602 struct s_smt_fp_txd volatile *t ; 592 struct s_smt_fp_txd volatile *t ;
603 593
604 SK_UNUSED(smc) ; 594 SK_UNUSED(smc) ;
605 595
606 t = queue->tx_curr_get ; 596 t = queue->tx_curr_get ;
607 tx_used = queue->tx_used ; 597 tx_used = queue->tx_used ;
608 for (i = tx_used+queue->tx_free-1 ; i 598 for (i = tx_used+queue->tx_free-1 ; i ; i-- ) {
609 t = t->txd_next ; 599 t = t->txd_next ;
610 } 600 }
611 phys = AIX_REVERSE(t->txd_ntdadr) ; !! 601 phys = le32_to_cpu(t->txd_ntdadr) ;
612 602
613 t = queue->tx_curr_get ; 603 t = queue->tx_curr_get ;
614 while (tx_used) { 604 while (tx_used) {
615 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_F 605 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
616 tbctrl = AIX_REVERSE(t->txd_tb !! 606 tbctrl = le32_to_cpu(t->txd_tbctrl) ;
617 607
618 if (tbctrl & BMU_OWN) { 608 if (tbctrl & BMU_OWN) {
619 if (tbctrl & BMU_STF) 609 if (tbctrl & BMU_STF) {
620 break ; 610 break ; /* exit the loop */
621 } 611 }
622 else { 612 else {
623 /* 613 /*
624 * repair the 614 * repair the descriptor
625 */ 615 */
626 t->txd_tbctrl !! 616 t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
627 } 617 }
628 } 618 }
629 phys = AIX_REVERSE(t->txd_ntda !! 619 phys = le32_to_cpu(t->txd_ntdadr) ;
630 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_F 620 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
631 t = t->txd_next ; 621 t = t->txd_next ;
632 tx_used-- ; 622 tx_used-- ;
633 } 623 }
634 return(phys) ; 624 return(phys) ;
635 } 625 }
636 626
637 /* 627 /*
638 * Repairs the receive descriptor ring and ret 628 * Repairs the receive descriptor ring and returns the physical address
639 * where the BMU should continue working. 629 * where the BMU should continue working.
640 * 630 *
641 * o The physical address where the BMU w 631 * o The physical address where the BMU was stopped has to be
642 * determined. This is the next RxD aft 632 * determined. This is the next RxD after rx_curr_get with an OWN
643 * bit set. 633 * bit set.
644 * o The BMU should start working at begi 634 * o The BMU should start working at beginning of the next frame.
645 * RxDs with an OWN bit set but with a 635 * RxDs with an OWN bit set but with a reset STF bit should be
646 * skipped and owned by the driver (OWN 636 * skipped and owned by the driver (OWN = 0).
647 */ 637 */
648 static u_long repair_rxd_ring(struct s_smc *sm 638 static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue)
649 { 639 {
650 int i ; 640 int i ;
651 int rx_used ; 641 int rx_used ;
652 u_long phys ; 642 u_long phys ;
653 u_long rbctrl ; 643 u_long rbctrl ;
654 struct s_smt_fp_rxd volatile *r ; 644 struct s_smt_fp_rxd volatile *r ;
655 645
656 SK_UNUSED(smc) ; 646 SK_UNUSED(smc) ;
657 647
658 r = queue->rx_curr_get ; 648 r = queue->rx_curr_get ;
659 rx_used = queue->rx_used ; 649 rx_used = queue->rx_used ;
660 for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- 650 for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- ) {
661 r = r->rxd_next ; 651 r = r->rxd_next ;
662 } 652 }
663 phys = AIX_REVERSE(r->rxd_nrdadr) ; !! 653 phys = le32_to_cpu(r->rxd_nrdadr) ;
664 654
665 r = queue->rx_curr_get ; 655 r = queue->rx_curr_get ;
666 while (rx_used) { 656 while (rx_used) {
667 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_F 657 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
668 rbctrl = AIX_REVERSE(r->rxd_rb !! 658 rbctrl = le32_to_cpu(r->rxd_rbctrl) ;
669 659
670 if (rbctrl & BMU_OWN) { 660 if (rbctrl & BMU_OWN) {
671 if (rbctrl & BMU_STF) 661 if (rbctrl & BMU_STF) {
672 break ; 662 break ; /* exit the loop */
673 } 663 }
674 else { 664 else {
675 /* 665 /*
676 * repair the 666 * repair the descriptor
677 */ 667 */
678 r->rxd_rbctrl !! 668 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
679 } 669 }
680 } 670 }
681 phys = AIX_REVERSE(r->rxd_nrda !! 671 phys = le32_to_cpu(r->rxd_nrdadr) ;
682 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_F 672 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
683 r = r->rxd_next ; 673 r = r->rxd_next ;
684 rx_used-- ; 674 rx_used-- ;
685 } 675 }
686 return(phys) ; 676 return(phys) ;
687 } 677 }
688 678
689 679
690 /* 680 /*
691 -------------------------------------- 681 -------------------------------------------------------------
692 INTERRUPT SERVICE ROUTINE: 682 INTERRUPT SERVICE ROUTINE:
693 -------------------------------------- 683 -------------------------------------------------------------
694 */ 684 */
695 685
696 /* 686 /*
697 * BEGIN_MANUAL_ENTRY(fddi_isr) 687 * BEGIN_MANUAL_ENTRY(fddi_isr)
698 * void fddi_isr(smc) 688 * void fddi_isr(smc)
699 * 689 *
700 * function DOWNCALL (drvsr.c) 690 * function DOWNCALL (drvsr.c)
701 * interrupt service routine, han 691 * interrupt service routine, handles the interrupt requests
702 * generated by the FDDI adapter. 692 * generated by the FDDI adapter.
703 * 693 *
704 * NOTE: The operating system dependent 694 * NOTE: The operating system dependent module must garantee that the
705 * interrupts of the adapter are 695 * interrupts of the adapter are disabled when it calls fddi_isr.
706 * 696 *
707 * About the USE_BREAK_ISR mechanismn: 697 * About the USE_BREAK_ISR mechanismn:
708 * 698 *
709 * The main requirement of this mechanism 699 * The main requirement of this mechanismn is to force an timer IRQ when
710 * leaving process_receive() with leave_i 700 * leaving process_receive() with leave_isr set. process_receive() may
711 * be called at any time from anywhere! 701 * be called at any time from anywhere!
712 * To be sure we don't miss such event we 702 * To be sure we don't miss such event we set 'force_irq' per default.
713 * We have to force and Timer IRQ if 'smc 703 * We have to force and Timer IRQ if 'smc->os.hwm.leave_isr' AND
714 * 'force_irq' are set. 'force_irq' may b 704 * 'force_irq' are set. 'force_irq' may be reset if a receive complete
715 * IRQ is pending. 705 * IRQ is pending.
716 * 706 *
717 * END_MANUAL_ENTRY 707 * END_MANUAL_ENTRY
718 */ 708 */
719 void fddi_isr(struct s_smc *smc) 709 void fddi_isr(struct s_smc *smc)
720 { 710 {
721 u_long is ; /* ISR 711 u_long is ; /* ISR source */
722 u_short stu, stl ; 712 u_short stu, stl ;
723 SMbuf *mb ; 713 SMbuf *mb ;
724 714
725 #ifdef USE_BREAK_ISR 715 #ifdef USE_BREAK_ISR
726 int force_irq ; 716 int force_irq ;
727 #endif 717 #endif
728 718
729 #ifdef ODI2 719 #ifdef ODI2
730 if (smc->os.hwm.rx_break) { 720 if (smc->os.hwm.rx_break) {
731 mac_drv_fill_rxd(smc) ; 721 mac_drv_fill_rxd(smc) ;
732 if (smc->hw.fp.rx_q[QUEUE_R1]. 722 if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
733 smc->os.hwm.rx_break = 723 smc->os.hwm.rx_break = 0 ;
734 process_receive(smc) ; 724 process_receive(smc) ;
735 } 725 }
736 else { 726 else {
737 smc->os.hwm.detec_coun 727 smc->os.hwm.detec_count = 0 ;
738 smt_force_irq(smc) ; 728 smt_force_irq(smc) ;
739 } 729 }
740 } 730 }
741 #endif 731 #endif
742 smc->os.hwm.isr_flag = TRUE ; 732 smc->os.hwm.isr_flag = TRUE ;
743 733
744 #ifdef USE_BREAK_ISR 734 #ifdef USE_BREAK_ISR
745 force_irq = TRUE ; 735 force_irq = TRUE ;
746 if (smc->os.hwm.leave_isr) { 736 if (smc->os.hwm.leave_isr) {
747 smc->os.hwm.leave_isr = FALSE 737 smc->os.hwm.leave_isr = FALSE ;
748 process_receive(smc) ; 738 process_receive(smc) ;
749 } 739 }
750 #endif 740 #endif
751 741
752 while ((is = GET_ISR() & ISR_MASK)) { 742 while ((is = GET_ISR() & ISR_MASK)) {
753 NDD_TRACE("CH0B",is,0,0) ; 743 NDD_TRACE("CH0B",is,0,0) ;
754 DB_GEN("ISA = 0x%x",is,0,7) ; 744 DB_GEN("ISA = 0x%x",is,0,7) ;
755 745
756 if (is & IMASK_SLOW) { 746 if (is & IMASK_SLOW) {
757 NDD_TRACE("CH1b",is,0, 747 NDD_TRACE("CH1b",is,0,0) ;
758 if (is & IS_PLINT1) { 748 if (is & IS_PLINT1) { /* PLC1 */
759 plc1_irq(smc) 749 plc1_irq(smc) ;
760 } 750 }
761 if (is & IS_PLINT2) { 751 if (is & IS_PLINT2) { /* PLC2 */
762 plc2_irq(smc) 752 plc2_irq(smc) ;
763 } 753 }
764 if (is & IS_MINTR1) { 754 if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
765 stu = inpw(FM_ 755 stu = inpw(FM_A(FM_ST1U)) ;
766 stl = inpw(FM_ 756 stl = inpw(FM_A(FM_ST1L)) ;
767 DB_GEN("Slow t 757 DB_GEN("Slow transmit complete",0,0,6) ;
768 mac1_irq(smc,s 758 mac1_irq(smc,stu,stl) ;
769 } 759 }
770 if (is & IS_MINTR2) { 760 if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
771 stu= inpw(FM_A 761 stu= inpw(FM_A(FM_ST2U)) ;
772 stl= inpw(FM_A 762 stl= inpw(FM_A(FM_ST2L)) ;
773 DB_GEN("Slow r 763 DB_GEN("Slow receive complete",0,0,6) ;
774 DB_GEN("stl = 764 DB_GEN("stl = %x : stu = %x",stl,stu,7) ;
775 mac2_irq(smc,s 765 mac2_irq(smc,stu,stl) ;
776 } 766 }
777 if (is & IS_MINTR3) { 767 if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
778 stu= inpw(FM_A 768 stu= inpw(FM_A(FM_ST3U)) ;
779 stl= inpw(FM_A 769 stl= inpw(FM_A(FM_ST3L)) ;
780 DB_GEN("FORMAC 770 DB_GEN("FORMAC Mode Register 3",0,0,6) ;
781 mac3_irq(smc,s 771 mac3_irq(smc,stu,stl) ;
782 } 772 }
783 if (is & IS_TIMINT) { 773 if (is & IS_TIMINT) { /* Timer 82C54-2 */
784 timer_irq(smc) 774 timer_irq(smc) ;
785 #ifdef NDIS_OS2 775 #ifdef NDIS_OS2
786 force_irq_pend 776 force_irq_pending = 0 ;
787 #endif 777 #endif
788 /* 778 /*
789 * out of RxD 779 * out of RxD detection
790 */ 780 */
791 if (++smc->os. 781 if (++smc->os.hwm.detec_count > 4) {
792 /* 782 /*
793 * che 783 * check out of RxD condition
794 */ 784 */
795 proce 785 process_receive(smc) ;
796 } 786 }
797 } 787 }
798 if (is & IS_TOKEN) { 788 if (is & IS_TOKEN) { /* Restricted Token Monitor */
799 rtm_irq(smc) ; 789 rtm_irq(smc) ;
800 } 790 }
801 if (is & IS_R1_P) { 791 if (is & IS_R1_P) { /* Parity error rx queue 1 */
802 /* clear IRQ * 792 /* clear IRQ */
803 outpd(ADDR(B4_ 793 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
804 SMT_PANIC(smc, 794 SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
805 } 795 }
806 if (is & IS_R1_C) { 796 if (is & IS_R1_C) { /* Encoding error rx queue 1 */
807 /* clear IRQ * 797 /* clear IRQ */
808 outpd(ADDR(B4_ 798 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
809 SMT_PANIC(smc, 799 SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
810 } 800 }
811 if (is & IS_XA_C) { 801 if (is & IS_XA_C) { /* Encoding error async tx q */
812 /* clear IRQ * 802 /* clear IRQ */
813 outpd(ADDR(B5_ 803 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
814 SMT_PANIC(smc, 804 SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
815 } 805 }
816 if (is & IS_XS_C) { 806 if (is & IS_XS_C) { /* Encoding error sync tx q */
817 /* clear IRQ * 807 /* clear IRQ */
818 outpd(ADDR(B5_ 808 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
819 SMT_PANIC(smc, 809 SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
820 } 810 }
821 } 811 }
822 812
823 /* 813 /*
824 * Fast Tx complete Async 814 * Fast Tx complete Async/Sync Queue (BMU service)
825 */ 815 */
826 if (is & (IS_XS_F|IS_XA_F)) { 816 if (is & (IS_XS_F|IS_XA_F)) {
827 DB_GEN("Fast tx comple 817 DB_GEN("Fast tx complete queue",0,0,6) ;
828 /* 818 /*
829 * clear IRQ, Note: no 819 * clear IRQ, Note: no IRQ is lost, because
830 * we always serv 820 * we always service both queues
831 */ 821 */
832 outpd(ADDR(B5_XS_CSR), 822 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
833 outpd(ADDR(B5_XA_CSR), 823 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
834 mac_drv_clear_txd(smc) 824 mac_drv_clear_txd(smc) ;
835 llc_restart_tx(smc) ; 825 llc_restart_tx(smc) ;
836 } 826 }
837 827
838 /* 828 /*
839 * Fast Rx Complete (BMU 829 * Fast Rx Complete (BMU service)
840 */ 830 */
841 if (is & IS_R1_F) { 831 if (is & IS_R1_F) {
842 DB_GEN("Fast receive c 832 DB_GEN("Fast receive complete",0,0,6) ;
843 /* clear IRQ */ 833 /* clear IRQ */
844 #ifndef USE_BREAK_ISR 834 #ifndef USE_BREAK_ISR
845 outpd(ADDR(B4_R1_CSR), 835 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
846 process_receive(smc) ; 836 process_receive(smc) ;
847 #else 837 #else
848 process_receive(smc) ; 838 process_receive(smc) ;
849 if (smc->os.hwm.leave_ 839 if (smc->os.hwm.leave_isr) {
850 force_irq = FA 840 force_irq = FALSE ;
851 } else { 841 } else {
852 outpd(ADDR(B4_ 842 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
853 process_receiv 843 process_receive(smc) ;
854 } 844 }
855 #endif 845 #endif
856 } 846 }
857 847
858 #ifndef NDIS_OS2 848 #ifndef NDIS_OS2
859 while ((mb = get_llc_rx(smc))) 849 while ((mb = get_llc_rx(smc))) {
860 smt_to_llc(smc,mb) ; 850 smt_to_llc(smc,mb) ;
861 } 851 }
862 #else 852 #else
863 if (offDepth) 853 if (offDepth)
864 post_proc() ; 854 post_proc() ;
865 855
866 while (!offDepth && (mb = get_ 856 while (!offDepth && (mb = get_llc_rx(smc))) {
867 smt_to_llc(smc,mb) ; 857 smt_to_llc(smc,mb) ;
868 } 858 }
869 859
870 if (!offDepth && smc->os.hwm.r 860 if (!offDepth && smc->os.hwm.rx_break) {
871 process_receive(smc) ; 861 process_receive(smc) ;
872 } 862 }
873 #endif 863 #endif
874 if (smc->q.ev_get != smc->q.ev 864 if (smc->q.ev_get != smc->q.ev_put) {
875 NDD_TRACE("CH2a",0,0,0 865 NDD_TRACE("CH2a",0,0,0) ;
876 ev_dispatcher(smc) ; 866 ev_dispatcher(smc) ;
877 } 867 }
878 #ifdef NDIS_OS2 868 #ifdef NDIS_OS2
879 post_proc() ; 869 post_proc() ;
880 if (offDepth) { /* lea 870 if (offDepth) { /* leave fddi_isr because */
881 break ; /* ind 871 break ; /* indications not allowed */
882 } 872 }
883 #endif 873 #endif
884 #ifdef USE_BREAK_ISR 874 #ifdef USE_BREAK_ISR
885 if (smc->os.hwm.leave_isr) { 875 if (smc->os.hwm.leave_isr) {
886 break ; /* lea 876 break ; /* leave fddi_isr */
887 } 877 }
888 #endif 878 #endif
889 879
890 /* NOTE: when the isr is left, 880 /* NOTE: when the isr is left, no rx is pending */
891 } /* end of interrupt source pol 881 } /* end of interrupt source polling loop */
892 882
893 #ifdef USE_BREAK_ISR 883 #ifdef USE_BREAK_ISR
894 if (smc->os.hwm.leave_isr && force_irq 884 if (smc->os.hwm.leave_isr && force_irq) {
895 smt_force_irq(smc) ; 885 smt_force_irq(smc) ;
896 } 886 }
897 #endif 887 #endif
898 smc->os.hwm.isr_flag = FALSE ; 888 smc->os.hwm.isr_flag = FALSE ;
899 NDD_TRACE("CH0E",0,0,0) ; 889 NDD_TRACE("CH0E",0,0,0) ;
900 } 890 }
901 891
902 892
903 /* 893 /*
904 -------------------------------------- 894 -------------------------------------------------------------
905 RECEIVE FUNCTIONS: 895 RECEIVE FUNCTIONS:
906 -------------------------------------- 896 -------------------------------------------------------------
907 */ 897 */
908 898
909 #ifndef NDIS_OS2 899 #ifndef NDIS_OS2
910 /* 900 /*
911 * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode) 901 * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode)
912 * void mac_drv_rx_mode(smc,mode) 902 * void mac_drv_rx_mode(smc,mode)
913 * 903 *
914 * function DOWNCALL (fplus.c) 904 * function DOWNCALL (fplus.c)
915 * Corresponding to the parameter 905 * Corresponding to the parameter mode, the operating system
916 * dependent module can activate 906 * dependent module can activate several receive modes.
917 * 907 *
918 * para mode = 1: RX_ENABLE_ALLMULTI 908 * para mode = 1: RX_ENABLE_ALLMULTI enable all multicasts
919 * = 2: RX_DISABLE_ALLMULTI 909 * = 2: RX_DISABLE_ALLMULTI disable "enable all multicasts"
920 * = 3: RX_ENABLE_PROMISC 910 * = 3: RX_ENABLE_PROMISC enable promiscuous
921 * = 4: RX_DISABLE_PROMISC 911 * = 4: RX_DISABLE_PROMISC disable promiscuous
922 * = 5: RX_ENABLE_NSA 912 * = 5: RX_ENABLE_NSA enable rec. of all NSA frames
923 * (disabled after 'drive 913 * (disabled after 'driver reset' & 'set station address')
924 * = 6: RX_DISABLE_NSA 914 * = 6: RX_DISABLE_NSA disable rec. of all NSA frames
925 * 915 *
926 * = 21: RX_ENABLE_PASS_SMT 916 * = 21: RX_ENABLE_PASS_SMT ( see description )
927 * = 22: RX_DISABLE_PASS_SMT 917 * = 22: RX_DISABLE_PASS_SMT ( " " )
928 * = 23: RX_ENABLE_PASS_NSA 918 * = 23: RX_ENABLE_PASS_NSA ( " " )
929 * = 24: RX_DISABLE_PASS_NSA 919 * = 24: RX_DISABLE_PASS_NSA ( " " )
930 * = 25: RX_ENABLE_PASS_DB 920 * = 25: RX_ENABLE_PASS_DB ( " " )
931 * = 26: RX_DISABLE_PASS_DB 921 * = 26: RX_DISABLE_PASS_DB ( " " )
932 * = 27: RX_DISABLE_PASS_ALL 922 * = 27: RX_DISABLE_PASS_ALL ( " " )
933 * = 28: RX_DISABLE_LLC_PROMISC 923 * = 28: RX_DISABLE_LLC_PROMISC ( " " )
934 * = 29: RX_ENABLE_LLC_PROMISC 924 * = 29: RX_ENABLE_LLC_PROMISC ( " " )
935 * 925 *
936 * 926 *
937 * RX_ENABLE_PASS_SMT / RX_DISABL 927 * RX_ENABLE_PASS_SMT / RX_DISABLE_PASS_SMT
938 * 928 *
939 * If the operating system depend 929 * If the operating system dependent module activates the
940 * mode RX_ENABLE_PASS_SMT, the h 930 * mode RX_ENABLE_PASS_SMT, the hardware module
941 * duplicates all SMT frames with 931 * duplicates all SMT frames with the frame control
942 * FC_SMT_INFO and passes them to 932 * FC_SMT_INFO and passes them to the LLC receive channel
943 * by calling mac_drv_rx_init. 933 * by calling mac_drv_rx_init.
944 * The SMT Frames which are sent 934 * The SMT Frames which are sent by the local SMT and the NSA
945 * frames whose A- and C-Indicato 935 * frames whose A- and C-Indicator is not set are also duplicated
946 * and passed. 936 * and passed.
947 * The receive mode RX_DISABLE_PA 937 * The receive mode RX_DISABLE_PASS_SMT disables the passing
948 * of SMT frames. 938 * of SMT frames.
949 * 939 *
950 * RX_ENABLE_PASS_NSA / RX_DISABL 940 * RX_ENABLE_PASS_NSA / RX_DISABLE_PASS_NSA
951 * 941 *
952 * If the operating system depend 942 * If the operating system dependent module activates the
953 * mode RX_ENABLE_PASS_NSA, the h 943 * mode RX_ENABLE_PASS_NSA, the hardware module
954 * duplicates all NSA frames with 944 * duplicates all NSA frames with frame control FC_SMT_NSA
955 * and a set A-Indicator and pass 945 * and a set A-Indicator and passed them to the LLC
956 * receive channel by calling mac 946 * receive channel by calling mac_drv_rx_init.
957 * All NSA Frames which are sent 947 * All NSA Frames which are sent by the local SMT
958 * are also duplicated and passed 948 * are also duplicated and passed.
959 * The receive mode RX_DISABLE_PA 949 * The receive mode RX_DISABLE_PASS_NSA disables the passing
960 * of NSA frames with the A- or C 950 * of NSA frames with the A- or C-Indicator set.
961 * 951 *
962 * NOTE: For fear that the hardware mod 952 * NOTE: For fear that the hardware module receives NSA frames with
963 * a reset A-Indicator, the opera 953 * a reset A-Indicator, the operating system dependent module
964 * has to call mac_drv_rx_mode wi 954 * has to call mac_drv_rx_mode with the mode RX_ENABLE_NSA
965 * before activate the RX_ENABLE_ 955 * before activate the RX_ENABLE_PASS_NSA mode and after every
966 * 'driver reset' and 'set statio 956 * 'driver reset' and 'set station address'.
967 * 957 *
968 * RX_ENABLE_PASS_DB / RX_DISABLE 958 * RX_ENABLE_PASS_DB / RX_DISABLE_PASS_DB
969 * 959 *
970 * If the operating system depend 960 * If the operating system dependent module activates the
971 * mode RX_ENABLE_PASS_DB, direct 961 * mode RX_ENABLE_PASS_DB, direct BEACON frames
972 * (FC_BEACON frame control) are 962 * (FC_BEACON frame control) are passed to the LLC receive
973 * channel by mac_drv_rx_init. 963 * channel by mac_drv_rx_init.
974 * The receive mode RX_DISABLE_PA 964 * The receive mode RX_DISABLE_PASS_DB disables the passing
975 * of direct BEACON frames. 965 * of direct BEACON frames.
976 * 966 *
977 * RX_DISABLE_PASS_ALL 967 * RX_DISABLE_PASS_ALL
978 * 968 *
979 * Disables all special receives 969 * Disables all special receives modes. It is equal to
980 * call mac_drv_set_rx_mode succe 970 * call mac_drv_set_rx_mode successively with the
981 * parameters RX_DISABLE_NSA, RX_ 971 * parameters RX_DISABLE_NSA, RX_DISABLE_PASS_SMT,
982 * RX_DISABLE_PASS_NSA and RX_DIS 972 * RX_DISABLE_PASS_NSA and RX_DISABLE_PASS_DB.
983 * 973 *
984 * RX_ENABLE_LLC_PROMISC 974 * RX_ENABLE_LLC_PROMISC
985 * 975 *
986 * (default) all received LLC fra 976 * (default) all received LLC frames and all SMT/NSA/DBEACON
987 * frames depending on the attitu 977 * frames depending on the attitude of the flags
988 * PASS_SMT/PASS_NSA/PASS_DBEACON 978 * PASS_SMT/PASS_NSA/PASS_DBEACON will be delivered to the
989 * LLC layer 979 * LLC layer
990 * 980 *
991 * RX_DISABLE_LLC_PROMISC 981 * RX_DISABLE_LLC_PROMISC
992 * 982 *
993 * all received SMT/NSA/DBEACON f 983 * all received SMT/NSA/DBEACON frames depending on the
994 * attitude of the flags PASS_SMT 984 * attitude of the flags PASS_SMT/PASS_NSA/PASS_DBEACON
995 * will be delivered to the LLC l 985 * will be delivered to the LLC layer.
996 * all received LLC frames with a 986 * all received LLC frames with a directed address, Multicast
997 * or Broadcast address will be d 987 * or Broadcast address will be delivered to the LLC
998 * layer too. 988 * layer too.
999 * 989 *
1000 * END_MANUAL_ENTRY 990 * END_MANUAL_ENTRY
1001 */ 991 */
1002 void mac_drv_rx_mode(struct s_smc *smc, int m 992 void mac_drv_rx_mode(struct s_smc *smc, int mode)
1003 { 993 {
1004 switch(mode) { 994 switch(mode) {
1005 case RX_ENABLE_PASS_SMT: 995 case RX_ENABLE_PASS_SMT:
1006 smc->os.hwm.pass_SMT = TRUE ; 996 smc->os.hwm.pass_SMT = TRUE ;
1007 break ; 997 break ;
1008 case RX_DISABLE_PASS_SMT: 998 case RX_DISABLE_PASS_SMT:
1009 smc->os.hwm.pass_SMT = FALSE 999 smc->os.hwm.pass_SMT = FALSE ;
1010 break ; 1000 break ;
1011 case RX_ENABLE_PASS_NSA: 1001 case RX_ENABLE_PASS_NSA:
1012 smc->os.hwm.pass_NSA = TRUE ; 1002 smc->os.hwm.pass_NSA = TRUE ;
1013 break ; 1003 break ;
1014 case RX_DISABLE_PASS_NSA: 1004 case RX_DISABLE_PASS_NSA:
1015 smc->os.hwm.pass_NSA = FALSE 1005 smc->os.hwm.pass_NSA = FALSE ;
1016 break ; 1006 break ;
1017 case RX_ENABLE_PASS_DB: 1007 case RX_ENABLE_PASS_DB:
1018 smc->os.hwm.pass_DB = TRUE ; 1008 smc->os.hwm.pass_DB = TRUE ;
1019 break ; 1009 break ;
1020 case RX_DISABLE_PASS_DB: 1010 case RX_DISABLE_PASS_DB:
1021 smc->os.hwm.pass_DB = FALSE ; 1011 smc->os.hwm.pass_DB = FALSE ;
1022 break ; 1012 break ;
1023 case RX_DISABLE_PASS_ALL: 1013 case RX_DISABLE_PASS_ALL:
1024 smc->os.hwm.pass_SMT = smc->o 1014 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = FALSE ;
1025 smc->os.hwm.pass_DB = FALSE ; 1015 smc->os.hwm.pass_DB = FALSE ;
1026 smc->os.hwm.pass_llc_promisc 1016 smc->os.hwm.pass_llc_promisc = TRUE ;
1027 mac_set_rx_mode(smc,RX_DISABL 1017 mac_set_rx_mode(smc,RX_DISABLE_NSA) ;
1028 break ; 1018 break ;
1029 case RX_DISABLE_LLC_PROMISC: 1019 case RX_DISABLE_LLC_PROMISC:
1030 smc->os.hwm.pass_llc_promisc 1020 smc->os.hwm.pass_llc_promisc = FALSE ;
1031 break ; 1021 break ;
1032 case RX_ENABLE_LLC_PROMISC: 1022 case RX_ENABLE_LLC_PROMISC:
1033 smc->os.hwm.pass_llc_promisc 1023 smc->os.hwm.pass_llc_promisc = TRUE ;
1034 break ; 1024 break ;
1035 case RX_ENABLE_ALLMULTI: 1025 case RX_ENABLE_ALLMULTI:
1036 case RX_DISABLE_ALLMULTI: 1026 case RX_DISABLE_ALLMULTI:
1037 case RX_ENABLE_PROMISC: 1027 case RX_ENABLE_PROMISC:
1038 case RX_DISABLE_PROMISC: 1028 case RX_DISABLE_PROMISC:
1039 case RX_ENABLE_NSA: 1029 case RX_ENABLE_NSA:
1040 case RX_DISABLE_NSA: 1030 case RX_DISABLE_NSA:
1041 default: 1031 default:
1042 mac_set_rx_mode(smc,mode) ; 1032 mac_set_rx_mode(smc,mode) ;
1043 break ; 1033 break ;
1044 } 1034 }
1045 } 1035 }
1046 #endif /* ifndef NDIS_OS2 */ 1036 #endif /* ifndef NDIS_OS2 */
1047 1037
1048 /* 1038 /*
1049 * process receive queue 1039 * process receive queue
1050 */ 1040 */
1051 void process_receive(struct s_smc *smc) 1041 void process_receive(struct s_smc *smc)
1052 { 1042 {
1053 int i ; 1043 int i ;
1054 int n ; 1044 int n ;
1055 int frag_count ; /* nu 1045 int frag_count ; /* number of RxDs of the curr rx buf */
1056 int used_frags ; /* nu 1046 int used_frags ; /* number of RxDs of the curr frame */
1057 struct s_smt_rx_queue *queue ; /* po 1047 struct s_smt_rx_queue *queue ; /* points to the queue ctl struct */
1058 struct s_smt_fp_rxd volatile *r ; 1048 struct s_smt_fp_rxd volatile *r ; /* rxd pointer */
1059 struct s_smt_fp_rxd volatile *rxd ; 1049 struct s_smt_fp_rxd volatile *rxd ; /* first rxd of rx frame */
1060 u_long rbctrl ; /* re 1050 u_long rbctrl ; /* receive buffer control word */
1061 u_long rfsw ; /* re 1051 u_long rfsw ; /* receive frame status word */
1062 u_short rx_used ; 1052 u_short rx_used ;
1063 u_char far *virt ; 1053 u_char far *virt ;
1064 char far *data ; 1054 char far *data ;
1065 SMbuf *mb ; 1055 SMbuf *mb ;
1066 u_char fc ; /* Fr 1056 u_char fc ; /* Frame control */
1067 int len ; /* Fr 1057 int len ; /* Frame length */
1068 1058
1069 smc->os.hwm.detec_count = 0 ; 1059 smc->os.hwm.detec_count = 0 ;
1070 queue = smc->hw.fp.rx[QUEUE_R1] ; 1060 queue = smc->hw.fp.rx[QUEUE_R1] ;
1071 NDD_TRACE("RHxB",0,0,0) ; 1061 NDD_TRACE("RHxB",0,0,0) ;
1072 for ( ; ; ) { 1062 for ( ; ; ) {
1073 r = queue->rx_curr_get ; 1063 r = queue->rx_curr_get ;
1074 rx_used = queue->rx_used ; 1064 rx_used = queue->rx_used ;
1075 frag_count = 0 ; 1065 frag_count = 0 ;
1076 1066
1077 #ifdef USE_BREAK_ISR 1067 #ifdef USE_BREAK_ISR
1078 if (smc->os.hwm.leave_isr) { 1068 if (smc->os.hwm.leave_isr) {
1079 goto rx_end ; 1069 goto rx_end ;
1080 } 1070 }
1081 #endif 1071 #endif
1082 #ifdef NDIS_OS2 1072 #ifdef NDIS_OS2
1083 if (offDepth) { 1073 if (offDepth) {
1084 smc->os.hwm.rx_break 1074 smc->os.hwm.rx_break = 1 ;
1085 goto rx_end ; 1075 goto rx_end ;
1086 } 1076 }
1087 smc->os.hwm.rx_break = 0 ; 1077 smc->os.hwm.rx_break = 0 ;
1088 #endif 1078 #endif
1089 #ifdef ODI2 1079 #ifdef ODI2
1090 if (smc->os.hwm.rx_break) { 1080 if (smc->os.hwm.rx_break) {
1091 goto rx_end ; 1081 goto rx_end ;
1092 } 1082 }
1093 #endif 1083 #endif
1094 n = 0 ; 1084 n = 0 ;
1095 do { 1085 do {
1096 DB_RX("Check RxD %x f 1086 DB_RX("Check RxD %x for OWN and EOF",(void *)r,0,5) ;
1097 DRV_BUF_FLUSH(r,DDI_D 1087 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1098 rbctrl = CR_READ(r->r !! 1088 rbctrl = le32_to_cpu(CR_READ(r->rxd_rbctrl));
1099 rbctrl = AIX_REVERSE( <<
1100 1089
1101 if (rbctrl & BMU_OWN) 1090 if (rbctrl & BMU_OWN) {
1102 NDD_TRACE("RH 1091 NDD_TRACE("RHxE",r,rfsw,rbctrl) ;
1103 DB_RX("End of 1092 DB_RX("End of RxDs",0,0,4) ;
1104 goto rx_end ; 1093 goto rx_end ;
1105 } 1094 }
1106 /* 1095 /*
1107 * out of RxD detecti 1096 * out of RxD detection
1108 */ 1097 */
1109 if (!rx_used) { 1098 if (!rx_used) {
1110 SK_BREAK() ; 1099 SK_BREAK() ;
1111 SMT_PANIC(smc 1100 SMT_PANIC(smc,HWM_E0009,HWM_E0009_MSG) ;
1112 /* Either we 1101 /* Either we don't have an RxD or all
1113 * RxDs are f 1102 * RxDs are filled. Therefore it's allowed
1114 * for to set 1103 * for to set the STOPPED flag */
1115 smc->hw.hw_st 1104 smc->hw.hw_state = STOPPED ;
1116 mac_drv_clear 1105 mac_drv_clear_rx_queue(smc) ;
1117 smc->hw.hw_st 1106 smc->hw.hw_state = STARTED ;
1118 mac_drv_fill_ 1107 mac_drv_fill_rxd(smc) ;
1119 smc->os.hwm.d 1108 smc->os.hwm.detec_count = 0 ;
1120 goto rx_end ; 1109 goto rx_end ;
1121 } 1110 }
1122 rfsw = AIX_REVERSE(r- !! 1111 rfsw = le32_to_cpu(r->rxd_rfsw) ;
1123 if ((rbctrl & BMU_STF 1112 if ((rbctrl & BMU_STF) != ((rbctrl & BMU_ST_BUF) <<5)) {
1124 /* 1113 /*
1125 * The BMU_ST 1114 * The BMU_STF bit is deleted, 1 frame is
1126 * placed int 1115 * placed into more than 1 rx buffer
1127 * 1116 *
1128 * skip frame 1117 * skip frame by setting the rx len to 0
1129 * 1118 *
1130 * if fragmen 1119 * if fragment count == 0
1131 * The m 1120 * The missing STF bit belongs to the
1132 * curre 1121 * current frame, search for the
1133 * EOF b 1122 * EOF bit to complete the frame
1134 * else 1123 * else
1135 * the f 1124 * the fragment belongs to the next frame,
1136 * exit 1125 * exit the loop and process the frame
1137 */ 1126 */
1138 SK_BREAK() ; 1127 SK_BREAK() ;
1139 rfsw = 0 ; 1128 rfsw = 0 ;
1140 if (frag_coun 1129 if (frag_count) {
1141 break 1130 break ;
1142 } 1131 }
1143 } 1132 }
1144 n += rbctrl & 0xffff 1133 n += rbctrl & 0xffff ;
1145 r = r->rxd_next ; 1134 r = r->rxd_next ;
1146 frag_count++ ; 1135 frag_count++ ;
1147 rx_used-- ; 1136 rx_used-- ;
1148 } while (!(rbctrl & BMU_EOF)) 1137 } while (!(rbctrl & BMU_EOF)) ;
1149 used_frags = frag_count ; 1138 used_frags = frag_count ;
1150 DB_RX("EOF set in RxD, used_f 1139 DB_RX("EOF set in RxD, used_frags = %d ",used_frags,0,5) ;
1151 1140
1152 /* may be next 2 DRV_BUF_FLUS 1141 /* may be next 2 DRV_BUF_FLUSH() can be skipped, because */
1153 /* BMU_ST_BUF will not be cha 1142 /* BMU_ST_BUF will not be changed by the ASIC */
1154 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_ 1143 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1155 while (rx_used && !(r->rxd_rb !! 1144 while (rx_used && !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
1156 DB_RX("Check STF bit 1145 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1157 r = r->rxd_next ; 1146 r = r->rxd_next ;
1158 DRV_BUF_FLUSH(r,DDI_D 1147 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1159 frag_count++ ; 1148 frag_count++ ;
1160 rx_used-- ; 1149 rx_used-- ;
1161 } 1150 }
1162 DB_RX("STF bit found",0,0,5) 1151 DB_RX("STF bit found",0,0,5) ;
1163 1152
1164 /* 1153 /*
1165 * The received frame is fini 1154 * The received frame is finished for the process receive
1166 */ 1155 */
1167 rxd = queue->rx_curr_get ; 1156 rxd = queue->rx_curr_get ;
1168 queue->rx_curr_get = r ; 1157 queue->rx_curr_get = r ;
1169 queue->rx_free += frag_count 1158 queue->rx_free += frag_count ;
1170 queue->rx_used = rx_used ; 1159 queue->rx_used = rx_used ;
1171 1160
1172 /* 1161 /*
1173 * ASIC Errata no. 7 (STF - B 1162 * ASIC Errata no. 7 (STF - Bit Bug)
1174 */ 1163 */
1175 rxd->rxd_rbctrl &= AIX_REVERS !! 1164 rxd->rxd_rbctrl &= cpu_to_le32(~BMU_STF) ;
1176 1165
1177 for (r=rxd, i=frag_count ; i 1166 for (r=rxd, i=frag_count ; i ; r=r->rxd_next, i--){
1178 DB_RX("dma_complete f 1167 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1179 dma_complete(smc,(uni 1168 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1180 } 1169 }
1181 smc->hw.fp.err_stats.err_vali 1170 smc->hw.fp.err_stats.err_valid++ ;
1182 smc->mib.m[MAC0].fddiMACCopie 1171 smc->mib.m[MAC0].fddiMACCopied_Ct++ ;
1183 1172
1184 /* the length of the data inc 1173 /* the length of the data including the FC */
1185 len = (rfsw & RD_LENGTH) - 4 1174 len = (rfsw & RD_LENGTH) - 4 ;
1186 1175
1187 DB_RX("frame length = %d",len 1176 DB_RX("frame length = %d",len,0,4) ;
1188 /* 1177 /*
1189 * check the frame_lenght and !! 1178 * check the frame_length and all error flags
1190 */ 1179 */
1191 if (rfsw & (RX_MSRABT|RX_FS_E 1180 if (rfsw & (RX_MSRABT|RX_FS_E|RX_FS_CRC|RX_FS_IMPL)){
1192 if (rfsw & RD_S_MSRAB 1181 if (rfsw & RD_S_MSRABT) {
1193 DB_RX("Frame 1182 DB_RX("Frame aborted by the FORMAC",0,0,2) ;
1194 smc->hw.fp.er 1183 smc->hw.fp.err_stats.err_abort++ ;
1195 } 1184 }
1196 /* 1185 /*
1197 * check frame status 1186 * check frame status
1198 */ 1187 */
1199 if (rfsw & RD_S_SEAC2 1188 if (rfsw & RD_S_SEAC2) {
1200 DB_RX("E-Indi 1189 DB_RX("E-Indicator set",0,0,2) ;
1201 smc->hw.fp.er 1190 smc->hw.fp.err_stats.err_e_indicator++ ;
1202 } 1191 }
1203 if (rfsw & RD_S_SFRME 1192 if (rfsw & RD_S_SFRMERR) {
1204 DB_RX("CRC er 1193 DB_RX("CRC error",0,0,2) ;
1205 smc->hw.fp.er 1194 smc->hw.fp.err_stats.err_crc++ ;
1206 } 1195 }
1207 if (rfsw & RX_FS_IMPL 1196 if (rfsw & RX_FS_IMPL) {
1208 DB_RX("Implem 1197 DB_RX("Implementer frame",0,0,2) ;
1209 smc->hw.fp.er 1198 smc->hw.fp.err_stats.err_imp_frame++ ;
1210 } 1199 }
1211 goto abort_frame ; 1200 goto abort_frame ;
1212 } 1201 }
1213 if (len > FDDI_RAW_MTU-4) { 1202 if (len > FDDI_RAW_MTU-4) {
1214 DB_RX("Frame too long 1203 DB_RX("Frame too long error",0,0,2) ;
1215 smc->hw.fp.err_stats. 1204 smc->hw.fp.err_stats.err_too_long++ ;
1216 goto abort_frame ; 1205 goto abort_frame ;
1217 } 1206 }
1218 /* 1207 /*
1219 * SUPERNET 3 Bug: FORMAC del 1208 * SUPERNET 3 Bug: FORMAC delivers status words
1220 * of aborded frames to the B 1209 * of aborded frames to the BMU
1221 */ 1210 */
1222 if (len <= 4) { 1211 if (len <= 4) {
1223 DB_RX("Frame length = 1212 DB_RX("Frame length = 0",0,0,2) ;
1224 goto abort_frame ; 1213 goto abort_frame ;
1225 } 1214 }
1226 1215
1227 if (len != (n-4)) { 1216 if (len != (n-4)) {
1228 DB_RX("BMU: rx len di 1217 DB_RX("BMU: rx len differs: [%d:%d]",len,n,4);
1229 smc->os.hwm.rx_len_er 1218 smc->os.hwm.rx_len_error++ ;
1230 goto abort_frame ; 1219 goto abort_frame ;
1231 } 1220 }
1232 1221
1233 /* 1222 /*
1234 * Check SA == MA 1223 * Check SA == MA
1235 */ 1224 */
1236 virt = (u_char far *) rxd->rx 1225 virt = (u_char far *) rxd->rxd_virt ;
1237 DB_RX("FC = %x",*virt,0,2) ; 1226 DB_RX("FC = %x",*virt,0,2) ;
1238 if (virt[12] == MA[5] && 1227 if (virt[12] == MA[5] &&
1239 virt[11] == MA[4] && 1228 virt[11] == MA[4] &&
1240 virt[10] == MA[3] && 1229 virt[10] == MA[3] &&
1241 virt[9] == MA[2] && 1230 virt[9] == MA[2] &&
1242 virt[8] == MA[1] && 1231 virt[8] == MA[1] &&
1243 (virt[7] & ~GROUP_ADDR_BI 1232 (virt[7] & ~GROUP_ADDR_BIT) == MA[0]) {
1244 goto abort_frame ; 1233 goto abort_frame ;
1245 } 1234 }
1246 1235
1247 /* 1236 /*
1248 * test if LLC frame 1237 * test if LLC frame
1249 */ 1238 */
1250 if (rfsw & RX_FS_LLC) { 1239 if (rfsw & RX_FS_LLC) {
1251 /* 1240 /*
1252 * if pass_llc_promis 1241 * if pass_llc_promisc is disable
1253 * if DA != Mult 1242 * if DA != Multicast or Broadcast or DA!=MA
1254 * abort 1243 * abort the frame
1255 */ 1244 */
1256 if (!smc->os.hwm.pass 1245 if (!smc->os.hwm.pass_llc_promisc) {
1257 if(!(virt[1] 1246 if(!(virt[1] & GROUP_ADDR_BIT)) {
1258 if (v 1247 if (virt[6] != MA[5] ||
1259 v 1248 virt[5] != MA[4] ||
1260 v 1249 virt[4] != MA[3] ||
1261 v 1250 virt[3] != MA[2] ||
1262 v 1251 virt[2] != MA[1] ||
1263 v 1252 virt[1] != MA[0]) {
1264 1253 DB_RX("DA != MA and not multi- or broadcast",0,0,2) ;
1265 1254 goto abort_frame ;
1266 } 1255 }
1267 } 1256 }
1268 } 1257 }
1269 1258
1270 /* 1259 /*
1271 * LLC frame received 1260 * LLC frame received
1272 */ 1261 */
1273 DB_RX("LLC - receive" 1262 DB_RX("LLC - receive",0,0,4) ;
1274 mac_drv_rx_complete(s 1263 mac_drv_rx_complete(smc,rxd,frag_count,len) ;
1275 } 1264 }
1276 else { 1265 else {
1277 if (!(mb = smt_get_mb 1266 if (!(mb = smt_get_mbuf(smc))) {
1278 smc->hw.fp.er 1267 smc->hw.fp.err_stats.err_no_buf++ ;
1279 DB_RX("No SMb 1268 DB_RX("No SMbuf; receive terminated",0,0,4) ;
1280 goto abort_fr 1269 goto abort_frame ;
1281 } 1270 }
1282 data = smtod(mb,char 1271 data = smtod(mb,char *) - 1 ;
1283 1272
1284 /* 1273 /*
1285 * copy the frame int 1274 * copy the frame into a SMT_MBuf
1286 */ 1275 */
1287 #ifdef USE_OS_CPY 1276 #ifdef USE_OS_CPY
1288 hwm_cpy_rxd2mb(rxd,da 1277 hwm_cpy_rxd2mb(rxd,data,len) ;
1289 #else 1278 #else
1290 for (r=rxd, i=used_fr 1279 for (r=rxd, i=used_frags ; i ; r=r->rxd_next, i--){
1291 n = AIX_REVER !! 1280 n = le32_to_cpu(r->rxd_rbctrl) & RD_LENGTH ;
1292 DB_RX("cp SMT 1281 DB_RX("cp SMT frame to mb: len = %d",n,0,6) ;
1293 memcpy(data,r 1282 memcpy(data,r->rxd_virt,n) ;
1294 data += n ; 1283 data += n ;
1295 } 1284 }
1296 data = smtod(mb,char 1285 data = smtod(mb,char *) - 1 ;
1297 #endif 1286 #endif
1298 fc = *(char *)mb->sm_ 1287 fc = *(char *)mb->sm_data = *data ;
1299 mb->sm_len = len - 1 1288 mb->sm_len = len - 1 ; /* len - fc */
1300 data++ ; 1289 data++ ;
1301 1290
1302 /* 1291 /*
1303 * SMT frame received 1292 * SMT frame received
1304 */ 1293 */
1305 switch(fc) { 1294 switch(fc) {
1306 case FC_SMT_INFO : 1295 case FC_SMT_INFO :
1307 smc->hw.fp.er 1296 smc->hw.fp.err_stats.err_smt_frame++ ;
1308 DB_RX("SMT fr 1297 DB_RX("SMT frame received ",0,0,5) ;
1309 1298
1310 if (smc->os.h 1299 if (smc->os.hwm.pass_SMT) {
1311 DB_RX 1300 DB_RX("pass SMT frame ",0,0,5) ;
1312 mac_d 1301 mac_drv_rx_complete(smc, rxd,
1313 1302 frag_count,len) ;
1314 } 1303 }
1315 else { 1304 else {
1316 DB_RX 1305 DB_RX("requeue RxD",0,0,5) ;
1317 mac_d 1306 mac_drv_requeue_rxd(smc,rxd,frag_count);
1318 } 1307 }
1319 1308
1320 smt_received_ 1309 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1321 break ; 1310 break ;
1322 case FC_SMT_NSA : 1311 case FC_SMT_NSA :
1323 smc->hw.fp.er 1312 smc->hw.fp.err_stats.err_smt_frame++ ;
1324 DB_RX("SMT fr 1313 DB_RX("SMT frame received ",0,0,5) ;
1325 1314
1326 /* if pass_NS 1315 /* if pass_NSA set pass the NSA frame or */
1327 /* pass_SMT s 1316 /* pass_SMT set and the A-Indicator */
1328 /* is not set 1317 /* is not set, pass the NSA frame */
1329 if (smc->os.h 1318 if (smc->os.hwm.pass_NSA ||
1330 (smc- 1319 (smc->os.hwm.pass_SMT &&
1331 !(rfs 1320 !(rfsw & A_INDIC))) {
1332 DB_RX 1321 DB_RX("pass SMT frame ",0,0,5) ;
1333 mac_d 1322 mac_drv_rx_complete(smc, rxd,
1334 1323 frag_count,len) ;
1335 } 1324 }
1336 else { 1325 else {
1337 DB_RX 1326 DB_RX("requeue RxD",0,0,5) ;
1338 mac_d 1327 mac_drv_requeue_rxd(smc,rxd,frag_count);
1339 } 1328 }
1340 1329
1341 smt_received_ 1330 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1342 break ; 1331 break ;
1343 case FC_BEACON : 1332 case FC_BEACON :
1344 if (smc->os.h 1333 if (smc->os.hwm.pass_DB) {
1345 DB_RX 1334 DB_RX("pass DB frame ",0,0,5) ;
1346 mac_d 1335 mac_drv_rx_complete(smc, rxd,
1347 1336 frag_count,len) ;
1348 } 1337 }
1349 else { 1338 else {
1350 DB_RX 1339 DB_RX("requeue RxD",0,0,5) ;
1351 mac_d 1340 mac_drv_requeue_rxd(smc,rxd,frag_count);
1352 } 1341 }
1353 smt_free_mbuf 1342 smt_free_mbuf(smc,mb) ;
1354 break ; 1343 break ;
1355 default : 1344 default :
1356 /* 1345 /*
1357 * unknown FC 1346 * unknown FC abord the frame
1358 */ 1347 */
1359 DB_RX("unknow 1348 DB_RX("unknown FC error",0,0,2) ;
1360 smt_free_mbuf 1349 smt_free_mbuf(smc,mb) ;
1361 DB_RX("requeu 1350 DB_RX("requeue RxD",0,0,5) ;
1362 mac_drv_reque 1351 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1363 if ((fc & 0xf 1352 if ((fc & 0xf0) == FC_MAC)
1364 smc-> 1353 smc->hw.fp.err_stats.err_mac_frame++ ;
1365 else 1354 else
1366 smc-> 1355 smc->hw.fp.err_stats.err_imp_frame++ ;
1367 1356
1368 break ; 1357 break ;
1369 } 1358 }
1370 } 1359 }
1371 1360
1372 DB_RX("next RxD is %x ",queue 1361 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1373 NDD_TRACE("RHx1",queue->rx_cu 1362 NDD_TRACE("RHx1",queue->rx_curr_get,0,0) ;
1374 1363
1375 continue ; 1364 continue ;
1376 /*----------------------------------- 1365 /*--------------------------------------------------------------------*/
1377 abort_frame: 1366 abort_frame:
1378 DB_RX("requeue RxD",0,0,5) ; 1367 DB_RX("requeue RxD",0,0,5) ;
1379 mac_drv_requeue_rxd(smc,rxd,f 1368 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1380 1369
1381 DB_RX("next RxD is %x ",queue 1370 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1382 NDD_TRACE("RHx2",queue->rx_cu 1371 NDD_TRACE("RHx2",queue->rx_curr_get,0,0) ;
1383 } 1372 }
1384 rx_end: 1373 rx_end:
1385 #ifdef ALL_RX_COMPLETE 1374 #ifdef ALL_RX_COMPLETE
1386 mac_drv_all_receives_complete(smc) ; 1375 mac_drv_all_receives_complete(smc) ;
1387 #endif 1376 #endif
1388 return ; /* lint bug: needs re 1377 return ; /* lint bug: needs return detect end of function */
1389 } 1378 }
1390 1379
1391 static void smt_to_llc(struct s_smc *smc, SMb 1380 static void smt_to_llc(struct s_smc *smc, SMbuf *mb)
1392 { 1381 {
1393 u_char fc ; 1382 u_char fc ;
1394 1383
1395 DB_RX("send a queued frame to the llc 1384 DB_RX("send a queued frame to the llc layer",0,0,4) ;
1396 smc->os.hwm.r.len = mb->sm_len ; 1385 smc->os.hwm.r.len = mb->sm_len ;
1397 smc->os.hwm.r.mb_pos = smtod(mb,char 1386 smc->os.hwm.r.mb_pos = smtod(mb,char *) ;
1398 fc = *smc->os.hwm.r.mb_pos ; 1387 fc = *smc->os.hwm.r.mb_pos ;
1399 (void)mac_drv_rx_init(smc,(int)mb->sm 1388 (void)mac_drv_rx_init(smc,(int)mb->sm_len,(int)fc,
1400 smc->os.hwm.r.mb_pos,(int)mb- 1389 smc->os.hwm.r.mb_pos,(int)mb->sm_len) ;
1401 smt_free_mbuf(smc,mb) ; 1390 smt_free_mbuf(smc,mb) ;
1402 } 1391 }
1403 1392
1404 /* 1393 /*
1405 * BEGIN_MANUAL_ENTRY(hwm_rx_frag) 1394 * BEGIN_MANUAL_ENTRY(hwm_rx_frag)
1406 * void hwm_rx_frag(smc,virt,phys,len,fr 1395 * void hwm_rx_frag(smc,virt,phys,len,frame_status)
1407 * 1396 *
1408 * function MACRO (hardware mod 1397 * function MACRO (hardware module, hwmtm.h)
1409 * This function calls dma_maste 1398 * This function calls dma_master for preparing the
1410 * system hardware for the DMA t 1399 * system hardware for the DMA transfer and initializes
1411 * the current RxD with the leng 1400 * the current RxD with the length and the physical and
1412 * virtual address of the fragme 1401 * virtual address of the fragment. Furthermore, it sets the
1413 * STF and EOF bits depending on 1402 * STF and EOF bits depending on the frame status byte,
1414 * switches the OWN flag of the 1403 * switches the OWN flag of the RxD, so that it is owned by the
1415 * adapter and issues an rx_star 1404 * adapter and issues an rx_start.
1416 * 1405 *
1417 * para virt virtual pointer to the fragme 1406 * para virt virtual pointer to the fragment
1418 * len the length of the fragment 1407 * len the length of the fragment
1419 * frame_status status of the frame, 1408 * frame_status status of the frame, see design description
1420 * 1409 *
1421 * NOTE: It is possible to call this f 1410 * NOTE: It is possible to call this function with a fragment length
1422 * of zero. 1411 * of zero.
1423 * 1412 *
1424 * END_MANUAL_ENTRY 1413 * END_MANUAL_ENTRY
1425 */ 1414 */
1426 void hwm_rx_frag(struct s_smc *smc, char far 1415 void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1427 int frame_status) 1416 int frame_status)
1428 { 1417 {
1429 struct s_smt_fp_rxd volatile *r ; 1418 struct s_smt_fp_rxd volatile *r ;
1430 u_int rbctrl ; !! 1419 __le32 rbctrl;
1431 1420
1432 NDD_TRACE("RHfB",virt,len,frame_statu 1421 NDD_TRACE("RHfB",virt,len,frame_status) ;
1433 DB_RX("hwm_rx_frag: len = %d, frame_s 1422 DB_RX("hwm_rx_frag: len = %d, frame_status = %x\n",len,frame_status,2) ;
1434 r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr 1423 r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put ;
1435 r->rxd_virt = virt ; 1424 r->rxd_virt = virt ;
1436 r->rxd_rbadr = AIX_REVERSE(phys) ; !! 1425 r->rxd_rbadr = cpu_to_le32(phys) ;
1437 rbctrl = AIX_REVERSE( (((u_long)frame !! 1426 rbctrl = cpu_to_le32( (((__u32)frame_status &
1438 (FIRST_FRAG|LAST_FRAG))<<26) 1427 (FIRST_FRAG|LAST_FRAG))<<26) |
1439 (((u_long) frame_status & FIR 1428 (((u_long) frame_status & FIRST_FRAG) << 21) |
1440 BMU_OWN | BMU_CHECK | BMU_EN_ 1429 BMU_OWN | BMU_CHECK | BMU_EN_IRQ_EOF | len) ;
1441 r->rxd_rbctrl = rbctrl ; 1430 r->rxd_rbctrl = rbctrl ;
1442 1431
1443 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) 1432 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1444 outpd(ADDR(B0_R1_CSR),CSR_START) ; 1433 outpd(ADDR(B0_R1_CSR),CSR_START) ;
1445 smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ; 1434 smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ;
1446 smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ; 1435 smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ;
1447 smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put 1436 smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put = r->rxd_next ;
1448 NDD_TRACE("RHfE",r,AIX_REVERSE(r->rxd !! 1437 NDD_TRACE("RHfE",r,le32_to_cpu(r->rxd_rbadr),0) ;
1449 } 1438 }
1450 1439
1451 #ifndef NDIS_OS2 <<
1452 /* <<
1453 * BEGIN_MANUAL_ENTRY(mac_drv_rx_frag) <<
1454 * int mac_drv_rx_frag(smc,virt,len) <<
1455 * <<
1456 * function DOWNCALL (hwmtm.c) <<
1457 * mac_drv_rx_frag fills the fra <<
1458 * <<
1459 * para virt the virtual address of the fr <<
1460 * len the length in bytes of the fr <<
1461 * <<
1462 * return 0: success code, no errors possi <<
1463 * <<
1464 * END_MANUAL_ENTRY <<
1465 */ <<
1466 int mac_drv_rx_frag(struct s_smc *smc, void f <<
1467 { <<
1468 NDD_TRACE("RHSB",virt,len,smc->os.hwm <<
1469 <<
1470 DB_RX("receive from queue: len/virt: <<
1471 memcpy((char far *)virt,smc->os.hwm.r <<
1472 smc->os.hwm.r.mb_pos += len ; <<
1473 <<
1474 NDD_TRACE("RHSE",smc->os.hwm.r.mb_pos <<
1475 return(0) ; <<
1476 } <<
1477 #endif <<
1478 <<
1479 <<
1480 /* 1440 /*
1481 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_ 1441 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
1482 * 1442 *
1483 * void mac_drv_clear_rx_queue(smc) 1443 * void mac_drv_clear_rx_queue(smc)
1484 * struct s_smc *smc ; 1444 * struct s_smc *smc ;
1485 * 1445 *
1486 * function DOWNCALL (hardware mod 1446 * function DOWNCALL (hardware module, hwmtm.c)
1487 * mac_drv_clear_rx_queue is cal 1447 * mac_drv_clear_rx_queue is called by the OS-specific module
1488 * after it has issued a card_st 1448 * after it has issued a card_stop.
1489 * In this case, the frames in t 1449 * In this case, the frames in the receive queue are obsolete and
1490 * should be removed. For removi 1450 * should be removed. For removing mac_drv_clear_rx_queue
1491 * calls dma_master for each RxD 1451 * calls dma_master for each RxD and mac_drv_clear_rxd for each
1492 * receive buffer. 1452 * receive buffer.
1493 * 1453 *
1494 * NOTE: calling sequence card_stop: 1454 * NOTE: calling sequence card_stop:
1495 * CLI_FBI(), card_stop(), 1455 * CLI_FBI(), card_stop(),
1496 * mac_drv_clear_tx_queue(), mac 1456 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
1497 * 1457 *
1498 * NOTE: The caller is responsible tha 1458 * NOTE: The caller is responsible that the BMUs are idle
1499 * when this function is called. 1459 * when this function is called.
1500 * 1460 *
1501 * END_MANUAL_ENTRY 1461 * END_MANUAL_ENTRY
1502 */ 1462 */
1503 void mac_drv_clear_rx_queue(struct s_smc *smc 1463 void mac_drv_clear_rx_queue(struct s_smc *smc)
1504 { 1464 {
1505 struct s_smt_fp_rxd volatile *r ; 1465 struct s_smt_fp_rxd volatile *r ;
1506 struct s_smt_fp_rxd volatile *next_rx 1466 struct s_smt_fp_rxd volatile *next_rxd ;
1507 struct s_smt_rx_queue *queue ; 1467 struct s_smt_rx_queue *queue ;
1508 int frag_count ; 1468 int frag_count ;
1509 int i ; 1469 int i ;
1510 1470
1511 if (smc->hw.hw_state != STOPPED) { 1471 if (smc->hw.hw_state != STOPPED) {
1512 SK_BREAK() ; 1472 SK_BREAK() ;
1513 SMT_PANIC(smc,HWM_E0012,HWM_E 1473 SMT_PANIC(smc,HWM_E0012,HWM_E0012_MSG) ;
1514 return ; 1474 return ;
1515 } 1475 }
1516 1476
1517 queue = smc->hw.fp.rx[QUEUE_R1] ; 1477 queue = smc->hw.fp.rx[QUEUE_R1] ;
1518 DB_RX("clear_rx_queue",0,0,5) ; 1478 DB_RX("clear_rx_queue",0,0,5) ;
1519 1479
1520 /* 1480 /*
1521 * dma_complete and mac_drv_clear_rxd 1481 * dma_complete and mac_drv_clear_rxd for all RxDs / receive buffers
1522 */ 1482 */
1523 r = queue->rx_curr_get ; 1483 r = queue->rx_curr_get ;
1524 while (queue->rx_used) { 1484 while (queue->rx_used) {
1525 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_ 1485 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1526 DB_RX("switch OWN bit of RxD 1486 DB_RX("switch OWN bit of RxD 0x%x ",r,0,5) ;
1527 r->rxd_rbctrl &= AIX_REVERSE( !! 1487 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
1528 frag_count = 1 ; 1488 frag_count = 1 ;
1529 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_ 1489 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1530 r = r->rxd_next ; 1490 r = r->rxd_next ;
1531 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_ 1491 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1532 while (r != queue->rx_curr_pu 1492 while (r != queue->rx_curr_put &&
1533 !(r->rxd_rbctrl & AIX !! 1493 !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
1534 DB_RX("Check STF bit 1494 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1535 r->rxd_rbctrl &= AIX_ !! 1495 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
1536 DRV_BUF_FLUSH(r,DDI_D 1496 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1537 r = r->rxd_next ; 1497 r = r->rxd_next ;
1538 DRV_BUF_FLUSH(r,DDI_D 1498 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1539 frag_count++ ; 1499 frag_count++ ;
1540 } 1500 }
1541 DB_RX("STF bit found",0,0,5) 1501 DB_RX("STF bit found",0,0,5) ;
1542 next_rxd = r ; 1502 next_rxd = r ;
1543 1503
1544 for (r=queue->rx_curr_get,i=f 1504 for (r=queue->rx_curr_get,i=frag_count; i ; r=r->rxd_next,i--){
1545 DB_RX("dma_complete f 1505 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1546 dma_complete(smc,(uni 1506 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1547 } 1507 }
1548 1508
1549 DB_RX("mac_drv_clear_rxd: RxD 1509 DB_RX("mac_drv_clear_rxd: RxD %x frag_count %d ",
1550 (void *)queue->rx_cur 1510 (void *)queue->rx_curr_get,frag_count,5) ;
1551 mac_drv_clear_rxd(smc,queue-> 1511 mac_drv_clear_rxd(smc,queue->rx_curr_get,frag_count) ;
1552 1512
1553 queue->rx_curr_get = next_rxd 1513 queue->rx_curr_get = next_rxd ;
1554 queue->rx_used -= frag_count 1514 queue->rx_used -= frag_count ;
1555 queue->rx_free += frag_count 1515 queue->rx_free += frag_count ;
1556 } 1516 }
1557 } 1517 }
1558 1518
1559 1519
1560 /* 1520 /*
1561 ------------------------------------- 1521 -------------------------------------------------------------
1562 SEND FUNCTIONS: 1522 SEND FUNCTIONS:
1563 ------------------------------------- 1523 -------------------------------------------------------------
1564 */ 1524 */
1565 1525
1566 /* 1526 /*
1567 * BEGIN_MANUAL_ENTRY(hwm_tx_init) 1527 * BEGIN_MANUAL_ENTRY(hwm_tx_init)
1568 * int hwm_tx_init(smc,fc,frag_count,fra 1528 * int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
1569 * 1529 *
1570 * function DOWN_CALL (hardware mod 1530 * function DOWN_CALL (hardware module, hwmtm.c)
1571 * hwm_tx_init checks if the fra 1531 * hwm_tx_init checks if the frame can be sent through the
1572 * corresponding send queue. 1532 * corresponding send queue.
1573 * 1533 *
1574 * para fc the frame control. To determi 1534 * para fc the frame control. To determine through which
1575 * send queue the frame should b 1535 * send queue the frame should be transmitted.
1576 * 0x50 - 0x57: asynchronous 1536 * 0x50 - 0x57: asynchronous LLC frame
1577 * 0xD0 - 0xD7: synchronous L 1537 * 0xD0 - 0xD7: synchronous LLC frame
1578 * 0x41, 0x4F: SMT frame to 1538 * 0x41, 0x4F: SMT frame to the network
1579 * 0x42: SMT frame to 1539 * 0x42: SMT frame to the network and to the local SMT
1580 * 0x43: SMT frame to 1540 * 0x43: SMT frame to the local SMT
1581 * frag_count count of the fragment 1541 * frag_count count of the fragments for this frame
1582 * frame_len length of the frame 1542 * frame_len length of the frame
1583 * frame_status status of the frame, 1543 * frame_status status of the frame, the send queue bit is already
1584 * specified 1544 * specified
1585 * 1545 *
1586 * return frame_status 1546 * return frame_status
1587 * 1547 *
1588 * END_MANUAL_ENTRY 1548 * END_MANUAL_ENTRY
1589 */ 1549 */
1590 int hwm_tx_init(struct s_smc *smc, u_char fc, 1550 int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
1591 int frame_status) 1551 int frame_status)
1592 { 1552 {
1593 NDD_TRACE("THiB",fc,frag_count,frame_ 1553 NDD_TRACE("THiB",fc,frag_count,frame_len) ;
1594 smc->os.hwm.tx_p = smc->hw.fp.tx[fram 1554 smc->os.hwm.tx_p = smc->hw.fp.tx[frame_status & QUEUE_A0] ;
1595 smc->os.hwm.tx_descr = TX_DESCRIPTOR 1555 smc->os.hwm.tx_descr = TX_DESCRIPTOR | (((u_long)(frame_len-1)&3)<<27) ;
1596 smc->os.hwm.tx_len = frame_len ; 1556 smc->os.hwm.tx_len = frame_len ;
1597 DB_TX("hwm_tx_init: fc = %x, len = %d 1557 DB_TX("hwm_tx_init: fc = %x, len = %d",fc,frame_len,3) ;
1598 if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR) 1558 if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
1599 frame_status |= LAN_TX ; 1559 frame_status |= LAN_TX ;
1600 } 1560 }
1601 else { 1561 else {
1602 switch (fc) { 1562 switch (fc) {
1603 case FC_SMT_INFO : 1563 case FC_SMT_INFO :
1604 case FC_SMT_NSA : 1564 case FC_SMT_NSA :
1605 frame_status |= LAN_T 1565 frame_status |= LAN_TX ;
1606 break ; 1566 break ;
1607 case FC_SMT_LOC : 1567 case FC_SMT_LOC :
1608 frame_status |= LOC_T 1568 frame_status |= LOC_TX ;
1609 break ; 1569 break ;
1610 case FC_SMT_LAN_LOC : 1570 case FC_SMT_LAN_LOC :
1611 frame_status |= LAN_T 1571 frame_status |= LAN_TX | LOC_TX ;
1612 break ; 1572 break ;
1613 default : 1573 default :
1614 SMT_PANIC(smc,HWM_E00 1574 SMT_PANIC(smc,HWM_E0010,HWM_E0010_MSG) ;
1615 } 1575 }
1616 } 1576 }
1617 if (!smc->hw.mac_ring_is_up) { 1577 if (!smc->hw.mac_ring_is_up) {
1618 frame_status &= ~LAN_TX ; 1578 frame_status &= ~LAN_TX ;
1619 frame_status |= RING_DOWN ; 1579 frame_status |= RING_DOWN ;
1620 DB_TX("Ring is down: terminat 1580 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1621 } 1581 }
1622 if (frag_count > smc->os.hwm.tx_p->tx 1582 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1623 #ifndef NDIS_OS2 1583 #ifndef NDIS_OS2
1624 mac_drv_clear_txd(smc) ; 1584 mac_drv_clear_txd(smc) ;
1625 if (frag_count > smc->os.hwm. 1585 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1626 DB_TX("Out of TxDs, t 1586 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1627 frame_status &= ~LAN_ 1587 frame_status &= ~LAN_TX ;
1628 frame_status |= OUT_O 1588 frame_status |= OUT_OF_TXD ;
1629 } 1589 }
1630 #else 1590 #else
1631 DB_TX("Out of TxDs, terminate 1591 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1632 frame_status &= ~LAN_TX ; 1592 frame_status &= ~LAN_TX ;
1633 frame_status |= OUT_OF_TXD ; 1593 frame_status |= OUT_OF_TXD ;
1634 #endif 1594 #endif
1635 } 1595 }
1636 DB_TX("frame_status = %x",frame_statu 1596 DB_TX("frame_status = %x",frame_status,0,3) ;
1637 NDD_TRACE("THiE",frame_status,smc->os 1597 NDD_TRACE("THiE",frame_status,smc->os.hwm.tx_p->tx_free,0) ;
1638 return(frame_status) ; 1598 return(frame_status) ;
1639 } 1599 }
1640 1600
1641 /* 1601 /*
1642 * BEGIN_MANUAL_ENTRY(hwm_tx_frag) 1602 * BEGIN_MANUAL_ENTRY(hwm_tx_frag)
1643 * void hwm_tx_frag(smc,virt,phys,len,fr 1603 * void hwm_tx_frag(smc,virt,phys,len,frame_status)
1644 * 1604 *
1645 * function DOWNCALL (hardware mod 1605 * function DOWNCALL (hardware module, hwmtm.c)
1646 * If the frame should be sent t 1606 * If the frame should be sent to the LAN, this function calls
1647 * dma_master, fills the current 1607 * dma_master, fills the current TxD with the virtual and the
1648 * physical address, sets the ST 1608 * physical address, sets the STF and EOF bits dependent on
1649 * the frame status, and request 1609 * the frame status, and requests the BMU to start the
1650 * transmit. 1610 * transmit.
1651 * If the frame should be sent t 1611 * If the frame should be sent to the local SMT, an SMT_MBuf
1652 * is allocated if the FIRST_FRA 1612 * is allocated if the FIRST_FRAG bit is set in the frame_status.
1653 * The fragment of the frame is 1613 * The fragment of the frame is copied into the SMT MBuf.
1654 * The function smt_received_pac 1614 * The function smt_received_pack is called if the LAST_FRAG
1655 * bit is set in the frame_statu 1615 * bit is set in the frame_status word.
1656 * 1616 *
1657 * para virt virtual pointer to the fragme 1617 * para virt virtual pointer to the fragment
1658 * len the length of the fragment 1618 * len the length of the fragment
1659 * frame_status status of the frame, 1619 * frame_status status of the frame, see design description
1660 * 1620 *
1661 * return nothing returned, no paramete 1621 * return nothing returned, no parameter is modified
1662 * 1622 *
1663 * NOTE: It is possible to invoke this 1623 * NOTE: It is possible to invoke this macro with a fragment length
1664 * of zero. 1624 * of zero.
1665 * 1625 *
1666 * END_MANUAL_ENTRY 1626 * END_MANUAL_ENTRY
1667 */ 1627 */
1668 void hwm_tx_frag(struct s_smc *smc, char far 1628 void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1669 int frame_status) 1629 int frame_status)
1670 { 1630 {
1671 struct s_smt_fp_txd volatile *t ; 1631 struct s_smt_fp_txd volatile *t ;
1672 struct s_smt_tx_queue *queue ; 1632 struct s_smt_tx_queue *queue ;
1673 u_int tbctrl ; !! 1633 __le32 tbctrl ;
1674 1634
1675 queue = smc->os.hwm.tx_p ; 1635 queue = smc->os.hwm.tx_p ;
1676 1636
1677 NDD_TRACE("THfB",virt,len,frame_statu 1637 NDD_TRACE("THfB",virt,len,frame_status) ;
1678 /* Bug fix: AF / May 31 1999 (#missin 1638 /* Bug fix: AF / May 31 1999 (#missing)
1679 * snmpinfo problem reported by IBM i 1639 * snmpinfo problem reported by IBM is caused by invalid
1680 * t-pointer (txd) if LAN_TX is not s 1640 * t-pointer (txd) if LAN_TX is not set but LOC_TX only.
1681 * Set: t = queue->tx_curr_put here 1641 * Set: t = queue->tx_curr_put here !
1682 */ 1642 */
1683 t = queue->tx_curr_put ; 1643 t = queue->tx_curr_put ;
1684 1644
1685 DB_TX("hwm_tx_frag: len = %d, frame_s 1645 DB_TX("hwm_tx_frag: len = %d, frame_status = %x ",len,frame_status,2) ;
1686 if (frame_status & LAN_TX) { 1646 if (frame_status & LAN_TX) {
1687 /* '*t' is already defined */ 1647 /* '*t' is already defined */
1688 DB_TX("LAN_TX: TxD = %x, virt 1648 DB_TX("LAN_TX: TxD = %x, virt = %x ",t,virt,3) ;
1689 t->txd_virt = virt ; 1649 t->txd_virt = virt ;
1690 t->txd_txdscr = AIX_REVERSE(s !! 1650 t->txd_txdscr = cpu_to_le32(smc->os.hwm.tx_descr) ;
1691 t->txd_tbadr = AIX_REVERSE(ph !! 1651 t->txd_tbadr = cpu_to_le32(phys) ;
1692 tbctrl = AIX_REVERSE((((u_lon !! 1652 tbctrl = cpu_to_le32((((__u32)frame_status &
1693 (FIRST_FRAG|LAST_FRAG 1653 (FIRST_FRAG|LAST_FRAG|EN_IRQ_EOF))<< 26) |
1694 BMU_OWN|BMU_CHECK |le 1654 BMU_OWN|BMU_CHECK |len) ;
1695 t->txd_tbctrl = tbctrl ; 1655 t->txd_tbctrl = tbctrl ;
1696 1656
1697 #ifndef AIX 1657 #ifndef AIX
1698 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_ 1658 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1699 outpd(queue->tx_bmu_ctl,CSR_S 1659 outpd(queue->tx_bmu_ctl,CSR_START) ;
1700 #else /* ifndef AIX */ 1660 #else /* ifndef AIX */
1701 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_ 1661 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1702 if (frame_status & QUEUE_A0) 1662 if (frame_status & QUEUE_A0) {
1703 outpd(ADDR(B0_XA_CSR) 1663 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1704 } 1664 }
1705 else { 1665 else {
1706 outpd(ADDR(B0_XS_CSR) 1666 outpd(ADDR(B0_XS_CSR),CSR_START) ;
1707 } 1667 }
1708 #endif 1668 #endif
1709 queue->tx_free-- ; 1669 queue->tx_free-- ;
1710 queue->tx_used++ ; 1670 queue->tx_used++ ;
1711 queue->tx_curr_put = t->txd_n 1671 queue->tx_curr_put = t->txd_next ;
1712 if (frame_status & LAST_FRAG) 1672 if (frame_status & LAST_FRAG) {
1713 smc->mib.m[MAC0].fddi 1673 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1714 } 1674 }
1715 } 1675 }
1716 if (frame_status & LOC_TX) { 1676 if (frame_status & LOC_TX) {
1717 DB_TX("LOC_TX: ",0,0,3) ; 1677 DB_TX("LOC_TX: ",0,0,3) ;
1718 if (frame_status & FIRST_FRAG 1678 if (frame_status & FIRST_FRAG) {
1719 if(!(smc->os.hwm.tx_m 1679 if(!(smc->os.hwm.tx_mb = smt_get_mbuf(smc))) {
1720 smc->hw.fp.er 1680 smc->hw.fp.err_stats.err_no_buf++ ;
1721 DB_TX("No SMb 1681 DB_TX("No SMbuf; transmit terminated",0,0,4) ;
1722 } 1682 }
1723 else { 1683 else {
1724 smc->os.hwm.t 1684 smc->os.hwm.tx_data =
1725 smtod 1685 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1726 #ifdef USE_OS_CPY 1686 #ifdef USE_OS_CPY
1727 #ifdef PASS_1ST_TXD_2_TX_COMP 1687 #ifdef PASS_1ST_TXD_2_TX_COMP
1728 hwm_cpy_txd2m 1688 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1729 smc-> 1689 smc->os.hwm.tx_len) ;
1730 #endif 1690 #endif
1731 #endif 1691 #endif
1732 } 1692 }
1733 } 1693 }
1734 if (smc->os.hwm.tx_mb) { 1694 if (smc->os.hwm.tx_mb) {
1735 #ifndef USE_OS_CPY 1695 #ifndef USE_OS_CPY
1736 DB_TX("copy fragment 1696 DB_TX("copy fragment into MBuf ",0,0,3) ;
1737 memcpy(smc->os.hwm.tx 1697 memcpy(smc->os.hwm.tx_data,virt,len) ;
1738 smc->os.hwm.tx_data + 1698 smc->os.hwm.tx_data += len ;
1739 #endif 1699 #endif
1740 if (frame_status & LA 1700 if (frame_status & LAST_FRAG) {
1741 #ifdef USE_OS_CPY 1701 #ifdef USE_OS_CPY
1742 #ifndef PASS_1ST_TXD_2_TX_COMP 1702 #ifndef PASS_1ST_TXD_2_TX_COMP
1743 /* 1703 /*
1744 * hwm_cpy_tx 1704 * hwm_cpy_txd2mb(txd,data,len) copies 'len'
1745 * bytes from 1705 * bytes from the virtual pointer in 'rxd'
1746 * to 'data'. 1706 * to 'data'. The virtual pointer of the
1747 * os-specifi 1707 * os-specific tx-buffer should be written
1748 * in the LAS 1708 * in the LAST txd.
1749 */ 1709 */
1750 hwm_cpy_txd2m 1710 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1751 smc-> 1711 smc->os.hwm.tx_len) ;
1752 #endif /* nPASS_1ST_TXD_2_TX_COMP */ 1712 #endif /* nPASS_1ST_TXD_2_TX_COMP */
1753 #endif /* USE_OS_CPY */ 1713 #endif /* USE_OS_CPY */
1754 smc->os.hwm.t 1714 smc->os.hwm.tx_data =
1755 smtod 1715 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1756 *(char *)smc- 1716 *(char *)smc->os.hwm.tx_mb->sm_data =
1757 *smc- 1717 *smc->os.hwm.tx_data ;
1758 smc->os.hwm.t 1718 smc->os.hwm.tx_data++ ;
1759 smc->os.hwm.t 1719 smc->os.hwm.tx_mb->sm_len =
1760 smc-> 1720 smc->os.hwm.tx_len - 1 ;
1761 DB_TX("pass L 1721 DB_TX("pass LLC frame to SMT ",0,0,3) ;
1762 smt_received_ 1722 smt_received_pack(smc,smc->os.hwm.tx_mb,
1763 1723 RD_FS_LOCAL) ;
1764 } 1724 }
1765 } 1725 }
1766 } 1726 }
1767 NDD_TRACE("THfE",t,queue->tx_free,0) 1727 NDD_TRACE("THfE",t,queue->tx_free,0) ;
1768 } 1728 }
1769 1729
1770 1730
1771 /* 1731 /*
1772 * queues a receive for later send 1732 * queues a receive for later send
1773 */ 1733 */
1774 static void queue_llc_rx(struct s_smc *smc, S 1734 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb)
1775 { 1735 {
1776 DB_GEN("queue_llc_rx: mb = %x",(void 1736 DB_GEN("queue_llc_rx: mb = %x",(void *)mb,0,4) ;
1777 smc->os.hwm.queued_rx_frames++ ; 1737 smc->os.hwm.queued_rx_frames++ ;
1778 mb->sm_next = (SMbuf *)NULL ; 1738 mb->sm_next = (SMbuf *)NULL ;
1779 if (smc->os.hwm.llc_rx_pipe == 0) { !! 1739 if (smc->os.hwm.llc_rx_pipe == NULL) {
1780 smc->os.hwm.llc_rx_pipe = mb 1740 smc->os.hwm.llc_rx_pipe = mb ;
1781 } 1741 }
1782 else { 1742 else {
1783 smc->os.hwm.llc_rx_tail->sm_n 1743 smc->os.hwm.llc_rx_tail->sm_next = mb ;
1784 } 1744 }
1785 smc->os.hwm.llc_rx_tail = mb ; 1745 smc->os.hwm.llc_rx_tail = mb ;
1786 1746
1787 /* 1747 /*
1788 * force an timer IRQ to receive the 1748 * force an timer IRQ to receive the data
1789 */ 1749 */
1790 if (!smc->os.hwm.isr_flag) { 1750 if (!smc->os.hwm.isr_flag) {
1791 smt_force_irq(smc) ; 1751 smt_force_irq(smc) ;
1792 } 1752 }
1793 } 1753 }
1794 1754
1795 /* 1755 /*
1796 * get a SMbuf from the llc_rx_queue 1756 * get a SMbuf from the llc_rx_queue
1797 */ 1757 */
1798 static SMbuf *get_llc_rx(struct s_smc *smc) 1758 static SMbuf *get_llc_rx(struct s_smc *smc)
1799 { 1759 {
1800 SMbuf *mb ; 1760 SMbuf *mb ;
1801 1761
1802 if ((mb = smc->os.hwm.llc_rx_pipe)) { 1762 if ((mb = smc->os.hwm.llc_rx_pipe)) {
1803 smc->os.hwm.queued_rx_frames- 1763 smc->os.hwm.queued_rx_frames-- ;
1804 smc->os.hwm.llc_rx_pipe = mb- 1764 smc->os.hwm.llc_rx_pipe = mb->sm_next ;
1805 } 1765 }
1806 DB_GEN("get_llc_rx: mb = 0x%x",(void 1766 DB_GEN("get_llc_rx: mb = 0x%x",(void *)mb,0,4) ;
1807 return(mb) ; 1767 return(mb) ;
1808 } 1768 }
1809 1769
1810 /* 1770 /*
1811 * queues a transmit SMT MBuf during the time 1771 * queues a transmit SMT MBuf during the time were the MBuf is
1812 * queued the TxD ring 1772 * queued the TxD ring
1813 */ 1773 */
1814 static void queue_txd_mb(struct s_smc *smc, S 1774 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb)
1815 { 1775 {
1816 DB_GEN("_rx: queue_txd_mb = %x",(void 1776 DB_GEN("_rx: queue_txd_mb = %x",(void *)mb,0,4) ;
1817 smc->os.hwm.queued_txd_mb++ ; 1777 smc->os.hwm.queued_txd_mb++ ;
1818 mb->sm_next = (SMbuf *)NULL ; 1778 mb->sm_next = (SMbuf *)NULL ;
1819 if (smc->os.hwm.txd_tx_pipe == 0) { !! 1779 if (smc->os.hwm.txd_tx_pipe == NULL) {
1820 smc->os.hwm.txd_tx_pipe = mb 1780 smc->os.hwm.txd_tx_pipe = mb ;
1821 } 1781 }
1822 else { 1782 else {
1823 smc->os.hwm.txd_tx_tail->sm_n 1783 smc->os.hwm.txd_tx_tail->sm_next = mb ;
1824 } 1784 }
1825 smc->os.hwm.txd_tx_tail = mb ; 1785 smc->os.hwm.txd_tx_tail = mb ;
1826 } 1786 }
1827 1787
1828 /* 1788 /*
1829 * get a SMbuf from the txd_tx_queue 1789 * get a SMbuf from the txd_tx_queue
1830 */ 1790 */
1831 static SMbuf *get_txd_mb(struct s_smc *smc) 1791 static SMbuf *get_txd_mb(struct s_smc *smc)
1832 { 1792 {
1833 SMbuf *mb ; 1793 SMbuf *mb ;
1834 1794
1835 if ((mb = smc->os.hwm.txd_tx_pipe)) { 1795 if ((mb = smc->os.hwm.txd_tx_pipe)) {
1836 smc->os.hwm.queued_txd_mb-- ; 1796 smc->os.hwm.queued_txd_mb-- ;
1837 smc->os.hwm.txd_tx_pipe = mb- 1797 smc->os.hwm.txd_tx_pipe = mb->sm_next ;
1838 } 1798 }
1839 DB_GEN("get_txd_mb: mb = 0x%x",(void 1799 DB_GEN("get_txd_mb: mb = 0x%x",(void *)mb,0,4) ;
1840 return(mb) ; 1800 return(mb) ;
1841 } 1801 }
1842 1802
1843 /* 1803 /*
1844 * SMT Send function 1804 * SMT Send function
1845 */ 1805 */
1846 void smt_send_mbuf(struct s_smc *smc, SMbuf * 1806 void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc)
1847 { 1807 {
1848 char far *data ; 1808 char far *data ;
1849 int len ; 1809 int len ;
1850 int n ; 1810 int n ;
1851 int i ; 1811 int i ;
1852 int frag_count ; 1812 int frag_count ;
1853 int frame_status ; 1813 int frame_status ;
1854 SK_LOC_DECL(char far,*virt[3]) ; 1814 SK_LOC_DECL(char far,*virt[3]) ;
1855 int frag_len[3] ; 1815 int frag_len[3] ;
1856 struct s_smt_tx_queue *queue ; 1816 struct s_smt_tx_queue *queue ;
1857 struct s_smt_fp_txd volatile *t ; 1817 struct s_smt_fp_txd volatile *t ;
1858 u_long phys ; 1818 u_long phys ;
1859 u_int tbctrl ; !! 1819 __le32 tbctrl;
1860 1820
1861 NDD_TRACE("THSB",mb,fc,0) ; 1821 NDD_TRACE("THSB",mb,fc,0) ;
1862 DB_TX("smt_send_mbuf: mb = 0x%x, fc = 1822 DB_TX("smt_send_mbuf: mb = 0x%x, fc = 0x%x",mb,fc,4) ;
1863 1823
1864 mb->sm_off-- ; /* set to fc */ 1824 mb->sm_off-- ; /* set to fc */
1865 mb->sm_len++ ; /* + fc */ 1825 mb->sm_len++ ; /* + fc */
1866 data = smtod(mb,char *) ; 1826 data = smtod(mb,char *) ;
1867 *data = fc ; 1827 *data = fc ;
1868 if (fc == FC_SMT_LOC) 1828 if (fc == FC_SMT_LOC)
1869 *data = FC_SMT_INFO ; 1829 *data = FC_SMT_INFO ;
1870 1830
1871 /* 1831 /*
1872 * determine the frag count and the v 1832 * determine the frag count and the virt addresses of the frags
1873 */ 1833 */
1874 frag_count = 0 ; 1834 frag_count = 0 ;
1875 len = mb->sm_len ; 1835 len = mb->sm_len ;
1876 while (len) { 1836 while (len) {
1877 n = SMT_PAGESIZE - ((long)dat 1837 n = SMT_PAGESIZE - ((long)data & (SMT_PAGESIZE-1)) ;
1878 if (n >= len) { 1838 if (n >= len) {
1879 n = len ; 1839 n = len ;
1880 } 1840 }
1881 DB_TX("frag: virt/len = 0x%x/ 1841 DB_TX("frag: virt/len = 0x%x/%d ",(void *)data,n,5) ;
1882 virt[frag_count] = data ; 1842 virt[frag_count] = data ;
1883 frag_len[frag_count] = n ; 1843 frag_len[frag_count] = n ;
1884 frag_count++ ; 1844 frag_count++ ;
1885 len -= n ; 1845 len -= n ;
1886 data += n ; 1846 data += n ;
1887 } 1847 }
1888 1848
1889 /* 1849 /*
1890 * determine the frame status 1850 * determine the frame status
1891 */ 1851 */
1892 queue = smc->hw.fp.tx[QUEUE_A0] ; 1852 queue = smc->hw.fp.tx[QUEUE_A0] ;
1893 if (fc == FC_BEACON || fc == FC_SMT_L 1853 if (fc == FC_BEACON || fc == FC_SMT_LOC) {
1894 frame_status = LOC_TX ; 1854 frame_status = LOC_TX ;
1895 } 1855 }
1896 else { 1856 else {
1897 frame_status = LAN_TX ; 1857 frame_status = LAN_TX ;
1898 if ((smc->os.hwm.pass_NSA &&( 1858 if ((smc->os.hwm.pass_NSA &&(fc == FC_SMT_NSA)) ||
1899 (smc->os.hwm.pass_SMT &&(f 1859 (smc->os.hwm.pass_SMT &&(fc == FC_SMT_INFO)))
1900 frame_status |= LOC_T 1860 frame_status |= LOC_TX ;
1901 } 1861 }
1902 1862
1903 if (!smc->hw.mac_ring_is_up || frag_c 1863 if (!smc->hw.mac_ring_is_up || frag_count > queue->tx_free) {
1904 frame_status &= ~LAN_TX; 1864 frame_status &= ~LAN_TX;
1905 if (frame_status) { 1865 if (frame_status) {
1906 DB_TX("Ring is down: 1866 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1907 } 1867 }
1908 else { 1868 else {
1909 DB_TX("Ring is down: 1869 DB_TX("Ring is down: terminate transmission",0,0,2) ;
1910 smt_free_mbuf(smc,mb) 1870 smt_free_mbuf(smc,mb) ;
1911 return ; 1871 return ;
1912 } 1872 }
1913 } 1873 }
1914 DB_TX("frame_status = 0x%x ",frame_st 1874 DB_TX("frame_status = 0x%x ",frame_status,0,5) ;
1915 1875
1916 if ((frame_status & LAN_TX) && (frame 1876 if ((frame_status & LAN_TX) && (frame_status & LOC_TX)) {
1917 mb->sm_use_count = 2 ; 1877 mb->sm_use_count = 2 ;
1918 } 1878 }
1919 1879
1920 if (frame_status & LAN_TX) { 1880 if (frame_status & LAN_TX) {
1921 t = queue->tx_curr_put ; 1881 t = queue->tx_curr_put ;
1922 frame_status |= FIRST_FRAG ; 1882 frame_status |= FIRST_FRAG ;
1923 for (i = 0; i < frag_count; i 1883 for (i = 0; i < frag_count; i++) {
1924 DB_TX("init TxD = 0x% 1884 DB_TX("init TxD = 0x%x",(void *)t,0,5) ;
1925 if (i == frag_count-1 1885 if (i == frag_count-1) {
1926 frame_status 1886 frame_status |= LAST_FRAG ;
1927 t->txd_txdscr !! 1887 t->txd_txdscr = cpu_to_le32(TX_DESCRIPTOR |
1928 (((u_ !! 1888 (((__u32)(mb->sm_len-1)&3) << 27)) ;
1929 } 1889 }
1930 t->txd_virt = virt[i] 1890 t->txd_virt = virt[i] ;
1931 phys = dma_master(smc 1891 phys = dma_master(smc, (void far *)virt[i],
1932 frag_len[i], 1892 frag_len[i], DMA_RD|SMT_BUF) ;
1933 t->txd_tbadr = AIX_RE !! 1893 t->txd_tbadr = cpu_to_le32(phys) ;
1934 tbctrl = AIX_REVERSE( !! 1894 tbctrl = cpu_to_le32((((__u32)frame_status &
1935 (FIRST_FRAG|L 1895 (FIRST_FRAG|LAST_FRAG)) << 26) |
1936 BMU_OWN | BMU 1896 BMU_OWN | BMU_CHECK | BMU_SMT_TX |frag_len[i]) ;
1937 t->txd_tbctrl = tbctr 1897 t->txd_tbctrl = tbctrl ;
1938 #ifndef AIX 1898 #ifndef AIX
1939 DRV_BUF_FLUSH(t,DDI_D 1899 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1940 outpd(queue->tx_bmu_c 1900 outpd(queue->tx_bmu_ctl,CSR_START) ;
1941 #else 1901 #else
1942 DRV_BUF_FLUSH(t,DDI_D 1902 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1943 outpd(ADDR(B0_XA_CSR) 1903 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1944 #endif 1904 #endif
1945 frame_status &= ~FIRS 1905 frame_status &= ~FIRST_FRAG ;
1946 queue->tx_curr_put = 1906 queue->tx_curr_put = t = t->txd_next ;
1947 queue->tx_free-- ; 1907 queue->tx_free-- ;
1948 queue->tx_used++ ; 1908 queue->tx_used++ ;
1949 } 1909 }
1950 smc->mib.m[MAC0].fddiMACTrans 1910 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1951 queue_txd_mb(smc,mb) ; 1911 queue_txd_mb(smc,mb) ;
1952 } 1912 }
1953 1913
1954 if (frame_status & LOC_TX) { 1914 if (frame_status & LOC_TX) {
1955 DB_TX("pass Mbuf to LLC queue 1915 DB_TX("pass Mbuf to LLC queue",0,0,5) ;
1956 queue_llc_rx(smc,mb) ; 1916 queue_llc_rx(smc,mb) ;
1957 } 1917 }
1958 1918
1959 /* 1919 /*
1960 * We need to unqueue the free SMT_MB 1920 * We need to unqueue the free SMT_MBUFs here, because it may
1961 * be that the SMT want's to send mor 1921 * be that the SMT want's to send more than 1 frame for one down call
1962 */ 1922 */
1963 mac_drv_clear_txd(smc) ; 1923 mac_drv_clear_txd(smc) ;
1964 NDD_TRACE("THSE",t,queue->tx_free,fra 1924 NDD_TRACE("THSE",t,queue->tx_free,frag_count) ;
1965 } 1925 }
1966 1926
1967 /* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd) 1927 /* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd)
1968 * void mac_drv_clear_txd(smc) 1928 * void mac_drv_clear_txd(smc)
1969 * 1929 *
1970 * function DOWNCALL (hardware mod 1930 * function DOWNCALL (hardware module, hwmtm.c)
1971 * mac_drv_clear_txd searches in 1931 * mac_drv_clear_txd searches in both send queues for TxD's
1972 * which were finished by the ad 1932 * which were finished by the adapter. It calls dma_complete
1973 * for each TxD. If the last fra 1933 * for each TxD. If the last fragment of an LLC frame is
1974 * reached, it calls mac_drv_tx_ 1934 * reached, it calls mac_drv_tx_complete to release the
1975 * send buffer. 1935 * send buffer.
1976 * 1936 *
1977 * return nothing 1937 * return nothing
1978 * 1938 *
1979 * END_MANUAL_ENTRY 1939 * END_MANUAL_ENTRY
1980 */ 1940 */
1981 void mac_drv_clear_txd(struct s_smc *smc) !! 1941 static void mac_drv_clear_txd(struct s_smc *smc)
1982 { 1942 {
1983 struct s_smt_tx_queue *queue ; 1943 struct s_smt_tx_queue *queue ;
1984 struct s_smt_fp_txd volatile *t1 ; 1944 struct s_smt_fp_txd volatile *t1 ;
1985 struct s_smt_fp_txd volatile *t2 = NU 1945 struct s_smt_fp_txd volatile *t2 = NULL ;
1986 SMbuf *mb ; 1946 SMbuf *mb ;
1987 u_long tbctrl ; 1947 u_long tbctrl ;
1988 int i ; 1948 int i ;
1989 int frag_count ; 1949 int frag_count ;
1990 int n ; 1950 int n ;
1991 1951
1992 NDD_TRACE("THcB",0,0,0) ; 1952 NDD_TRACE("THcB",0,0,0) ;
1993 for (i = QUEUE_S; i <= QUEUE_A0; i++) 1953 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
1994 queue = smc->hw.fp.tx[i] ; 1954 queue = smc->hw.fp.tx[i] ;
1995 t1 = queue->tx_curr_get ; 1955 t1 = queue->tx_curr_get ;
1996 DB_TX("clear_txd: QUEUE = %d 1956 DB_TX("clear_txd: QUEUE = %d (0=sync/1=async)",i,0,5) ;
1997 1957
1998 for ( ; ; ) { 1958 for ( ; ; ) {
1999 frag_count = 0 ; 1959 frag_count = 0 ;
2000 1960
2001 do { 1961 do {
2002 DRV_BUF_FLUSH 1962 DRV_BUF_FLUSH(t1,DDI_DMA_SYNC_FORCPU) ;
2003 DB_TX("check 1963 DB_TX("check OWN/EOF bit of TxD 0x%x",t1,0,5) ;
2004 tbctrl = CR_R !! 1964 tbctrl = le32_to_cpu(CR_READ(t1->txd_tbctrl));
2005 tbctrl = AIX_ <<
2006 1965
2007 if (tbctrl & 1966 if (tbctrl & BMU_OWN || !queue->tx_used){
2008 DB_TX 1967 DB_TX("End of TxDs queue %d",i,0,4) ;
2009 goto 1968 goto free_next_queue ; /* next queue */
2010 } 1969 }
2011 t1 = t1->txd_ 1970 t1 = t1->txd_next ;
2012 frag_count++ 1971 frag_count++ ;
2013 } while (!(tbctrl & B 1972 } while (!(tbctrl & BMU_EOF)) ;
2014 1973
2015 t1 = queue->tx_curr_g 1974 t1 = queue->tx_curr_get ;
2016 for (n = frag_count; 1975 for (n = frag_count; n; n--) {
2017 tbctrl = AIX_ !! 1976 tbctrl = le32_to_cpu(t1->txd_tbctrl) ;
2018 dma_complete( 1977 dma_complete(smc,
2019 (unio 1978 (union s_fp_descr volatile *) t1,
2020 (int) 1979 (int) (DMA_RD |
2021 ((tbc 1980 ((tbctrl & BMU_SMT_TX) >> 18))) ;
2022 t2 = t1 ; 1981 t2 = t1 ;
2023 t1 = t1->txd_ 1982 t1 = t1->txd_next ;
2024 } 1983 }
2025 1984
2026 if (tbctrl & BMU_SMT_ 1985 if (tbctrl & BMU_SMT_TX) {
2027 mb = get_txd_ 1986 mb = get_txd_mb(smc) ;
2028 smt_free_mbuf 1987 smt_free_mbuf(smc,mb) ;
2029 } 1988 }
2030 else { 1989 else {
2031 #ifndef PASS_1ST_TXD_2_TX_COMP 1990 #ifndef PASS_1ST_TXD_2_TX_COMP
2032 DB_TX("mac_dr 1991 DB_TX("mac_drv_tx_comp for TxD 0x%x",t2,0,4) ;
2033 mac_drv_tx_co 1992 mac_drv_tx_complete(smc,t2) ;
2034 #else 1993 #else
2035 DB_TX("mac_dr 1994 DB_TX("mac_drv_tx_comp for TxD 0x%x",
2036 queue 1995 queue->tx_curr_get,0,4) ;
2037 mac_drv_tx_co 1996 mac_drv_tx_complete(smc,queue->tx_curr_get) ;
2038 #endif 1997 #endif
2039 } 1998 }
2040 queue->tx_curr_get = 1999 queue->tx_curr_get = t1 ;
2041 queue->tx_free += fra 2000 queue->tx_free += frag_count ;
2042 queue->tx_used -= fra 2001 queue->tx_used -= frag_count ;
2043 } 2002 }
2044 free_next_queue: ; 2003 free_next_queue: ;
2045 } 2004 }
2046 NDD_TRACE("THcE",0,0,0) ; 2005 NDD_TRACE("THcE",0,0,0) ;
2047 } 2006 }
2048 2007
2049 /* 2008 /*
2050 * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_ 2009 * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_queue)
2051 * 2010 *
2052 * void mac_drv_clear_tx_queue(smc) 2011 * void mac_drv_clear_tx_queue(smc)
2053 * struct s_smc *smc ; 2012 * struct s_smc *smc ;
2054 * 2013 *
2055 * function DOWNCALL (hardware mod 2014 * function DOWNCALL (hardware module, hwmtm.c)
2056 * mac_drv_clear_tx_queue is cal 2015 * mac_drv_clear_tx_queue is called from the SMT when
2057 * the RMT state machine has ent 2016 * the RMT state machine has entered the ISOLATE state.
2058 * This function is also called 2017 * This function is also called by the os-specific module
2059 * after it has called the funct 2018 * after it has called the function card_stop().
2060 * In this case, the frames in t 2019 * In this case, the frames in the send queues are obsolete and
2061 * should be removed. 2020 * should be removed.
2062 * 2021 *
2063 * note calling sequence: 2022 * note calling sequence:
2064 * CLI_FBI(), card_stop(), 2023 * CLI_FBI(), card_stop(),
2065 * mac_drv_clear_tx_queue(), mac 2024 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
2066 * 2025 *
2067 * NOTE: The caller is responsible tha 2026 * NOTE: The caller is responsible that the BMUs are idle
2068 * when this function is called. 2027 * when this function is called.
2069 * 2028 *
2070 * END_MANUAL_ENTRY 2029 * END_MANUAL_ENTRY
2071 */ 2030 */
2072 void mac_drv_clear_tx_queue(struct s_smc *smc 2031 void mac_drv_clear_tx_queue(struct s_smc *smc)
2073 { 2032 {
2074 struct s_smt_fp_txd volatile *t ; 2033 struct s_smt_fp_txd volatile *t ;
2075 struct s_smt_tx_queue *queue ; 2034 struct s_smt_tx_queue *queue ;
2076 int tx_used ; 2035 int tx_used ;
2077 int i ; 2036 int i ;
2078 2037
2079 if (smc->hw.hw_state != STOPPED) { 2038 if (smc->hw.hw_state != STOPPED) {
2080 SK_BREAK() ; 2039 SK_BREAK() ;
2081 SMT_PANIC(smc,HWM_E0011,HWM_E 2040 SMT_PANIC(smc,HWM_E0011,HWM_E0011_MSG) ;
2082 return ; 2041 return ;
2083 } 2042 }
2084 2043
2085 for (i = QUEUE_S; i <= QUEUE_A0; i++) 2044 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2086 queue = smc->hw.fp.tx[i] ; 2045 queue = smc->hw.fp.tx[i] ;
2087 DB_TX("clear_tx_queue: QUEUE 2046 DB_TX("clear_tx_queue: QUEUE = %d (0=sync/1=async)",i,0,5) ;
2088 2047
2089 /* 2048 /*
2090 * switch the OWN bit of all 2049 * switch the OWN bit of all pending frames to the host
2091 */ 2050 */
2092 t = queue->tx_curr_get ; 2051 t = queue->tx_curr_get ;
2093 tx_used = queue->tx_used ; 2052 tx_used = queue->tx_used ;
2094 while (tx_used) { 2053 while (tx_used) {
2095 DRV_BUF_FLUSH(t,DDI_D 2054 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
2096 DB_TX("switch OWN bit 2055 DB_TX("switch OWN bit of TxD 0x%x ",t,0,5) ;
2097 t->txd_tbctrl &= AIX_ !! 2056 t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
2098 DRV_BUF_FLUSH(t,DDI_D 2057 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
2099 t = t->txd_next ; 2058 t = t->txd_next ;
2100 tx_used-- ; 2059 tx_used-- ;
2101 } 2060 }
2102 } 2061 }
2103 2062
2104 /* 2063 /*
2105 * release all TxD's for both send qu 2064 * release all TxD's for both send queues
2106 */ 2065 */
2107 mac_drv_clear_txd(smc) ; 2066 mac_drv_clear_txd(smc) ;
2108 2067
2109 for (i = QUEUE_S; i <= QUEUE_A0; i++) 2068 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2110 queue = smc->hw.fp.tx[i] ; 2069 queue = smc->hw.fp.tx[i] ;
2111 t = queue->tx_curr_get ; 2070 t = queue->tx_curr_get ;
2112 2071
2113 /* 2072 /*
2114 * write the phys pointer of 2073 * write the phys pointer of the NEXT descriptor into the
2115 * BMU's current address desc 2074 * BMU's current address descriptor pointer and set
2116 * tx_curr_get and tx_curr_pu 2075 * tx_curr_get and tx_curr_put to this position
2117 */ 2076 */
2118 if (i == QUEUE_S) { 2077 if (i == QUEUE_S) {
2119 outpd(ADDR(B5_XS_DA), !! 2078 outpd(ADDR(B5_XS_DA),le32_to_cpu(t->txd_ntdadr)) ;
2120 } 2079 }
2121 else { 2080 else {
2122 outpd(ADDR(B5_XA_DA), !! 2081 outpd(ADDR(B5_XA_DA),le32_to_cpu(t->txd_ntdadr)) ;
2123 } 2082 }
2124 2083
2125 queue->tx_curr_put = queue->t 2084 queue->tx_curr_put = queue->tx_curr_get->txd_next ;
2126 queue->tx_curr_get = queue->t 2085 queue->tx_curr_get = queue->tx_curr_put ;
2127 } 2086 }
2128 } 2087 }
2129 2088
2130 2089
2131 /* 2090 /*
2132 ------------------------------------- 2091 -------------------------------------------------------------
2133 TEST FUNCTIONS: 2092 TEST FUNCTIONS:
2134 ------------------------------------- 2093 -------------------------------------------------------------
2135 */ 2094 */
2136 2095
2137 #ifdef DEBUG 2096 #ifdef DEBUG
2138 /* 2097 /*
2139 * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev) 2098 * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev)
2140 * void mac_drv_debug_lev(smc,flag,lev) 2099 * void mac_drv_debug_lev(smc,flag,lev)
2141 * 2100 *
2142 * function DOWNCALL (drvsr.c) 2101 * function DOWNCALL (drvsr.c)
2143 * To get a special debug info t 2102 * To get a special debug info the user can assign a debug level
2144 * to any debug flag. 2103 * to any debug flag.
2145 * 2104 *
2146 * para flag debug flag, possible values a 2105 * para flag debug flag, possible values are:
2147 * = 0: reset all deb 2106 * = 0: reset all debug flags (the defined level is
2148 * ignored) 2107 * ignored)
2149 * = 1: debug.d_smtf 2108 * = 1: debug.d_smtf
2150 * = 2: debug.d_smt 2109 * = 2: debug.d_smt
2151 * = 3: debug.d_ecm 2110 * = 3: debug.d_ecm
2152 * = 4: debug.d_rmt 2111 * = 4: debug.d_rmt
2153 * = 5: debug.d_cfm 2112 * = 5: debug.d_cfm
2154 * = 6: debug.d_pcm 2113 * = 6: debug.d_pcm
2155 * 2114 *
2156 * = 10: debug.d_os.hw 2115 * = 10: debug.d_os.hwm_rx (hardware module receive path)
2157 * = 11: debug.d_os.hw 2116 * = 11: debug.d_os.hwm_tx(hardware module transmit path)
2158 * = 12: debug.d_os.hw 2117 * = 12: debug.d_os.hwm_gen(hardware module general flag)
2159 * 2118 *
2160 * lev debug level 2119 * lev debug level
2161 * 2120 *
2162 * END_MANUAL_ENTRY 2121 * END_MANUAL_ENTRY
2163 */ 2122 */
2164 void mac_drv_debug_lev(struct s_smc *smc, int 2123 void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev)
2165 { 2124 {
2166 switch(flag) { 2125 switch(flag) {
2167 case (int)NULL: 2126 case (int)NULL:
2168 DB_P.d_smtf = DB_P.d_smt = DB 2127 DB_P.d_smtf = DB_P.d_smt = DB_P.d_ecm = DB_P.d_rmt = 0 ;
2169 DB_P.d_cfm = 0 ; 2128 DB_P.d_cfm = 0 ;
2170 DB_P.d_os.hwm_rx = DB_P.d_os. 2129 DB_P.d_os.hwm_rx = DB_P.d_os.hwm_tx = DB_P.d_os.hwm_gen = 0 ;
2171 #ifdef SBA 2130 #ifdef SBA
2172 DB_P.d_sba = 0 ; 2131 DB_P.d_sba = 0 ;
2173 #endif 2132 #endif
2174 #ifdef ESS 2133 #ifdef ESS
2175 DB_P.d_ess = 0 ; 2134 DB_P.d_ess = 0 ;
2176 #endif 2135 #endif
2177 break ; 2136 break ;
2178 case DEBUG_SMTF: 2137 case DEBUG_SMTF:
2179 DB_P.d_smtf = lev ; 2138 DB_P.d_smtf = lev ;
2180 break ; 2139 break ;
2181 case DEBUG_SMT: 2140 case DEBUG_SMT:
2182 DB_P.d_smt = lev ; 2141 DB_P.d_smt = lev ;
2183 break ; 2142 break ;
2184 case DEBUG_ECM: 2143 case DEBUG_ECM:
2185 DB_P.d_ecm = lev ; 2144 DB_P.d_ecm = lev ;
2186 break ; 2145 break ;
2187 case DEBUG_RMT: 2146 case DEBUG_RMT:
2188 DB_P.d_rmt = lev ; 2147 DB_P.d_rmt = lev ;
2189 break ; 2148 break ;
2190 case DEBUG_CFM: 2149 case DEBUG_CFM:
2191 DB_P.d_cfm = lev ; 2150 DB_P.d_cfm = lev ;
2192 break ; 2151 break ;
2193 case DEBUG_PCM: 2152 case DEBUG_PCM:
2194 DB_P.d_pcm = lev ; 2153 DB_P.d_pcm = lev ;
2195 break ; 2154 break ;
2196 case DEBUG_SBA: 2155 case DEBUG_SBA:
2197 #ifdef SBA 2156 #ifdef SBA
2198 DB_P.d_sba = lev ; 2157 DB_P.d_sba = lev ;
2199 #endif 2158 #endif
2200 break ; 2159 break ;
2201 case DEBUG_ESS: 2160 case DEBUG_ESS:
2202 #ifdef ESS 2161 #ifdef ESS
2203 DB_P.d_ess = lev ; 2162 DB_P.d_ess = lev ;
2204 #endif 2163 #endif
2205 break ; 2164 break ;
2206 case DB_HWM_RX: 2165 case DB_HWM_RX:
2207 DB_P.d_os.hwm_rx = lev ; 2166 DB_P.d_os.hwm_rx = lev ;
2208 break ; 2167 break ;
2209 case DB_HWM_TX: 2168 case DB_HWM_TX:
2210 DB_P.d_os.hwm_tx = lev ; 2169 DB_P.d_os.hwm_tx = lev ;
2211 break ; 2170 break ;
2212 case DB_HWM_GEN: 2171 case DB_HWM_GEN:
2213 DB_P.d_os.hwm_gen = lev ; 2172 DB_P.d_os.hwm_gen = lev ;
2214 break ; 2173 break ;
2215 default: 2174 default:
2216 break ; 2175 break ;
2217 } 2176 }
2218 } 2177 }
2219 #endif 2178 #endif
2220 2179
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