Diff markup
1 /* 1 /*
2 * drivers/net/mv64340_eth.c - Driver for MV64 !! 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@mo 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 * 4 *
5 * Based on the 64360 driver from: 5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il 6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 * 7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc., 8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani (lachwani@p !! 9 * written by Manish Lachwani
10 * 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux 11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 * 12 *
>> 13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
>> 14 * Dale Farnsworth <dale@farnsworth.org>
>> 15 *
>> 16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
>> 17 * <sjhill@realitydiluted.com>
>> 18 *
13 * This program is free software; you can redi 19 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Genera 20 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundatio 21 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any lat 22 * of the License, or (at your option) any later version.
17 * 23 *
18 * This program is distributed in the hope tha 24 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details 27 * GNU General Public License for more details.
22 * 28 *
23 * You should have received a copy of the GNU 29 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to t 30 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place - Suite 3 31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */ 32 */
27 #include <linux/config.h> <<
28 #include <linux/version.h> <<
29 #include <linux/module.h> <<
30 #include <linux/kernel.h> <<
31 #include <linux/config.h> <<
32 #include <linux/sched.h> <<
33 #include <linux/ptrace.h> <<
34 #include <linux/fcntl.h> <<
35 #include <linux/ioport.h> <<
36 #include <linux/interrupt.h> <<
37 #include <linux/slab.h> <<
38 #include <linux/string.h> <<
39 #include <linux/errno.h> <<
40 #include <linux/ip.h> <<
41 #include <linux/init.h> 33 #include <linux/init.h>
>> 34 #include <linux/dma-mapping.h>
42 #include <linux/in.h> 35 #include <linux/in.h>
43 #include <linux/pci.h> !! 36 #include <linux/ip.h>
44 #include <linux/workqueue.h> <<
45 #include <asm/smp.h> <<
46 #include <linux/skbuff.h> <<
47 #include <linux/tcp.h> 37 #include <linux/tcp.h>
48 #include <linux/netdevice.h> !! 38 #include <linux/udp.h>
49 #include <linux/etherdevice.h> 39 #include <linux/etherdevice.h>
50 #include <net/ip.h> <<
51 40
52 #include <linux/bitops.h> 41 #include <linux/bitops.h>
>> 42 #include <linux/delay.h>
>> 43 #include <linux/ethtool.h>
>> 44 #include <linux/platform_device.h>
>> 45
>> 46 #include <linux/module.h>
>> 47 #include <linux/kernel.h>
>> 48 #include <linux/spinlock.h>
>> 49 #include <linux/workqueue.h>
>> 50 #include <linux/mii.h>
>> 51
>> 52 #include <linux/mv643xx_eth.h>
>> 53
53 #include <asm/io.h> 54 #include <asm/io.h>
54 #include <asm/types.h> 55 #include <asm/types.h>
55 #include <asm/pgtable.h> 56 #include <asm/pgtable.h>
56 #include <asm/system.h> 57 #include <asm/system.h>
57 #include "mv643xx_eth.h" !! 58 #include <asm/delay.h>
>> 59 #include <asm/dma-mapping.h>
>> 60
>> 61 #define MV643XX_CHECKSUM_OFFLOAD_TX
>> 62 #define MV643XX_NAPI
>> 63 #define MV643XX_TX_FAST_REFILL
>> 64 #undef MV643XX_COAL
58 65
59 /* 66 /*
60 * The first part is the high level driver of !! 67 * Number of RX / TX descriptors on RX / TX rings.
>> 68 * Note that allocating RX descriptors is done by allocating the RX
>> 69 * ring AND a preallocated RX buffers (skb's) for each descriptor.
>> 70 * The TX descriptors only allocates the TX descriptors ring,
>> 71 * with no pre allocated TX buffers (skb's are allocated by higher layers.
61 */ 72 */
62 73
63 /* Definition for configuring driver */ !! 74 /* Default TX ring size is 1000 descriptors */
64 #undef MV64340_RX_QUEUE_FILL_ON_TASK !! 75 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
>> 76
>> 77 /* Default RX ring size is 400 descriptors */
>> 78 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
>> 79
>> 80 #define MV643XX_TX_COAL 100
>> 81 #ifdef MV643XX_COAL
>> 82 #define MV643XX_RX_COAL 100
>> 83 #endif
>> 84
>> 85 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
>> 86 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
>> 87 #else
>> 88 #define MAX_DESCS_PER_SKB 1
>> 89 #endif
>> 90
>> 91 #define ETH_VLAN_HLEN 4
>> 92 #define ETH_FCS_LEN 4
>> 93 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
>> 94 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
>> 95 ETH_VLAN_HLEN + ETH_FCS_LEN)
>> 96 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
>> 97 dma_get_cache_alignment())
>> 98
>> 99 /*
>> 100 * Registers shared between all ports.
>> 101 */
>> 102 #define PHY_ADDR_REG 0x0000
>> 103 #define SMI_REG 0x0004
>> 104
>> 105 /*
>> 106 * Per-port registers.
>> 107 */
>> 108 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
>> 109 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
>> 110 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
>> 111 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
>> 112 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
>> 113 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
>> 114 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
>> 115 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
>> 116 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
>> 117 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
>> 118 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
>> 119 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
>> 120 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
>> 121 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
>> 122 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
>> 123 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
>> 124 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
>> 125 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
>> 126 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
>> 127 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
>> 128 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
>> 129
>> 130 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
>> 131 #define UNICAST_NORMAL_MODE (0 << 0)
>> 132 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
>> 133 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
>> 134 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
>> 135 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
>> 136 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
>> 137 #define RECEIVE_BC_IF_IP (0 << 8)
>> 138 #define REJECT_BC_IF_IP (1 << 8)
>> 139 #define RECEIVE_BC_IF_ARP (0 << 9)
>> 140 #define REJECT_BC_IF_ARP (1 << 9)
>> 141 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
>> 142 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
>> 143 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
>> 144 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
>> 145 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
>> 146 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
>> 147 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
>> 148 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
>> 149
>> 150 #define PORT_CONFIG_DEFAULT_VALUE \
>> 151 UNICAST_NORMAL_MODE | \
>> 152 DEFAULT_RX_QUEUE(0) | \
>> 153 DEFAULT_RX_ARP_QUEUE(0) | \
>> 154 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
>> 155 RECEIVE_BC_IF_IP | \
>> 156 RECEIVE_BC_IF_ARP | \
>> 157 CAPTURE_TCP_FRAMES_DIS | \
>> 158 CAPTURE_UDP_FRAMES_DIS | \
>> 159 DEFAULT_RX_TCP_QUEUE(0) | \
>> 160 DEFAULT_RX_UDP_QUEUE(0) | \
>> 161 DEFAULT_RX_BPDU_QUEUE(0)
>> 162
>> 163 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
>> 164 #define CLASSIFY_EN (1 << 0)
>> 165 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
>> 166 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
>> 167 #define PARTITION_DISABLE (0 << 2)
>> 168 #define PARTITION_ENABLE (1 << 2)
>> 169
>> 170 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
>> 171 SPAN_BPDU_PACKETS_AS_NORMAL | \
>> 172 PARTITION_DISABLE
>> 173
>> 174 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
>> 175 #define RIFB (1 << 0)
>> 176 #define RX_BURST_SIZE_1_64BIT (0 << 1)
>> 177 #define RX_BURST_SIZE_2_64BIT (1 << 1)
>> 178 #define RX_BURST_SIZE_4_64BIT (2 << 1)
>> 179 #define RX_BURST_SIZE_8_64BIT (3 << 1)
>> 180 #define RX_BURST_SIZE_16_64BIT (4 << 1)
>> 181 #define BLM_RX_NO_SWAP (1 << 4)
>> 182 #define BLM_RX_BYTE_SWAP (0 << 4)
>> 183 #define BLM_TX_NO_SWAP (1 << 5)
>> 184 #define BLM_TX_BYTE_SWAP (0 << 5)
>> 185 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
>> 186 #define DESCRIPTORS_NO_SWAP (0 << 6)
>> 187 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
>> 188 #define TX_BURST_SIZE_1_64BIT (0 << 22)
>> 189 #define TX_BURST_SIZE_2_64BIT (1 << 22)
>> 190 #define TX_BURST_SIZE_4_64BIT (2 << 22)
>> 191 #define TX_BURST_SIZE_8_64BIT (3 << 22)
>> 192 #define TX_BURST_SIZE_16_64BIT (4 << 22)
>> 193
>> 194 #if defined(__BIG_ENDIAN)
>> 195 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
>> 196 RX_BURST_SIZE_4_64BIT | \
>> 197 IPG_INT_RX(0) | \
>> 198 TX_BURST_SIZE_4_64BIT
>> 199 #elif defined(__LITTLE_ENDIAN)
>> 200 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
>> 201 RX_BURST_SIZE_4_64BIT | \
>> 202 BLM_RX_NO_SWAP | \
>> 203 BLM_TX_NO_SWAP | \
>> 204 IPG_INT_RX(0) | \
>> 205 TX_BURST_SIZE_4_64BIT
>> 206 #else
>> 207 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
>> 208 #endif
65 209
66 /* Constants */ !! 210 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
67 #define EXTRA_BYTES 32 !! 211 #define SERIAL_PORT_DISABLE (0 << 0)
68 #define WRAP ETH_HLEN + 2 + 4 + 16 !! 212 #define SERIAL_PORT_ENABLE (1 << 0)
69 #define BUFFER_MTU dev->mtu + WRAP !! 213 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
70 #define INT_CAUSE_UNMASK_ALL 0x0007 !! 214 #define FORCE_LINK_PASS (1 << 1)
71 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011 !! 215 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
72 #ifdef MV64340_RX_FILL_ON_TASK !! 216 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
73 #define INT_CAUSE_MASK_ALL 0x0000 !! 217 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
74 #define INT_CAUSE_CHECK_BITS INT_CA !! 218 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
75 #define INT_CAUSE_CHECK_BITS_EXT INT_CA !! 219 #define ADV_NO_FLOW_CTRL (0 << 4)
>> 220 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
>> 221 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
>> 222 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
>> 223 #define FORCE_BP_MODE_NO_JAM (0 << 7)
>> 224 #define FORCE_BP_MODE_JAM_TX (1 << 7)
>> 225 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
>> 226 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
>> 227 #define FORCE_LINK_FAIL (0 << 10)
>> 228 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
>> 229 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
>> 230 #define RETRANSMIT_FOREVER (1 << 11)
>> 231 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
>> 232 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
>> 233 #define DTE_ADV_0 (0 << 14)
>> 234 #define DTE_ADV_1 (1 << 14)
>> 235 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
>> 236 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
>> 237 #define AUTO_NEG_NO_CHANGE (0 << 16)
>> 238 #define RESTART_AUTO_NEG (1 << 16)
>> 239 #define MAX_RX_PACKET_1518BYTE (0 << 17)
>> 240 #define MAX_RX_PACKET_1522BYTE (1 << 17)
>> 241 #define MAX_RX_PACKET_1552BYTE (2 << 17)
>> 242 #define MAX_RX_PACKET_9022BYTE (3 << 17)
>> 243 #define MAX_RX_PACKET_9192BYTE (4 << 17)
>> 244 #define MAX_RX_PACKET_9700BYTE (5 << 17)
>> 245 #define MAX_RX_PACKET_MASK (7 << 17)
>> 246 #define CLR_EXT_LOOPBACK (0 << 20)
>> 247 #define SET_EXT_LOOPBACK (1 << 20)
>> 248 #define SET_HALF_DUPLEX_MODE (0 << 21)
>> 249 #define SET_FULL_DUPLEX_MODE (1 << 21)
>> 250 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
>> 251 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
>> 252 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
>> 253 #define SET_GMII_SPEED_TO_1000 (1 << 23)
>> 254 #define SET_MII_SPEED_TO_10 (0 << 24)
>> 255 #define SET_MII_SPEED_TO_100 (1 << 24)
>> 256
>> 257 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
>> 258 DO_NOT_FORCE_LINK_PASS | \
>> 259 ENABLE_AUTO_NEG_FOR_DUPLX | \
>> 260 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
>> 261 ADV_SYMMETRIC_FLOW_CTRL | \
>> 262 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
>> 263 FORCE_BP_MODE_NO_JAM | \
>> 264 (1 << 9) /* reserved */ | \
>> 265 DO_NOT_FORCE_LINK_FAIL | \
>> 266 RETRANSMIT_16_ATTEMPTS | \
>> 267 ENABLE_AUTO_NEG_SPEED_GMII | \
>> 268 DTE_ADV_0 | \
>> 269 DISABLE_AUTO_NEG_BYPASS | \
>> 270 AUTO_NEG_NO_CHANGE | \
>> 271 MAX_RX_PACKET_9700BYTE | \
>> 272 CLR_EXT_LOOPBACK | \
>> 273 SET_FULL_DUPLEX_MODE | \
>> 274 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
>> 275
>> 276 /* These macros describe Ethernet Serial Status reg (PSR) bits */
>> 277 #define PORT_STATUS_MODE_10_BIT (1 << 0)
>> 278 #define PORT_STATUS_LINK_UP (1 << 1)
>> 279 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
>> 280 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
>> 281 #define PORT_STATUS_GMII_1000 (1 << 4)
>> 282 #define PORT_STATUS_MII_100 (1 << 5)
>> 283 /* PSR bit 6 is undocumented */
>> 284 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
>> 285 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
>> 286 #define PORT_STATUS_PARTITION (1 << 9)
>> 287 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
>> 288 /* PSR bits 11-31 are reserved */
>> 289
>> 290 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
>> 291 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
>> 292
>> 293 #define DESC_SIZE 64
>> 294
>> 295 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
>> 296 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
>> 297
>> 298 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
>> 299 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
>> 300 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
>> 301 #define ETH_INT_CAUSE_EXT 0x00000002
>> 302 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
>> 303
>> 304 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
>> 305 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
>> 306 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
>> 307 #define ETH_INT_CAUSE_PHY 0x00010000
>> 308 #define ETH_INT_CAUSE_STATE 0x00100000
>> 309 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
>> 310 ETH_INT_CAUSE_STATE)
>> 311
>> 312 #define ETH_INT_MASK_ALL 0x00000000
>> 313 #define ETH_INT_MASK_ALL_EXT 0x00000000
>> 314
>> 315 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
>> 316 #define PHY_WAIT_MICRO_SECONDS 10
>> 317
>> 318 /* Buffer offset from buffer pointer */
>> 319 #define RX_BUF_OFFSET 0x2
>> 320
>> 321 /* Gigabit Ethernet Unit Global Registers */
>> 322
>> 323 /* MIB Counters register definitions */
>> 324 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
>> 325 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
>> 326 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
>> 327 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
>> 328 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
>> 329 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
>> 330 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
>> 331 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
>> 332 #define ETH_MIB_FRAMES_64_OCTETS 0x20
>> 333 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
>> 334 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
>> 335 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
>> 336 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
>> 337 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
>> 338 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
>> 339 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
>> 340 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
>> 341 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
>> 342 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
>> 343 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
>> 344 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
>> 345 #define ETH_MIB_FC_SENT 0x54
>> 346 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
>> 347 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
>> 348 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
>> 349 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
>> 350 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
>> 351 #define ETH_MIB_JABBER_RECEIVED 0x6c
>> 352 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
>> 353 #define ETH_MIB_BAD_CRC_EVENT 0x74
>> 354 #define ETH_MIB_COLLISION 0x78
>> 355 #define ETH_MIB_LATE_COLLISION 0x7c
>> 356
>> 357 /* Port serial status reg (PSR) */
>> 358 #define ETH_INTERFACE_PCM 0x00000001
>> 359 #define ETH_LINK_IS_UP 0x00000002
>> 360 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
>> 361 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
>> 362 #define ETH_GMII_SPEED_1000 0x00000010
>> 363 #define ETH_MII_SPEED_100 0x00000020
>> 364 #define ETH_TX_IN_PROGRESS 0x00000080
>> 365 #define ETH_BYPASS_ACTIVE 0x00000100
>> 366 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
>> 367 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
>> 368
>> 369 /* SMI reg */
>> 370 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
>> 371 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
>> 372 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
>> 373 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
>> 374
>> 375 /* Interrupt Cause Register Bit Definitions */
>> 376
>> 377 /* SDMA command status fields macros */
>> 378
>> 379 /* Tx & Rx descriptors status */
>> 380 #define ETH_ERROR_SUMMARY 0x00000001
>> 381
>> 382 /* Tx & Rx descriptors command */
>> 383 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
>> 384
>> 385 /* Tx descriptors status */
>> 386 #define ETH_LC_ERROR 0
>> 387 #define ETH_UR_ERROR 0x00000002
>> 388 #define ETH_RL_ERROR 0x00000004
>> 389 #define ETH_LLC_SNAP_FORMAT 0x00000200
>> 390
>> 391 /* Rx descriptors status */
>> 392 #define ETH_OVERRUN_ERROR 0x00000002
>> 393 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
>> 394 #define ETH_RESOURCE_ERROR 0x00000006
>> 395 #define ETH_VLAN_TAGGED 0x00080000
>> 396 #define ETH_BPDU_FRAME 0x00100000
>> 397 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
>> 398 #define ETH_OTHER_FRAME_TYPE 0x00400000
>> 399 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
>> 400 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
>> 401 #define ETH_FRAME_HEADER_OK 0x02000000
>> 402 #define ETH_RX_LAST_DESC 0x04000000
>> 403 #define ETH_RX_FIRST_DESC 0x08000000
>> 404 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
>> 405 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
>> 406 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
>> 407
>> 408 /* Rx descriptors byte count */
>> 409 #define ETH_FRAME_FRAGMENTED 0x00000004
>> 410
>> 411 /* Tx descriptors command */
>> 412 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
>> 413 #define ETH_FRAME_SET_TO_VLAN 0x00008000
>> 414 #define ETH_UDP_FRAME 0x00010000
>> 415 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
>> 416 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
>> 417 #define ETH_ZERO_PADDING 0x00080000
>> 418 #define ETH_TX_LAST_DESC 0x00100000
>> 419 #define ETH_TX_FIRST_DESC 0x00200000
>> 420 #define ETH_GEN_CRC 0x00400000
>> 421 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
>> 422 #define ETH_AUTO_MODE 0x40000000
>> 423
>> 424 #define ETH_TX_IHL_SHIFT 11
>> 425
>> 426 /* typedefs */
>> 427
>> 428 typedef enum _eth_func_ret_status {
>> 429 ETH_OK, /* Returned as expected. */
>> 430 ETH_ERROR, /* Fundamental error. */
>> 431 ETH_RETRY, /* Could not process request. Try later.*/
>> 432 ETH_END_OF_JOB, /* Ring has nothing to process. */
>> 433 ETH_QUEUE_FULL, /* Ring resource error. */
>> 434 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
>> 435 } ETH_FUNC_RET_STATUS;
>> 436
>> 437 typedef enum _eth_target {
>> 438 ETH_TARGET_DRAM,
>> 439 ETH_TARGET_DEVICE,
>> 440 ETH_TARGET_CBS,
>> 441 ETH_TARGET_PCI0,
>> 442 ETH_TARGET_PCI1
>> 443 } ETH_TARGET;
>> 444
>> 445 /* These are for big-endian machines. Little endian needs different
>> 446 * definitions.
>> 447 */
>> 448 #if defined(__BIG_ENDIAN)
>> 449 struct eth_rx_desc {
>> 450 u16 byte_cnt; /* Descriptor buffer byte count */
>> 451 u16 buf_size; /* Buffer size */
>> 452 u32 cmd_sts; /* Descriptor command status */
>> 453 u32 next_desc_ptr; /* Next descriptor pointer */
>> 454 u32 buf_ptr; /* Descriptor buffer pointer */
>> 455 };
>> 456
>> 457 struct eth_tx_desc {
>> 458 u16 byte_cnt; /* buffer byte count */
>> 459 u16 l4i_chk; /* CPU provided TCP checksum */
>> 460 u32 cmd_sts; /* Command/status field */
>> 461 u32 next_desc_ptr; /* Pointer to next descriptor */
>> 462 u32 buf_ptr; /* pointer to buffer for this descriptor*/
>> 463 };
>> 464 #elif defined(__LITTLE_ENDIAN)
>> 465 struct eth_rx_desc {
>> 466 u32 cmd_sts; /* Descriptor command status */
>> 467 u16 buf_size; /* Buffer size */
>> 468 u16 byte_cnt; /* Descriptor buffer byte count */
>> 469 u32 buf_ptr; /* Descriptor buffer pointer */
>> 470 u32 next_desc_ptr; /* Next descriptor pointer */
>> 471 };
>> 472
>> 473 struct eth_tx_desc {
>> 474 u32 cmd_sts; /* Command/status field */
>> 475 u16 l4i_chk; /* CPU provided TCP checksum */
>> 476 u16 byte_cnt; /* buffer byte count */
>> 477 u32 buf_ptr; /* pointer to buffer for this descriptor*/
>> 478 u32 next_desc_ptr; /* Pointer to next descriptor */
>> 479 };
>> 480 #else
>> 481 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
76 #endif 482 #endif
77 483
>> 484 /* Unified struct for Rx and Tx operations. The user is not required to */
>> 485 /* be familier with neither Tx nor Rx descriptors. */
>> 486 struct pkt_info {
>> 487 unsigned short byte_cnt; /* Descriptor buffer byte count */
>> 488 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
>> 489 unsigned int cmd_sts; /* Descriptor command status */
>> 490 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
>> 491 struct sk_buff *return_info; /* User resource return information */
>> 492 };
>> 493
>> 494 /* Ethernet port specific information */
>> 495 struct mv643xx_mib_counters {
>> 496 u64 good_octets_received;
>> 497 u32 bad_octets_received;
>> 498 u32 internal_mac_transmit_err;
>> 499 u32 good_frames_received;
>> 500 u32 bad_frames_received;
>> 501 u32 broadcast_frames_received;
>> 502 u32 multicast_frames_received;
>> 503 u32 frames_64_octets;
>> 504 u32 frames_65_to_127_octets;
>> 505 u32 frames_128_to_255_octets;
>> 506 u32 frames_256_to_511_octets;
>> 507 u32 frames_512_to_1023_octets;
>> 508 u32 frames_1024_to_max_octets;
>> 509 u64 good_octets_sent;
>> 510 u32 good_frames_sent;
>> 511 u32 excessive_collision;
>> 512 u32 multicast_frames_sent;
>> 513 u32 broadcast_frames_sent;
>> 514 u32 unrec_mac_control_received;
>> 515 u32 fc_sent;
>> 516 u32 good_fc_received;
>> 517 u32 bad_fc_received;
>> 518 u32 undersize_received;
>> 519 u32 fragments_received;
>> 520 u32 oversize_received;
>> 521 u32 jabber_received;
>> 522 u32 mac_receive_error;
>> 523 u32 bad_crc_event;
>> 524 u32 collision;
>> 525 u32 late_collision;
>> 526 };
>> 527
>> 528 struct mv643xx_private {
>> 529 int port_num; /* User Ethernet port number */
>> 530
>> 531 u32 rx_sram_addr; /* Base address of rx sram area */
>> 532 u32 rx_sram_size; /* Size of rx sram area */
>> 533 u32 tx_sram_addr; /* Base address of tx sram area */
>> 534 u32 tx_sram_size; /* Size of tx sram area */
>> 535
>> 536 int rx_resource_err; /* Rx ring resource error flag */
>> 537
>> 538 /* Tx/Rx rings managment indexes fields. For driver use */
>> 539
>> 540 /* Next available and first returning Rx resource */
>> 541 int rx_curr_desc_q, rx_used_desc_q;
>> 542
>> 543 /* Next available and first returning Tx resource */
>> 544 int tx_curr_desc_q, tx_used_desc_q;
>> 545
>> 546 #ifdef MV643XX_TX_FAST_REFILL
>> 547 u32 tx_clean_threshold;
>> 548 #endif
>> 549
>> 550 struct eth_rx_desc *p_rx_desc_area;
>> 551 dma_addr_t rx_desc_dma;
>> 552 int rx_desc_area_size;
>> 553 struct sk_buff **rx_skb;
>> 554
>> 555 struct eth_tx_desc *p_tx_desc_area;
>> 556 dma_addr_t tx_desc_dma;
>> 557 int tx_desc_area_size;
>> 558 struct sk_buff **tx_skb;
>> 559
>> 560 struct work_struct tx_timeout_task;
>> 561
>> 562 struct net_device *dev;
>> 563 struct napi_struct napi;
>> 564 struct net_device_stats stats;
>> 565 struct mv643xx_mib_counters mib_counters;
>> 566 spinlock_t lock;
>> 567 /* Size of Tx Ring per queue */
>> 568 int tx_ring_size;
>> 569 /* Number of tx descriptors in use */
>> 570 int tx_desc_count;
>> 571 /* Size of Rx Ring per queue */
>> 572 int rx_ring_size;
>> 573 /* Number of rx descriptors in use */
>> 574 int rx_desc_count;
>> 575
>> 576 /*
>> 577 * Used in case RX Ring is empty, which can be caused when
>> 578 * system does not have resources (skb's)
>> 579 */
>> 580 struct timer_list timeout;
>> 581
>> 582 u32 rx_int_coal;
>> 583 u32 tx_int_coal;
>> 584 struct mii_if_info mii;
>> 585 };
>> 586
78 /* Static function declarations */ 587 /* Static function declarations */
79 static int mv64340_eth_real_open(struct net_de !! 588 static void eth_port_init(struct mv643xx_private *mp);
80 static int mv64340_eth_real_stop(struct net_de !! 589 static void eth_port_reset(unsigned int eth_port_num);
81 static int mv64340_eth_change_mtu(struct net_d !! 590 static void eth_port_start(struct net_device *dev);
82 static struct net_device_stats *mv64340_eth_ge !! 591
>> 592 static void ethernet_phy_reset(unsigned int eth_port_num);
>> 593
>> 594 static void eth_port_write_smi_reg(unsigned int eth_port_num,
>> 595 unsigned int phy_reg, unsigned int value);
>> 596
>> 597 static void eth_port_read_smi_reg(unsigned int eth_port_num,
>> 598 unsigned int phy_reg, unsigned int *value);
>> 599
>> 600 static void eth_clear_mib_counters(unsigned int eth_port_num);
>> 601
>> 602 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
>> 603 struct pkt_info *p_pkt_info);
>> 604 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
>> 605 struct pkt_info *p_pkt_info);
>> 606
>> 607 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
>> 608 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
>> 609 static void eth_port_set_multicast_list(struct net_device *);
>> 610 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
>> 611 unsigned int queues);
>> 612 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
>> 613 unsigned int queues);
>> 614 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
>> 615 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
>> 616 static int mv643xx_eth_open(struct net_device *);
>> 617 static int mv643xx_eth_stop(struct net_device *);
>> 618 static int mv643xx_eth_change_mtu(struct net_device *, int);
83 static void eth_port_init_mac_tables(unsigned 619 static void eth_port_init_mac_tables(unsigned int eth_port_num);
84 #ifdef MV64340_NAPI !! 620 #ifdef MV643XX_NAPI
85 static int mv64340_poll(struct net_device *dev !! 621 static int mv643xx_poll(struct napi_struct *napi, int budget);
86 #endif 622 #endif
>> 623 static int ethernet_phy_get(unsigned int eth_port_num);
>> 624 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
>> 625 static int ethernet_phy_detect(unsigned int eth_port_num);
>> 626 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
>> 627 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
>> 628 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
>> 629 static const struct ethtool_ops mv643xx_ethtool_ops;
87 630
88 unsigned char prom_mac_addr_base[6]; !! 631 static char mv643xx_driver_name[] = "mv643xx_eth";
89 unsigned long mv64340_sram_base; !! 632 static char mv643xx_driver_version[] = "1.0";
>> 633
>> 634 static void __iomem *mv643xx_eth_base;
>> 635
>> 636 /* used to protect SMI_REG, which is shared across ports */
>> 637 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
>> 638
>> 639 static inline u32 mv_read(int offset)
>> 640 {
>> 641 return readl(mv643xx_eth_base + offset);
>> 642 }
>> 643
>> 644 static inline void mv_write(int offset, u32 data)
>> 645 {
>> 646 writel(data, mv643xx_eth_base + offset);
>> 647 }
90 648
91 /* 649 /*
92 * Changes MTU (maximum transfer unit) of the 650 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
93 * 651 *
94 * Input : pointer to ethernet interface netwo !! 652 * Input : pointer to ethernet interface network device structure
95 * new mtu size !! 653 * new mtu size
96 * Output : 0 upon success, -EINVAL upon failu !! 654 * Output : 0 upon success, -EINVAL upon failure
97 */ 655 */
98 static int mv64340_eth_change_mtu(struct net_d !! 656 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
99 { 657 {
100 struct mv64340_private *mp = netdev_pr !! 658 if ((new_mtu > 9500) || (new_mtu < 64))
101 unsigned long flags; <<
102 <<
103 spin_lock_irqsave(&mp->lock, flags); <<
104 <<
105 if ((new_mtu > 9500) || (new_mtu < 64) <<
106 spin_unlock_irqrestore(&mp->lo <<
107 return -EINVAL; 659 return -EINVAL;
108 } <<
109 660
110 dev->mtu = new_mtu; 661 dev->mtu = new_mtu;
111 /* !! 662 /*
112 * Stop then re-open the interface. Th 663 * Stop then re-open the interface. This will allocate RX skb's with
113 * the new MTU. 664 * the new MTU.
114 * There is a possible danger that the 665 * There is a possible danger that the open will not successed, due
115 * to memory is full, which might fail 666 * to memory is full, which might fail the open function.
116 */ 667 */
117 if (netif_running(dev)) { 668 if (netif_running(dev)) {
118 if (mv64340_eth_real_stop(dev) !! 669 mv643xx_eth_stop(dev);
119 printk(KERN_ERR !! 670 if (mv643xx_eth_open(dev))
120 "%s: Fatal erro <<
121 dev->name); <<
122 if (mv64340_eth_real_open(dev) <<
123 printk(KERN_ERR 671 printk(KERN_ERR
124 "%s: Fatal erro !! 672 "%s: Fatal error on opening device\n",
125 dev->name); !! 673 dev->name);
126 } 674 }
127 675
128 spin_unlock_irqrestore(&mp->lock, flag <<
129 return 0; 676 return 0;
130 } 677 }
131 678
132 /* 679 /*
133 * mv64340_eth_rx_task !! 680 * mv643xx_eth_rx_refill_descs
134 * !! 681 *
135 * Fills / refills RX queue on a certain gigab 682 * Fills / refills RX queue on a certain gigabit ethernet port
136 * 683 *
137 * Input : pointer to ethernet interface netwo !! 684 * Input : pointer to ethernet interface network device structure
138 * Output : N/A !! 685 * Output : N/A
139 */ 686 */
140 static void mv64340_eth_rx_task(void *data) !! 687 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
141 { 688 {
142 struct net_device *dev = (struct net_d !! 689 struct mv643xx_private *mp = netdev_priv(dev);
143 struct mv64340_private *mp = netdev_pr <<
144 struct pkt_info pkt_info; 690 struct pkt_info pkt_info;
145 struct sk_buff *skb; 691 struct sk_buff *skb;
>> 692 int unaligned;
146 693
147 if (test_and_set_bit(0, &mp->rx_task_b !! 694 while (mp->rx_desc_count < mp->rx_ring_size) {
148 panic("%s: Error in test_set_b !! 695 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
149 <<
150 while (mp->rx_ring_skbs < (mp->rx_ring <<
151 /* The +8 for buffer allignmen <<
152 <<
153 skb = dev_alloc_skb(BUFFER_MTU <<
154 if (!skb) 696 if (!skb)
155 /* Better luck next ti <<
156 break; 697 break;
157 mp->rx_ring_skbs++; !! 698 mp->rx_desc_count++;
>> 699 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
>> 700 if (unaligned)
>> 701 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
158 pkt_info.cmd_sts = ETH_RX_ENAB 702 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
159 pkt_info.byte_cnt = dev->mtu + !! 703 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
160 /* Allign buffer to 8 bytes */ !! 704 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
161 if (pkt_info.byte_cnt & ~0x7) !! 705 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
162 pkt_info.byte_cnt &= ~ <<
163 pkt_info.byte_cnt += 8 <<
164 } <<
165 pkt_info.buf_ptr = <<
166 pci_map_single(0, skb->dat <<
167 dev->mtu + <<
168 PCI_DMA_FRO <<
169 pkt_info.return_info = skb; 706 pkt_info.return_info = skb;
170 if (eth_rx_return_buff(mp, &pk 707 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
171 printk(KERN_ERR 708 printk(KERN_ERR
172 "%s: Error allo !! 709 "%s: Error allocating RX Ring\n", dev->name);
173 break; 710 break;
174 } 711 }
175 skb_reserve(skb, 2); !! 712 skb_reserve(skb, ETH_HW_IP_ALIGN);
176 } 713 }
177 clear_bit(0, &mp->rx_task_busy); <<
178 /* 714 /*
179 * If RX ring is empty of SKB, set a t 715 * If RX ring is empty of SKB, set a timer to try allocating
180 * again in a later time . !! 716 * again at a later time.
181 */ 717 */
182 if ((mp->rx_ring_skbs == 0) && (mp->rx !! 718 if (mp->rx_desc_count == 0) {
183 printk(KERN_INFO "%s: Rx ring 719 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
184 /* After 100mSec */ !! 720 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
185 mp->timeout.expires = jiffies <<
186 add_timer(&mp->timeout); 721 add_timer(&mp->timeout);
187 mp->rx_timer_flag = 1; <<
188 } <<
189 #if MV64340_RX_QUEUE_FILL_ON_TASK <<
190 else { <<
191 /* Return interrupts */ <<
192 MV_WRITE(MV64340_ETH_INTERRUPT <<
193 INT_CAUSE_UNMASK_ALL) <<
194 } 722 }
195 #endif <<
196 } 723 }
197 724
198 /* 725 /*
199 * mv64340_eth_rx_task_timer_wrapper !! 726 * mv643xx_eth_rx_refill_descs_timer_wrapper
200 * !! 727 *
201 * Timer routine to wake up RX queue filling t 728 * Timer routine to wake up RX queue filling task. This function is
202 * used only in case the RX queue is empty, an 729 * used only in case the RX queue is empty, and all alloc_skb has
203 * failed (due to out of memory event). 730 * failed (due to out of memory event).
204 * 731 *
205 * Input : pointer to ethernet interface netwo !! 732 * Input : pointer to ethernet interface network device structure
206 * Output : N/A !! 733 * Output : N/A
207 */ 734 */
208 static void mv64340_eth_rx_task_timer_wrapper( !! 735 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
209 { 736 {
210 struct net_device *dev = (struct net_d !! 737 mv643xx_eth_rx_refill_descs((struct net_device *)data);
211 struct mv64340_private *mp = netdev_pr <<
212 <<
213 mp->rx_timer_flag = 0; <<
214 mv64340_eth_rx_task((void *) data); <<
215 } 738 }
216 739
217 <<
218 /* 740 /*
219 * mv64340_eth_update_mac_address !! 741 * mv643xx_eth_update_mac_address
220 * !! 742 *
221 * Update the MAC address of the port in the a 743 * Update the MAC address of the port in the address table
222 * 744 *
223 * Input : pointer to ethernet interface netwo !! 745 * Input : pointer to ethernet interface network device structure
224 * Output : N/A !! 746 * Output : N/A
225 */ 747 */
226 static void mv64340_eth_update_mac_address(str !! 748 static void mv643xx_eth_update_mac_address(struct net_device *dev)
227 { 749 {
228 struct mv64340_private *mp = netdev_pr !! 750 struct mv643xx_private *mp = netdev_priv(dev);
229 unsigned int port_num = mp->port_num; 751 unsigned int port_num = mp->port_num;
230 752
231 eth_port_init_mac_tables(port_num); 753 eth_port_init_mac_tables(port_num);
232 memcpy(mp->port_mac_addr, dev->dev_add !! 754 eth_port_uc_addr_set(port_num, dev->dev_addr);
233 eth_port_uc_addr_set(port_num, mp->por <<
234 } 755 }
235 756
236 /* 757 /*
237 * mv64340_eth_set_rx_mode !! 758 * mv643xx_eth_set_rx_mode
238 * !! 759 *
239 * Change from promiscuos to regular rx mode 760 * Change from promiscuos to regular rx mode
240 * 761 *
241 * Input : pointer to ethernet interface netwo !! 762 * Input : pointer to ethernet interface network device structure
242 * Output : N/A !! 763 * Output : N/A
243 */ 764 */
244 static void mv64340_eth_set_rx_mode(struct net !! 765 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
245 { 766 {
246 struct mv64340_private *mp = netdev_pr !! 767 struct mv643xx_private *mp = netdev_priv(dev);
>> 768 u32 config_reg;
247 769
248 if (dev->flags & IFF_PROMISC) { !! 770 config_reg = mv_read(PORT_CONFIG_REG(mp->port_num));
249 ethernet_set_config_reg !! 771 if (dev->flags & IFF_PROMISC)
250 (mp->port_num, !! 772 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
251 ethernet_get_config_reg(m !! 773 else
252 ETH_UNICAST_PROMISCUOUS_M !! 774 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
253 } else { !! 775 mv_write(PORT_CONFIG_REG(mp->port_num), config_reg);
254 ethernet_set_config_reg <<
255 (mp->port_num, <<
256 ethernet_get_config_reg(m <<
257 ~(unsigned int) ETH_UNICA <<
258 } <<
259 } <<
260 776
>> 777 eth_port_set_multicast_list(dev);
>> 778 }
261 779
262 /* 780 /*
263 * mv64340_eth_set_mac_address !! 781 * mv643xx_eth_set_mac_address
264 * !! 782 *
265 * Change the interface's mac address. 783 * Change the interface's mac address.
266 * No special hardware thing should be done be 784 * No special hardware thing should be done because interface is always
267 * put in promiscuous mode. 785 * put in promiscuous mode.
268 * 786 *
269 * Input : pointer to ethernet interface netwo !! 787 * Input : pointer to ethernet interface network device structure and
270 * a pointer to the designated entry t !! 788 * a pointer to the designated entry to be added to the cache.
271 * Output : zero upon success, negative upon f !! 789 * Output : zero upon success, negative upon failure
272 */ 790 */
273 static int mv64340_eth_set_mac_address(struct !! 791 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
274 { 792 {
275 int i; 793 int i;
276 794
277 for (i = 0; i < 6; i++) 795 for (i = 0; i < 6; i++)
278 /* +2 is for the offset of the 796 /* +2 is for the offset of the HW addr type */
279 dev->dev_addr[i] = ((unsigned !! 797 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
280 mv64340_eth_update_mac_address(dev); !! 798 mv643xx_eth_update_mac_address(dev);
281 return 0; 799 return 0;
282 } 800 }
283 801
284 /* 802 /*
285 * mv64340_eth_tx_timeout !! 803 * mv643xx_eth_tx_timeout
286 * !! 804 *
287 * Called upon a timeout on transmitting a pac 805 * Called upon a timeout on transmitting a packet
288 * 806 *
289 * Input : pointer to ethernet interface netwo !! 807 * Input : pointer to ethernet interface network device structure.
290 * Output : N/A !! 808 * Output : N/A
291 */ 809 */
292 static void mv64340_eth_tx_timeout(struct net_ !! 810 static void mv643xx_eth_tx_timeout(struct net_device *dev)
293 { 811 {
294 struct mv64340_private *mp = netdev_pr !! 812 struct mv643xx_private *mp = netdev_priv(dev);
295 813
296 printk(KERN_INFO "%s: TX timeout ", d 814 printk(KERN_INFO "%s: TX timeout ", dev->name);
297 815
298 /* Do the reset outside of interrupt c 816 /* Do the reset outside of interrupt context */
299 schedule_work(&mp->tx_timeout_task); 817 schedule_work(&mp->tx_timeout_task);
300 } 818 }
301 819
302 /* 820 /*
303 * mv64340_eth_tx_timeout_task !! 821 * mv643xx_eth_tx_timeout_task
304 * 822 *
305 * Actual routine to reset the adapter when a 823 * Actual routine to reset the adapter when a timeout on Tx has occurred
306 */ 824 */
307 static void mv64340_eth_tx_timeout_task(struct !! 825 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
308 { 826 {
309 struct mv64340_private *mp = netdev_pr !! 827 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
>> 828 tx_timeout_task);
>> 829 struct net_device *dev = mp->mii.dev; /* yuck */
>> 830
>> 831 if (!netif_running(dev))
>> 832 return;
>> 833
>> 834 netif_stop_queue(dev);
>> 835
>> 836 eth_port_reset(mp->port_num);
>> 837 eth_port_start(dev);
310 838
311 netif_device_detach(dev); !! 839 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
312 eth_port_reset(mp->port_num); !! 840 netif_wake_queue(dev);
313 eth_port_start(mp); <<
314 netif_device_attach(dev); <<
315 } 841 }
316 842
317 /* !! 843 /**
318 * mv64340_eth_free_tx_queue !! 844 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
319 * 845 *
320 * Input : dev - a pointer to the required int !! 846 * If force is non-zero, frees uncompleted descriptors as well
321 * <<
322 * Output : 0 if was able to release skb , non <<
323 */ 847 */
324 static int mv64340_eth_free_tx_queue(struct ne !! 848 int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
325 unsigned int eth <<
326 { 849 {
327 struct mv64340_private *mp = netdev_pr !! 850 struct mv643xx_private *mp = netdev_priv(dev);
328 struct net_device_stats *stats = &mp-> !! 851 struct eth_tx_desc *desc;
329 struct pkt_info pkt_info; !! 852 u32 cmd_sts;
330 int released = 1; !! 853 struct sk_buff *skb;
>> 854 unsigned long flags;
>> 855 int tx_index;
>> 856 dma_addr_t addr;
>> 857 int count;
>> 858 int released = 0;
>> 859
>> 860 while (mp->tx_desc_count > 0) {
>> 861 spin_lock_irqsave(&mp->lock, flags);
331 862
332 if (!(eth_int_cause_ext & (BIT0 | BIT8 !! 863 /* tx_desc_count might have changed before acquiring the lock */
333 return released; !! 864 if (mp->tx_desc_count <= 0) {
>> 865 spin_unlock_irqrestore(&mp->lock, flags);
>> 866 return released;
>> 867 }
>> 868
>> 869 tx_index = mp->tx_used_desc_q;
>> 870 desc = &mp->p_tx_desc_area[tx_index];
>> 871 cmd_sts = desc->cmd_sts;
>> 872
>> 873 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
>> 874 spin_unlock_irqrestore(&mp->lock, flags);
>> 875 return released;
>> 876 }
>> 877
>> 878 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
>> 879 mp->tx_desc_count--;
334 880
335 spin_lock(&mp->lock); !! 881 addr = desc->buf_ptr;
>> 882 count = desc->byte_cnt;
>> 883 skb = mp->tx_skb[tx_index];
>> 884 if (skb)
>> 885 mp->tx_skb[tx_index] = NULL;
336 886
337 /* Check only queue 0 */ !! 887 if (cmd_sts & ETH_ERROR_SUMMARY) {
338 while (eth_tx_return_desc(mp, &pkt_inf <<
339 if (pkt_info.cmd_sts & BIT0) { <<
340 printk("%s: Error in T 888 printk("%s: Error in TX\n", dev->name);
341 stats->tx_errors++; !! 889 dev->stats.tx_errors++;
342 } 890 }
343 891
344 /* !! 892 spin_unlock_irqrestore(&mp->lock, flags);
345 * If return_info is different <<
346 * The case where return_info <<
347 * when transmitted a scatter/ <<
348 * last skb releases the whole <<
349 */ <<
350 if (pkt_info.return_info) { <<
351 dev_kfree_skb_irq((str <<
352 pkt_ <<
353 released = 0; <<
354 if (skb_shinfo(pkt_inf <<
355 pci_unmap_page <<
356 pkt_in <<
357 <<
358 if (mp->tx_ring_skbs ! <<
359 mp->tx_ring_sk <<
360 } else <<
361 pci_unmap_page(NULL, p <<
362 pkt_in <<
363 <<
364 /* <<
365 * Decrement the number of out <<
366 * the TX queue. <<
367 */ <<
368 if (mp->tx_ring_skbs == 0) <<
369 panic("ERROR - TX outs <<
370 893
371 } !! 894 if (cmd_sts & ETH_TX_FIRST_DESC)
>> 895 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
>> 896 else
>> 897 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
372 898
373 spin_unlock(&mp->lock); !! 899 if (skb)
>> 900 dev_kfree_skb_irq(skb);
>> 901
>> 902 released = 1;
>> 903 }
374 904
375 return released; 905 return released;
376 } 906 }
377 907
>> 908 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
>> 909 {
>> 910 struct mv643xx_private *mp = netdev_priv(dev);
>> 911
>> 912 if (mv643xx_eth_free_tx_descs(dev, 0) &&
>> 913 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
>> 914 netif_wake_queue(dev);
>> 915 }
>> 916
>> 917 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
>> 918 {
>> 919 mv643xx_eth_free_tx_descs(dev, 1);
>> 920 }
>> 921
378 /* 922 /*
379 * mv64340_eth_receive !! 923 * mv643xx_eth_receive
380 * 924 *
381 * This function is forward packets that are r 925 * This function is forward packets that are received from the port's
382 * queues toward kernel core or FastRoute them 926 * queues toward kernel core or FastRoute them to another interface.
383 * 927 *
384 * Input : dev - a pointer to the required int !! 928 * Input : dev - a pointer to the required interface
385 * max - maximum number to receive (0 !! 929 * max - maximum number to receive (0 means unlimted)
386 * 930 *
387 * Output : number of served packets !! 931 * Output : number of served packets
388 */ 932 */
389 #ifdef MV64340_NAPI !! 933 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
390 static int mv64340_eth_receive_queue(struct ne <<
391 <<
392 #else <<
393 static int mv64340_eth_receive_queue(struct ne <<
394 #endif <<
395 { 934 {
396 struct mv64340_private *mp = netdev_pr !! 935 struct mv643xx_private *mp = netdev_priv(dev);
397 struct net_device_stats *stats = &mp-> !! 936 struct net_device_stats *stats = &dev->stats;
398 unsigned int received_packets = 0; 937 unsigned int received_packets = 0;
399 struct sk_buff *skb; 938 struct sk_buff *skb;
400 struct pkt_info pkt_info; 939 struct pkt_info pkt_info;
401 940
402 #ifdef MV64340_NAPI !! 941 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
403 while (eth_port_receive(mp, &pkt_info) !! 942 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
404 #else !! 943 DMA_FROM_DEVICE);
405 while ((--max) && eth_port_receive(mp, !! 944 mp->rx_desc_count--;
406 #endif <<
407 mp->rx_ring_skbs--; <<
408 received_packets++; 945 received_packets++;
409 #ifdef MV64340_NAPI !! 946
410 budget--; !! 947 /*
411 #endif !! 948 * Update statistics.
412 /* Update statistics. Note byt !! 949 * Note byte count includes 4 byte CRC count
>> 950 */
413 stats->rx_packets++; 951 stats->rx_packets++;
414 stats->rx_bytes += pkt_info.by 952 stats->rx_bytes += pkt_info.byte_cnt;
415 skb = (struct sk_buff *) pkt_i !! 953 skb = pkt_info.return_info;
416 /* 954 /*
417 * In case received a packet w 955 * In case received a packet without first / last bits on OR
418 * the error summary bit is on 956 * the error summary bit is on, the packets needs to be dropeed.
419 */ 957 */
420 if (((pkt_info.cmd_sts 958 if (((pkt_info.cmd_sts
421 & (ETH_RX_FIRST_DESC | E !! 959 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
422 (ETH_RX_FIRST_DESC | ETH_ !! 960 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
423 || (pkt_info.cmd_sts & ETH !! 961 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
424 stats->rx_dropped++; 962 stats->rx_dropped++;
425 if ((pkt_info.cmd_sts 963 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
426 !! 964 ETH_RX_LAST_DESC)) !=
427 (ETH_RX_FIRST_DESC !! 965 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
428 if (net_rateli 966 if (net_ratelimit())
429 printk 967 printk(KERN_ERR
430 !! 968 "%s: Received packet spread "
431 !! 969 "on multiple descriptors\n",
432 !! 970 dev->name);
433 } 971 }
434 if (pkt_info.cmd_sts & 972 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
435 stats->rx_erro 973 stats->rx_errors++;
436 974
437 dev_kfree_skb_irq(skb) 975 dev_kfree_skb_irq(skb);
438 } else { 976 } else {
439 /* 977 /*
440 * The -4 is for the C 978 * The -4 is for the CRC in the trailer of the
441 * received packet 979 * received packet
442 */ 980 */
443 skb_put(skb, pkt_info. 981 skb_put(skb, pkt_info.byte_cnt - 4);
444 skb->dev = dev; <<
445 982
446 if (pkt_info.cmd_sts & 983 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
447 skb->ip_summed 984 skb->ip_summed = CHECKSUM_UNNECESSARY;
448 skb->csum = ht !! 985 skb->csum = htons(
449 !! 986 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
450 } 987 }
451 skb->protocol = eth_ty 988 skb->protocol = eth_type_trans(skb, dev);
452 #ifdef MV64340_NAPI !! 989 #ifdef MV643XX_NAPI
453 netif_receive_skb(skb) 990 netif_receive_skb(skb);
454 #else 991 #else
455 netif_rx(skb); 992 netif_rx(skb);
456 #endif 993 #endif
457 } 994 }
>> 995 dev->last_rx = jiffies;
458 } 996 }
>> 997 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
459 998
460 return received_packets; 999 return received_packets;
461 } 1000 }
462 1001
>> 1002 /* Set the mv643xx port configuration register for the speed/duplex mode. */
>> 1003 static void mv643xx_eth_update_pscr(struct net_device *dev,
>> 1004 struct ethtool_cmd *ecmd)
>> 1005 {
>> 1006 struct mv643xx_private *mp = netdev_priv(dev);
>> 1007 int port_num = mp->port_num;
>> 1008 u32 o_pscr, n_pscr;
>> 1009 unsigned int queues;
>> 1010
>> 1011 o_pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
>> 1012 n_pscr = o_pscr;
>> 1013
>> 1014 /* clear speed, duplex and rx buffer size fields */
>> 1015 n_pscr &= ~(SET_MII_SPEED_TO_100 |
>> 1016 SET_GMII_SPEED_TO_1000 |
>> 1017 SET_FULL_DUPLEX_MODE |
>> 1018 MAX_RX_PACKET_MASK);
>> 1019
>> 1020 if (ecmd->duplex == DUPLEX_FULL)
>> 1021 n_pscr |= SET_FULL_DUPLEX_MODE;
>> 1022
>> 1023 if (ecmd->speed == SPEED_1000)
>> 1024 n_pscr |= SET_GMII_SPEED_TO_1000 |
>> 1025 MAX_RX_PACKET_9700BYTE;
>> 1026 else {
>> 1027 if (ecmd->speed == SPEED_100)
>> 1028 n_pscr |= SET_MII_SPEED_TO_100;
>> 1029 n_pscr |= MAX_RX_PACKET_1522BYTE;
>> 1030 }
>> 1031
>> 1032 if (n_pscr != o_pscr) {
>> 1033 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
>> 1034 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
>> 1035 else {
>> 1036 queues = mv643xx_eth_port_disable_tx(port_num);
>> 1037
>> 1038 o_pscr &= ~SERIAL_PORT_ENABLE;
>> 1039 mv_write(PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
>> 1040 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
>> 1041 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
>> 1042 if (queues)
>> 1043 mv643xx_eth_port_enable_tx(port_num, queues);
>> 1044 }
>> 1045 }
>> 1046 }
>> 1047
463 /* 1048 /*
464 * mv64340_eth_int_handler !! 1049 * mv643xx_eth_int_handler
465 * 1050 *
466 * Main interrupt handler for the gigbit ether 1051 * Main interrupt handler for the gigbit ethernet ports
467 * 1052 *
468 * Input : irq - irq number (not used) !! 1053 * Input : irq - irq number (not used)
469 * dev_id - a pointer to the required !! 1054 * dev_id - a pointer to the required interface's data structure
470 * regs - not used !! 1055 * regs - not used
471 * Output : N/A !! 1056 * Output : N/A
472 */ 1057 */
473 1058
474 static irqreturn_t mv64340_eth_int_handler(int !! 1059 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
475 struct pt_regs *regs) <<
476 { 1060 {
477 struct net_device *dev = (struct net_d !! 1061 struct net_device *dev = (struct net_device *)dev_id;
478 struct mv64340_private *mp = netdev_pr !! 1062 struct mv643xx_private *mp = netdev_priv(dev);
479 u32 eth_int_cause, eth_int_cause_ext = 1063 u32 eth_int_cause, eth_int_cause_ext = 0;
480 unsigned int port_num = mp->port_num; 1064 unsigned int port_num = mp->port_num;
481 1065
482 /* Read interrupt cause registers */ 1066 /* Read interrupt cause registers */
483 eth_int_cause = MV_READ(MV64340_ETH_IN !! 1067 eth_int_cause = mv_read(INTERRUPT_CAUSE_REG(port_num)) &
484 INT_CAUSE_UNMASK_ALL; !! 1068 ETH_INT_UNMASK_ALL;
485 !! 1069 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
486 if (eth_int_cause & BIT1) !! 1070 eth_int_cause_ext = mv_read(
487 eth_int_cause_ext = !! 1071 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
488 MV_READ(MV64340_ETH_INTERRUPT_ !! 1072 ETH_INT_UNMASK_ALL_EXT;
489 INT_CAUSE_UNMASK_ALL_EXT; !! 1073 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num),
490 !! 1074 ~eth_int_cause_ext);
491 #ifdef MV64340_NAPI <<
492 if (!(eth_int_cause & 0x0007fffd)) { <<
493 /* Dont ack the Rx interrupt */ <<
494 #endif <<
495 /* <<
496 * Clear specific ethernet por <<
497 * acknowleding relevant bits. <<
498 */ <<
499 MV_WRITE(MV64340_ETH_INTERRUPT <<
500 ~eth_int_cause); <<
501 if (eth_int_cause_ext != 0x0) <<
502 MV_WRITE(MV64340_ETH_I <<
503 ~eth_int_caus <<
504 <<
505 /* UDP change : We may need th <<
506 if ((eth_int_cause_ext & 0x000 <<
507 (mv64340_eth_free_tx_queue <<
508 (MV64340_TX_QUEUE_SIZE > m <<
509 netif <<
510 #ifdef MV64340_NAPI <<
511 } else { <<
512 if (netif_rx_schedule_prep(dev <<
513 /* Mask all the interr <<
514 MV_WRITE(MV64340_ETH_I <<
515 MV_WRITE(MV64340_ETH_I <<
516 __netif_rx_schedule(de <<
517 } <<
518 #else <<
519 { <<
520 if (eth_int_cause & (BIT2 | BI <<
521 mv64340_eth_receive_qu <<
522 <<
523 /* <<
524 * After forwarded received pa <<
525 * in an interrupts enabled co <<
526 * with skb's. <<
527 */ <<
528 #if MV64340_RX_QUEUE_FILL_ON_TASK <<
529 /* Unmask all interrupts on et <<
530 MV_WRITE(MV64340_ETH_INTERRUPT <<
531 INT_CAUSE_MASK_ALL); <<
532 queue_task(&mp->rx_task, &tq_i <<
533 mark_bh(IMMEDIATE_BH); <<
534 #else <<
535 mp->rx_task.func(dev); <<
536 #endif <<
537 #endif <<
538 } 1075 }
>> 1076
539 /* PHY status changed */ 1077 /* PHY status changed */
540 if (eth_int_cause_ext & (BIT16 | BIT20 !! 1078 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
541 unsigned int phy_reg_data; !! 1079 struct ethtool_cmd cmd;
542 1080
543 /* Check Link status on ethern !! 1081 if (mii_link_ok(&mp->mii)) {
544 eth_port_read_smi_reg(port_num !! 1082 mii_ethtool_gset(&mp->mii, &cmd);
545 if (!(phy_reg_data & 0x20)) { !! 1083 mv643xx_eth_update_pscr(dev, &cmd);
>> 1084 mv643xx_eth_port_enable_tx(port_num,
>> 1085 ETH_TX_QUEUES_ENABLED);
>> 1086 if (!netif_carrier_ok(dev)) {
>> 1087 netif_carrier_on(dev);
>> 1088 if (mp->tx_ring_size - mp->tx_desc_count >=
>> 1089 MAX_DESCS_PER_SKB)
>> 1090 netif_wake_queue(dev);
>> 1091 }
>> 1092 } else if (netif_carrier_ok(dev)) {
546 netif_stop_queue(dev); 1093 netif_stop_queue(dev);
547 } else { !! 1094 netif_carrier_off(dev);
548 netif_wake_queue(dev); <<
549 <<
550 /* <<
551 * Start all TX queues <<
552 * case of previous pa <<
553 * to link down and th <<
554 * queues. <<
555 * Note that it is pos <<
556 * interrupt after iss <<
557 * are enabled, or has <<
558 */ <<
559 MV_WRITE(MV64340_ETH_T <<
560 } 1095 }
561 } 1096 }
562 1097
>> 1098 #ifdef MV643XX_NAPI
>> 1099 if (eth_int_cause & ETH_INT_CAUSE_RX) {
>> 1100 /* schedule the NAPI poll routine to maintain port */
>> 1101 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
>> 1102
>> 1103 /* wait for previous write to complete */
>> 1104 mv_read(INTERRUPT_MASK_REG(port_num));
>> 1105
>> 1106 netif_rx_schedule(dev, &mp->napi);
>> 1107 }
>> 1108 #else
>> 1109 if (eth_int_cause & ETH_INT_CAUSE_RX)
>> 1110 mv643xx_eth_receive_queue(dev, INT_MAX);
>> 1111 #endif
>> 1112 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
>> 1113 mv643xx_eth_free_completed_tx_descs(dev);
>> 1114
563 /* 1115 /*
564 * If no real interrupt occured, exit. 1116 * If no real interrupt occured, exit.
565 * This can happen when using gigE int 1117 * This can happen when using gigE interrupt coalescing mechanism.
566 */ 1118 */
567 if ((eth_int_cause == 0x0) && (eth_int 1119 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
568 return IRQ_NONE; 1120 return IRQ_NONE;
569 1121
570 return IRQ_HANDLED; 1122 return IRQ_HANDLED;
571 } 1123 }
572 1124
573 #ifdef MV64340_COAL !! 1125 #ifdef MV643XX_COAL
574 1126
575 /* 1127 /*
576 * eth_port_set_rx_coal - Sets coalescing inte 1128 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
577 * 1129 *
578 * DESCRIPTION: 1130 * DESCRIPTION:
579 * This routine sets the RX coalescing in 1131 * This routine sets the RX coalescing interrupt mechanism parameter.
580 * This parameter is a timeout counter, t 1132 * This parameter is a timeout counter, that counts in 64 t_clk
581 * chunks ; that when timeout event occur 1133 * chunks ; that when timeout event occurs a maskable interrupt
582 * occurs. 1134 * occurs.
583 * The parameter is calculated using the 1135 * The parameter is calculated using the tClk of the MV-643xx chip
584 * , and the required delay of the interr 1136 * , and the required delay of the interrupt in usec.
585 * 1137 *
586 * INPUT: 1138 * INPUT:
587 * unsigned int eth_port_num Etherne !! 1139 * unsigned int eth_port_num Ethernet port number
588 * unsigned int t_clk t_clk of the !! 1140 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
589 * unsigned int delay Delay in usec !! 1141 * unsigned int delay Delay in usec
590 * 1142 *
591 * OUTPUT: 1143 * OUTPUT:
592 * Interrupt coalescing mechanism value i 1144 * Interrupt coalescing mechanism value is set in MV-643xx chip.
593 * 1145 *
594 * RETURN: 1146 * RETURN:
595 * The interrupt coalescing value set in 1147 * The interrupt coalescing value set in the gigE port.
596 * 1148 *
597 */ 1149 */
598 static unsigned int eth_port_set_rx_coal(unsig 1150 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
599 unsigned int t_clk, unsigned int delay !! 1151 unsigned int t_clk, unsigned int delay)
600 { 1152 {
601 unsigned int coal = ((t_clk / 1000000) 1153 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
602 1154
603 /* Set RX Coalescing mechanism */ 1155 /* Set RX Coalescing mechanism */
604 MV_WRITE(MV64340_ETH_SDMA_CONFIG_REG(e !! 1156 mv_write(SDMA_CONFIG_REG(eth_port_num),
605 ((coal & 0x3fff) << 8) | !! 1157 ((coal & 0x3fff) << 8) |
606 (MV_READ(MV64340_ETH_SDMA_CON !! 1158 (mv_read(SDMA_CONFIG_REG(eth_port_num))
607 & 0xffc000ff)); !! 1159 & 0xffc000ff));
608 1160
609 return coal; 1161 return coal;
610 } 1162 }
611 #endif 1163 #endif
612 1164
613 /* 1165 /*
614 * eth_port_set_tx_coal - Sets coalescing inte 1166 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
615 * 1167 *
616 * DESCRIPTION: 1168 * DESCRIPTION:
617 * This routine sets the TX coalescing in 1169 * This routine sets the TX coalescing interrupt mechanism parameter.
618 * This parameter is a timeout counter, t 1170 * This parameter is a timeout counter, that counts in 64 t_clk
619 * chunks ; that when timeout event occur 1171 * chunks ; that when timeout event occurs a maskable interrupt
620 * occurs. 1172 * occurs.
621 * The parameter is calculated using the !! 1173 * The parameter is calculated using the t_cLK frequency of the
622 * MV-643xx chip and the required delay i 1174 * MV-643xx chip and the required delay in the interrupt in uSec
623 * 1175 *
624 * INPUT: 1176 * INPUT:
625 * unsigned int eth_port_num Etherne !! 1177 * unsigned int eth_port_num Ethernet port number
626 * unsigned int t_clk t_clk of the !! 1178 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
627 * unsigned int delay Delay in uSec !! 1179 * unsigned int delay Delay in uSeconds
628 * 1180 *
629 * OUTPUT: 1181 * OUTPUT:
630 * Interrupt coalescing mechanism value i 1182 * Interrupt coalescing mechanism value is set in MV-643xx chip.
631 * 1183 *
632 * RETURN: 1184 * RETURN:
633 * The interrupt coalescing value set in 1185 * The interrupt coalescing value set in the gigE port.
634 * 1186 *
635 */ 1187 */
636 static unsigned int eth_port_set_tx_coal(unsig 1188 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
637 unsigned int t_clk, unsigned int delay !! 1189 unsigned int t_clk, unsigned int delay)
638 { 1190 {
639 unsigned int coal; 1191 unsigned int coal;
640 coal = ((t_clk / 1000000) * delay) / 6 1192 coal = ((t_clk / 1000000) * delay) / 64;
641 /* Set TX Coalescing mechanism */ 1193 /* Set TX Coalescing mechanism */
642 MV_WRITE(MV64340_ETH_TX_FIFO_URGENT_TH !! 1194 mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), coal << 4);
643 coal << 4); <<
644 return coal; 1195 return coal;
645 } 1196 }
646 1197
647 /* 1198 /*
648 * mv64340_eth_open <<
649 * <<
650 * This function is called when openning the n <<
651 * should initialize all the hardware, initial <<
652 * descriptors chain and buffers and allocate <<
653 * device. <<
654 * <<
655 * Input : a pointer to the network device str <<
656 * <<
657 * Output : zero of success , nonzero if fails <<
658 */ <<
659 <<
660 static int mv64340_eth_open(struct net_device <<
661 { <<
662 struct mv64340_private *mp = netdev_pr <<
663 unsigned int port_num = mp->port_num; <<
664 int err = err; <<
665 <<
666 spin_lock_irq(&mp->lock); <<
667 <<
668 err = request_irq(dev->irq, mv64340_et <<
669 SA_INTERRUPT | SA_SA <<
670 <<
671 if (err) { <<
672 printk(KERN_ERR "Can not assig <<
673 port_num); <<
674 err = -EAGAIN; <<
675 goto out; <<
676 } <<
677 <<
678 if (mv64340_eth_real_open(dev)) { <<
679 printk("%s: Error opening inte <<
680 err = -EBUSY; <<
681 goto out_free; <<
682 } <<
683 <<
684 spin_unlock_irq(&mp->lock); <<
685 <<
686 return 0; <<
687 <<
688 out_free: <<
689 free_irq(dev->irq, dev); <<
690 <<
691 out: <<
692 spin_unlock_irq(&mp->lock); <<
693 <<
694 return err; <<
695 } <<
696 <<
697 /* <<
698 * ether_init_rx_desc_ring - Curve a Rx chain 1199 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
699 * 1200 *
700 * DESCRIPTION: 1201 * DESCRIPTION:
701 * This function prepares a Rx chained l !! 1202 * This function prepares a Rx chained list of descriptors and packet
702 * buffers in a form of a ring. The rout !! 1203 * buffers in a form of a ring. The routine must be called after port
703 * initialization routine and before por !! 1204 * initialization routine and before port start routine.
704 * The Ethernet SDMA engine uses CPU bus !! 1205 * The Ethernet SDMA engine uses CPU bus addresses to access the various
705 * devices in the system (i.e. DRAM). Th !! 1206 * devices in the system (i.e. DRAM). This function uses the ethernet
706 * struct 'virtual to physical' routine !! 1207 * struct 'virtual to physical' routine (set by the user) to set the ring
707 * with physical addresses. !! 1208 * with physical addresses.
708 * 1209 *
709 * INPUT: 1210 * INPUT:
710 * struct mv64340_private *mp Etherne !! 1211 * struct mv643xx_private *mp Ethernet Port Control srtuct.
711 * int rx_desc_num <<
712 * int rx_buff_size <<
713 * unsigned int rx_desc_base_addr Rx <<
714 * unsigned int rx_buff_base_addr Rx <<
715 * 1212 *
716 * OUTPUT: 1213 * OUTPUT:
717 * The routine updates the Ethernet port !! 1214 * The routine updates the Ethernet port control struct with information
718 * regarding the Rx descriptors and buffe !! 1215 * regarding the Rx descriptors and buffers.
719 * 1216 *
720 * RETURN: 1217 * RETURN:
721 * false if the given descriptors memory !! 1218 * None.
722 * Ethernet SDMA specifications. <<
723 * true otherwise. <<
724 */ 1219 */
725 static int ether_init_rx_desc_ring(struct mv64 !! 1220 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
726 unsigned long rx_buff_base_addr) <<
727 { 1221 {
728 unsigned long buffer_addr = rx_buff_ba <<
729 volatile struct eth_rx_desc *p_rx_desc 1222 volatile struct eth_rx_desc *p_rx_desc;
730 int rx_desc_num = mp->rx_ring_size; 1223 int rx_desc_num = mp->rx_ring_size;
731 unsigned long rx_desc_base_addr = (uns <<
732 int rx_buff_size = 1536; /* Dum <<
733 int i; 1224 int i;
734 1225
735 p_rx_desc = (struct eth_rx_desc *) rx_ !! 1226 /* initialize the next_desc_ptr links in the Rx descriptors ring */
736 !! 1227 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
737 /* Rx desc Must be 4LW aligned (i.e. D <<
738 if (rx_buff_base_addr & 0xf) <<
739 return 0; <<
740 <<
741 /* Rx buffers are limited to 64K bytes <<
742 if ((rx_buff_size < 8) || (rx_buff_siz <<
743 return 0; <<
744 <<
745 /* Rx buffers must be 64-bit aligned. <<
746 if ((rx_buff_base_addr + rx_buff_size) <<
747 return 0; <<
748 <<
749 /* initialize the Rx descriptors ring <<
750 for (i = 0; i < rx_desc_num; i++) { 1228 for (i = 0; i < rx_desc_num; i++) {
751 p_rx_desc[i].buf_size = rx_buf <<
752 p_rx_desc[i].byte_cnt = 0x0000 <<
753 p_rx_desc[i].cmd_sts = <<
754 ETH_BUFFER_OWNED_BY_DM <<
755 p_rx_desc[i].next_desc_ptr = m 1229 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
756 ((i + 1) % rx_desc_num 1230 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
757 p_rx_desc[i].buf_ptr = buffer_ <<
758 <<
759 mp->rx_skb[i] = NULL; <<
760 buffer_addr += rx_buff_size; <<
761 } 1231 }
762 1232
763 /* Save Rx desc pointer to driver stru 1233 /* Save Rx desc pointer to driver struct. */
764 mp->rx_curr_desc_q = 0; 1234 mp->rx_curr_desc_q = 0;
765 mp->rx_used_desc_q = 0; 1235 mp->rx_used_desc_q = 0;
766 1236
767 mp->rx_desc_area_size = rx_desc_num * 1237 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
768 <<
769 mp->port_rx_queue_command |= 1; <<
770 <<
771 return 1; <<
772 } 1238 }
773 1239
774 /* 1240 /*
775 * ether_init_tx_desc_ring - Curve a Tx chain 1241 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
776 * 1242 *
777 * DESCRIPTION: 1243 * DESCRIPTION:
778 * This function prepares a Tx chained l !! 1244 * This function prepares a Tx chained list of descriptors and packet
779 * buffers in a form of a ring. The rout !! 1245 * buffers in a form of a ring. The routine must be called after port
780 * initialization routine and before por !! 1246 * initialization routine and before port start routine.
781 * The Ethernet SDMA engine uses CPU bus !! 1247 * The Ethernet SDMA engine uses CPU bus addresses to access the various
782 * devices in the system (i.e. DRAM). Th !! 1248 * devices in the system (i.e. DRAM). This function uses the ethernet
783 * struct 'virtual to physical' routine !! 1249 * struct 'virtual to physical' routine (set by the user) to set the ring
784 * with physical addresses. !! 1250 * with physical addresses.
785 * 1251 *
786 * INPUT: 1252 * INPUT:
787 * struct mv64340_private *mp Etherne !! 1253 * struct mv643xx_private *mp Ethernet Port Control srtuct.
788 * int tx_desc_num Num <<
789 * int tx_buff_size Siz <<
790 * unsigned int tx_desc_base_addr Tx <<
791 * 1254 *
792 * OUTPUT: 1255 * OUTPUT:
793 * The routine updates the Ethernet port !! 1256 * The routine updates the Ethernet port control struct with information
794 * regarding the Tx descriptors and buffe !! 1257 * regarding the Tx descriptors and buffers.
795 * 1258 *
796 * RETURN: 1259 * RETURN:
797 * false if the given descriptors memory !! 1260 * None.
798 * Ethernet SDMA specifications. <<
799 * true otherwise. <<
800 */ 1261 */
801 static int ether_init_tx_desc_ring(struct mv64 !! 1262 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
802 { 1263 {
803 unsigned long tx_desc_base_addr = (uns <<
804 int tx_desc_num = mp->tx_ring_size; 1264 int tx_desc_num = mp->tx_ring_size;
805 struct eth_tx_desc *p_tx_desc; 1265 struct eth_tx_desc *p_tx_desc;
806 int i; 1266 int i;
807 1267
808 /* Tx desc Must be 4LW aligned (i.e. D !! 1268 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
809 if (tx_desc_base_addr & 0xf) !! 1269 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
810 return 0; <<
811 <<
812 /* save the first desc pointer to link <<
813 p_tx_desc = (struct eth_tx_desc *) tx_ <<
814 <<
815 /* Initialize the Tx descriptors ring <<
816 for (i = 0; i < tx_desc_num; i++) { 1270 for (i = 0; i < tx_desc_num; i++) {
817 p_tx_desc[i].byte_cnt = 0x00 <<
818 p_tx_desc[i].l4i_chk = 0x00 <<
819 p_tx_desc[i].cmd_sts = 0x00 <<
820 p_tx_desc[i].next_desc_ptr = m 1271 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
821 ((i + 1) % tx_desc_num 1272 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
822 p_tx_desc[i].buf_ptr = 0x00 <<
823 mp->tx_skb[i] = NULL <<
824 } 1273 }
825 1274
826 /* Set Tx desc pointer in driver struc <<
827 mp->tx_curr_desc_q = 0; 1275 mp->tx_curr_desc_q = 0;
828 mp->tx_used_desc_q = 0; 1276 mp->tx_used_desc_q = 0;
829 #ifdef MV64340_CHECKSUM_OFFLOAD_TX <<
830 mp->tx_first_desc_q = 0; <<
831 #endif <<
832 /* Init Tx ring base and size paramete <<
833 mp->tx_desc_area_size = tx_desc_num <<
834 1277
835 /* Add the queue to the list of Tx que !! 1278 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
836 mp->port_tx_queue_command |= 1; !! 1279 }
>> 1280
>> 1281 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
>> 1282 {
>> 1283 struct mv643xx_private *mp = netdev_priv(dev);
>> 1284 int err;
>> 1285
>> 1286 spin_lock_irq(&mp->lock);
>> 1287 err = mii_ethtool_sset(&mp->mii, cmd);
>> 1288 spin_unlock_irq(&mp->lock);
837 1289
838 return 1; !! 1290 return err;
839 } 1291 }
840 1292
841 /* Helper function for mv64340_eth_open */ !! 1293 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
842 static int mv64340_eth_real_open(struct net_de <<
843 { 1294 {
844 struct mv64340_private *mp = netdev_pr !! 1295 struct mv643xx_private *mp = netdev_priv(dev);
845 unsigned int port_num = mp->port_num; !! 1296 int err;
846 u32 phy_reg_data; <<
847 unsigned int size; <<
848 1297
849 /* Stop RX Queues */ !! 1298 spin_lock_irq(&mp->lock);
850 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COM !! 1299 err = mii_ethtool_gset(&mp->mii, cmd);
851 0x0000ff00); !! 1300 spin_unlock_irq(&mp->lock);
852 1301
853 /* Clear the ethernet port interrupts !! 1302 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
854 MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_R !! 1303 cmd->supported &= ~SUPPORTED_1000baseT_Half;
855 MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_E !! 1304 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
856 1305
857 /* Unmask RX buffer and TX end interru !! 1306 return err;
858 MV_WRITE(MV64340_ETH_INTERRUPT_MASK_RE !! 1307 }
859 INT_CAUSE_UNMASK_ALL); <<
860 1308
861 /* Unmask phy and link status changes !! 1309 /*
862 MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_ !! 1310 * mv643xx_eth_open
863 INT_CAUSE_UNMASK_ALL_EXT); !! 1311 *
>> 1312 * This function is called when openning the network device. The function
>> 1313 * should initialize all the hardware, initialize cyclic Rx/Tx
>> 1314 * descriptors chain and buffers and allocate an IRQ to the network
>> 1315 * device.
>> 1316 *
>> 1317 * Input : a pointer to the network device structure
>> 1318 *
>> 1319 * Output : zero of success , nonzero if fails.
>> 1320 */
864 1321
865 /* Set the MAC Address */ !! 1322 static int mv643xx_eth_open(struct net_device *dev)
866 memcpy(mp->port_mac_addr, dev->dev_add !! 1323 {
>> 1324 struct mv643xx_private *mp = netdev_priv(dev);
>> 1325 unsigned int port_num = mp->port_num;
>> 1326 unsigned int size;
>> 1327 int err;
867 1328
868 eth_port_init(mp); !! 1329 /* Clear any pending ethernet port interrupts */
>> 1330 mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
>> 1331 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
>> 1332 /* wait for previous write to complete */
>> 1333 mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num));
>> 1334
>> 1335 err = request_irq(dev->irq, mv643xx_eth_int_handler,
>> 1336 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
>> 1337 if (err) {
>> 1338 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
>> 1339 port_num);
>> 1340 return -EAGAIN;
>> 1341 }
869 1342
870 INIT_WORK(&mp->rx_task, (void (*)(void !! 1343 eth_port_init(mp);
871 1344
872 memset(&mp->timeout, 0, sizeof(struct 1345 memset(&mp->timeout, 0, sizeof(struct timer_list));
873 mp->timeout.function = mv64340_eth_rx_ !! 1346 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
874 mp->timeout.data = (unsigned long) dev !! 1347 mp->timeout.data = (unsigned long)dev;
875 1348
876 mp->rx_task_busy = 0; !! 1349 /* Allocate RX and TX skb rings */
877 mp->rx_timer_flag = 0; !! 1350 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
>> 1351 GFP_KERNEL);
>> 1352 if (!mp->rx_skb) {
>> 1353 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
>> 1354 err = -ENOMEM;
>> 1355 goto out_free_irq;
>> 1356 }
>> 1357 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
>> 1358 GFP_KERNEL);
>> 1359 if (!mp->tx_skb) {
>> 1360 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
>> 1361 err = -ENOMEM;
>> 1362 goto out_free_rx_skb;
>> 1363 }
878 1364
879 /* Allocate TX ring */ 1365 /* Allocate TX ring */
880 mp->tx_ring_skbs = 0; !! 1366 mp->tx_desc_count = 0;
881 mp->tx_ring_size = MV64340_TX_QUEUE_SI <<
882 size = mp->tx_ring_size * sizeof(struc 1367 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
883 mp->tx_desc_area_size = size; 1368 mp->tx_desc_area_size = size;
884 1369
885 /* Assumes allocated ring is 16 bytes !! 1370 if (mp->tx_sram_size) {
886 mp->p_tx_desc_area = pci_alloc_consist !! 1371 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
>> 1372 mp->tx_sram_size);
>> 1373 mp->tx_desc_dma = mp->tx_sram_addr;
>> 1374 } else
>> 1375 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
>> 1376 &mp->tx_desc_dma,
>> 1377 GFP_KERNEL);
>> 1378
887 if (!mp->p_tx_desc_area) { 1379 if (!mp->p_tx_desc_area) {
888 printk(KERN_ERR "%s: Cannot al 1380 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
889 dev->name, size); !! 1381 dev->name, size);
890 return -ENOMEM; !! 1382 err = -ENOMEM;
>> 1383 goto out_free_tx_skb;
891 } 1384 }
892 memset((void *) mp->p_tx_desc_area, 0, !! 1385 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
>> 1386 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
893 1387
894 /* Dummy will be replaced upon real tx <<
895 ether_init_tx_desc_ring(mp); 1388 ether_init_tx_desc_ring(mp);
896 1389
897 /* Allocate RX ring */ 1390 /* Allocate RX ring */
898 /* Meantime RX Ring are fixed - but mu !! 1391 mp->rx_desc_count = 0;
899 mp->rx_ring_size = MV64340_RX_QUEUE_SI <<
900 mp->rx_ring_skbs = 0; <<
901 size = mp->rx_ring_size * sizeof(struc 1392 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
902 mp->rx_desc_area_size = size; 1393 mp->rx_desc_area_size = size;
903 1394
904 /* Assumes allocated ring is 16 bytes !! 1395 if (mp->rx_sram_size) {
905 !! 1396 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
906 mp->p_rx_desc_area = pci_alloc_consist !! 1397 mp->rx_sram_size);
>> 1398 mp->rx_desc_dma = mp->rx_sram_addr;
>> 1399 } else
>> 1400 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
>> 1401 &mp->rx_desc_dma,
>> 1402 GFP_KERNEL);
907 1403
908 if (!mp->p_rx_desc_area) { 1404 if (!mp->p_rx_desc_area) {
909 printk(KERN_ERR "%s: Cannot al 1405 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
910 dev->name, size); !! 1406 dev->name, size);
911 printk(KERN_ERR "%s: Freeing p 1407 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
912 dev->name); !! 1408 dev->name);
913 pci_free_consistent(0, mp->tx_ !! 1409 if (mp->rx_sram_size)
914 (void *) m !! 1410 iounmap(mp->p_tx_desc_area);
915 mp->tx_des !! 1411 else
916 return -ENOMEM; !! 1412 dma_free_coherent(NULL, mp->tx_desc_area_size,
>> 1413 mp->p_tx_desc_area, mp->tx_desc_dma);
>> 1414 err = -ENOMEM;
>> 1415 goto out_free_tx_skb;
917 } 1416 }
918 memset(mp->p_rx_desc_area, 0, size); !! 1417 memset((void *)mp->p_rx_desc_area, 0, size);
919 1418
920 if (!(ether_init_rx_desc_ring(mp, 0))) !! 1419 ether_init_rx_desc_ring(mp);
921 panic("%s: Error initializing <<
922 1420
923 mv64340_eth_rx_task(dev); /* Fil !! 1421 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
>> 1422
>> 1423 #ifdef MV643XX_NAPI
>> 1424 napi_enable(&mp->napi);
>> 1425 #endif
924 1426
925 eth_port_start(mp); !! 1427 eth_port_start(dev);
926 1428
927 /* Interrupt Coalescing */ 1429 /* Interrupt Coalescing */
928 1430
929 #ifdef MV64340_COAL !! 1431 #ifdef MV643XX_COAL
930 mp->rx_int_coal = 1432 mp->rx_int_coal =
931 eth_port_set_rx_coal(port_num, !! 1433 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
932 #endif 1434 #endif
933 1435
934 mp->tx_int_coal = 1436 mp->tx_int_coal =
935 eth_port_set_tx_coal (port_num !! 1437 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
936 1438
937 /* Increase the Rx side buffer size */ !! 1439 /* Unmask phy and link status changes interrupts */
938 !! 1440 mv_write(INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
939 MV_WRITE (MV64340_ETH_PORT_SERIAL_CONT <<
940 (MV_READ(MV64340_ETH_P <<
941 & 0xff <<
942 1441
943 /* Check Link status on phy */ !! 1442 /* Unmask RX buffer and TX end interrupt */
944 eth_port_read_smi_reg(port_num, 1, &ph !! 1443 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
945 if (!(phy_reg_data & 0x20)) <<
946 netif_stop_queue(dev); <<
947 else <<
948 netif_start_queue(dev); <<
949 1444
950 return 0; 1445 return 0;
>> 1446
>> 1447 out_free_tx_skb:
>> 1448 kfree(mp->tx_skb);
>> 1449 out_free_rx_skb:
>> 1450 kfree(mp->rx_skb);
>> 1451 out_free_irq:
>> 1452 free_irq(dev->irq, dev);
>> 1453
>> 1454 return err;
951 } 1455 }
952 1456
953 static void mv64340_eth_free_tx_rings(struct n !! 1457 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
954 { 1458 {
955 struct mv64340_private *mp = netdev_pr !! 1459 struct mv643xx_private *mp = netdev_priv(dev);
956 unsigned int port_num = mp->port_num; <<
957 unsigned int curr; <<
958 1460
959 /* Stop Tx Queues */ 1461 /* Stop Tx Queues */
960 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_CO !! 1462 mv643xx_eth_port_disable_tx(mp->port_num);
961 0x0000ff00); <<
962 1463
963 /* Free TX rings */ !! 1464 /* Free outstanding skb's on TX ring */
964 /* Free outstanding skb's on TX rings !! 1465 mv643xx_eth_free_all_tx_descs(dev);
965 for (curr = 0; !! 1466
966 (mp->tx_ring_skbs) && (curr < MV6 !! 1467 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
967 curr++) { !! 1468
968 if (mp->tx_skb[curr]) { !! 1469 /* Free TX ring */
969 dev_kfree_skb(mp->tx_s !! 1470 if (mp->tx_sram_size)
970 mp->tx_ring_skbs--; !! 1471 iounmap(mp->p_tx_desc_area);
971 } !! 1472 else
972 } !! 1473 dma_free_coherent(NULL, mp->tx_desc_area_size,
973 if (mp->tx_ring_skbs != 0) !! 1474 mp->p_tx_desc_area, mp->tx_desc_dma);
974 printk("%s: Error on Tx descri <<
975 " descriptors\n", dev->na <<
976 mp->tx_ring_skbs); <<
977 pci_free_consistent(0, mp->tx_desc_are <<
978 (void *) mp->p_tx_ <<
979 } 1475 }
980 1476
981 static void mv64340_eth_free_rx_rings(struct n !! 1477 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
982 { 1478 {
983 struct mv64340_private *mp = netdev_pr !! 1479 struct mv643xx_private *mp = netdev_priv(dev);
984 unsigned int port_num = mp->port_num; 1480 unsigned int port_num = mp->port_num;
985 int curr; 1481 int curr;
986 1482
987 /* Stop RX Queues */ 1483 /* Stop RX Queues */
988 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COM !! 1484 mv643xx_eth_port_disable_rx(port_num);
989 0x0000ff00); <<
990 1485
991 /* Free RX rings */ <<
992 /* Free preallocated skb's on RX rings 1486 /* Free preallocated skb's on RX rings */
993 for (curr = 0; !! 1487 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
994 mp->rx_ring_skbs && (curr < MV <<
995 curr++) { <<
996 if (mp->rx_skb[curr]) { 1488 if (mp->rx_skb[curr]) {
997 dev_kfree_skb(mp->rx_s 1489 dev_kfree_skb(mp->rx_skb[curr]);
998 mp->rx_ring_skbs--; !! 1490 mp->rx_desc_count--;
999 } 1491 }
1000 } 1492 }
1001 1493
1002 if (mp->rx_ring_skbs != 0) !! 1494 if (mp->rx_desc_count)
1003 printk(KERN_ERR 1495 printk(KERN_ERR
1004 "%s: Error in freeing !! 1496 "%s: Error in freeing Rx Ring. %d skb's still"
1005 " stuck in RX Ring - i !! 1497 " stuck in RX Ring - ignoring them\n", dev->name,
1006 mp->rx_ring_skbs); !! 1498 mp->rx_desc_count);
1007 pci_free_consistent(0, mp->rx_desc_ar !! 1499 /* Free RX ring */
1008 (void *) mp->p_rx !! 1500 if (mp->rx_sram_size)
1009 mp->rx_desc_dma); !! 1501 iounmap(mp->p_rx_desc_area);
>> 1502 else
>> 1503 dma_free_coherent(NULL, mp->rx_desc_area_size,
>> 1504 mp->p_rx_desc_area, mp->rx_desc_dma);
1010 } 1505 }
1011 1506
1012 /* 1507 /*
1013 * mv64340_eth_stop !! 1508 * mv643xx_eth_stop
1014 * 1509 *
1015 * This function is used when closing the net !! 1510 * This function is used when closing the network device.
1016 * It updates the hardware, !! 1511 * It updates the hardware,
1017 * release all memory that holds buffers and 1512 * release all memory that holds buffers and descriptors and release the IRQ.
1018 * Input : a pointer to the device structure !! 1513 * Input : a pointer to the device structure
1019 * Output : zero if success , nonzero if fail !! 1514 * Output : zero if success , nonzero if fails
1020 */ 1515 */
1021 1516
1022 /* Helper function for mv64340_eth_stop */ !! 1517 static int mv643xx_eth_stop(struct net_device *dev)
1023 <<
1024 static int mv64340_eth_real_stop(struct net_d <<
1025 { 1518 {
1026 struct mv64340_private *mp = netdev_p !! 1519 struct mv643xx_private *mp = netdev_priv(dev);
1027 unsigned int port_num = mp->port_num; 1520 unsigned int port_num = mp->port_num;
1028 1521
1029 netif_stop_queue(dev); !! 1522 /* Mask all interrupts on ethernet port */
>> 1523 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
>> 1524 /* wait for previous write to complete */
>> 1525 mv_read(INTERRUPT_MASK_REG(port_num));
1030 1526
1031 mv64340_eth_free_tx_rings(dev); !! 1527 #ifdef MV643XX_NAPI
1032 mv64340_eth_free_rx_rings(dev); !! 1528 napi_disable(&mp->napi);
>> 1529 #endif
>> 1530 netif_carrier_off(dev);
>> 1531 netif_stop_queue(dev);
1033 1532
1034 eth_port_reset(mp->port_num); 1533 eth_port_reset(mp->port_num);
1035 1534
1036 /* Disable ethernet port interrupts * !! 1535 mv643xx_eth_free_tx_rings(dev);
1037 MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_ !! 1536 mv643xx_eth_free_rx_rings(dev);
1038 MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_ <<
1039 1537
1040 /* Mask RX buffer and TX end interrup !! 1538 free_irq(dev->irq, dev);
1041 MV_WRITE(MV64340_ETH_INTERRUPT_MASK_R <<
1042 <<
1043 /* Mask phy and link status changes i <<
1044 MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND <<
1045 1539
1046 return 0; 1540 return 0;
1047 } 1541 }
1048 1542
1049 static int mv64340_eth_stop(struct net_device !! 1543 #ifdef MV643XX_NAPI
1050 { <<
1051 struct mv64340_private *mp = netdev_p <<
1052 <<
1053 spin_lock_irq(&mp->lock); <<
1054 <<
1055 mv64340_eth_real_stop(dev); <<
1056 <<
1057 free_irq(dev->irq, dev); <<
1058 spin_unlock_irq(&mp->lock); <<
1059 <<
1060 return 0; <<
1061 } <<
1062 <<
1063 #ifdef MV64340_NAPI <<
1064 static void mv64340_tx(struct net_device *dev <<
1065 { <<
1066 struct mv64340_private *mp = netdev_p <<
1067 struct pkt_info pkt_info; <<
1068 <<
1069 while (eth_tx_return_desc(mp, &pkt_in <<
1070 if (pkt_info.return_info) { <<
1071 dev_kfree_skb_irq((st <<
1072 <<
1073 if (skb_shinfo(pkt_in <<
1074 pci_unmap_pa <<
1075 <<
1076 <<
1077 <<
1078 if (mp->tx_ring_skbs <<
1079 mp->tx_ring <<
1080 } else <<
1081 pci_unmap_page(NULL, p <<
1082 PCI_DMA <<
1083 } <<
1084 <<
1085 if (netif_queue_stopped(dev) && <<
1086 MV64340_TX_QUEUE_SIZE > mp->tx_ri <<
1087 netif_wake_queue(dev); <<
1088 } <<
1089 <<
1090 /* 1544 /*
1091 * mv64340_poll !! 1545 * mv643xx_poll
1092 * 1546 *
1093 * This function is used in case of NAPI 1547 * This function is used in case of NAPI
1094 */ 1548 */
1095 static int mv64340_poll(struct net_device *de !! 1549 static int mv643xx_poll(struct napi_struct *napi, int budget)
1096 { 1550 {
1097 struct mv64340_private *mp = netdev_p !! 1551 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
1098 int done = 1, orig_budget, work_d !! 1552 struct net_device *dev = mp->dev;
1099 unsigned int port_num = mp->port_num; 1553 unsigned int port_num = mp->port_num;
1100 unsigned long flags; !! 1554 int work_done;
1101 1555
1102 #ifdef MV64340_TX_FAST_REFILL !! 1556 #ifdef MV643XX_TX_FAST_REFILL
1103 if (++mp->tx_clean_threshold > 5) { 1557 if (++mp->tx_clean_threshold > 5) {
1104 spin_lock_irqsave(&mp->lock, !! 1558 mv643xx_eth_free_completed_tx_descs(dev);
1105 mv64340_tx(dev); <<
1106 mp->tx_clean_threshold = 0; 1559 mp->tx_clean_threshold = 0;
1107 spin_unlock_irqrestore(&mp->l <<
1108 } 1560 }
1109 #endif 1561 #endif
1110 1562
1111 if ((u32)(MV_READ(MV64340_ETH_RX_CURR !! 1563 work_done = 0;
1112 orig_budget = *budget; !! 1564 if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1113 if (orig_budget > dev->quota) !! 1565 != (u32) mp->rx_used_desc_q)
1114 orig_budget = dev->qu !! 1566 work_done = mv643xx_eth_receive_queue(dev, budget);
1115 work_done = mv64340_eth_recei <<
1116 mp->rx_task.func(dev); <<
1117 *budget -= work_done; <<
1118 dev->quota -= work_done; <<
1119 if (work_done >= orig_budget) <<
1120 done = 0; <<
1121 } <<
1122 1567
1123 if (done) { !! 1568 if (work_done < budget) {
1124 spin_lock_irqsave(&mp->lock, !! 1569 netif_rx_complete(dev, napi);
1125 __netif_rx_complete(dev); !! 1570 mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
1126 MV_WRITE(MV64340_ETH_INTERRUP !! 1571 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1127 MV_WRITE(MV64340_ETH_INTERRUP !! 1572 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1128 MV_WRITE(MV64340_ETH_INTERRUP <<
1129 <<
1130 MV_WRITE(MV64340_ETH_INTERRUP <<
1131 <<
1132 spin_unlock_irqrestore(&mp->l <<
1133 } 1573 }
1134 1574
1135 return done ? 0 : 1; !! 1575 return work_done;
1136 } 1576 }
1137 #endif 1577 #endif
1138 1578
1139 /* !! 1579 /**
1140 * mv64340_eth_start_xmit !! 1580 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1141 * <<
1142 * This function is queues a packet in the Tx <<
1143 * required port. <<
1144 * <<
1145 * Input : skb - a pointer to socket buffer <<
1146 * dev - a pointer to the required po <<
1147 * 1581 *
1148 * Output : zero upon success !! 1582 * Hardware can't handle unaligned fragments smaller than 9 bytes.
>> 1583 * This helper function detects that case.
1149 */ 1584 */
1150 static int mv64340_eth_start_xmit(struct sk_b !! 1585
>> 1586 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1151 { 1587 {
1152 struct mv64340_private *mp = netdev_p !! 1588 unsigned int frag;
1153 struct net_device_stats *stats = &mp- !! 1589 skb_frag_t *fragp;
1154 ETH_FUNC_RET_STATUS status; <<
1155 unsigned long flags; <<
1156 struct pkt_info pkt_info; <<
1157 1590
1158 if (netif_queue_stopped(dev)) { !! 1591 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1159 printk(KERN_ERR !! 1592 fragp = &skb_shinfo(skb)->frags[frag];
1160 "%s: Tried sending pac !! 1593 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1161 dev->name); !! 1594 return 1;
1162 return 1; <<
1163 } 1595 }
>> 1596 return 0;
>> 1597 }
1164 1598
1165 /* This is a hard error, log it. */ !! 1599 /**
1166 if ((MV64340_TX_QUEUE_SIZE - mp->tx_r !! 1600 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1167 (skb_shinfo(skb)->nr_frags + 1)) !! 1601 */
1168 netif_stop_queue(dev); !! 1602 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1169 printk(KERN_ERR !! 1603 {
1170 "%s: Bug in mv64340_et !! 1604 int tx_desc_curr;
1171 " queue full !\n", dev <<
1172 return 1; <<
1173 } <<
1174 1605
1175 /* Paranoid check - this shouldn't ha !! 1606 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1176 if (skb == NULL) { !! 1607
1177 stats->tx_dropped++; !! 1608 tx_desc_curr = mp->tx_curr_desc_q;
1178 return 1; !! 1609 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
>> 1610
>> 1611 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
>> 1612
>> 1613 return tx_desc_curr;
>> 1614 }
>> 1615
>> 1616 /**
>> 1617 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
>> 1618 *
>> 1619 * Ensure the data for each fragment to be transmitted is mapped properly,
>> 1620 * then fill in descriptors in the tx hw queue.
>> 1621 */
>> 1622 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
>> 1623 struct sk_buff *skb)
>> 1624 {
>> 1625 int frag;
>> 1626 int tx_index;
>> 1627 struct eth_tx_desc *desc;
>> 1628
>> 1629 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
>> 1630 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
>> 1631
>> 1632 tx_index = eth_alloc_tx_desc_index(mp);
>> 1633 desc = &mp->p_tx_desc_area[tx_index];
>> 1634
>> 1635 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
>> 1636 /* Last Frag enables interrupt and frees the skb */
>> 1637 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
>> 1638 desc->cmd_sts |= ETH_ZERO_PADDING |
>> 1639 ETH_TX_LAST_DESC |
>> 1640 ETH_TX_ENABLE_INTERRUPT;
>> 1641 mp->tx_skb[tx_index] = skb;
>> 1642 } else
>> 1643 mp->tx_skb[tx_index] = NULL;
>> 1644
>> 1645 desc = &mp->p_tx_desc_area[tx_index];
>> 1646 desc->l4i_chk = 0;
>> 1647 desc->byte_cnt = this_frag->size;
>> 1648 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
>> 1649 this_frag->page_offset,
>> 1650 this_frag->size,
>> 1651 DMA_TO_DEVICE);
1179 } 1652 }
>> 1653 }
1180 1654
1181 spin_lock_irqsave(&mp->lock, flags); !! 1655 static inline __be16 sum16_as_be(__sum16 sum)
>> 1656 {
>> 1657 return (__force __be16)sum;
>> 1658 }
1182 1659
1183 /* Update packet info data structure !! 1660 /**
1184 #ifdef MV64340_CHECKSUM_OFFLOAD_TX !! 1661 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1185 if (!skb_shinfo(skb)->nr_frags || (sk !! 1662 *
1186 #endif !! 1663 * Ensure the data for an skb to be transmitted is mapped properly,
1187 pkt_info.cmd_sts = ETH_TX_ENA !! 1664 * then fill in descriptors in the tx hw queue and start the hardware.
1188 ETH_TX_FIR !! 1665 */
1189 !! 1666 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1190 pkt_info.byte_cnt = skb->len; !! 1667 struct sk_buff *skb)
1191 pkt_info.buf_ptr = pci_map_si !! 1668 {
1192 !! 1669 int tx_index;
>> 1670 struct eth_tx_desc *desc;
>> 1671 u32 cmd_sts;
>> 1672 int length;
>> 1673 int nr_frags = skb_shinfo(skb)->nr_frags;
1193 1674
>> 1675 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1194 1676
1195 pkt_info.return_info = skb; !! 1677 tx_index = eth_alloc_tx_desc_index(mp);
1196 status = eth_port_send(mp, &p !! 1678 desc = &mp->p_tx_desc_area[tx_index];
1197 if ((status == ETH_ERROR) || !! 1679
1198 printk(KERN_ERR "%s: !! 1680 if (nr_frags) {
1199 dev->n !! 1681 eth_tx_fill_frag_descs(mp, skb);
1200 mp->tx_ring_skbs++; <<
1201 #ifdef MV64340_CHECKSUM_OFFLOAD_TX <<
1202 } else { <<
1203 unsigned int frag; <<
1204 u32 ipheader; <<
1205 1682
1206 /* first frag which is skb he !! 1683 length = skb_headlen(skb);
1207 pkt_info.byte_cnt = skb_headl !! 1684 mp->tx_skb[tx_index] = NULL;
1208 pkt_info.buf_ptr = pci_map_si !! 1685 } else {
1209 skb_h !! 1686 cmd_sts |= ETH_ZERO_PADDING |
1210 pkt_info.return_info = 0; !! 1687 ETH_TX_LAST_DESC |
1211 ipheader = skb->nh.iph->ihl < !! 1688 ETH_TX_ENABLE_INTERRUPT;
1212 pkt_info.cmd_sts = ETH_TX_FIR !! 1689 length = skb->len;
1213 ETH_G !! 1690 mp->tx_skb[tx_index] = skb;
1214 ETH_G !! 1691 }
1215 iphea !! 1692
1216 /* CPU already calculated pse !! 1693 desc->byte_cnt = length;
1217 pkt_info.l4i_chk = skb->h.th- !! 1694 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1218 status = eth_port_send(mp, &p !! 1695
1219 if (status != ETH_OK) { !! 1696 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1220 if ((status == ETH_ER !! 1697 BUG_ON(skb->protocol != htons(ETH_P_IP));
1221 printk(KERN_E !! 1698
1222 if (status == ETH_QUE !! 1699 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1223 printk("Error !! 1700 ETH_GEN_IP_V_4_CHECKSUM |
1224 if (status == ETH_QUE !! 1701 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
1225 printk("Tx re !! 1702
>> 1703 switch (ip_hdr(skb)->protocol) {
>> 1704 case IPPROTO_UDP:
>> 1705 cmd_sts |= ETH_UDP_FRAME;
>> 1706 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
>> 1707 break;
>> 1708 case IPPROTO_TCP:
>> 1709 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
>> 1710 break;
>> 1711 default:
>> 1712 BUG();
1226 } 1713 }
>> 1714 } else {
>> 1715 /* Errata BTS #50, IHL must be 5 if no HW checksum */
>> 1716 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
>> 1717 desc->l4i_chk = 0;
>> 1718 }
1227 1719
1228 /* Check for the remaining fr !! 1720 /* ensure all other descriptors are written before first cmd_sts */
1229 for (frag = 0; frag < skb_shi !! 1721 wmb();
1230 skb_frag_t *this_frag !! 1722 desc->cmd_sts = cmd_sts;
1231 pkt_info.l4i_chk = 0x <<
1232 pkt_info.cmd_sts = 0x <<
1233 <<
1234 /* Last Frag enables <<
1235 if (frag == (skb_shin <<
1236 pkt_info.cmd_ <<
1237 <<
1238 pkt_info.retu <<
1239 mp->tx_ring_s <<
1240 } <<
1241 else { <<
1242 pkt_info.retu <<
1243 } <<
1244 pkt_info.byte_cnt = t <<
1245 if (this_frag->size < <<
1246 printk("%d : <<
1247 <<
1248 pkt_info.buf_ptr = pc <<
1249 this_ <<
1250 this_ <<
1251 <<
1252 status = eth_port_sen <<
1253 <<
1254 if (status != ETH_OK) <<
1255 if ((status = <<
1256 print <<
1257 1723
1258 if (status = !! 1724 /* ensure all descriptors are written before poking hardware */
1259 print !! 1725 wmb();
>> 1726 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1260 1727
1261 if (status == !! 1728 mp->tx_desc_count += nr_frags + 1;
1262 print !! 1729 }
1263 } <<
1264 } <<
1265 } <<
1266 #endif <<
1267 1730
1268 /* Check if TX queue can handle anoth !! 1731 /**
1269 * signal higher layers to stop reque !! 1732 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1270 */ !! 1733 *
1271 if (MV64340_TX_QUEUE_SIZE <= (mp->tx_ !! 1734 */
1272 /* !! 1735 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1273 * Stop getting skb's from up !! 1736 {
1274 * Getting skb's from upper l !! 1737 struct mv643xx_private *mp = netdev_priv(dev);
1275 * packets are released. !! 1738 struct net_device_stats *stats = &dev->stats;
1276 */ !! 1739 unsigned long flags;
>> 1740
>> 1741 BUG_ON(netif_queue_stopped(dev));
>> 1742 BUG_ON(skb == NULL);
>> 1743
>> 1744 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
>> 1745 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1277 netif_stop_queue(dev); 1746 netif_stop_queue(dev);
>> 1747 return 1;
>> 1748 }
>> 1749
>> 1750 if (has_tiny_unaligned_frags(skb)) {
>> 1751 if (__skb_linearize(skb)) {
>> 1752 stats->tx_dropped++;
>> 1753 printk(KERN_DEBUG "%s: failed to linearize tiny "
>> 1754 "unaligned fragment\n", dev->name);
>> 1755 return 1;
>> 1756 }
>> 1757 }
1278 1758
1279 /* Update statistics and start of tra !! 1759 spin_lock_irqsave(&mp->lock, flags);
>> 1760
>> 1761 eth_tx_submit_descs_for_skb(mp, skb);
1280 stats->tx_bytes += skb->len; 1762 stats->tx_bytes += skb->len;
1281 stats->tx_packets++; 1763 stats->tx_packets++;
1282 dev->trans_start = jiffies; 1764 dev->trans_start = jiffies;
1283 1765
>> 1766 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
>> 1767 netif_stop_queue(dev);
>> 1768
1284 spin_unlock_irqrestore(&mp->lock, fla 1769 spin_unlock_irqrestore(&mp->lock, flags);
1285 1770
1286 return 0; /* success */ 1771 return 0; /* success */
1287 } 1772 }
1288 1773
1289 /* !! 1774 #ifdef CONFIG_NET_POLL_CONTROLLER
1290 * mv64340_eth_get_stats !! 1775 static void mv643xx_netpoll(struct net_device *netdev)
1291 * !! 1776 {
1292 * Returns a pointer to the interface statist !! 1777 struct mv643xx_private *mp = netdev_priv(netdev);
1293 * !! 1778 int port_num = mp->port_num;
1294 * Input : dev - a pointer to the required in !! 1779
1295 * !! 1780 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1296 * Output : a pointer to the interface's stat !! 1781 /* wait for previous write to complete */
1297 */ !! 1782 mv_read(INTERRUPT_MASK_REG(port_num));
>> 1783
>> 1784 mv643xx_eth_int_handler(netdev->irq, netdev);
>> 1785
>> 1786 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
>> 1787 }
>> 1788 #endif
1298 1789
1299 static struct net_device_stats *mv64340_eth_g !! 1790 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
>> 1791 int speed, int duplex,
>> 1792 struct ethtool_cmd *cmd)
1300 { 1793 {
1301 struct mv64340_private *mp = netdev_p !! 1794 struct mv643xx_private *mp = netdev_priv(dev);
>> 1795
>> 1796 memset(cmd, 0, sizeof(*cmd));
1302 1797
1303 return &mp->stats; !! 1798 cmd->port = PORT_MII;
>> 1799 cmd->transceiver = XCVR_INTERNAL;
>> 1800 cmd->phy_address = phy_address;
>> 1801
>> 1802 if (speed == 0) {
>> 1803 cmd->autoneg = AUTONEG_ENABLE;
>> 1804 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
>> 1805 cmd->speed = SPEED_100;
>> 1806 cmd->advertising = ADVERTISED_10baseT_Half |
>> 1807 ADVERTISED_10baseT_Full |
>> 1808 ADVERTISED_100baseT_Half |
>> 1809 ADVERTISED_100baseT_Full;
>> 1810 if (mp->mii.supports_gmii)
>> 1811 cmd->advertising |= ADVERTISED_1000baseT_Full;
>> 1812 } else {
>> 1813 cmd->autoneg = AUTONEG_DISABLE;
>> 1814 cmd->speed = speed;
>> 1815 cmd->duplex = duplex;
>> 1816 }
1304 } 1817 }
1305 1818
1306 /*/ 1819 /*/
1307 * mv64340_eth_init !! 1820 * mv643xx_eth_probe
1308 * !! 1821 *
1309 * First function called after registering th !! 1822 * First function called after registering the network device.
1310 * It's purpose is to initialize the device a !! 1823 * It's purpose is to initialize the device as an ethernet device,
1311 * fill the structure that was given in regis !! 1824 * fill the ethernet device structure with pointers * to functions,
1312 * to functions, and setting the MAC address !! 1825 * and set the MAC address of the interface
1313 * 1826 *
1314 * Input : number of port to initialize !! 1827 * Input : struct device *
1315 * Output : -ENONMEM if failed , 0 if success !! 1828 * Output : -ENOMEM if failed , 0 if success
1316 */ 1829 */
1317 static struct net_device *mv64340_eth_init(in !! 1830 static int mv643xx_eth_probe(struct platform_device *pdev)
1318 { 1831 {
1319 struct mv64340_private *mp; !! 1832 struct mv643xx_eth_platform_data *pd;
>> 1833 int port_num;
>> 1834 struct mv643xx_private *mp;
1320 struct net_device *dev; 1835 struct net_device *dev;
>> 1836 u8 *p;
>> 1837 struct resource *res;
1321 int err; 1838 int err;
>> 1839 struct ethtool_cmd cmd;
>> 1840 int duplex = DUPLEX_HALF;
>> 1841 int speed = 0; /* default to auto-negotiation */
>> 1842 DECLARE_MAC_BUF(mac);
>> 1843
>> 1844 pd = pdev->dev.platform_data;
>> 1845 if (pd == NULL) {
>> 1846 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
>> 1847 return -ENODEV;
>> 1848 }
1322 1849
1323 dev = alloc_etherdev(sizeof(struct mv !! 1850 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1324 if (!dev) 1851 if (!dev)
1325 return NULL; !! 1852 return -ENOMEM;
1326 1853
1327 mp = netdev_priv(dev); !! 1854 platform_set_drvdata(pdev, dev);
1328 1855
1329 dev->irq = ETH_PORT0_IRQ_NUM + port_n !! 1856 mp = netdev_priv(dev);
>> 1857 mp->dev = dev;
>> 1858 #ifdef MV643XX_NAPI
>> 1859 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
>> 1860 #endif
1330 1861
1331 dev->open = mv64340_eth_open; !! 1862 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1332 dev->stop = mv64340_eth_stop; !! 1863 BUG_ON(!res);
1333 dev->hard_start_xmit = mv64340_eth_st !! 1864 dev->irq = res->start;
1334 dev->get_stats = mv64340_eth_get_stat !! 1865
1335 dev->set_mac_address = mv64340_eth_se !! 1866 dev->open = mv643xx_eth_open;
1336 dev->set_multicast_list = mv64340_eth !! 1867 dev->stop = mv643xx_eth_stop;
>> 1868 dev->hard_start_xmit = mv643xx_eth_start_xmit;
>> 1869 dev->set_mac_address = mv643xx_eth_set_mac_address;
>> 1870 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1337 1871
1338 /* No need to Tx Timeout */ 1872 /* No need to Tx Timeout */
1339 dev->tx_timeout = mv64340_eth_tx_time !! 1873 dev->tx_timeout = mv643xx_eth_tx_timeout;
1340 #ifdef MV64340_NAPI !! 1874
1341 dev->poll = mv64340_poll; !! 1875 #ifdef CONFIG_NET_POLL_CONTROLLER
1342 dev->weight = 64; !! 1876 dev->poll_controller = mv643xx_netpoll;
1343 #endif 1877 #endif
1344 1878
1345 dev->watchdog_timeo = 2 * HZ; 1879 dev->watchdog_timeo = 2 * HZ;
1346 dev->tx_queue_len = MV64340_TX_QUEUE_ <<
1347 dev->base_addr = 0; 1880 dev->base_addr = 0;
1348 dev->change_mtu = mv64340_eth_change_ !! 1881 dev->change_mtu = mv643xx_eth_change_mtu;
>> 1882 dev->do_ioctl = mv643xx_eth_do_ioctl;
>> 1883 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1349 1884
1350 #ifdef MV64340_CHECKSUM_OFFLOAD_TX !! 1885 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1351 #ifdef MAX_SKB_FRAGS 1886 #ifdef MAX_SKB_FRAGS
1352 #ifndef CONFIG_JAGUAR_DMALOW !! 1887 /*
1353 /* !! 1888 * Zero copy can only work if we use Discovery II memory. Else, we will
1354 * Zero copy can only work if we use !! 1889 * have to map the buffers to ISA memory which is only 16 MB
1355 * have to map the buffers to ISA mem !! 1890 */
1356 */ !! 1891 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1357 dev->features = NETIF_F_SG | NETIF_F_ <<
1358 #endif <<
1359 #endif 1892 #endif
1360 #endif 1893 #endif
1361 1894
1362 mp->port_num = port_num; <<
1363 <<
1364 /* Configure the timeout task */ 1895 /* Configure the timeout task */
1365 INIT_WORK(&mp->tx_timeout_task, !! 1896 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1366 (void (*)(void *))mv64340_e <<
1367 1897
1368 spin_lock_init(&mp->lock); 1898 spin_lock_init(&mp->lock);
1369 1899
1370 /* set MAC addresses */ !! 1900 port_num = mp->port_num = pd->port_number;
1371 memcpy(dev->dev_addr, prom_mac_addr_b !! 1901
1372 dev->dev_addr[5] += port_num; !! 1902 /* set default config values */
>> 1903 eth_port_uc_addr_get(port_num, dev->dev_addr);
>> 1904 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
>> 1905 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
>> 1906
>> 1907 if (is_valid_ether_addr(pd->mac_addr))
>> 1908 memcpy(dev->dev_addr, pd->mac_addr, 6);
>> 1909
>> 1910 if (pd->phy_addr || pd->force_phy_addr)
>> 1911 ethernet_phy_set(port_num, pd->phy_addr);
>> 1912
>> 1913 if (pd->rx_queue_size)
>> 1914 mp->rx_ring_size = pd->rx_queue_size;
>> 1915
>> 1916 if (pd->tx_queue_size)
>> 1917 mp->tx_ring_size = pd->tx_queue_size;
>> 1918
>> 1919 if (pd->tx_sram_size) {
>> 1920 mp->tx_sram_size = pd->tx_sram_size;
>> 1921 mp->tx_sram_addr = pd->tx_sram_addr;
>> 1922 }
>> 1923
>> 1924 if (pd->rx_sram_size) {
>> 1925 mp->rx_sram_size = pd->rx_sram_size;
>> 1926 mp->rx_sram_addr = pd->rx_sram_addr;
>> 1927 }
>> 1928
>> 1929 duplex = pd->duplex;
>> 1930 speed = pd->speed;
>> 1931
>> 1932 /* Hook up MII support for ethtool */
>> 1933 mp->mii.dev = dev;
>> 1934 mp->mii.mdio_read = mv643xx_mdio_read;
>> 1935 mp->mii.mdio_write = mv643xx_mdio_write;
>> 1936 mp->mii.phy_id = ethernet_phy_get(port_num);
>> 1937 mp->mii.phy_id_mask = 0x3f;
>> 1938 mp->mii.reg_num_mask = 0x1f;
>> 1939
>> 1940 err = ethernet_phy_detect(port_num);
>> 1941 if (err) {
>> 1942 pr_debug("MV643xx ethernet port %d: "
>> 1943 "No PHY detected at addr %d\n",
>> 1944 port_num, ethernet_phy_get(port_num));
>> 1945 goto out;
>> 1946 }
>> 1947
>> 1948 ethernet_phy_reset(port_num);
>> 1949 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
>> 1950 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
>> 1951 mv643xx_eth_update_pscr(dev, &cmd);
>> 1952 mv643xx_set_settings(dev, &cmd);
1373 1953
>> 1954 SET_NETDEV_DEV(dev, &pdev->dev);
1374 err = register_netdev(dev); 1955 err = register_netdev(dev);
1375 if (err) 1956 if (err)
1376 goto out_free_dev; !! 1957 goto out;
1377 1958
1378 printk(KERN_NOTICE "%s: port %d with !! 1959 p = dev->dev_addr;
1379 dev->name, port_num, !! 1960 printk(KERN_NOTICE
1380 dev->dev_addr[0], dev->dev_ad !! 1961 "%s: port %d with MAC address %s\n",
1381 dev->dev_addr[3], dev->dev_ad !! 1962 dev->name, port_num, print_mac(mac, p));
1382 1963
1383 if (dev->features & NETIF_F_SG) 1964 if (dev->features & NETIF_F_SG)
1384 printk("Scatter Gather Enable !! 1965 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1385 1966
1386 if (dev->features & NETIF_F_IP_CSUM) 1967 if (dev->features & NETIF_F_IP_CSUM)
1387 printk("TX TCP/IP Checksummin !! 1968 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
>> 1969 dev->name);
>> 1970
>> 1971 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
>> 1972 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
>> 1973 #endif
1388 1974
1389 printk("RX TCP/UDP Checksum Offload O !! 1975 #ifdef MV643XX_COAL
1390 printk("TX and RX Interrupt Coalescin !! 1976 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
>> 1977 dev->name);
>> 1978 #endif
1391 1979
1392 #ifdef MV64340_NAPI !! 1980 #ifdef MV643XX_NAPI
1393 printk("RX NAPI Enabled \n"); !! 1981 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1394 #endif 1982 #endif
1395 1983
1396 return dev; !! 1984 if (mp->tx_sram_size > 0)
>> 1985 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
>> 1986
>> 1987 return 0;
1397 1988
1398 out_free_dev: !! 1989 out:
1399 free_netdev(dev); 1990 free_netdev(dev);
1400 1991
1401 return NULL; !! 1992 return err;
1402 } 1993 }
1403 1994
1404 static void mv64340_eth_remove(struct net_dev !! 1995 static int mv643xx_eth_remove(struct platform_device *pdev)
1405 { 1996 {
1406 struct mv64340_private *mp = netdev_p !! 1997 struct net_device *dev = platform_get_drvdata(pdev);
1407 1998
1408 unregister_netdev(dev); 1999 unregister_netdev(dev);
1409 flush_scheduled_work(); 2000 flush_scheduled_work();
>> 2001
1410 free_netdev(dev); 2002 free_netdev(dev);
>> 2003 platform_set_drvdata(pdev, NULL);
>> 2004 return 0;
1411 } 2005 }
1412 2006
1413 static struct net_device *mv64340_dev0; !! 2007 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1414 static struct net_device *mv64340_dev1; !! 2008 {
1415 static struct net_device *mv64340_dev2; !! 2009 struct resource *res;
>> 2010
>> 2011 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
>> 2012
>> 2013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> 2014 if (res == NULL)
>> 2015 return -ENODEV;
>> 2016
>> 2017 mv643xx_eth_base = ioremap(res->start, res->end - res->start + 1);
>> 2018 if (mv643xx_eth_base == NULL)
>> 2019 return -ENOMEM;
>> 2020
>> 2021 return 0;
>> 2022
>> 2023 }
>> 2024
>> 2025 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
>> 2026 {
>> 2027 iounmap(mv643xx_eth_base);
>> 2028 mv643xx_eth_base = NULL;
>> 2029
>> 2030 return 0;
>> 2031 }
>> 2032
>> 2033 static void mv643xx_eth_shutdown(struct platform_device *pdev)
>> 2034 {
>> 2035 struct net_device *dev = platform_get_drvdata(pdev);
>> 2036 struct mv643xx_private *mp = netdev_priv(dev);
>> 2037 unsigned int port_num = mp->port_num;
>> 2038
>> 2039 /* Mask all interrupts on ethernet port */
>> 2040 mv_write(INTERRUPT_MASK_REG(port_num), 0);
>> 2041 mv_read (INTERRUPT_MASK_REG(port_num));
>> 2042
>> 2043 eth_port_reset(port_num);
>> 2044 }
>> 2045
>> 2046 static struct platform_driver mv643xx_eth_driver = {
>> 2047 .probe = mv643xx_eth_probe,
>> 2048 .remove = mv643xx_eth_remove,
>> 2049 .shutdown = mv643xx_eth_shutdown,
>> 2050 .driver = {
>> 2051 .name = MV643XX_ETH_NAME,
>> 2052 },
>> 2053 };
>> 2054
>> 2055 static struct platform_driver mv643xx_eth_shared_driver = {
>> 2056 .probe = mv643xx_eth_shared_probe,
>> 2057 .remove = mv643xx_eth_shared_remove,
>> 2058 .driver = {
>> 2059 .name = MV643XX_ETH_SHARED_NAME,
>> 2060 },
>> 2061 };
1416 2062
1417 /* 2063 /*
1418 * mv64340_init_module !! 2064 * mv643xx_init_module
1419 * 2065 *
1420 * Registers the network drivers into the Lin 2066 * Registers the network drivers into the Linux kernel
1421 * 2067 *
1422 * Input : N/A !! 2068 * Input : N/A
1423 * 2069 *
1424 * Output : N/A !! 2070 * Output : N/A
1425 */ 2071 */
1426 static int __init mv64340_init_module(void) !! 2072 static int __init mv643xx_init_module(void)
1427 { 2073 {
1428 printk(KERN_NOTICE "MV-643xx 10/100/1 !! 2074 int rc;
1429 2075
1430 #ifdef CONFIG_MV643XX_ETH_0 !! 2076 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1431 mv64340_dev0 = mv64340_eth_init(0); !! 2077 if (!rc) {
1432 if (!mv64340_dev0) { !! 2078 rc = platform_driver_register(&mv643xx_eth_driver);
1433 printk(KERN_ERR !! 2079 if (rc)
1434 "Error registering MV- !! 2080 platform_driver_unregister(&mv643xx_eth_shared_driver);
1435 } 2081 }
1436 #endif !! 2082 return rc;
1437 #ifdef CONFIG_MV643XX_ETH_1 <<
1438 mv64340_dev1 = mv64340_eth_init(1); <<
1439 if (!mv64340_dev1) { <<
1440 printk(KERN_ERR <<
1441 "Error registering MV- <<
1442 } <<
1443 #endif <<
1444 #ifdef CONFIG_MV643XX_ETH_2 <<
1445 mv64340_dev2 = mv64340_eth_init(2); <<
1446 if (!mv64340_dev2) { <<
1447 printk(KERN_ERR <<
1448 "Error registering MV- <<
1449 } <<
1450 #endif <<
1451 return 0; <<
1452 } 2083 }
1453 2084
1454 /* 2085 /*
1455 * mv64340_cleanup_module !! 2086 * mv643xx_cleanup_module
1456 * 2087 *
1457 * Registers the network drivers into the Lin 2088 * Registers the network drivers into the Linux kernel
1458 * 2089 *
1459 * Input : N/A !! 2090 * Input : N/A
1460 * 2091 *
1461 * Output : N/A !! 2092 * Output : N/A
1462 */ 2093 */
1463 static void __exit mv64340_cleanup_module(voi !! 2094 static void __exit mv643xx_cleanup_module(void)
1464 { 2095 {
1465 if (mv64340_dev2) !! 2096 platform_driver_unregister(&mv643xx_eth_driver);
1466 mv64340_eth_remove(mv64340_de !! 2097 platform_driver_unregister(&mv643xx_eth_shared_driver);
1467 if (mv64340_dev1) <<
1468 mv64340_eth_remove(mv64340_de <<
1469 if (mv64340_dev0) <<
1470 mv64340_eth_remove(mv64340_de <<
1471 } 2098 }
1472 2099
1473 module_init(mv64340_init_module); !! 2100 module_init(mv643xx_init_module);
1474 module_exit(mv64340_cleanup_module); !! 2101 module_exit(mv643xx_cleanup_module);
1475 2102
1476 MODULE_LICENSE("GPL"); 2103 MODULE_LICENSE("GPL");
1477 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, !! 2104 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1478 MODULE_DESCRIPTION("Ethernet driver for Marve !! 2105 " and Dale Farnsworth");
>> 2106 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
>> 2107 MODULE_ALIAS("platform:mv643xx_eth");
1479 2108
1480 /* 2109 /*
1481 * The second part is the low level driver o !! 2110 * The second part is the low level driver of the gigE ethernet ports.
1482 */ 2111 */
1483 2112
1484 /* 2113 /*
1485 * Marvell's Gigabit Ethernet controller low 2114 * Marvell's Gigabit Ethernet controller low level driver
1486 * 2115 *
1487 * DESCRIPTION: 2116 * DESCRIPTION:
1488 * This file introduce low level API to !! 2117 * This file introduce low level API to Marvell's Gigabit Ethernet
1489 * controller. This Gigabit Ethe 2118 * controller. This Gigabit Ethernet Controller driver API controls
1490 * 1) Operations (i.e. port init 2119 * 1) Operations (i.e. port init, start, reset etc').
1491 * 2) Data flow (i.e. port send, 2120 * 2) Data flow (i.e. port send, receive etc').
1492 * Each Gigabit Ethernet port is 2121 * Each Gigabit Ethernet port is controlled via
1493 * struct mv64340_private. !! 2122 * struct mv643xx_private.
1494 * This struct includes user con 2123 * This struct includes user configuration information as well as
1495 * driver internal data needed f 2124 * driver internal data needed for its operations.
1496 * 2125 *
1497 * Supported Features: !! 2126 * Supported Features:
1498 * - This low level driver is OS 2127 * - This low level driver is OS independent. Allocating memory for
1499 * the descriptor rings and bu 2128 * the descriptor rings and buffers are not within the scope of
1500 * this driver. 2129 * this driver.
1501 * - The user is free from Rx/Tx 2130 * - The user is free from Rx/Tx queue managing.
1502 * - This low level driver intro 2131 * - This low level driver introduce functionality API that enable
1503 * the to operate Marvell's Gi 2132 * the to operate Marvell's Gigabit Ethernet Controller in a
1504 * convenient way. 2133 * convenient way.
1505 * - Simple Gigabit Ethernet por 2134 * - Simple Gigabit Ethernet port operation API.
1506 * - Simple Gigabit Ethernet por 2135 * - Simple Gigabit Ethernet port data flow API.
1507 * - Data flow and operation API 2136 * - Data flow and operation API support per queue functionality.
1508 * - Support cached descriptors 2137 * - Support cached descriptors for better performance.
1509 * - Enable access to all four D 2138 * - Enable access to all four DRAM banks and internal SRAM memory
1510 * spaces. 2139 * spaces.
1511 * - PHY access and control API. 2140 * - PHY access and control API.
1512 * - Port control register confi 2141 * - Port control register configuration API.
1513 * - Full control over Unicast a 2142 * - Full control over Unicast and Multicast MAC configurations.
1514 * !! 2143 *
1515 * Operation flow: 2144 * Operation flow:
1516 * 2145 *
1517 * Initialization phase 2146 * Initialization phase
1518 * This phase complete the initi !! 2147 * This phase complete the initialization of the the
1519 * struct. !! 2148 * mv643xx_private struct.
1520 * User information regarding po 2149 * User information regarding port configuration has to be set
1521 * prior to calling the port ini 2150 * prior to calling the port initialization routine.
1522 * 2151 *
1523 * In this phase any port Tx/Rx 2152 * In this phase any port Tx/Rx activity is halted, MIB counters
1524 * are cleared, PHY address is s 2153 * are cleared, PHY address is set according to user parameter and
1525 * access to DRAM and internal S 2154 * access to DRAM and internal SRAM memory spaces.
1526 * 2155 *
1527 * Driver ring initialization 2156 * Driver ring initialization
1528 * Allocating memory for the des !! 2157 * Allocating memory for the descriptor rings and buffers is not
1529 * within the scope of this driv 2158 * within the scope of this driver. Thus, the user is required to
1530 * allocate memory for the descr 2159 * allocate memory for the descriptors ring and buffers. Those
1531 * memory parameters are used by 2160 * memory parameters are used by the Rx and Tx ring initialization
1532 * routines in order to curve th 2161 * routines in order to curve the descriptor linked list in a form
1533 * of a ring. 2162 * of a ring.
1534 * Note: Pay special attention t 2163 * Note: Pay special attention to alignment issues when using
1535 * cached descriptors/buffers. I 2164 * cached descriptors/buffers. In this phase the driver store
1536 * information in the mv64340_pr !! 2165 * information in the mv643xx_private struct regarding each queue
1537 * ring. 2166 * ring.
1538 * 2167 *
1539 * Driver start !! 2168 * Driver start
1540 * This phase prepares the Ether 2169 * This phase prepares the Ethernet port for Rx and Tx activity.
1541 * It uses the information store !! 2170 * It uses the information stored in the mv643xx_private struct to
1542 * initialize the various port r 2171 * initialize the various port registers.
1543 * 2172 *
1544 * Data flow: 2173 * Data flow:
1545 * All packet references to/from 2174 * All packet references to/from the driver are done using
1546 * struct pkt_info. !! 2175 * struct pkt_info.
1547 * This struct is a unified stru !! 2176 * This struct is a unified struct used with Rx and Tx operations.
1548 * This way the user is not requ 2177 * This way the user is not required to be familiar with neither
1549 * Tx nor Rx descriptors structu 2178 * Tx nor Rx descriptors structures.
1550 * The driver's descriptors ring 2179 * The driver's descriptors rings are management by indexes.
1551 * Those indexes controls the ri 2180 * Those indexes controls the ring resources and used to indicate
1552 * a SW resource error: 2181 * a SW resource error:
1553 * 'current' !! 2182 * 'current'
1554 * This index points to the curr !! 2183 * This index points to the current available resource for use. For
1555 * example in Rx process this in !! 2184 * example in Rx process this index will point to the descriptor
1556 * that will be passed to the us !! 2185 * that will be passed to the user upon calling the receive
1557 * In Tx process, this index wil !! 2186 * routine. In Tx process, this index will point to the descriptor
1558 * that will be assigned with th 2187 * that will be assigned with the user packet info and transmitted.
1559 * 'used' !! 2188 * 'used'
1560 * This index points to the desc !! 2189 * This index points to the descriptor that need to restore its
1561 * resources. For example in Rx 2190 * resources. For example in Rx process, using the Rx buffer return
1562 * API will attach the buffer re 2191 * API will attach the buffer returned in packet info to the
1563 * descriptor pointed by 'used'. 2192 * descriptor pointed by 'used'. In Tx process, using the Tx
1564 * descriptor return will merely 2193 * descriptor return will merely return the user packet info with
1565 * the command status of the tr !! 2194 * the command status of the transmitted buffer pointed by the
1566 * 'used' index. Nevertheless, i 2195 * 'used' index. Nevertheless, it is essential to use this routine
1567 * to update the 'used' index. 2196 * to update the 'used' index.
1568 * 'first' 2197 * 'first'
1569 * This index supports Tx Scatte !! 2198 * This index supports Tx Scatter-Gather. It points to the first
1570 * descriptor of a packet assemb !! 2199 * descriptor of a packet assembled of multiple buffers. For
1571 * when in middle of Such packet !! 2200 * example when in middle of Such packet we have a Tx resource
1572 * 'curr' index get the value of !! 2201 * error the 'curr' index get the value of 'first' to indicate
1573 * returned to its state before !! 2202 * that the ring returned to its state before trying to transmit
>> 2203 * this packet.
1574 * 2204 *
1575 * Receive operation: 2205 * Receive operation:
1576 * The eth_port_receive API set 2206 * The eth_port_receive API set the packet information struct,
1577 * passed by the caller, with re !! 2207 * passed by the caller, with received information from the
1578 * 'current' SDMA descriptor. !! 2208 * 'current' SDMA descriptor.
1579 * It is the user responsibility 2209 * It is the user responsibility to return this resource back
1580 * to the Rx descriptor ring to 2210 * to the Rx descriptor ring to enable the reuse of this source.
1581 * Return Rx resource is done us 2211 * Return Rx resource is done using the eth_rx_return_buff API.
1582 * 2212 *
1583 * Transmit operation: !! 2213 * Prior to calling the initialization routine eth_port_init() the user
1584 * The eth_port_send API support !! 2214 * must set the following fields under mv643xx_private struct:
1585 * send a packet spanned over mu !! 2215 * port_num User Ethernet port number.
1586 * for each packet info structur !! 2216 * port_config User port configuration value.
1587 * the Tx descriptors ring, will !! 2217 * port_config_extend User port config extend value.
1588 * bit will be set in the packet !! 2218 * port_sdma_config User port SDMA config value.
1589 * API also consider restriction !! 2219 * port_serial_control User port serial control value.
1590 * sizes. <<
1591 * The user must return a Tx res <<
1592 * has been transmitted to enabl <<
1593 * <<
1594 * BOARD LAYOUT <<
1595 * This device is on-board. No <<
1596 * <<
1597 * EXTERNAL INTERFACE <<
1598 * <<
1599 * Prior to calling the initialization <<
1600 * must set the following fields under <<
1601 * port_num User Ethernet p <<
1602 * port_mac_addr[6] User defi <<
1603 * port_config User port confi <<
1604 * port_config_extend User port conf <<
1605 * port_sdma_config User port SDMA <<
1606 * port_serial_control User port seri <<
1607 * <<
1608 * This driver introduce a set of defau <<
1609 * PORT_CONFIG_VALUE Default <<
1610 * PORT_CONFIG_EXTEND_VALUE Default <<
1611 * PORT_SDMA_CONFIG_VALUE Default <<
1612 * PORT_SERIAL_CONTROL_VALUE Default <<
1613 * 2220 *
1614 * This driver data flow is done 2221 * This driver data flow is done using the struct pkt_info which
1615 * is a unified struct for Rx an !! 2222 * is a unified struct for Rx and Tx operations:
1616 * 2223 *
1617 * byte_cnt Tx/Rx descrip 2224 * byte_cnt Tx/Rx descriptor buffer byte count.
1618 * l4i_chk CPU provided 2225 * l4i_chk CPU provided TCP Checksum. For Tx operation
1619 * only. !! 2226 * only.
1620 * cmd_sts Tx/Rx descrip 2227 * cmd_sts Tx/Rx descriptor command status.
1621 * buf_ptr Tx/Rx descrip 2228 * buf_ptr Tx/Rx descriptor buffer pointer.
1622 * return_info Tx/Rx user re 2229 * return_info Tx/Rx user resource return information.
1623 */ 2230 */
1624 2231
1625 /* defines */ <<
1626 /* SDMA command macros */ <<
1627 #define ETH_ENABLE_TX_QUEUE(eth_port) \ <<
1628 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_C <<
1629 <<
1630 #define ETH_DISABLE_TX_QUEUE(eth_port) \ <<
1631 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_C <<
1632 (1 << 8)) <<
1633 <<
1634 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_por <<
1635 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_CO <<
1636 (1 << rx_queue)) <<
1637 <<
1638 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_po <<
1639 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_CO <<
1640 (1 << (8 + rx_queue))) <<
1641 <<
1642 #define LINK_UP_TIMEOUT 100000 <<
1643 #define PHY_BUSY_TIMEOUT 10000000 <<
1644 <<
1645 /* locals */ <<
1646 <<
1647 /* PHY routines */ 2232 /* PHY routines */
1648 static int ethernet_phy_get(unsigned int eth_ 2233 static int ethernet_phy_get(unsigned int eth_port_num);
>> 2234 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1649 2235
1650 /* Ethernet Port routines */ 2236 /* Ethernet Port routines */
1651 static int eth_port_uc_addr(unsigned int eth_ !! 2237 static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1652 int option); <<
1653 2238
1654 /* 2239 /*
1655 * eth_port_init - Initialize the Ethernet po 2240 * eth_port_init - Initialize the Ethernet port driver
1656 * 2241 *
1657 * DESCRIPTION: 2242 * DESCRIPTION:
1658 * This function prepares the ethernet !! 2243 * This function prepares the ethernet port to start its activity:
1659 * 1) Completes the ethernet port drive !! 2244 * 1) Completes the ethernet port driver struct initialization toward port
1660 * start routine. !! 2245 * start routine.
1661 * 2) Resets the device to a quiescent !! 2246 * 2) Resets the device to a quiescent state in case of warm reboot.
1662 * 3) Enable SDMA access to all four DR !! 2247 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1663 * 4) Clean MAC tables. The reset statu !! 2248 * 4) Clean MAC tables. The reset status of those tables is unknown.
1664 * 5) Set PHY address. !! 2249 * 5) Set PHY address.
1665 * Note: Call this routine prior to eth !! 2250 * Note: Call this routine prior to eth_port_start routine and after
1666 * setting user values in the user fiel !! 2251 * setting user values in the user fields of Ethernet port control
1667 * struct. !! 2252 * struct.
1668 * 2253 *
1669 * INPUT: 2254 * INPUT:
1670 * struct mv64340_private *mp Etherne !! 2255 * struct mv643xx_private *mp Ethernet port control struct
1671 * 2256 *
1672 * OUTPUT: 2257 * OUTPUT:
1673 * See description. !! 2258 * See description.
1674 * 2259 *
1675 * RETURN: 2260 * RETURN:
1676 * None. !! 2261 * None.
1677 */ 2262 */
1678 static void eth_port_init(struct mv64340_priv !! 2263 static void eth_port_init(struct mv643xx_private *mp)
1679 { 2264 {
1680 mp->port_config = PORT_CONFIG_VALUE; <<
1681 mp->port_config_extend = PORT_CONFIG_ <<
1682 #if defined(__BIG_ENDIAN) <<
1683 mp->port_sdma_config = PORT_SDMA_CONF <<
1684 #elif defined(__LITTLE_ENDIAN) <<
1685 mp->port_sdma_config = PORT_SDMA_CONF <<
1686 ETH_BLM_RX_NO_SWAP | ETH_BLM_ <<
1687 #else <<
1688 #error One of __LITTLE_ENDIAN or __BIG_ENDIAN <<
1689 #endif <<
1690 mp->port_serial_control = PORT_SERIAL <<
1691 <<
1692 mp->port_rx_queue_command = 0; <<
1693 mp->port_tx_queue_command = 0; <<
1694 <<
1695 mp->rx_resource_err = 0; 2265 mp->rx_resource_err = 0;
1696 mp->tx_resource_err = 0; <<
1697 2266
1698 eth_port_reset(mp->port_num); 2267 eth_port_reset(mp->port_num);
1699 2268
1700 eth_port_init_mac_tables(mp->port_num 2269 eth_port_init_mac_tables(mp->port_num);
1701 <<
1702 ethernet_phy_reset(mp->port_num); <<
1703 } 2270 }
1704 2271
1705 /* 2272 /*
1706 * eth_port_start - Start the Ethernet port a 2273 * eth_port_start - Start the Ethernet port activity.
1707 * 2274 *
1708 * DESCRIPTION: 2275 * DESCRIPTION:
1709 * This routine prepares the Ethernet p !! 2276 * This routine prepares the Ethernet port for Rx and Tx activity:
1710 * 1. Initialize Tx and Rx Current Desc !! 2277 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1711 * has been initialized a descriptor !! 2278 * has been initialized a descriptor's ring (using
1712 * ether_init_tx_desc_ring for Tx an !! 2279 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1713 * 2. Initialize and enable the Etherne !! 2280 * 2. Initialize and enable the Ethernet configuration port by writing to
1714 * the port's configuration and comm !! 2281 * the port's configuration and command registers.
1715 * 3. Initialize and enable the SDMA by !! 2282 * 3. Initialize and enable the SDMA by writing to the SDMA's
1716 * configuration and command registe !! 2283 * configuration and command registers. After completing these steps,
1717 * the ethernet port SDMA can starts !! 2284 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1718 * !! 2285 *
1719 * Note: Each Rx and Tx queue descripto !! 2286 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1720 * to calling this function (use ether_ !! 2287 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1721 * and ether_init_rx_desc_ring for Rx q !! 2288 * and ether_init_rx_desc_ring for Rx queues).
1722 * 2289 *
1723 * INPUT: 2290 * INPUT:
1724 * struct mv64340_private *mp !! 2291 * dev - a pointer to the required interface
1725 * 2292 *
1726 * OUTPUT: 2293 * OUTPUT:
1727 * Ethernet port is ready to receive an !! 2294 * Ethernet port is ready to receive and transmit.
1728 * 2295 *
1729 * RETURN: 2296 * RETURN:
1730 * false if the port PHY is not up. !! 2297 * None.
1731 * true otherwise. <<
1732 */ 2298 */
1733 static int eth_port_start(struct mv64340_priv !! 2299 static void eth_port_start(struct net_device *dev)
1734 { 2300 {
1735 unsigned int eth_port_num = mp->port_ !! 2301 struct mv643xx_private *mp = netdev_priv(dev);
>> 2302 unsigned int port_num = mp->port_num;
1736 int tx_curr_desc, rx_curr_desc; 2303 int tx_curr_desc, rx_curr_desc;
1737 unsigned int phy_reg_data; !! 2304 u32 pscr;
>> 2305 struct ethtool_cmd ethtool_cmd;
1738 2306
1739 /* Assignment of Tx CTRP of given que 2307 /* Assignment of Tx CTRP of given queue */
1740 tx_curr_desc = mp->tx_curr_desc_q; 2308 tx_curr_desc = mp->tx_curr_desc_q;
1741 MV_WRITE(MV64340_ETH_TX_CURRENT_QUEUE !! 2309 mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1742 (struct eth_tx_desc *) mp->t !! 2310 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1743 2311
1744 /* Assignment of Rx CRDP of given que 2312 /* Assignment of Rx CRDP of given queue */
1745 rx_curr_desc = mp->rx_curr_desc_q; 2313 rx_curr_desc = mp->rx_curr_desc_q;
1746 MV_WRITE(MV64340_ETH_RX_CURRENT_QUEUE !! 2314 mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1747 (struct eth_rx_desc *) mp->r !! 2315 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1748 2316
1749 /* Add the assigned Ethernet address 2317 /* Add the assigned Ethernet address to the port's address table */
1750 eth_port_uc_addr_set(mp->port_num, mp !! 2318 eth_port_uc_addr_set(port_num, dev->dev_addr);
1751 2319
1752 /* Assign port configuration and comm 2320 /* Assign port configuration and command. */
1753 MV_WRITE(MV64340_ETH_PORT_CONFIG_REG( !! 2321 mv_write(PORT_CONFIG_REG(port_num),
1754 mp->port_config); !! 2322 PORT_CONFIG_DEFAULT_VALUE);
>> 2323
>> 2324 mv_write(PORT_CONFIG_EXTEND_REG(port_num),
>> 2325 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
>> 2326
>> 2327 pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
1755 2328
1756 MV_WRITE(MV64340_ETH_PORT_CONFIG_EXTE !! 2329 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1757 mp->port_config_extend); !! 2330 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
1758 2331
1759 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONT !! 2332 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1760 mp->port_serial_control); !! 2333 DISABLE_AUTO_NEG_SPEED_GMII |
>> 2334 DISABLE_AUTO_NEG_FOR_DUPLX |
>> 2335 DO_NOT_FORCE_LINK_FAIL |
>> 2336 SERIAL_PORT_CONTROL_RESERVED;
1761 2337
1762 MV_SET_REG_BITS(MV64340_ETH_PORT_SERI !! 2338 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
1763 ETH_SERIAL_PORT_ENABL !! 2339
>> 2340 pscr |= SERIAL_PORT_ENABLE;
>> 2341 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
1764 2342
1765 /* Assign port SDMA configuration */ 2343 /* Assign port SDMA configuration */
1766 MV_WRITE(MV64340_ETH_SDMA_CONFIG_REG( !! 2344 mv_write(SDMA_CONFIG_REG(port_num),
1767 mp->port_sdma_config); !! 2345 PORT_SDMA_CONFIG_DEFAULT_VALUE);
1768 2346
1769 /* Enable port Rx. */ 2347 /* Enable port Rx. */
1770 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_CO !! 2348 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
1771 mp->port_rx_queue_command); <<
1772 <<
1773 /* Check if link is up */ <<
1774 eth_port_read_smi_reg(eth_port_num, 1 <<
1775 2349
1776 if (!(phy_reg_data & 0x20)) !! 2350 /* Disable port bandwidth limits by clearing MTU register */
1777 return 0; !! 2351 mv_write(MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1778 2352
1779 return 1; !! 2353 /* save phy settings across reset */
>> 2354 mv643xx_get_settings(dev, ðtool_cmd);
>> 2355 ethernet_phy_reset(mp->port_num);
>> 2356 mv643xx_set_settings(dev, ðtool_cmd);
1780 } 2357 }
1781 2358
1782 /* 2359 /*
1783 * eth_port_uc_addr_set - This function Set t !! 2360 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1784 * <<
1785 * DESCRIPTION: <<
1786 * This function Set the port Et <<
1787 * <<
1788 * INPUT: <<
1789 * unsigned int eth_port_num Port nu <<
1790 * char * p_addr Addre <<
1791 * <<
1792 * OUTPUT: <<
1793 * Set MAC address low and high register <<
1794 * To set the unicast table with the pr <<
1795 * <<
1796 * RETURN: <<
1797 * N/A. <<
1798 * <<
1799 */ 2361 */
1800 static void eth_port_uc_addr_set(unsigned int !! 2362 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
1801 unsigned cha <<
1802 { 2363 {
1803 unsigned int mac_h; 2364 unsigned int mac_h;
1804 unsigned int mac_l; 2365 unsigned int mac_l;
>> 2366 int table;
1805 2367
1806 mac_l = (p_addr[4] << 8) | (p_addr[5] 2368 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1807 mac_h = (p_addr[0] << 24) | (p_addr[1 !! 2369 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1808 (p_addr[2] << 8) | (p_addr[3] << !! 2370 (p_addr[3] << 0);
1809 2371
1810 MV_WRITE(MV64340_ETH_MAC_ADDR_LOW(eth !! 2372 mv_write(MAC_ADDR_LOW(port_num), mac_l);
1811 MV_WRITE(MV64340_ETH_MAC_ADDR_HIGH(et !! 2373 mv_write(MAC_ADDR_HIGH(port_num), mac_h);
>> 2374
>> 2375 /* Accept frames with this address */
>> 2376 table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
>> 2377 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
>> 2378 }
>> 2379
>> 2380 /*
>> 2381 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
>> 2382 */
>> 2383 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
>> 2384 {
>> 2385 unsigned int mac_h;
>> 2386 unsigned int mac_l;
1812 2387
1813 /* Accept frames of this address */ !! 2388 mac_h = mv_read(MAC_ADDR_HIGH(port_num));
1814 eth_port_uc_addr(eth_port_num, p_addr !! 2389 mac_l = mv_read(MAC_ADDR_LOW(port_num));
1815 2390
1816 return; !! 2391 p_addr[0] = (mac_h >> 24) & 0xff;
>> 2392 p_addr[1] = (mac_h >> 16) & 0xff;
>> 2393 p_addr[2] = (mac_h >> 8) & 0xff;
>> 2394 p_addr[3] = mac_h & 0xff;
>> 2395 p_addr[4] = (mac_l >> 8) & 0xff;
>> 2396 p_addr[5] = mac_l & 0xff;
1817 } 2397 }
1818 2398
1819 /* 2399 /*
1820 * eth_port_uc_addr - This function Set the p !! 2400 * The entries in each table are indexed by a hash of a packet's MAC
1821 * !! 2401 * address. One bit in each entry determines whether the packet is
1822 * DESCRIPTION: !! 2402 * accepted. There are 4 entries (each 8 bits wide) in each register
1823 * This function locates the proper entr !! 2403 * of the table. The bits in each entry are defined as follows:
1824 * specified MAC nibble and sets its pro !! 2404 * 0 Accept=1, Drop=0
1825 * parameters. !! 2405 * 3-1 Queue (ETH_Q0=0)
1826 * !! 2406 * 7-4 Reserved = 0;
1827 * INPUT: <<
1828 * unsigned int eth_port_num Por <<
1829 * unsigned char uc_nibble Unica <<
1830 * int option 0 <<
1831 * <<
1832 * OUTPUT: <<
1833 * This function add/removes MAC address <<
1834 * table. <<
1835 * <<
1836 * RETURN: <<
1837 * true is output succeeded. <<
1838 * false if option parameter is invalid. <<
1839 * <<
1840 */ 2407 */
1841 static int eth_port_uc_addr(unsigned int eth_ !! 2408 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1842 unsigned char uc_nibble, int option) <<
1843 { 2409 {
1844 unsigned int unicast_reg; !! 2410 unsigned int table_reg;
1845 unsigned int tbl_offset; 2411 unsigned int tbl_offset;
1846 unsigned int reg_offset; 2412 unsigned int reg_offset;
1847 2413
1848 /* Locate the Unicast table entry */ !! 2414 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1849 uc_nibble = (0xf & uc_nibble); !! 2415 reg_offset = entry % 4; /* Entry offset within the register */
1850 tbl_offset = (uc_nibble / 4) * 4; <<
1851 reg_offset = uc_nibble % 4; /* En <<
1852 <<
1853 switch (option) { <<
1854 case REJECT_MAC_ADDR: <<
1855 /* Clear accepts frame bit at <<
1856 unicast_reg = MV_READ((MV6434 <<
1857 (eth_port_n <<
1858 <<
1859 unicast_reg &= (0x0E << (8 * <<
1860 <<
1861 MV_WRITE( <<
1862 (MV64340_ETH_DA_FILT <<
1863 (eth_port_num) + tb <<
1864 break; <<
1865 2416
1866 case ACCEPT_MAC_ADDR: !! 2417 /* Set "accepts frame bit" at specified table entry */
1867 /* Set accepts frame bit at u !! 2418 table_reg = mv_read(table + tbl_offset);
1868 unicast_reg = !! 2419 table_reg |= 0x01 << (8 * reg_offset);
1869 MV_READ( !! 2420 mv_write(table + tbl_offset, table_reg);
1870 (MV64340_ETH !! 2421 }
1871 (eth_port_n <<
1872 <<
1873 unicast_reg |= (0x01 << (8 * <<
1874 <<
1875 MV_WRITE( <<
1876 (MV64340_ETH_DA_FILT <<
1877 (eth_port_num) + tb <<
1878 2422
1879 break; !! 2423 /*
>> 2424 * eth_port_mc_addr - Multicast address settings.
>> 2425 *
>> 2426 * The MV device supports multicast using two tables:
>> 2427 * 1) Special Multicast Table for MAC addresses of the form
>> 2428 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
>> 2429 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
>> 2430 * Table entries in the DA-Filter table.
>> 2431 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
>> 2432 * is used as an index to the Other Multicast Table entries in the
>> 2433 * DA-Filter table. This function calculates the CRC-8bit value.
>> 2434 * In either case, eth_port_set_filter_table_entry() is then called
>> 2435 * to set to set the actual table entry.
>> 2436 */
>> 2437 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
>> 2438 {
>> 2439 unsigned int mac_h;
>> 2440 unsigned int mac_l;
>> 2441 unsigned char crc_result = 0;
>> 2442 int table;
>> 2443 int mac_array[48];
>> 2444 int crc[8];
>> 2445 int i;
1880 2446
1881 default: !! 2447 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1882 return 0; !! 2448 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
>> 2449 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
>> 2450 (eth_port_num);
>> 2451 eth_port_set_filter_table_entry(table, p_addr[5]);
>> 2452 return;
>> 2453 }
>> 2454
>> 2455 /* Calculate CRC-8 out of the given address */
>> 2456 mac_h = (p_addr[0] << 8) | (p_addr[1]);
>> 2457 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
>> 2458 (p_addr[4] << 8) | (p_addr[5] << 0);
>> 2459
>> 2460 for (i = 0; i < 32; i++)
>> 2461 mac_array[i] = (mac_l >> i) & 0x1;
>> 2462 for (i = 32; i < 48; i++)
>> 2463 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
>> 2464
>> 2465 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
>> 2466 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
>> 2467 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
>> 2468 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
>> 2469 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
>> 2470
>> 2471 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
>> 2472 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
>> 2473 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
>> 2474 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
>> 2475 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
>> 2476 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
>> 2477 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
>> 2478
>> 2479 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
>> 2480 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
>> 2481 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
>> 2482 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
>> 2483 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
>> 2484 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
>> 2485
>> 2486 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
>> 2487 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
>> 2488 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
>> 2489 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
>> 2490 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
>> 2491 mac_array[3] ^ mac_array[2] ^ mac_array[1];
>> 2492
>> 2493 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
>> 2494 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
>> 2495 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
>> 2496 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
>> 2497 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
>> 2498 mac_array[3] ^ mac_array[2];
>> 2499
>> 2500 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
>> 2501 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
>> 2502 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
>> 2503 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
>> 2504 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
>> 2505 mac_array[4] ^ mac_array[3];
>> 2506
>> 2507 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
>> 2508 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
>> 2509 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
>> 2510 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
>> 2511 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
>> 2512 mac_array[4];
>> 2513
>> 2514 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
>> 2515 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
>> 2516 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
>> 2517 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
>> 2518 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
>> 2519
>> 2520 for (i = 0; i < 8; i++)
>> 2521 crc_result = crc_result | (crc[i] << i);
>> 2522
>> 2523 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
>> 2524 eth_port_set_filter_table_entry(table, crc_result);
>> 2525 }
>> 2526
>> 2527 /*
>> 2528 * Set the entire multicast list based on dev->mc_list.
>> 2529 */
>> 2530 static void eth_port_set_multicast_list(struct net_device *dev)
>> 2531 {
>> 2532
>> 2533 struct dev_mc_list *mc_list;
>> 2534 int i;
>> 2535 int table_index;
>> 2536 struct mv643xx_private *mp = netdev_priv(dev);
>> 2537 unsigned int eth_port_num = mp->port_num;
>> 2538
>> 2539 /* If the device is in promiscuous mode or in all multicast mode,
>> 2540 * we will fully populate both multicast tables with accept.
>> 2541 * This is guaranteed to yield a match on all multicast addresses...
>> 2542 */
>> 2543 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
>> 2544 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
>> 2545 /* Set all entries in DA filter special multicast
>> 2546 * table (Ex_dFSMT)
>> 2547 * Set for ETH_Q0 for now
>> 2548 * Bits
>> 2549 * 0 Accept=1, Drop=0
>> 2550 * 3-1 Queue ETH_Q0=0
>> 2551 * 7-4 Reserved = 0;
>> 2552 */
>> 2553 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
>> 2554
>> 2555 /* Set all entries in DA filter other multicast
>> 2556 * table (Ex_dFOMT)
>> 2557 * Set for ETH_Q0 for now
>> 2558 * Bits
>> 2559 * 0 Accept=1, Drop=0
>> 2560 * 3-1 Queue ETH_Q0=0
>> 2561 * 7-4 Reserved = 0;
>> 2562 */
>> 2563 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
>> 2564 }
>> 2565 return;
>> 2566 }
>> 2567
>> 2568 /* We will clear out multicast tables every time we get the list.
>> 2569 * Then add the entire new list...
>> 2570 */
>> 2571 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
>> 2572 /* Clear DA filter special multicast table (Ex_dFSMT) */
>> 2573 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
>> 2574 (eth_port_num) + table_index, 0);
>> 2575
>> 2576 /* Clear DA filter other multicast table (Ex_dFOMT) */
>> 2577 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
>> 2578 (eth_port_num) + table_index, 0);
1883 } 2579 }
1884 2580
1885 return 1; !! 2581 /* Get pointer to net_device multicast list and add each one... */
>> 2582 for (i = 0, mc_list = dev->mc_list;
>> 2583 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
>> 2584 i++, mc_list = mc_list->next)
>> 2585 if (mc_list->dmi_addrlen == 6)
>> 2586 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
1886 } 2587 }
1887 2588
1888 /* 2589 /*
1889 * eth_port_init_mac_tables - Clear all entra 2590 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1890 * 2591 *
1891 * DESCRIPTION: 2592 * DESCRIPTION:
1892 * Go through all the DA filter tables !! 2593 * Go through all the DA filter tables (Unicast, Special Multicast &
1893 * Other Multicast) and set each entry !! 2594 * Other Multicast) and set each entry to 0.
1894 * 2595 *
1895 * INPUT: 2596 * INPUT:
1896 * unsigned int eth_port_num Ethern !! 2597 * unsigned int eth_port_num Ethernet Port number.
1897 * 2598 *
1898 * OUTPUT: 2599 * OUTPUT:
1899 * Multicast and Unicast packets are re !! 2600 * Multicast and Unicast packets are rejected.
1900 * 2601 *
1901 * RETURN: 2602 * RETURN:
1902 * None. !! 2603 * None.
1903 */ 2604 */
1904 static void eth_port_init_mac_tables(unsigned 2605 static void eth_port_init_mac_tables(unsigned int eth_port_num)
1905 { 2606 {
1906 int table_index; 2607 int table_index;
1907 2608
1908 /* Clear DA filter unicast table (Ex_ 2609 /* Clear DA filter unicast table (Ex_dFUT) */
1909 for (table_index = 0; table_index <= 2610 for (table_index = 0; table_index <= 0xC; table_index += 4)
1910 MV_WRITE( !! 2611 mv_write(DA_FILTER_UNICAST_TABLE_BASE
1911 (MV64340_ETH_DA_FILT !! 2612 (eth_port_num) + table_index, 0);
1912 (eth_port_num) + ta <<
1913 2613
1914 for (table_index = 0; table_index <= 2614 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1915 /* Clear DA filter special mu 2615 /* Clear DA filter special multicast table (Ex_dFSMT) */
1916 MV_WRITE( !! 2616 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1917 (MV64340_ETH_DA_FILT !! 2617 (eth_port_num) + table_index, 0);
1918 (eth_port_num) + ta <<
1919 /* Clear DA filter other mult 2618 /* Clear DA filter other multicast table (Ex_dFOMT) */
1920 MV_WRITE((MV64340_ETH_DA_FILT !! 2619 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
1921 (eth_port_num) + ta !! 2620 (eth_port_num) + table_index, 0);
1922 } 2621 }
1923 } 2622 }
1924 2623
1925 /* 2624 /*
1926 * eth_clear_mib_counters - Clear all MIB cou 2625 * eth_clear_mib_counters - Clear all MIB counters
1927 * 2626 *
1928 * DESCRIPTION: 2627 * DESCRIPTION:
1929 * This function clears all MIB counter !! 2628 * This function clears all MIB counters of a specific ethernet port.
1930 * A read from the MIB counter will res !! 2629 * A read from the MIB counter will reset the counter.
1931 * 2630 *
1932 * INPUT: 2631 * INPUT:
1933 * unsigned int eth_port_num Ethern !! 2632 * unsigned int eth_port_num Ethernet Port number.
1934 * 2633 *
1935 * OUTPUT: 2634 * OUTPUT:
1936 * After reading all MIB counters, the !! 2635 * After reading all MIB counters, the counters resets.
1937 * 2636 *
1938 * RETURN: 2637 * RETURN:
1939 * MIB counter value. !! 2638 * MIB counter value.
1940 * 2639 *
1941 */ 2640 */
1942 static void eth_clear_mib_counters(unsigned i 2641 static void eth_clear_mib_counters(unsigned int eth_port_num)
1943 { 2642 {
1944 int i; 2643 int i;
1945 2644
1946 /* Perform dummy reads from MIB count 2645 /* Perform dummy reads from MIB counters */
1947 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED !! 2646 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
1948 MV_READ(MV64340_ETH_MIB_COUNT !! 2647 i += 4)
>> 2648 mv_read(MIB_COUNTERS_BASE(eth_port_num) + i);
1949 } 2649 }
1950 2650
>> 2651 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
>> 2652 {
>> 2653 return mv_read(MIB_COUNTERS_BASE(mp->port_num) + offset);
>> 2654 }
1951 2655
1952 /* !! 2656 static void eth_update_mib_counters(struct mv643xx_private *mp)
1953 * ethernet_phy_get - Get the ethernet port P <<
1954 * <<
1955 * DESCRIPTION: <<
1956 * This routine returns the given ether <<
1957 * <<
1958 * INPUT: <<
1959 * unsigned int eth_port_num <<
1960 * <<
1961 * OUTPUT: <<
1962 * None. <<
1963 * <<
1964 * RETURN: <<
1965 * PHY address. <<
1966 * <<
1967 */ <<
1968 static int ethernet_phy_get(unsigned int eth_ <<
1969 { 2657 {
1970 unsigned int reg_data; !! 2658 struct mv643xx_mib_counters *p = &mp->mib_counters;
>> 2659 int offset;
1971 2660
1972 reg_data = MV_READ(MV64340_ETH_PHY_AD !! 2661 p->good_octets_received +=
>> 2662 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
>> 2663 p->good_octets_received +=
>> 2664 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
1973 2665
1974 return ((reg_data >> (5 * eth_port_nu !! 2666 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
>> 2667 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
>> 2668 offset += 4)
>> 2669 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
>> 2670
>> 2671 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
>> 2672 p->good_octets_sent +=
>> 2673 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
>> 2674
>> 2675 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
>> 2676 offset <= ETH_MIB_LATE_COLLISION;
>> 2677 offset += 4)
>> 2678 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1975 } 2679 }
1976 2680
1977 /* 2681 /*
1978 * ethernet_phy_reset - Reset Ethernet port P !! 2682 * ethernet_phy_detect - Detect whether a phy is present
1979 * 2683 *
1980 * DESCRIPTION: 2684 * DESCRIPTION:
1981 * This routine utilize the SMI interfa !! 2685 * This function tests whether there is a PHY present on
1982 * The routine waits until the link is !! 2686 * the specified port.
1983 * 2687 *
1984 * INPUT: 2688 * INPUT:
1985 * unsigned int eth_port_num Etherne !! 2689 * unsigned int eth_port_num Ethernet Port number.
1986 * 2690 *
1987 * OUTPUT: 2691 * OUTPUT:
1988 * The ethernet port PHY renew its link !! 2692 * None
1989 * 2693 *
1990 * RETURN: 2694 * RETURN:
1991 * None. !! 2695 * 0 on success
>> 2696 * -ENODEV on failure
1992 * 2697 *
1993 */ 2698 */
1994 static int ethernet_phy_reset(unsigned int et !! 2699 static int ethernet_phy_detect(unsigned int port_num)
1995 { 2700 {
1996 unsigned int time_out = 50; !! 2701 unsigned int phy_reg_data0;
1997 unsigned int phy_reg_data; !! 2702 int auto_neg;
1998 <<
1999 /* Reset the PHY */ <<
2000 eth_port_read_smi_reg(eth_port_num, 0 <<
2001 phy_reg_data |= 0x8000; /* Set bit 15 <<
2002 eth_port_write_smi_reg(eth_port_num, <<
2003 2703
2004 /* Poll on the PHY LINK */ !! 2704 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2005 do { !! 2705 auto_neg = phy_reg_data0 & 0x1000;
2006 eth_port_read_smi_reg(eth_por !! 2706 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
>> 2707 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2007 2708
2008 if (time_out-- == 0) !! 2709 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2009 return 0; !! 2710 if ((phy_reg_data0 & 0x1000) == auto_neg)
2010 } while (!(phy_reg_data & 0x20)); !! 2711 return -ENODEV; /* change didn't take */
2011 2712
2012 return 1; !! 2713 phy_reg_data0 ^= 0x1000;
>> 2714 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
>> 2715 return 0;
2013 } 2716 }
2014 2717
2015 /* 2718 /*
2016 * eth_port_reset - Reset Ethernet port !! 2719 * ethernet_phy_get - Get the ethernet port PHY address.
2017 * 2720 *
2018 * DESCRIPTION: 2721 * DESCRIPTION:
2019 * This routine resets the chip by abort !! 2722 * This routine returns the given ethernet port PHY address.
2020 * clearing the MIB counters. The Receiv <<
2021 * idle state after this command is perf <<
2022 * 2723 *
2023 * INPUT: 2724 * INPUT:
2024 * unsigned int eth_port_num Etherne !! 2725 * unsigned int eth_port_num Ethernet Port number.
2025 * 2726 *
2026 * OUTPUT: 2727 * OUTPUT:
2027 * Channel activity is halted. !! 2728 * None.
2028 * 2729 *
2029 * RETURN: 2730 * RETURN:
2030 * None. !! 2731 * PHY address.
2031 * 2732 *
2032 */ 2733 */
2033 static void eth_port_reset(unsigned int eth_p !! 2734 static int ethernet_phy_get(unsigned int eth_port_num)
2034 { 2735 {
2035 unsigned int reg_data; 2736 unsigned int reg_data;
2036 2737
2037 /* Stop Tx port activity. Check port !! 2738 reg_data = mv_read(PHY_ADDR_REG);
2038 reg_data = <<
2039 MV_READ(MV64340_ETH_TRANSMIT_QUEU <<
2040 <<
2041 if (reg_data & 0xFF) { <<
2042 /* Issue stop command for act <<
2043 MV_WRITE(MV64340_ETH_TRANSMIT <<
2044 (eth_port_num), (reg <<
2045 <<
2046 /* Wait for all Tx activity t <<
2047 do { <<
2048 /* Check port cause r <<
2049 reg_data = <<
2050 MV_READ <<
2051 (MV64340_ETH_TRAN <<
2052 (eth_port_num)); <<
2053 } <<
2054 while (reg_data & 0xFF); <<
2055 } <<
2056 <<
2057 /* Stop Rx port activity. Check port <<
2058 reg_data = <<
2059 MV_READ(MV64340_ETH_RECEIVE_QUEUE <<
2060 (eth_port_num)); <<
2061 <<
2062 if (reg_data & 0xFF) { <<
2063 /* Issue stop command for act <<
2064 MV_WRITE(MV64340_ETH_RECEIVE_ <<
2065 (eth_port_num), (reg <<
2066 <<
2067 /* Wait for all Rx activity t <<
2068 do { <<
2069 /* Check port cause r <<
2070 reg_data = <<
2071 MV_READ <<
2072 (MV64340_ETH_RECE <<
2073 (eth_port_num)); <<
2074 } <<
2075 while (reg_data & 0xFF); <<
2076 } <<
2077 <<
2078 <<
2079 /* Clear all MIB counters */ <<
2080 eth_clear_mib_counters(eth_port_num); <<
2081 2739
2082 /* Reset the Enable bit in the Config !! 2740 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2083 reg_data = <<
2084 MV_READ(MV64340_ETH_PORT_SERIAL_C <<
2085 reg_data &= ~ETH_SERIAL_PORT_ENABLE; <<
2086 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONT <<
2087 <<
2088 return; <<
2089 } 2741 }
2090 2742
2091 /* 2743 /*
2092 * ethernet_set_config_reg - Set specified bi !! 2744 * ethernet_phy_set - Set the ethernet port PHY address.
2093 * 2745 *
2094 * DESCRIPTION: 2746 * DESCRIPTION:
2095 * This function sets specified bits in !! 2747 * This routine sets the given ethernet port PHY address.
2096 * configuration register. <<
2097 * 2748 *
2098 * INPUT: 2749 * INPUT:
2099 * unsigned int eth_port_num Etherne !! 2750 * unsigned int eth_port_num Ethernet Port number.
2100 * unsigned int value 32 bit value. !! 2751 * int phy_addr PHY address.
2101 * 2752 *
2102 * OUTPUT: 2753 * OUTPUT:
2103 * The set bits in the value parameter a !! 2754 * None.
2104 * register. <<
2105 * 2755 *
2106 * RETURN: 2756 * RETURN:
2107 * None. !! 2757 * None.
2108 * 2758 *
2109 */ 2759 */
2110 static void ethernet_set_config_reg(unsigned !! 2760 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2111 unsigned <<
2112 { 2761 {
2113 unsigned int eth_config_reg; !! 2762 u32 reg_data;
>> 2763 int addr_shift = 5 * eth_port_num;
2114 2764
2115 eth_config_reg = !! 2765 reg_data = mv_read(PHY_ADDR_REG);
2116 MV_READ(MV64340_ETH_PORT_CONFIG_R !! 2766 reg_data &= ~(0x1f << addr_shift);
2117 eth_config_reg |= value; !! 2767 reg_data |= (phy_addr & 0x1f) << addr_shift;
2118 MV_WRITE(MV64340_ETH_PORT_CONFIG_REG( !! 2768 mv_write(PHY_ADDR_REG, reg_data);
2119 eth_config_reg); <<
2120 } 2769 }
2121 2770
2122 /* 2771 /*
2123 * ethernet_get_config_reg - Get the port con !! 2772 * ethernet_phy_reset - Reset Ethernet port PHY.
2124 * 2773 *
2125 * DESCRIPTION: 2774 * DESCRIPTION:
2126 * This function returns the configurat !! 2775 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2127 * ethernet port. <<
2128 * 2776 *
2129 * INPUT: 2777 * INPUT:
2130 * unsigned int eth_port_num Etherne !! 2778 * unsigned int eth_port_num Ethernet Port number.
2131 * 2779 *
2132 * OUTPUT: 2780 * OUTPUT:
2133 * None. !! 2781 * The PHY is reset.
2134 * 2782 *
2135 * RETURN: 2783 * RETURN:
2136 * Port configuration register value. !! 2784 * None.
>> 2785 *
2137 */ 2786 */
2138 static unsigned int ethernet_get_config_reg(u !! 2787 static void ethernet_phy_reset(unsigned int eth_port_num)
2139 { 2788 {
2140 unsigned int eth_config_reg; !! 2789 unsigned int phy_reg_data;
>> 2790
>> 2791 /* Reset the PHY */
>> 2792 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
>> 2793 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
>> 2794 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2141 2795
2142 eth_config_reg = MV_READ(MV64340_ETH_ !! 2796 /* wait for PHY to come out of reset */
2143 (eth_po !! 2797 do {
2144 return eth_config_reg; !! 2798 udelay(1);
>> 2799 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
>> 2800 } while (phy_reg_data & 0x8000);
2145 } 2801 }
2146 2802
>> 2803 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
>> 2804 unsigned int queues)
>> 2805 {
>> 2806 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
>> 2807 }
2147 2808
2148 /* !! 2809 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2149 * eth_port_read_smi_reg - Read PHY registers !! 2810 unsigned int queues)
2150 * <<
2151 * DESCRIPTION: <<
2152 * This routine utilize the SMI interfa <<
2153 * order to perform PHY register read. <<
2154 * <<
2155 * INPUT: <<
2156 * unsigned int eth_port_num Etherne <<
2157 * unsigned int phy_reg PHY registe <<
2158 * unsigned int *value Register val <<
2159 * <<
2160 * OUTPUT: <<
2161 * Write the value of a specified PHY r <<
2162 * <<
2163 * RETURN: <<
2164 * false if the PHY is busy or read dat <<
2165 * true otherwise. <<
2166 * <<
2167 */ <<
2168 static int eth_port_read_smi_reg(unsigned int <<
2169 unsigned int phy_reg, unsigned int *v <<
2170 { 2811 {
2171 int phy_addr = ethernet_phy_get(eth_p !! 2812 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
2172 unsigned int time_out = PHY_BUSY_TIME !! 2813 }
2173 unsigned int reg_value; <<
2174 2814
2175 /* first check that it is not busy */ !! 2815 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2176 do { !! 2816 {
2177 reg_value = MV_READ(MV64340_E !! 2817 u32 queues;
2178 if (time_out-- == 0) <<
2179 return 0; <<
2180 } while (reg_value & ETH_SMI_BUSY); <<
2181 2818
2182 /* not busy */ !! 2819 /* Stop Tx port activity. Check port Tx activity. */
>> 2820 queues = mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
>> 2821 if (queues) {
>> 2822 /* Issue stop command for active queues only */
>> 2823 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
2183 2824
2184 MV_WRITE(MV64340_ETH_SMI_REG, !! 2825 /* Wait for all Tx activity to terminate. */
2185 (phy_addr << 16) | (phy_reg !! 2826 /* Check port cause register that all Tx queues are stopped */
>> 2827 while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
>> 2828 udelay(PHY_WAIT_MICRO_SECONDS);
2186 2829
2187 time_out = PHY_BUSY_TIMEOUT; /* in !! 2830 /* Wait for Tx FIFO to empty */
>> 2831 while (mv_read(PORT_STATUS_REG(port_num)) &
>> 2832 ETH_PORT_TX_FIFO_EMPTY)
>> 2833 udelay(PHY_WAIT_MICRO_SECONDS);
>> 2834 }
2188 2835
2189 do { !! 2836 return queues;
2190 reg_value = MV_READ(MV64340_E !! 2837 }
2191 if (time_out-- == 0) <<
2192 return 0; <<
2193 } while (reg_value & ETH_SMI_READ_VAL <<
2194 2838
2195 /* Wait for the data to update in the !! 2839 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2196 for (time_out = 0; time_out < PHY_BUS !! 2840 {
>> 2841 u32 queues;
2197 2842
2198 reg_value = MV_READ(MV64340_ETH_SMI_R !! 2843 /* Stop Rx port activity. Check port Rx activity. */
>> 2844 queues = mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
>> 2845 if (queues) {
>> 2846 /* Issue stop command for active queues only */
>> 2847 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
2199 2848
2200 *value = reg_value & 0xffff; !! 2849 /* Wait for all Rx activity to terminate. */
>> 2850 /* Check port cause register that all Rx queues are stopped */
>> 2851 while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
>> 2852 udelay(PHY_WAIT_MICRO_SECONDS);
>> 2853 }
2201 2854
2202 return 1; !! 2855 return queues;
2203 } 2856 }
2204 2857
2205 /* 2858 /*
2206 * eth_port_write_smi_reg - Write to PHY regi !! 2859 * eth_port_reset - Reset Ethernet port
2207 * 2860 *
2208 * DESCRIPTION: 2861 * DESCRIPTION:
2209 * This routine utilize the SMI interfa !! 2862 * This routine resets the chip by aborting any SDMA engine activity and
2210 * order to perform writes to PHY regis !! 2863 * clearing the MIB counters. The Receiver and the Transmit unit are in
>> 2864 * idle state after this command is performed and the port is disabled.
2211 * 2865 *
2212 * INPUT: 2866 * INPUT:
2213 * unsigned int eth_port_num Etherne !! 2867 * unsigned int eth_port_num Ethernet Port number.
2214 * unsigned int phy_reg PHY register <<
2215 * unsigned int value Register valu <<
2216 * 2868 *
2217 * OUTPUT: 2869 * OUTPUT:
2218 * Write the given value to the specifie !! 2870 * Channel activity is halted.
2219 * 2871 *
2220 * RETURN: 2872 * RETURN:
2221 * false if the PHY is busy. !! 2873 * None.
2222 * true otherwise. <<
2223 * 2874 *
2224 */ 2875 */
2225 static int eth_port_write_smi_reg(unsigned in !! 2876 static void eth_port_reset(unsigned int port_num)
2226 unsigned int phy_reg, unsigned int va <<
2227 { 2877 {
2228 unsigned int time_out = PHY_BUSY_TIME !! 2878 unsigned int reg_data;
2229 unsigned int reg_value; <<
2230 int phy_addr; <<
2231 <<
2232 phy_addr = ethernet_phy_get(eth_port_ <<
2233 2879
2234 /* first check that it is not busy */ !! 2880 mv643xx_eth_port_disable_tx(port_num);
2235 do { !! 2881 mv643xx_eth_port_disable_rx(port_num);
2236 reg_value = MV_READ(MV64340_E <<
2237 if (time_out-- == 0) <<
2238 return 0; <<
2239 } while (reg_value & ETH_SMI_BUSY); <<
2240 2882
2241 /* not busy */ !! 2883 /* Clear all MIB counters */
2242 MV_WRITE(MV64340_ETH_SMI_REG, (phy_ad !! 2884 eth_clear_mib_counters(port_num);
2243 ETH_SMI_OPCODE_WRITE | (valu <<
2244 2885
2245 return 1; !! 2886 /* Reset the Enable bit in the Configuration Register */
>> 2887 reg_data = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
>> 2888 reg_data &= ~(SERIAL_PORT_ENABLE |
>> 2889 DO_NOT_FORCE_LINK_FAIL |
>> 2890 FORCE_LINK_PASS);
>> 2891 mv_write(PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2246 } 2892 }
2247 2893
>> 2894
2248 /* 2895 /*
2249 * eth_port_send - Send an Ethernet packet !! 2896 * eth_port_read_smi_reg - Read PHY registers
2250 * 2897 *
2251 * DESCRIPTION: 2898 * DESCRIPTION:
2252 * This routine send a given packet desc !! 2899 * This routine utilize the SMI interface to interact with the PHY in
2253 * supports transmitting of a packet spa !! 2900 * order to perform PHY register read.
2254 * routine updates 'curr' and 'first' in <<
2255 * segment passed to the routine. In cas <<
2256 * the 'first' index is update. In any c <<
2257 * If the routine get into Tx resource e <<
2258 * 'first'. This way the function can ab <<
2259 * descriptors per packet. <<
2260 * 2901 *
2261 * INPUT: 2902 * INPUT:
2262 * struct mv64340_private *mp Ethern !! 2903 * unsigned int port_num Ethernet Port number.
2263 * struct pkt_info *p_pkt_info !! 2904 * unsigned int phy_reg PHY register address offset.
>> 2905 * unsigned int *value Register value buffer.
2264 * 2906 *
2265 * OUTPUT: 2907 * OUTPUT:
2266 * Tx ring 'curr' and 'first' indexes ar !! 2908 * Write the value of a specified PHY register into given buffer.
2267 * 2909 *
2268 * RETURN: 2910 * RETURN:
2269 * ETH_QUEUE_FULL in case of Tx resource !! 2911 * false if the PHY is busy or read data is not in valid state.
2270 * ETH_ERROR in case the routine can not !! 2912 * true otherwise.
2271 * ETH_QUEUE_LAST_RESOURCE if the routin <<
2272 * ETH_OK otherwise. <<
2273 * 2913 *
2274 */ 2914 */
2275 #ifdef MV64340_CHECKSUM_OFFLOAD_TX !! 2915 static void eth_port_read_smi_reg(unsigned int port_num,
2276 /* !! 2916 unsigned int phy_reg, unsigned int *value)
2277 * Modified to include the first descriptor p <<
2278 */ <<
2279 static ETH_FUNC_RET_STATUS eth_port_send(stru <<
2280 stru <<
2281 { 2917 {
2282 int tx_desc_curr, tx_desc_used, tx_fi !! 2918 int phy_addr = ethernet_phy_get(port_num);
2283 volatile struct eth_tx_desc *current_ !! 2919 unsigned long flags;
2284 volatile struct eth_tx_desc *first_de !! 2920 int i;
2285 u32 command_status, first_chip_ptr; <<
2286 <<
2287 /* Do not process Tx ring in case of <<
2288 if (mp->tx_resource_err) <<
2289 return ETH_QUEUE_FULL; <<
2290 <<
2291 /* Get the Tx Desc ring indexes */ <<
2292 tx_desc_curr = mp->tx_curr_desc_q; <<
2293 tx_desc_used = mp->tx_used_desc_q; <<
2294 <<
2295 current_descriptor = &mp->p_tx_desc_a <<
2296 if (current_descriptor == NULL) <<
2297 return ETH_ERROR; <<
2298 <<
2299 tx_next_desc = (tx_desc_curr + 1) % M <<
2300 command_status = p_pkt_info->cmd_sts <<
2301 <<
2302 if (command_status & ETH_TX_FIRST_DES <<
2303 tx_first_desc = tx_desc_curr; <<
2304 mp->tx_first_desc_q = tx_firs <<
2305 <<
2306 /* fill first descriptor */ <<
2307 first_descriptor = &mp->p_tx_ <<
2308 first_descriptor->l4i_chk = p <<
2309 first_descriptor->cmd_sts = c <<
2310 first_descriptor->byte_cnt = <<
2311 first_descriptor->buf_ptr = p <<
2312 first_descriptor->next_desc_p <<
2313 tx_next_desc * sizeof <<
2314 wmb(); <<
2315 } else { <<
2316 tx_first_desc = mp->tx_first_ <<
2317 first_descriptor = &mp->p_tx_ <<
2318 if (first_descriptor == NULL) <<
2319 printk("First desc is <<
2320 return ETH_ERROR; <<
2321 } <<
2322 if (command_status & ETH_TX_L <<
2323 current_descriptor->n <<
2324 else { <<
2325 command_status |= ETH <<
2326 current_descriptor->n <<
2327 tx_next_desc <<
2328 } <<
2329 } <<
2330 <<
2331 if (p_pkt_info->byte_cnt < 8) { <<
2332 printk(" < 8 problem \n"); <<
2333 return ETH_ERROR; <<
2334 } <<
2335 <<
2336 current_descriptor->buf_ptr = p_pkt_i <<
2337 current_descriptor->byte_cnt = p_pkt_ <<
2338 current_descriptor->l4i_chk = p_pkt_i <<
2339 current_descriptor->cmd_sts = command <<
2340 <<
2341 mp->tx_skb[tx_desc_curr] = (struct sk <<
2342 <<
2343 wmb(); <<
2344 <<
2345 /* Set last desc with DMA ownership a <<
2346 if (command_status & ETH_TX_LAST_DESC <<
2347 current_descriptor->cmd_sts = <<
2348 ETH_T <<
2349 ETH_B <<
2350 <<
2351 if (!(command_status & ETH_TX <<
2352 first_descriptor->cmd <<
2353 wmb(); <<
2354 <<
2355 first_chip_ptr = MV_READ(MV64 <<
2356 <<
2357 /* Apply send command */ <<
2358 if (first_chip_ptr == 0x00000 <<
2359 MV_WRITE(MV64340_ETH_ <<
2360 2921
2361 ETH_ENABLE_TX_QUEUE(mp->port_ !! 2922 /* the SMI register is a shared resource */
>> 2923 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2362 2924
2363 /* !! 2925 /* wait for the SMI register to become available */
2364 * Finish Tx packet. Update f !! 2926 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
2365 * error */ !! 2927 if (i == PHY_WAIT_ITERATIONS) {
2366 tx_first_desc = tx_next_desc; !! 2928 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2367 mp->tx_first_desc_q = tx_firs !! 2929 goto out;
2368 } else { <<
2369 if (! (command_status & ETH_T <<
2370 current_descriptor->c <<
2371 wmb(); <<
2372 } 2930 }
>> 2931 udelay(PHY_WAIT_MICRO_SECONDS);
2373 } 2932 }
2374 2933
2375 /* Check for ring index overlap in th !! 2934 mv_write(SMI_REG,
2376 if (tx_next_desc == tx_desc_used) { !! 2935 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2377 mp->tx_resource_err = 1; <<
2378 mp->tx_curr_desc_q = tx_first <<
2379 <<
2380 return ETH_QUEUE_LAST_RESOURC <<
2381 } <<
2382 <<
2383 mp->tx_curr_desc_q = tx_next_desc; <<
2384 wmb(); <<
2385 <<
2386 return ETH_OK; <<
2387 } <<
2388 #else <<
2389 static ETH_FUNC_RET_STATUS eth_port_send(stru <<
2390 stru <<
2391 { <<
2392 int tx_desc_curr; <<
2393 int tx_desc_used; <<
2394 volatile struct eth_tx_desc* current_ <<
2395 unsigned int command_status; <<
2396 <<
2397 /* Do not process Tx ring in case of <<
2398 if (mp->tx_resource_err) <<
2399 return ETH_QUEUE_FULL; <<
2400 <<
2401 /* Get the Tx Desc ring indexes */ <<
2402 tx_desc_curr = mp->tx_curr_desc_q; <<
2403 tx_desc_used = mp->tx_used_desc_q; <<
2404 current_descriptor = &mp->p_tx_desc_a <<
2405 <<
2406 if (current_descriptor == NULL) <<
2407 return ETH_ERROR; <<
2408 <<
2409 command_status = p_pkt_info->cmd_sts <<
2410 <<
2411 /* XXX Is this for real ?!?!? */ <<
2412 /* Buffers with a payload smaller tha <<
2413 * 64-bit boundary. We use the memory <<
2414 * This memory is located in TX_BUF_O <<
2415 * Tx descriptor. */ <<
2416 if (p_pkt_info->byte_cnt <= 8) { <<
2417 printk(KERN_ERR <<
2418 "You have failed in th <<
2419 return ETH_ERROR; <<
2420 } <<
2421 current_descriptor->buf_ptr = p_pkt_i <<
2422 current_descriptor->byte_cnt = p_pkt_ <<
2423 mp->tx_skb[tx_desc_curr] = (struct sk <<
2424 <<
2425 mb(); <<
2426 2936
2427 /* Set last desc with DMA ownership a !! 2937 /* now wait for the data to be valid */
2428 current_descriptor->cmd_sts = command !! 2938 for (i = 0; !(mv_read(SMI_REG) & ETH_SMI_READ_VALID); i++) {
2429 ETH_BUFFER_OWNED_BY_D !! 2939 if (i == PHY_WAIT_ITERATIONS) {
2430 !! 2940 printk("mv643xx PHY read timeout, port %d\n", port_num);
2431 /* Apply send command */ !! 2941 goto out;
2432 ETH_ENABLE_TX_QUEUE(mp->port_num); !! 2942 }
2433 !! 2943 udelay(PHY_WAIT_MICRO_SECONDS);
2434 /* Finish Tx packet. Update first des <<
2435 tx_desc_curr = (tx_desc_curr + 1) % M <<
2436 <<
2437 /* Update the current descriptor */ <<
2438 mp->tx_curr_desc_q = tx_desc_curr; <<
2439 <<
2440 /* Check for ring index overlap in th <<
2441 if (tx_desc_curr == tx_desc_used) { <<
2442 mp->tx_resource_err = 1; <<
2443 return ETH_QUEUE_LAST_RESOURC <<
2444 } 2944 }
2445 2945
2446 return ETH_OK; !! 2946 *value = mv_read(SMI_REG) & 0xffff;
>> 2947 out:
>> 2948 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2447 } 2949 }
2448 #endif <<
2449 2950
2450 /* 2951 /*
2451 * eth_tx_return_desc - Free all used Tx desc !! 2952 * eth_port_write_smi_reg - Write to PHY registers
2452 * 2953 *
2453 * DESCRIPTION: 2954 * DESCRIPTION:
2454 * This routine returns the transmitted !! 2955 * This routine utilize the SMI interface to interact with the PHY in
2455 * It uses the 'first' index to support !! 2956 * order to perform writes to PHY registers.
2456 * of a packet spanned over multiple buf <<
2457 * In case the Tx queue was in "resource <<
2458 * no available Tx resources, the functi <<
2459 * 2957 *
2460 * INPUT: 2958 * INPUT:
2461 * struct mv64340_private *mp Ethern !! 2959 * unsigned int eth_port_num Ethernet Port number.
2462 * struct pkt_info *p_pkt_info !! 2960 * unsigned int phy_reg PHY register address offset.
>> 2961 * unsigned int value Register value.
2463 * 2962 *
2464 * OUTPUT: 2963 * OUTPUT:
2465 * Tx ring 'first' and 'used' indexes ar !! 2964 * Write the given value to the specified PHY register.
2466 * 2965 *
2467 * RETURN: 2966 * RETURN:
2468 * ETH_ERROR in case the routine can not !! 2967 * false if the PHY is busy.
2469 * ETH_RETRY in case there is transmissi !! 2968 * true otherwise.
2470 * ETH_END_OF_JOB if the routine has not <<
2471 * ETH_OK otherwise. <<
2472 * 2969 *
2473 */ 2970 */
2474 static ETH_FUNC_RET_STATUS eth_tx_return_desc !! 2971 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2475 !! 2972 unsigned int phy_reg, unsigned int value)
2476 { 2973 {
2477 int tx_desc_used, tx_desc_curr; !! 2974 int phy_addr;
2478 #ifdef MV64340_CHECKSUM_OFFLOAD_TX !! 2975 int i;
2479 int tx_first_desc; !! 2976 unsigned long flags;
2480 #endif <<
2481 volatile struct eth_tx_desc *p_tx_des <<
2482 unsigned int command_status; <<
2483 2977
2484 /* Get the Tx Desc ring indexes */ !! 2978 phy_addr = ethernet_phy_get(eth_port_num);
2485 tx_desc_curr = mp->tx_curr_desc_q; <<
2486 tx_desc_used = mp->tx_used_desc_q; <<
2487 #ifdef MV64340_CHECKSUM_OFFLOAD_TX <<
2488 tx_first_desc = mp->tx_first_desc_q; <<
2489 #endif <<
2490 p_tx_desc_used = &mp->p_tx_desc_area[ <<
2491 <<
2492 /* XXX Sanity check */ <<
2493 if (p_tx_desc_used == NULL) <<
2494 return ETH_ERROR; <<
2495 <<
2496 command_status = p_tx_desc_used->cmd_ <<
2497 <<
2498 /* Still transmitting... */ <<
2499 #ifndef MV64340_CHECKSUM_OFFLOAD_TX <<
2500 if (command_status & (ETH_BUFFER_OWNE <<
2501 return ETH_RETRY; <<
2502 #endif <<
2503 /* Stop release. About to overlap the <<
2504 #ifdef MV64340_CHECKSUM_OFFLOAD_TX <<
2505 if (tx_desc_used == tx_first_desc && <<
2506 return ETH_END_OF_JOB; <<
2507 #else <<
2508 if (tx_desc_used == tx_desc_curr && ! <<
2509 return ETH_END_OF_JOB; <<
2510 #endif <<
2511 2979
2512 /* Pass the packet information to the !! 2980 /* the SMI register is a shared resource */
2513 p_pkt_info->cmd_sts = command_status; !! 29