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1 /********************************************* 1 /*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation. !! 4 Copyright(c) 2007 Intel Corporation.
5 5
6 This program is free software; you can redis 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU Ge 7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software 8 version 2, as published by the Free Software Foundation.
9 9
10 This program is distributed in the hope it w 10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warra 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the G 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details. 13 more details.
14 14
15 You should have received a copy of the GNU G 15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Soft 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 021 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 18
19 The full GNU General Public License is inclu 19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING". 20 the file called "COPYING".
21 21
22 Contact Information: 22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists. 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Park 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 25
26 ********************************************** 26 *******************************************************************************/
27 27
28 #include <linux/if_ether.h> 28 #include <linux/if_ether.h>
29 #include <linux/delay.h> 29 #include <linux/delay.h>
30 30
31 #include "e1000_mac.h" 31 #include "e1000_mac.h"
32 #include "e1000_phy.h" 32 #include "e1000_phy.h"
33 33
>> 34 static s32 igb_get_phy_cfg_done(struct e1000_hw *hw);
>> 35 static void igb_release_phy(struct e1000_hw *hw);
>> 36 static s32 igb_acquire_phy(struct e1000_hw *hw);
>> 37 static s32 igb_phy_reset_dsp(struct e1000_hw *hw);
34 static s32 igb_phy_setup_autoneg(struct e1000 38 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35 static void igb_phy_force_speed_duplex_setup(s 39 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
36 40 u16 *phy_ctrl);
37 static s32 igb_wait_autoneg(struct e1000_hw * 41 static s32 igb_wait_autoneg(struct e1000_hw *hw);
38 42
39 /* Cable length tables */ 43 /* Cable length tables */
40 static const u16 e1000_m88_cable_length_table[ 44 static const u16 e1000_m88_cable_length_table[] =
41 { 0, 50, 80, 110, 140, 140, E1000_CABL 45 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
>> 46 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
>> 47 (sizeof(e1000_m88_cable_length_table) / \
>> 48 sizeof(e1000_m88_cable_length_table[0]))
42 49
43 static const u16 e1000_igp_2_cable_length_tabl 50 static const u16 e1000_igp_2_cable_length_table[] =
44 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
45 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 2 52 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
46 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 4 53 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
47 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 54 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
48 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 55 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
49 60, 66, 72, 77, 82, 87, 92, 96, 100, 104 56 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
50 83, 89, 95, 100, 105, 109, 113, 116, 119 57 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
51 104, 109, 114, 118, 121, 124}; 58 104, 109, 114, 118, 121, 124};
52 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
53 (sizeof(e1000_igp_2_cable_leng 60 (sizeof(e1000_igp_2_cable_length_table) / \
54 sizeof(e1000_igp_2_cable_leng 61 sizeof(e1000_igp_2_cable_length_table[0]))
55 62
56 /** 63 /**
57 * igb_check_reset_block - Check if PHY reset !! 64 * e1000_check_reset_block - Check if PHY reset is blocked
58 * @hw: pointer to the HW structure 65 * @hw: pointer to the HW structure
59 * 66 *
60 * Read the PHY management control register a 67 * Read the PHY management control register and check whether a PHY reset
61 * is blocked. If a reset is not blocked ret 68 * is blocked. If a reset is not blocked return 0, otherwise
62 * return E1000_BLK_PHY_RESET (12). 69 * return E1000_BLK_PHY_RESET (12).
63 **/ 70 **/
64 s32 igb_check_reset_block(struct e1000_hw *hw) 71 s32 igb_check_reset_block(struct e1000_hw *hw)
65 { 72 {
66 u32 manc; 73 u32 manc;
67 74
68 manc = rd32(E1000_MANC); 75 manc = rd32(E1000_MANC);
69 76
70 return (manc & E1000_MANC_BLK_PHY_RST_ 77 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
71 E1000_BLK_PHY_RESET : 0; 78 E1000_BLK_PHY_RESET : 0;
72 } 79 }
73 80
74 /** 81 /**
75 * igb_get_phy_id - Retrieve the PHY ID and r !! 82 * e1000_get_phy_id - Retrieve the PHY ID and revision
76 * @hw: pointer to the HW structure 83 * @hw: pointer to the HW structure
77 * 84 *
78 * Reads the PHY registers and stores the PHY 85 * Reads the PHY registers and stores the PHY ID and possibly the PHY
79 * revision in the hardware structure. 86 * revision in the hardware structure.
80 **/ 87 **/
81 s32 igb_get_phy_id(struct e1000_hw *hw) 88 s32 igb_get_phy_id(struct e1000_hw *hw)
82 { 89 {
83 struct e1000_phy_info *phy = &hw->phy; 90 struct e1000_phy_info *phy = &hw->phy;
84 s32 ret_val = 0; 91 s32 ret_val = 0;
85 u16 phy_id; 92 u16 phy_id;
86 93
87 ret_val = phy->ops.read_reg(hw, PHY_ID !! 94 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID1, &phy_id);
88 if (ret_val) 95 if (ret_val)
89 goto out; 96 goto out;
90 97
91 phy->id = (u32)(phy_id << 16); 98 phy->id = (u32)(phy_id << 16);
92 udelay(20); 99 udelay(20);
93 ret_val = phy->ops.read_reg(hw, PHY_ID !! 100 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID2, &phy_id);
94 if (ret_val) 101 if (ret_val)
95 goto out; 102 goto out;
96 103
97 phy->id |= (u32)(phy_id & PHY_REVISION 104 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
98 phy->revision = (u32)(phy_id & ~PHY_RE 105 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
99 106
100 out: 107 out:
101 return ret_val; 108 return ret_val;
102 } 109 }
103 110
104 /** 111 /**
105 * igb_phy_reset_dsp - Reset PHY DSP !! 112 * e1000_phy_reset_dsp - Reset PHY DSP
106 * @hw: pointer to the HW structure 113 * @hw: pointer to the HW structure
107 * 114 *
108 * Reset the digital signal processor. 115 * Reset the digital signal processor.
109 **/ 116 **/
110 static s32 igb_phy_reset_dsp(struct e1000_hw * 117 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
111 { 118 {
112 s32 ret_val; 119 s32 ret_val;
113 120
114 ret_val = hw->phy.ops.write_reg(hw, M8 !! 121 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
115 if (ret_val) 122 if (ret_val)
116 goto out; 123 goto out;
117 124
118 ret_val = hw->phy.ops.write_reg(hw, M8 !! 125 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
119 126
120 out: 127 out:
121 return ret_val; 128 return ret_val;
122 } 129 }
123 130
124 /** 131 /**
125 * igb_read_phy_reg_mdic - Read MDI control r !! 132 * e1000_read_phy_reg_mdic - Read MDI control register
126 * @hw: pointer to the HW structure 133 * @hw: pointer to the HW structure
127 * @offset: register offset to be read 134 * @offset: register offset to be read
128 * @data: pointer to the read data 135 * @data: pointer to the read data
129 * 136 *
130 * Reads the MDI control regsiter in the PHY 137 * Reads the MDI control regsiter in the PHY at offset and stores the
131 * information read to data. 138 * information read to data.
132 **/ 139 **/
133 static s32 igb_read_phy_reg_mdic(struct e1000_ 140 static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
134 { 141 {
135 struct e1000_phy_info *phy = &hw->phy; 142 struct e1000_phy_info *phy = &hw->phy;
136 u32 i, mdic = 0; 143 u32 i, mdic = 0;
137 s32 ret_val = 0; 144 s32 ret_val = 0;
138 145
139 if (offset > MAX_PHY_REG_ADDRESS) { 146 if (offset > MAX_PHY_REG_ADDRESS) {
140 hw_dbg("PHY Address %d is out !! 147 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
141 ret_val = -E1000_ERR_PARAM; 148 ret_val = -E1000_ERR_PARAM;
142 goto out; 149 goto out;
143 } 150 }
144 151
145 /* 152 /*
146 * Set up Op-code, Phy Address, and re 153 * Set up Op-code, Phy Address, and register offset in the MDI
147 * Control register. The MAC will tak 154 * Control register. The MAC will take care of interfacing with the
148 * PHY to retrieve the desired data. 155 * PHY to retrieve the desired data.
149 */ 156 */
150 mdic = ((offset << E1000_MDIC_REG_SHIF 157 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
151 (phy->addr << E1000_MDIC_PHY_S 158 (phy->addr << E1000_MDIC_PHY_SHIFT) |
152 (E1000_MDIC_OP_READ)); 159 (E1000_MDIC_OP_READ));
153 160
154 wr32(E1000_MDIC, mdic); 161 wr32(E1000_MDIC, mdic);
155 162
156 /* 163 /*
157 * Poll the ready bit to see if the MD 164 * Poll the ready bit to see if the MDI read completed
158 * Increasing the time out as testing 165 * Increasing the time out as testing showed failures with
159 * the lower time out 166 * the lower time out
160 */ 167 */
161 for (i = 0; i < (E1000_GEN_POLL_TIMEOU 168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
162 udelay(50); 169 udelay(50);
163 mdic = rd32(E1000_MDIC); 170 mdic = rd32(E1000_MDIC);
164 if (mdic & E1000_MDIC_READY) 171 if (mdic & E1000_MDIC_READY)
165 break; 172 break;
166 } 173 }
167 if (!(mdic & E1000_MDIC_READY)) { 174 if (!(mdic & E1000_MDIC_READY)) {
168 hw_dbg("MDI Read did not compl !! 175 hw_dbg(hw, "MDI Read did not complete\n");
169 ret_val = -E1000_ERR_PHY; 176 ret_val = -E1000_ERR_PHY;
170 goto out; 177 goto out;
171 } 178 }
172 if (mdic & E1000_MDIC_ERROR) { 179 if (mdic & E1000_MDIC_ERROR) {
173 hw_dbg("MDI Error\n"); !! 180 hw_dbg(hw, "MDI Error\n");
174 ret_val = -E1000_ERR_PHY; 181 ret_val = -E1000_ERR_PHY;
175 goto out; 182 goto out;
176 } 183 }
177 *data = (u16) mdic; 184 *data = (u16) mdic;
178 185
179 out: 186 out:
180 return ret_val; 187 return ret_val;
181 } 188 }
182 189
183 /** 190 /**
184 * igb_write_phy_reg_mdic - Write MDI control !! 191 * e1000_write_phy_reg_mdic - Write MDI control register
185 * @hw: pointer to the HW structure 192 * @hw: pointer to the HW structure
186 * @offset: register offset to write to 193 * @offset: register offset to write to
187 * @data: data to write to register at offset 194 * @data: data to write to register at offset
188 * 195 *
189 * Writes data to MDI control register in the 196 * Writes data to MDI control register in the PHY at offset.
190 **/ 197 **/
191 static s32 igb_write_phy_reg_mdic(struct e1000 198 static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
192 { 199 {
193 struct e1000_phy_info *phy = &hw->phy; 200 struct e1000_phy_info *phy = &hw->phy;
194 u32 i, mdic = 0; 201 u32 i, mdic = 0;
195 s32 ret_val = 0; 202 s32 ret_val = 0;
196 203
197 if (offset > MAX_PHY_REG_ADDRESS) { 204 if (offset > MAX_PHY_REG_ADDRESS) {
198 hw_dbg("PHY Address %d is out !! 205 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
199 ret_val = -E1000_ERR_PARAM; 206 ret_val = -E1000_ERR_PARAM;
200 goto out; 207 goto out;
201 } 208 }
202 209
203 /* 210 /*
204 * Set up Op-code, Phy Address, and re 211 * Set up Op-code, Phy Address, and register offset in the MDI
205 * Control register. The MAC will tak 212 * Control register. The MAC will take care of interfacing with the
206 * PHY to retrieve the desired data. 213 * PHY to retrieve the desired data.
207 */ 214 */
208 mdic = (((u32)data) | 215 mdic = (((u32)data) |
209 (offset << E1000_MDIC_REG_SHIF 216 (offset << E1000_MDIC_REG_SHIFT) |
210 (phy->addr << E1000_MDIC_PHY_S 217 (phy->addr << E1000_MDIC_PHY_SHIFT) |
211 (E1000_MDIC_OP_WRITE)); 218 (E1000_MDIC_OP_WRITE));
212 219
213 wr32(E1000_MDIC, mdic); 220 wr32(E1000_MDIC, mdic);
214 221
215 /* 222 /*
216 * Poll the ready bit to see if the MD 223 * Poll the ready bit to see if the MDI read completed
217 * Increasing the time out as testing 224 * Increasing the time out as testing showed failures with
218 * the lower time out 225 * the lower time out
219 */ 226 */
220 for (i = 0; i < (E1000_GEN_POLL_TIMEOU 227 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
221 udelay(50); 228 udelay(50);
222 mdic = rd32(E1000_MDIC); 229 mdic = rd32(E1000_MDIC);
223 if (mdic & E1000_MDIC_READY) 230 if (mdic & E1000_MDIC_READY)
224 break; 231 break;
225 } 232 }
226 if (!(mdic & E1000_MDIC_READY)) { 233 if (!(mdic & E1000_MDIC_READY)) {
227 hw_dbg("MDI Write did not comp !! 234 hw_dbg(hw, "MDI Write did not complete\n");
228 ret_val = -E1000_ERR_PHY; 235 ret_val = -E1000_ERR_PHY;
229 goto out; 236 goto out;
230 } 237 }
231 if (mdic & E1000_MDIC_ERROR) { 238 if (mdic & E1000_MDIC_ERROR) {
232 hw_dbg("MDI Error\n"); !! 239 hw_dbg(hw, "MDI Error\n");
233 ret_val = -E1000_ERR_PHY; 240 ret_val = -E1000_ERR_PHY;
234 goto out; 241 goto out;
235 } 242 }
236 243
237 out: 244 out:
238 return ret_val; 245 return ret_val;
239 } 246 }
240 247
241 /** 248 /**
242 * igb_read_phy_reg_igp - Read igp PHY regist !! 249 * e1000_read_phy_reg_igp - Read igp PHY register
243 * @hw: pointer to the HW structure 250 * @hw: pointer to the HW structure
244 * @offset: register offset to be read 251 * @offset: register offset to be read
245 * @data: pointer to the read data 252 * @data: pointer to the read data
246 * 253 *
247 * Acquires semaphore, if necessary, then rea 254 * Acquires semaphore, if necessary, then reads the PHY register at offset
248 * and storing the retrieved information in d 255 * and storing the retrieved information in data. Release any acquired
249 * semaphores before exiting. 256 * semaphores before exiting.
250 **/ 257 **/
251 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, 258 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
252 { 259 {
253 s32 ret_val = 0; !! 260 s32 ret_val;
254 <<
255 if (!(hw->phy.ops.acquire)) <<
256 goto out; <<
257 261
258 ret_val = hw->phy.ops.acquire(hw); !! 262 ret_val = igb_acquire_phy(hw);
259 if (ret_val) 263 if (ret_val)
260 goto out; 264 goto out;
261 265
262 if (offset > MAX_PHY_MULTI_PAGE_REG) { 266 if (offset > MAX_PHY_MULTI_PAGE_REG) {
263 ret_val = igb_write_phy_reg_md 267 ret_val = igb_write_phy_reg_mdic(hw,
264 268 IGP01E1000_PHY_PAGE_SELECT,
265 269 (u16)offset);
266 if (ret_val) { 270 if (ret_val) {
267 hw->phy.ops.release(hw !! 271 igb_release_phy(hw);
268 goto out; 272 goto out;
269 } 273 }
270 } 274 }
271 275
272 ret_val = igb_read_phy_reg_mdic(hw, MA !! 276 ret_val = igb_read_phy_reg_mdic(hw,
273 data); !! 277 MAX_PHY_REG_ADDRESS & offset,
>> 278 data);
274 279
275 hw->phy.ops.release(hw); !! 280 igb_release_phy(hw);
276 281
277 out: 282 out:
278 return ret_val; 283 return ret_val;
279 } 284 }
280 285
281 /** 286 /**
282 * igb_write_phy_reg_igp - Write igp PHY regi !! 287 * e1000_write_phy_reg_igp - Write igp PHY register
283 * @hw: pointer to the HW structure 288 * @hw: pointer to the HW structure
284 * @offset: register offset to write to 289 * @offset: register offset to write to
285 * @data: data to write at register offset 290 * @data: data to write at register offset
286 * 291 *
287 * Acquires semaphore, if necessary, then wri 292 * Acquires semaphore, if necessary, then writes the data to PHY register
288 * at the offset. Release any acquired semap 293 * at the offset. Release any acquired semaphores before exiting.
289 **/ 294 **/
290 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, 295 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
291 { 296 {
292 s32 ret_val = 0; !! 297 s32 ret_val;
293 <<
294 if (!(hw->phy.ops.acquire)) <<
295 goto out; <<
296 298
297 ret_val = hw->phy.ops.acquire(hw); !! 299 ret_val = igb_acquire_phy(hw);
298 if (ret_val) 300 if (ret_val)
299 goto out; 301 goto out;
300 302
301 if (offset > MAX_PHY_MULTI_PAGE_REG) { 303 if (offset > MAX_PHY_MULTI_PAGE_REG) {
302 ret_val = igb_write_phy_reg_md 304 ret_val = igb_write_phy_reg_mdic(hw,
303 305 IGP01E1000_PHY_PAGE_SELECT,
304 306 (u16)offset);
305 if (ret_val) { 307 if (ret_val) {
306 hw->phy.ops.release(hw !! 308 igb_release_phy(hw);
307 goto out; 309 goto out;
308 } 310 }
309 } 311 }
310 312
311 ret_val = igb_write_phy_reg_mdic(hw, M !! 313 ret_val = igb_write_phy_reg_mdic(hw,
>> 314 MAX_PHY_REG_ADDRESS & offset,
312 dat 315 data);
313 316
314 hw->phy.ops.release(hw); !! 317 igb_release_phy(hw);
315 318
316 out: 319 out:
317 return ret_val; 320 return ret_val;
318 } 321 }
319 322
320 /** 323 /**
321 * igb_copper_link_setup_m88 - Setup m88 PHY' !! 324 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
322 * @hw: pointer to the HW structure 325 * @hw: pointer to the HW structure
323 * 326 *
324 * Sets up MDI/MDI-X and polarity for m88 PHY 327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
325 * and downshift values are set also. 328 * and downshift values are set also.
326 **/ 329 **/
327 s32 igb_copper_link_setup_m88(struct e1000_hw 330 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
328 { 331 {
329 struct e1000_phy_info *phy = &hw->phy; 332 struct e1000_phy_info *phy = &hw->phy;
330 s32 ret_val; 333 s32 ret_val;
331 u16 phy_data; 334 u16 phy_data;
332 335
333 if (phy->reset_disable) { 336 if (phy->reset_disable) {
334 ret_val = 0; 337 ret_val = 0;
335 goto out; 338 goto out;
336 } 339 }
337 340
338 /* Enable CRS on TX. This must be set 341 /* Enable CRS on TX. This must be set for half-duplex operation. */
339 ret_val = phy->ops.read_reg(hw, M88E10 !! 342 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 343 &phy_data);
340 if (ret_val) 344 if (ret_val)
341 goto out; 345 goto out;
342 346
343 phy_data |= M88E1000_PSCR_ASSERT_CRS_O 347 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
344 348
345 /* 349 /*
346 * Options: 350 * Options:
347 * MDI/MDI-X = 0 (default) 351 * MDI/MDI-X = 0 (default)
348 * 0 - Auto for all speeds 352 * 0 - Auto for all speeds
349 * 1 - MDI mode 353 * 1 - MDI mode
350 * 2 - MDI-X mode 354 * 2 - MDI-X mode
351 * 3 - Auto for 1000Base-T only (MDI 355 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
352 */ 356 */
353 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE 357 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
354 358
355 switch (phy->mdix) { 359 switch (phy->mdix) {
356 case 1: 360 case 1:
357 phy_data |= M88E1000_PSCR_MDI_ 361 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
358 break; 362 break;
359 case 2: 363 case 2:
360 phy_data |= M88E1000_PSCR_MDIX 364 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
361 break; 365 break;
362 case 3: 366 case 3:
363 phy_data |= M88E1000_PSCR_AUTO 367 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
364 break; 368 break;
365 case 0: 369 case 0:
366 default: 370 default:
367 phy_data |= M88E1000_PSCR_AUTO 371 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
368 break; 372 break;
369 } 373 }
370 374
371 /* 375 /*
372 * Options: 376 * Options:
373 * disable_polarity_correction = 0 ( 377 * disable_polarity_correction = 0 (default)
374 * Automatic Correction for Reve 378 * Automatic Correction for Reversed Cable Polarity
375 * 0 - Disabled 379 * 0 - Disabled
376 * 1 - Enabled 380 * 1 - Enabled
377 */ 381 */
378 phy_data &= ~M88E1000_PSCR_POLARITY_RE 382 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
379 if (phy->disable_polarity_correction = 383 if (phy->disable_polarity_correction == 1)
380 phy_data |= M88E1000_PSCR_POLA 384 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
381 385
382 ret_val = phy->ops.write_reg(hw, M88E1 !! 386 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 387 phy_data);
383 if (ret_val) 388 if (ret_val)
384 goto out; 389 goto out;
385 390
386 if (phy->revision < E1000_REVISION_4) 391 if (phy->revision < E1000_REVISION_4) {
387 /* 392 /*
388 * Force TX_CLK in the Extende 393 * Force TX_CLK in the Extended PHY Specific Control Register
389 * to 25MHz clock. 394 * to 25MHz clock.
390 */ 395 */
391 ret_val = phy->ops.read_reg(hw !! 396 ret_val = hw->phy.ops.read_phy_reg(hw,
>> 397 M88E1000_EXT_PHY_SPEC_CTRL,
392 & 398 &phy_data);
393 if (ret_val) 399 if (ret_val)
394 goto out; 400 goto out;
395 401
396 phy_data |= M88E1000_EPSCR_TX_ 402 phy_data |= M88E1000_EPSCR_TX_CLK_25;
397 403
398 if ((phy->revision == E1000_RE 404 if ((phy->revision == E1000_REVISION_2) &&
399 (phy->id == M88E1111_I_PHY 405 (phy->id == M88E1111_I_PHY_ID)) {
400 /* 82573L PHY - set th 406 /* 82573L PHY - set the downshift counter to 5x. */
401 phy_data &= ~M88EC018_ 407 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
402 phy_data |= M88EC018_E 408 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
403 } else { 409 } else {
404 /* Configure Master an 410 /* Configure Master and Slave downshift values */
405 phy_data &= ~(M88E1000 411 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
406 M88E1000 412 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
407 phy_data |= (M88E1000_ 413 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
408 M88E1000_ 414 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
409 } 415 }
410 ret_val = phy->ops.write_reg(h !! 416 ret_val = hw->phy.ops.write_phy_reg(hw,
>> 417 M88E1000_EXT_PHY_SPEC_CTRL,
411 p 418 phy_data);
412 if (ret_val) 419 if (ret_val)
413 goto out; 420 goto out;
414 } 421 }
415 422
416 /* Commit the changes. */ 423 /* Commit the changes. */
417 ret_val = igb_phy_sw_reset(hw); 424 ret_val = igb_phy_sw_reset(hw);
418 if (ret_val) { 425 if (ret_val) {
419 hw_dbg("Error committing the P !! 426 hw_dbg(hw, "Error committing the PHY changes\n");
420 goto out; 427 goto out;
421 } 428 }
422 429
423 out: 430 out:
424 return ret_val; 431 return ret_val;
425 } 432 }
426 433
427 /** 434 /**
428 * igb_copper_link_setup_igp - Setup igp PHY' !! 435 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
429 * @hw: pointer to the HW structure 436 * @hw: pointer to the HW structure
430 * 437 *
431 * Sets up LPLU, MDI/MDI-X, polarity, Smartsp 438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
432 * igp PHY's. 439 * igp PHY's.
433 **/ 440 **/
434 s32 igb_copper_link_setup_igp(struct e1000_hw 441 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
435 { 442 {
436 struct e1000_phy_info *phy = &hw->phy; 443 struct e1000_phy_info *phy = &hw->phy;
437 s32 ret_val; 444 s32 ret_val;
438 u16 data; 445 u16 data;
439 446
440 if (phy->reset_disable) { 447 if (phy->reset_disable) {
441 ret_val = 0; 448 ret_val = 0;
442 goto out; 449 goto out;
443 } 450 }
444 451
445 ret_val = phy->ops.reset(hw); !! 452 ret_val = hw->phy.ops.reset_phy(hw);
446 if (ret_val) { 453 if (ret_val) {
447 hw_dbg("Error resetting the PH !! 454 hw_dbg(hw, "Error resetting the PHY.\n");
448 goto out; 455 goto out;
449 } 456 }
450 457
451 /* !! 458 /* Wait 15ms for MAC to configure PHY from NVM settings. */
452 * Wait 100ms for MAC to configure PHY !! 459 msleep(15);
453 * timeout issues when LFS is enabled. <<
454 */ <<
455 msleep(100); <<
456 460
457 /* 461 /*
458 * The NVM settings will configure LPL 462 * The NVM settings will configure LPLU in D3 for
459 * non-IGP1 PHYs. 463 * non-IGP1 PHYs.
460 */ 464 */
461 if (phy->type == e1000_phy_igp) { 465 if (phy->type == e1000_phy_igp) {
462 /* disable lplu d3 during driv 466 /* disable lplu d3 during driver init */
463 if (phy->ops.set_d3_lplu_state !! 467 if (hw->phy.ops.set_d3_lplu_state)
464 ret_val = phy->ops.set !! 468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
465 if (ret_val) { 469 if (ret_val) {
466 hw_dbg("Error Disablin !! 470 hw_dbg(hw, "Error Disabling LPLU D3\n");
467 goto out; 471 goto out;
468 } 472 }
469 } 473 }
470 474
471 /* disable lplu d0 during driver init 475 /* disable lplu d0 during driver init */
472 ret_val = phy->ops.set_d0_lplu_state(h !! 476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
473 if (ret_val) { 477 if (ret_val) {
474 hw_dbg("Error Disabling LPLU D !! 478 hw_dbg(hw, "Error Disabling LPLU D0\n");
475 goto out; 479 goto out;
476 } 480 }
477 /* Configure mdi-mdix settings */ 481 /* Configure mdi-mdix settings */
478 ret_val = phy->ops.read_reg(hw, IGP01E !! 482 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
479 if (ret_val) 483 if (ret_val)
480 goto out; 484 goto out;
481 485
482 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 486 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
483 487
484 switch (phy->mdix) { 488 switch (phy->mdix) {
485 case 1: 489 case 1:
486 data &= ~IGP01E1000_PSCR_FORCE 490 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
487 break; 491 break;
488 case 2: 492 case 2:
489 data |= IGP01E1000_PSCR_FORCE_ 493 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
490 break; 494 break;
491 case 0: 495 case 0:
492 default: 496 default:
493 data |= IGP01E1000_PSCR_AUTO_M 497 data |= IGP01E1000_PSCR_AUTO_MDIX;
494 break; 498 break;
495 } 499 }
496 ret_val = phy->ops.write_reg(hw, IGP01 !! 500 ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
497 if (ret_val) 501 if (ret_val)
498 goto out; 502 goto out;
499 503
500 /* set auto-master slave resolution se 504 /* set auto-master slave resolution settings */
501 if (hw->mac.autoneg) { 505 if (hw->mac.autoneg) {
502 /* 506 /*
503 * when autonegotiation advert 507 * when autonegotiation advertisement is only 1000Mbps then we
504 * should disable SmartSpeed a 508 * should disable SmartSpeed and enable Auto MasterSlave
505 * resolution as hardware defa 509 * resolution as hardware default.
506 */ 510 */
507 if (phy->autoneg_advertised == 511 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
508 /* Disable SmartSpeed 512 /* Disable SmartSpeed */
509 ret_val = phy->ops.rea !! 513 ret_val = hw->phy.ops.read_phy_reg(hw,
510 !! 514 IGP01E1000_PHY_PORT_CONFIG,
511 !! 515 &data);
512 if (ret_val) 516 if (ret_val)
513 goto out; 517 goto out;
514 518
515 data &= ~IGP01E1000_PS 519 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
516 ret_val = phy->ops.wri !! 520 ret_val = hw->phy.ops.write_phy_reg(hw,
517 521 IGP01E1000_PHY_PORT_CONFIG,
518 522 data);
519 if (ret_val) 523 if (ret_val)
520 goto out; 524 goto out;
521 525
522 /* Set auto Master/Sla 526 /* Set auto Master/Slave resolution process */
523 ret_val = phy->ops.rea !! 527 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL,
>> 528 &data);
524 if (ret_val) 529 if (ret_val)
525 goto out; 530 goto out;
526 531
527 data &= ~CR_1000T_MS_E 532 data &= ~CR_1000T_MS_ENABLE;
528 ret_val = phy->ops.wri !! 533 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL,
>> 534 data);
529 if (ret_val) 535 if (ret_val)
530 goto out; 536 goto out;
531 } 537 }
532 538
533 ret_val = phy->ops.read_reg(hw !! 539 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL, &data);
534 if (ret_val) 540 if (ret_val)
535 goto out; 541 goto out;
536 542
537 /* load defaults for future us 543 /* load defaults for future use */
538 phy->original_ms_type = (data 544 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
539 ((data & CR_1000T_MS_V 545 ((data & CR_1000T_MS_VALUE) ?
540 e1000_ms_force_master 546 e1000_ms_force_master :
541 e1000_ms_force_slave) 547 e1000_ms_force_slave) :
542 e1000_ms_auto; 548 e1000_ms_auto;
543 549
544 switch (phy->ms_type) { 550 switch (phy->ms_type) {
545 case e1000_ms_force_master: 551 case e1000_ms_force_master:
546 data |= (CR_1000T_MS_E 552 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
547 break; 553 break;
548 case e1000_ms_force_slave: 554 case e1000_ms_force_slave:
549 data |= CR_1000T_MS_EN 555 data |= CR_1000T_MS_ENABLE;
550 data &= ~(CR_1000T_MS_ 556 data &= ~(CR_1000T_MS_VALUE);
551 break; 557 break;
552 case e1000_ms_auto: 558 case e1000_ms_auto:
553 data &= ~CR_1000T_MS_E 559 data &= ~CR_1000T_MS_ENABLE;
554 default: 560 default:
555 break; 561 break;
556 } 562 }
557 ret_val = phy->ops.write_reg(h !! 563 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL, data);
558 if (ret_val) 564 if (ret_val)
559 goto out; 565 goto out;
560 } 566 }
561 567
562 out: 568 out:
563 return ret_val; 569 return ret_val;
564 } 570 }
565 571
566 /** 572 /**
567 * igb_copper_link_autoneg - Setup/Enable aut !! 573 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
568 * @hw: pointer to the HW structure 574 * @hw: pointer to the HW structure
569 * 575 *
570 * Performs initial bounds checking on autone 576 * Performs initial bounds checking on autoneg advertisement parameter, then
571 * configure to advertise the full capability 577 * configure to advertise the full capability. Setup the PHY to autoneg
572 * and restart the negotiation process betwee 578 * and restart the negotiation process between the link partner. If
573 * autoneg_wait_to_complete, then wait for au 579 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
574 **/ 580 **/
575 s32 igb_copper_link_autoneg(struct e1000_hw *h 581 s32 igb_copper_link_autoneg(struct e1000_hw *hw)
576 { 582 {
577 struct e1000_phy_info *phy = &hw->phy; 583 struct e1000_phy_info *phy = &hw->phy;
578 s32 ret_val; 584 s32 ret_val;
579 u16 phy_ctrl; 585 u16 phy_ctrl;
580 586
581 /* 587 /*
582 * Perform some bounds checking on the 588 * Perform some bounds checking on the autoneg advertisement
583 * parameter. 589 * parameter.
584 */ 590 */
585 phy->autoneg_advertised &= phy->autone 591 phy->autoneg_advertised &= phy->autoneg_mask;
586 592
587 /* 593 /*
588 * If autoneg_advertised is zero, we a 594 * If autoneg_advertised is zero, we assume it was not defaulted
589 * by the calling code so we set to ad 595 * by the calling code so we set to advertise full capability.
590 */ 596 */
591 if (phy->autoneg_advertised == 0) 597 if (phy->autoneg_advertised == 0)
592 phy->autoneg_advertised = phy- 598 phy->autoneg_advertised = phy->autoneg_mask;
593 599
594 hw_dbg("Reconfiguring auto-neg adverti !! 600 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
595 ret_val = igb_phy_setup_autoneg(hw); 601 ret_val = igb_phy_setup_autoneg(hw);
596 if (ret_val) { 602 if (ret_val) {
597 hw_dbg("Error Setting up Auto- !! 603 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
598 goto out; 604 goto out;
599 } 605 }
600 hw_dbg("Restarting Auto-Neg\n"); !! 606 hw_dbg(hw, "Restarting Auto-Neg\n");
601 607
602 /* 608 /*
603 * Restart auto-negotiation by setting 609 * Restart auto-negotiation by setting the Auto Neg Enable bit and
604 * the Auto Neg Restart bit in the PHY 610 * the Auto Neg Restart bit in the PHY control register.
605 */ 611 */
606 ret_val = phy->ops.read_reg(hw, PHY_CO !! 612 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
607 if (ret_val) 613 if (ret_val)
608 goto out; 614 goto out;
609 615
610 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_ 616 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
611 ret_val = phy->ops.write_reg(hw, PHY_C !! 617 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
612 if (ret_val) 618 if (ret_val)
613 goto out; 619 goto out;
614 620
615 /* 621 /*
616 * Does the user want to wait for Auto 622 * Does the user want to wait for Auto-Neg to complete here, or
617 * check at a later time (for example, 623 * check at a later time (for example, callback routine).
618 */ 624 */
619 if (phy->autoneg_wait_to_complete) { 625 if (phy->autoneg_wait_to_complete) {
620 ret_val = igb_wait_autoneg(hw) 626 ret_val = igb_wait_autoneg(hw);
621 if (ret_val) { 627 if (ret_val) {
622 hw_dbg("Error while wa !! 628 hw_dbg(hw, "Error while waiting for "
623 "autoneg to com !! 629 "autoneg to complete\n");
624 goto out; 630 goto out;
625 } 631 }
626 } 632 }
627 633
628 hw->mac.get_link_status = true; 634 hw->mac.get_link_status = true;
629 635
630 out: 636 out:
631 return ret_val; 637 return ret_val;
632 } 638 }
633 639
634 /** 640 /**
635 * igb_phy_setup_autoneg - Configure PHY for !! 641 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
636 * @hw: pointer to the HW structure 642 * @hw: pointer to the HW structure
637 * 643 *
638 * Reads the MII auto-neg advertisement regis 644 * Reads the MII auto-neg advertisement register and/or the 1000T control
639 * register and if the PHY is already setup f 645 * register and if the PHY is already setup for auto-negotiation, then
640 * return successful. Otherwise, setup adver 646 * return successful. Otherwise, setup advertisement and flow control to
641 * the appropriate values for the wanted auto 647 * the appropriate values for the wanted auto-negotiation.
642 **/ 648 **/
643 static s32 igb_phy_setup_autoneg(struct e1000_ 649 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
644 { 650 {
645 struct e1000_phy_info *phy = &hw->phy; 651 struct e1000_phy_info *phy = &hw->phy;
646 s32 ret_val; 652 s32 ret_val;
647 u16 mii_autoneg_adv_reg; 653 u16 mii_autoneg_adv_reg;
648 u16 mii_1000t_ctrl_reg = 0; 654 u16 mii_1000t_ctrl_reg = 0;
649 655
650 phy->autoneg_advertised &= phy->autone 656 phy->autoneg_advertised &= phy->autoneg_mask;
651 657
652 /* Read the MII Auto-Neg Advertisement 658 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
653 ret_val = phy->ops.read_reg(hw, PHY_AU !! 659 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV,
>> 660 &mii_autoneg_adv_reg);
654 if (ret_val) 661 if (ret_val)
655 goto out; 662 goto out;
656 663
657 if (phy->autoneg_mask & ADVERTISE_1000 664 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
658 /* Read the MII 1000Base-T Con 665 /* Read the MII 1000Base-T Control Register (Address 9). */
659 ret_val = phy->ops.read_reg(hw !! 666 ret_val = hw->phy.ops.read_phy_reg(hw,
>> 667 PHY_1000T_CTRL,
660 &m 668 &mii_1000t_ctrl_reg);
661 if (ret_val) 669 if (ret_val)
662 goto out; 670 goto out;
663 } 671 }
664 672
665 /* 673 /*
666 * Need to parse both autoneg_advertis 674 * Need to parse both autoneg_advertised and fc and set up
667 * the appropriate PHY registers. Fir 675 * the appropriate PHY registers. First we will parse for
668 * autoneg_advertised software overrid 676 * autoneg_advertised software override. Since we can advertise
669 * a plethora of combinations, we need 677 * a plethora of combinations, we need to check each bit
670 * individually. 678 * individually.
671 */ 679 */
672 680
673 /* 681 /*
674 * First we clear all the 10/100 mb sp 682 * First we clear all the 10/100 mb speed bits in the Auto-Neg
675 * Advertisement Register (Address 4) 683 * Advertisement Register (Address 4) and the 1000 mb speed bits in
676 * the 1000Base-T Control Register (A 684 * the 1000Base-T Control Register (Address 9).
677 */ 685 */
678 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX 686 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
679 NWAY_AR_100TX 687 NWAY_AR_100TX_HD_CAPS |
680 NWAY_AR_10T_F 688 NWAY_AR_10T_FD_CAPS |
681 NWAY_AR_10T_H 689 NWAY_AR_10T_HD_CAPS);
682 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CA 690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
683 691
684 hw_dbg("autoneg_advertised %x\n", phy- !! 692 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
685 693
686 /* Do we want to advertise 10 Mb Half 694 /* Do we want to advertise 10 Mb Half Duplex? */
687 if (phy->autoneg_advertised & ADVERTIS 695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
688 hw_dbg("Advertise 10mb Half du !! 696 hw_dbg(hw, "Advertise 10mb Half duplex\n");
689 mii_autoneg_adv_reg |= NWAY_AR 697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
690 } 698 }
691 699
692 /* Do we want to advertise 10 Mb Full 700 /* Do we want to advertise 10 Mb Full Duplex? */
693 if (phy->autoneg_advertised & ADVERTIS 701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
694 hw_dbg("Advertise 10mb Full du !! 702 hw_dbg(hw, "Advertise 10mb Full duplex\n");
695 mii_autoneg_adv_reg |= NWAY_AR 703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
696 } 704 }
697 705
698 /* Do we want to advertise 100 Mb Half 706 /* Do we want to advertise 100 Mb Half Duplex? */
699 if (phy->autoneg_advertised & ADVERTIS 707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
700 hw_dbg("Advertise 100mb Half d !! 708 hw_dbg(hw, "Advertise 100mb Half duplex\n");
701 mii_autoneg_adv_reg |= NWAY_AR 709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
702 } 710 }
703 711
704 /* Do we want to advertise 100 Mb Full 712 /* Do we want to advertise 100 Mb Full Duplex? */
705 if (phy->autoneg_advertised & ADVERTIS 713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
706 hw_dbg("Advertise 100mb Full d !! 714 hw_dbg(hw, "Advertise 100mb Full duplex\n");
707 mii_autoneg_adv_reg |= NWAY_AR 715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
708 } 716 }
709 717
710 /* We do not allow the Phy to advertis 718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
711 if (phy->autoneg_advertised & ADVERTIS 719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
712 hw_dbg("Advertise 1000mb Half !! 720 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
713 721
714 /* Do we want to advertise 1000 Mb Ful 722 /* Do we want to advertise 1000 Mb Full Duplex? */
715 if (phy->autoneg_advertised & ADVERTIS 723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
716 hw_dbg("Advertise 1000mb Full !! 724 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
717 mii_1000t_ctrl_reg |= CR_1000T 725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
718 } 726 }
719 727
720 /* 728 /*
721 * Check for a software override of th 729 * Check for a software override of the flow control settings, and
722 * setup the PHY advertisement registe 730 * setup the PHY advertisement registers accordingly. If
723 * auto-negotiation is enabled, then s 731 * auto-negotiation is enabled, then software will have to set the
724 * "PAUSE" bits to the correct value i 732 * "PAUSE" bits to the correct value in the Auto-Negotiation
725 * Advertisement Register (PHY_AUTONEG 733 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
726 * negotiation. 734 * negotiation.
727 * 735 *
728 * The possible values of the "fc" par 736 * The possible values of the "fc" parameter are:
729 * 0: Flow control is completely 737 * 0: Flow control is completely disabled
730 * 1: Rx flow control is enabled 738 * 1: Rx flow control is enabled (we can receive pause frames
731 * but not send pause frames) 739 * but not send pause frames).
732 * 2: Tx flow control is enabled 740 * 2: Tx flow control is enabled (we can send pause frames
733 * but we do not support rece 741 * but we do not support receiving pause frames).
734 * 3: Both Rx and TX flow contro 742 * 3: Both Rx and TX flow control (symmetric) are enabled.
735 * other: No software override. The 743 * other: No software override. The flow control configuration
736 * in the EEPROM is used. 744 * in the EEPROM is used.
737 */ 745 */
738 switch (hw->fc.type) { 746 switch (hw->fc.type) {
739 case e1000_fc_none: 747 case e1000_fc_none:
740 /* 748 /*
741 * Flow control (RX & TX) is c 749 * Flow control (RX & TX) is completely disabled by a
742 * software over-ride. 750 * software over-ride.
743 */ 751 */
744 mii_autoneg_adv_reg &= ~(NWAY_ 752 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
745 break; 753 break;
746 case e1000_fc_rx_pause: 754 case e1000_fc_rx_pause:
747 /* 755 /*
748 * RX Flow control is enabled, 756 * RX Flow control is enabled, and TX Flow control is
749 * disabled, by a software ove 757 * disabled, by a software over-ride.
750 * 758 *
751 * Since there really isn't a 759 * Since there really isn't a way to advertise that we are
752 * capable of RX Pause ONLY, w 760 * capable of RX Pause ONLY, we will advertise that we
753 * support both symmetric and 761 * support both symmetric and asymmetric RX PAUSE. Later
754 * (in e1000_config_fc_after_l 762 * (in e1000_config_fc_after_link_up) we will disable the
755 * hw's ability to send PAUSE 763 * hw's ability to send PAUSE frames.
756 */ 764 */
757 mii_autoneg_adv_reg |= (NWAY_A 765 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
758 break; 766 break;
759 case e1000_fc_tx_pause: 767 case e1000_fc_tx_pause:
760 /* 768 /*
761 * TX Flow control is enabled, 769 * TX Flow control is enabled, and RX Flow control is
762 * disabled, by a software ove 770 * disabled, by a software over-ride.
763 */ 771 */
764 mii_autoneg_adv_reg |= NWAY_AR 772 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
765 mii_autoneg_adv_reg &= ~NWAY_A 773 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
766 break; 774 break;
767 case e1000_fc_full: 775 case e1000_fc_full:
768 /* 776 /*
769 * Flow control (both RX and T 777 * Flow control (both RX and TX) is enabled by a software
770 * over-ride. 778 * over-ride.
771 */ 779 */
772 mii_autoneg_adv_reg |= (NWAY_A 780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
773 break; 781 break;
774 default: 782 default:
775 hw_dbg("Flow control param set !! 783 hw_dbg(hw, "Flow control param set incorrectly\n");
776 ret_val = -E1000_ERR_CONFIG; 784 ret_val = -E1000_ERR_CONFIG;
777 goto out; 785 goto out;
778 } 786 }
779 787
780 ret_val = phy->ops.write_reg(hw, PHY_A !! 788 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_AUTONEG_ADV,
>> 789 mii_autoneg_adv_reg);
781 if (ret_val) 790 if (ret_val)
782 goto out; 791 goto out;
783 792
784 hw_dbg("Auto-Neg Advertising %x\n", mi !! 793 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
785 794
786 if (phy->autoneg_mask & ADVERTISE_1000 795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
787 ret_val = phy->ops.write_reg(h !! 796 ret_val = hw->phy.ops.write_phy_reg(hw,
788 P !! 797 PHY_1000T_CTRL,
789 m !! 798 mii_1000t_ctrl_reg);
790 if (ret_val) 799 if (ret_val)
791 goto out; 800 goto out;
792 } 801 }
793 802
794 out: 803 out:
795 return ret_val; 804 return ret_val;
796 } 805 }
797 806
798 /** 807 /**
799 * igb_phy_force_speed_duplex_igp - Force spe !! 808 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
800 * @hw: pointer to the HW structure 809 * @hw: pointer to the HW structure
801 * 810 *
802 * Calls the PHY setup function to force spee 811 * Calls the PHY setup function to force speed and duplex. Clears the
803 * auto-crossover to force MDI manually. Wai 812 * auto-crossover to force MDI manually. Waits for link and returns
804 * successful if link up is successful, else 813 * successful if link up is successful, else -E1000_ERR_PHY (-2).
805 **/ 814 **/
806 s32 igb_phy_force_speed_duplex_igp(struct e100 815 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
807 { 816 {
808 struct e1000_phy_info *phy = &hw->phy; 817 struct e1000_phy_info *phy = &hw->phy;
809 s32 ret_val; 818 s32 ret_val;
810 u16 phy_data; 819 u16 phy_data;
811 bool link; 820 bool link;
812 821
813 ret_val = phy->ops.read_reg(hw, PHY_CO !! 822 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
814 if (ret_val) 823 if (ret_val)
815 goto out; 824 goto out;
816 825
817 igb_phy_force_speed_duplex_setup(hw, & 826 igb_phy_force_speed_duplex_setup(hw, &phy_data);
818 827
819 ret_val = phy->ops.write_reg(hw, PHY_C !! 828 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
820 if (ret_val) 829 if (ret_val)
821 goto out; 830 goto out;
822 831
823 /* 832 /*
824 * Clear Auto-Crossover to force MDI m 833 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
825 * forced whenever speed and duplex ar 834 * forced whenever speed and duplex are forced.
826 */ 835 */
827 ret_val = phy->ops.read_reg(hw, IGP01E !! 836 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
>> 837 &phy_data);
828 if (ret_val) 838 if (ret_val)
829 goto out; 839 goto out;
830 840
831 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX 841 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
832 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI 842 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
833 843
834 ret_val = phy->ops.write_reg(hw, IGP01 !! 844 ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
>> 845 phy_data);
835 if (ret_val) 846 if (ret_val)
836 goto out; 847 goto out;
837 848
838 hw_dbg("IGP PSCR: %X\n", phy_data); !! 849 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
839 850
840 udelay(1); 851 udelay(1);
841 852
842 if (phy->autoneg_wait_to_complete) { 853 if (phy->autoneg_wait_to_complete) {
843 hw_dbg("Waiting for forced spe !! 854 hw_dbg(hw,
>> 855 "Waiting for forced speed/duplex link on IGP phy.\n");
844 856
845 ret_val = igb_phy_has_link(hw, 857 ret_val = igb_phy_has_link(hw,
846 858 PHY_FORCE_LIMIT,
847 859 100000,
848 860 &link);
849 if (ret_val) 861 if (ret_val)
850 goto out; 862 goto out;
851 863
852 if (!link) 864 if (!link)
853 hw_dbg("Link taking lo !! 865 hw_dbg(hw, "Link taking longer than expected.\n");
854 866
855 /* Try once more */ 867 /* Try once more */
856 ret_val = igb_phy_has_link(hw, 868 ret_val = igb_phy_has_link(hw,
857 869 PHY_FORCE_LIMIT,
858 870 100000,
859 871 &link);
860 if (ret_val) 872 if (ret_val)
861 goto out; 873 goto out;
862 } 874 }
863 875
864 out: 876 out:
865 return ret_val; 877 return ret_val;
866 } 878 }
867 879
868 /** 880 /**
869 * igb_phy_force_speed_duplex_m88 - Force spe !! 881 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
870 * @hw: pointer to the HW structure 882 * @hw: pointer to the HW structure
871 * 883 *
872 * Calls the PHY setup function to force spee 884 * Calls the PHY setup function to force speed and duplex. Clears the
873 * auto-crossover to force MDI manually. Res 885 * auto-crossover to force MDI manually. Resets the PHY to commit the
874 * changes. If time expires while waiting fo 886 * changes. If time expires while waiting for link up, we reset the DSP.
875 * After reset, TX_CLK and CRS on TX must be 887 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
876 * successful completion, else return corresp 888 * successful completion, else return corresponding error code.
877 **/ 889 **/
878 s32 igb_phy_force_speed_duplex_m88(struct e100 890 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
879 { 891 {
880 struct e1000_phy_info *phy = &hw->phy; 892 struct e1000_phy_info *phy = &hw->phy;
881 s32 ret_val; 893 s32 ret_val;
882 u16 phy_data; 894 u16 phy_data;
883 bool link; 895 bool link;
884 896
885 /* 897 /*
886 * Clear Auto-Crossover to force MDI m 898 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
887 * forced whenever speed and duplex ar 899 * forced whenever speed and duplex are forced.
888 */ 900 */
889 ret_val = phy->ops.read_reg(hw, M88E10 !! 901 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 902 &phy_data);
890 if (ret_val) 903 if (ret_val)
891 goto out; 904 goto out;
892 905
893 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE 906 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
894 ret_val = phy->ops.write_reg(hw, M88E1 !! 907 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 908 phy_data);
895 if (ret_val) 909 if (ret_val)
896 goto out; 910 goto out;
897 911
898 hw_dbg("M88E1000 PSCR: %X\n", phy_data !! 912 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
899 913
900 ret_val = phy->ops.read_reg(hw, PHY_CO !! 914 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
901 if (ret_val) 915 if (ret_val)
902 goto out; 916 goto out;
903 917
904 igb_phy_force_speed_duplex_setup(hw, & 918 igb_phy_force_speed_duplex_setup(hw, &phy_data);
905 919
906 /* Reset the phy to commit changes. */ 920 /* Reset the phy to commit changes. */
907 phy_data |= MII_CR_RESET; 921 phy_data |= MII_CR_RESET;
908 922
909 ret_val = phy->ops.write_reg(hw, PHY_C !! 923 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
910 if (ret_val) 924 if (ret_val)
911 goto out; 925 goto out;
912 926
913 udelay(1); 927 udelay(1);
914 928
915 if (phy->autoneg_wait_to_complete) { 929 if (phy->autoneg_wait_to_complete) {
916 hw_dbg("Waiting for forced spe !! 930 hw_dbg(hw,
>> 931 "Waiting for forced speed/duplex link on M88 phy.\n");
917 932
918 ret_val = igb_phy_has_link(hw, 933 ret_val = igb_phy_has_link(hw,
919 934 PHY_FORCE_LIMIT,
920 935 100000,
921 936 &link);
922 if (ret_val) 937 if (ret_val)
923 goto out; 938 goto out;
924 939
925 if (!link) { 940 if (!link) {
926 /* 941 /*
927 * We didn't get link. 942 * We didn't get link.
928 * Reset the DSP and c 943 * Reset the DSP and cross our fingers.
929 */ 944 */
930 ret_val = phy->ops.wri !! 945 ret_val = hw->phy.ops.write_phy_reg(hw,
931 946 M88E1000_PHY_PAGE_SELECT,
932 947 0x001d);
933 if (ret_val) 948 if (ret_val)
934 goto out; 949 goto out;
935 ret_val = igb_phy_rese 950 ret_val = igb_phy_reset_dsp(hw);
936 if (ret_val) 951 if (ret_val)
937 goto out; 952 goto out;
938 } 953 }
939 954
940 /* Try once more */ 955 /* Try once more */
941 ret_val = igb_phy_has_link(hw, 956 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
942 1 957 100000, &link);
943 if (ret_val) 958 if (ret_val)
944 goto out; 959 goto out;
945 } 960 }
946 961
947 ret_val = phy->ops.read_reg(hw, M88E10 !! 962 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
>> 963 &phy_data);
948 if (ret_val) 964 if (ret_val)
949 goto out; 965 goto out;
950 966
951 /* 967 /*
952 * Resetting the phy means we need to 968 * Resetting the phy means we need to re-force TX_CLK in the
953 * Extended PHY Specific Control Regis 969 * Extended PHY Specific Control Register to 25MHz clock from
954 * the reset value of 2.5MHz. 970 * the reset value of 2.5MHz.
955 */ 971 */
956 phy_data |= M88E1000_EPSCR_TX_CLK_25; 972 phy_data |= M88E1000_EPSCR_TX_CLK_25;
957 ret_val = phy->ops.write_reg(hw, M88E1 !! 973 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
>> 974 phy_data);
958 if (ret_val) 975 if (ret_val)
959 goto out; 976 goto out;
960 977
961 /* 978 /*
962 * In addition, we must re-enable CRS 979 * In addition, we must re-enable CRS on Tx for both half and full
963 * duplex. 980 * duplex.
964 */ 981 */
965 ret_val = phy->ops.read_reg(hw, M88E10 !! 982 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 983 &phy_data);
966 if (ret_val) 984 if (ret_val)
967 goto out; 985 goto out;
968 986
969 phy_data |= M88E1000_PSCR_ASSERT_CRS_O 987 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
970 ret_val = phy->ops.write_reg(hw, M88E1 !! 988 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 989 phy_data);
971 990
972 out: 991 out:
973 return ret_val; 992 return ret_val;
974 } 993 }
975 994
976 /** 995 /**
977 * igb_phy_force_speed_duplex_setup - Configu !! 996 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
978 * @hw: pointer to the HW structure 997 * @hw: pointer to the HW structure
979 * @phy_ctrl: pointer to current value of PHY 998 * @phy_ctrl: pointer to current value of PHY_CONTROL
980 * 999 *
981 * Forces speed and duplex on the PHY by doin 1000 * Forces speed and duplex on the PHY by doing the following: disable flow
982 * control, force speed/duplex on the MAC, di 1001 * control, force speed/duplex on the MAC, disable auto speed detection,
983 * disable auto-negotiation, configure duplex 1002 * disable auto-negotiation, configure duplex, configure speed, configure
984 * the collision distance, write configuratio 1003 * the collision distance, write configuration to CTRL register. The
985 * caller must write to the PHY_CONTROL regis 1004 * caller must write to the PHY_CONTROL register for these settings to
986 * take affect. 1005 * take affect.
987 **/ 1006 **/
988 static void igb_phy_force_speed_duplex_setup(s 1007 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
989 1008 u16 *phy_ctrl)
990 { 1009 {
991 struct e1000_mac_info *mac = &hw->mac; 1010 struct e1000_mac_info *mac = &hw->mac;
992 u32 ctrl; 1011 u32 ctrl;
993 1012
994 /* Turn off flow control when forcing 1013 /* Turn off flow control when forcing speed/duplex */
995 hw->fc.type = e1000_fc_none; 1014 hw->fc.type = e1000_fc_none;
996 1015
997 /* Force speed/duplex on the mac */ 1016 /* Force speed/duplex on the mac */
998 ctrl = rd32(E1000_CTRL); 1017 ctrl = rd32(E1000_CTRL);
999 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTR 1018 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1000 ctrl &= ~E1000_CTRL_SPD_SEL; 1019 ctrl &= ~E1000_CTRL_SPD_SEL;
1001 1020
1002 /* Disable Auto Speed Detection */ 1021 /* Disable Auto Speed Detection */
1003 ctrl &= ~E1000_CTRL_ASDE; 1022 ctrl &= ~E1000_CTRL_ASDE;
1004 1023
1005 /* Disable autoneg on the phy */ 1024 /* Disable autoneg on the phy */
1006 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1025 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1007 1026
1008 /* Forcing Full or Half Duplex? */ 1027 /* Forcing Full or Half Duplex? */
1009 if (mac->forced_speed_duplex & E1000_ 1028 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1010 ctrl &= ~E1000_CTRL_FD; 1029 ctrl &= ~E1000_CTRL_FD;
1011 *phy_ctrl &= ~MII_CR_FULL_DUP 1030 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1012 hw_dbg("Half Duplex\n"); !! 1031 hw_dbg(hw, "Half Duplex\n");
1013 } else { 1032 } else {
1014 ctrl |= E1000_CTRL_FD; 1033 ctrl |= E1000_CTRL_FD;
1015 *phy_ctrl |= MII_CR_FULL_DUPL 1034 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1016 hw_dbg("Full Duplex\n"); !! 1035 hw_dbg(hw, "Full Duplex\n");
1017 } 1036 }
1018 1037
1019 /* Forcing 10mb or 100mb? */ 1038 /* Forcing 10mb or 100mb? */
1020 if (mac->forced_speed_duplex & E1000_ 1039 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1021 ctrl |= E1000_CTRL_SPD_100; 1040 ctrl |= E1000_CTRL_SPD_100;
1022 *phy_ctrl |= MII_CR_SPEED_100 1041 *phy_ctrl |= MII_CR_SPEED_100;
1023 *phy_ctrl &= ~(MII_CR_SPEED_1 1042 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1024 hw_dbg("Forcing 100mb\n"); !! 1043 hw_dbg(hw, "Forcing 100mb\n");
1025 } else { 1044 } else {
1026 ctrl &= ~(E1000_CTRL_SPD_1000 1045 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1027 *phy_ctrl |= MII_CR_SPEED_10; 1046 *phy_ctrl |= MII_CR_SPEED_10;
1028 *phy_ctrl &= ~(MII_CR_SPEED_1 1047 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1029 hw_dbg("Forcing 10mb\n"); !! 1048 hw_dbg(hw, "Forcing 10mb\n");
1030 } 1049 }
1031 1050
1032 igb_config_collision_dist(hw); 1051 igb_config_collision_dist(hw);
1033 1052
1034 wr32(E1000_CTRL, ctrl); 1053 wr32(E1000_CTRL, ctrl);
1035 } 1054 }
1036 1055
1037 /** 1056 /**
1038 * igb_set_d3_lplu_state - Sets low power li !! 1057 * e1000_set_d3_lplu_state - Sets low power link up state for D3
1039 * @hw: pointer to the HW structure 1058 * @hw: pointer to the HW structure
1040 * @active: boolean used to enable/disable l 1059 * @active: boolean used to enable/disable lplu
1041 * 1060 *
1042 * Success returns 0, Failure returns 1 1061 * Success returns 0, Failure returns 1
1043 * 1062 *
1044 * The low power link up (lplu) state is set 1063 * The low power link up (lplu) state is set to the power management level D3
1045 * and SmartSpeed is disabled when active is 1064 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1046 * and enable Smartspeed. LPLU and Smartspe 1065 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1047 * is used during Dx states where the power 1066 * is used during Dx states where the power conservation is most important.
1048 * During driver activity, SmartSpeed should 1067 * During driver activity, SmartSpeed should be enabled so performance is
1049 * maintained. 1068 * maintained.
1050 **/ 1069 **/
1051 s32 igb_set_d3_lplu_state(struct e1000_hw *hw 1070 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1052 { 1071 {
1053 struct e1000_phy_info *phy = &hw->phy 1072 struct e1000_phy_info *phy = &hw->phy;
1054 s32 ret_val; 1073 s32 ret_val;
1055 u16 data; 1074 u16 data;
1056 1075
1057 ret_val = phy->ops.read_reg(hw, IGP02 !! 1076 ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
>> 1077 &data);
1058 if (ret_val) 1078 if (ret_val)
1059 goto out; 1079 goto out;
1060 1080
1061 if (!active) { 1081 if (!active) {
1062 data &= ~IGP02E1000_PM_D3_LPL 1082 data &= ~IGP02E1000_PM_D3_LPLU;
1063 ret_val = phy->ops.write_reg( !! 1083 ret_val = hw->phy.ops.write_phy_reg(hw,
>> 1084 IGP02E1000_PHY_POWER_MGMT,
1064 1085 data);
1065 if (ret_val) 1086 if (ret_val)
1066 goto out; 1087 goto out;
1067 /* 1088 /*
1068 * LPLU and SmartSpeed are mu 1089 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1069 * during Dx states where the 1090 * during Dx states where the power conservation is most
1070 * important. During driver 1091 * important. During driver activity we should enable
1071 * SmartSpeed, so performance 1092 * SmartSpeed, so performance is maintained.
1072 */ 1093 */
1073 if (phy->smart_speed == e1000 1094 if (phy->smart_speed == e1000_smart_speed_on) {
1074 ret_val = phy->ops.re !! 1095 ret_val = hw->phy.ops.read_phy_reg(hw,
1075 1096 IGP01E1000_PHY_PORT_CONFIG,
1076 1097 &data);
1077 if (ret_val) 1098 if (ret_val)
1078 goto out; 1099 goto out;
1079 1100
1080 data |= IGP01E1000_PS 1101 data |= IGP01E1000_PSCFR_SMART_SPEED;
1081 ret_val = phy->ops.wr !! 1102 ret_val = hw->phy.ops.write_phy_reg(hw,
1082 1103 IGP01E1000_PHY_PORT_CONFIG,
1083 1104 data);
1084 if (ret_val) 1105 if (ret_val)
1085 goto out; 1106 goto out;
1086 } else if (phy->smart_speed = 1107 } else if (phy->smart_speed == e1000_smart_speed_off) {
1087 ret_val = phy->ops.re !! 1108 ret_val = hw->phy.ops.read_phy_reg(hw,
1088 1109 IGP01E1000_PHY_PORT_CONFIG,
1089 1110 &data);
1090 if (ret_val) 1111 if (ret_val)
1091 goto out; 1112 goto out;
1092 1113
1093 data &= ~IGP01E1000_P 1114 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1094 ret_val = phy->ops.wr !! 1115 ret_val = hw->phy.ops.write_phy_reg(hw,
1095 1116 IGP01E1000_PHY_PORT_CONFIG,
1096 1117 data);
1097 if (ret_val) 1118 if (ret_val)
1098 goto out; 1119 goto out;
1099 } 1120 }
1100 } else if ((phy->autoneg_advertised = 1121 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1101 (phy->autoneg_advertised = 1122 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1102 (phy->autoneg_advertised = 1123 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1103 data |= IGP02E1000_PM_D3_LPLU 1124 data |= IGP02E1000_PM_D3_LPLU;
1104 ret_val = phy->ops.write_reg( !! 1125 ret_val = hw->phy.ops.write_phy_reg(hw,
>> 1126 IGP02E1000_PHY_POWER_MGMT,
1105 1127 data);
1106 if (ret_val) 1128 if (ret_val)
1107 goto out; 1129 goto out;
1108 1130
1109 /* When LPLU is enabled, we s 1131 /* When LPLU is enabled, we should disable SmartSpeed */
1110 ret_val = phy->ops.read_reg(h !! 1132 ret_val = hw->phy.ops.read_phy_reg(hw,
>> 1133 IGP01E1000_PHY_PORT_CONFIG,
1111 1134 &data);
1112 if (ret_val) 1135 if (ret_val)
1113 goto out; 1136 goto out;
1114 1137
1115 data &= ~IGP01E1000_PSCFR_SMA 1138 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1116 ret_val = phy->ops.write_reg( !! 1139 ret_val = hw->phy.ops.write_phy_reg(hw,
>> 1140 IGP01E1000_PHY_PORT_CONFIG,
1117 1141 data);
1118 } 1142 }
1119 1143
1120 out: 1144 out:
1121 return ret_val; 1145 return ret_val;
1122 } 1146 }
1123 1147
1124 /** 1148 /**
1125 * igb_check_downshift - Checks whether a do !! 1149 * e1000_check_downshift - Checks whether a downshift in speed occured
1126 * @hw: pointer to the HW structure 1150 * @hw: pointer to the HW structure
1127 * 1151 *
1128 * Success returns 0, Failure returns 1 1152 * Success returns 0, Failure returns 1
1129 * 1153 *
1130 * A downshift is detected by querying the P 1154 * A downshift is detected by querying the PHY link health.
1131 **/ 1155 **/
1132 s32 igb_check_downshift(struct e1000_hw *hw) 1156 s32 igb_check_downshift(struct e1000_hw *hw)
1133 { 1157 {
1134 struct e1000_phy_info *phy = &hw->phy 1158 struct e1000_phy_info *phy = &hw->phy;
1135 s32 ret_val; 1159 s32 ret_val;
1136 u16 phy_data, offset, mask; 1160 u16 phy_data, offset, mask;
1137 1161
1138 switch (phy->type) { 1162 switch (phy->type) {
1139 case e1000_phy_m88: 1163 case e1000_phy_m88:
1140 case e1000_phy_gg82563: 1164 case e1000_phy_gg82563:
1141 offset = M88E1000_PHY_SPEC_S 1165 offset = M88E1000_PHY_SPEC_STATUS;
1142 mask = M88E1000_PSSR_DOWNS 1166 mask = M88E1000_PSSR_DOWNSHIFT;
1143 break; 1167 break;
1144 case e1000_phy_igp_2: 1168 case e1000_phy_igp_2:
1145 case e1000_phy_igp: 1169 case e1000_phy_igp:
1146 case e1000_phy_igp_3: 1170 case e1000_phy_igp_3:
1147 offset = IGP01E1000_PHY_LINK 1171 offset = IGP01E1000_PHY_LINK_HEALTH;
1148 mask = IGP01E1000_PLHR_SS_ 1172 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1149 break; 1173 break;
1150 default: 1174 default:
1151 /* speed downshift not suppor 1175 /* speed downshift not supported */
1152 phy->speed_downgraded = false 1176 phy->speed_downgraded = false;
1153 ret_val = 0; 1177 ret_val = 0;
1154 goto out; 1178 goto out;
1155 } 1179 }
1156 1180
1157 ret_val = phy->ops.read_reg(hw, offse !! 1181 ret_val = hw->phy.ops.read_phy_reg(hw, offset, &phy_data);
1158 1182
1159 if (!ret_val) 1183 if (!ret_val)
1160 phy->speed_downgraded = (phy_ 1184 phy->speed_downgraded = (phy_data & mask) ? true : false;
1161 1185
1162 out: 1186 out:
1163 return ret_val; 1187 return ret_val;
1164 } 1188 }
1165 1189
1166 /** 1190 /**
1167 * igb_check_polarity_m88 - Checks the polar !! 1191 * e1000_check_polarity_m88 - Checks the polarity.
1168 * @hw: pointer to the HW structure 1192 * @hw: pointer to the HW structure
1169 * 1193 *
1170 * Success returns 0, Failure returns -E1000 1194 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1171 * 1195 *
1172 * Polarity is determined based on the PHY s 1196 * Polarity is determined based on the PHY specific status register.
1173 **/ 1197 **/
1174 static s32 igb_check_polarity_m88(struct e100 1198 static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1175 { 1199 {
1176 struct e1000_phy_info *phy = &hw->phy 1200 struct e1000_phy_info *phy = &hw->phy;
1177 s32 ret_val; 1201 s32 ret_val;
1178 u16 data; 1202 u16 data;
1179 1203
1180 ret_val = phy->ops.read_reg(hw, M88E1 !! 1204 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1181 1205
1182 if (!ret_val) 1206 if (!ret_val)
1183 phy->cable_polarity = (data & 1207 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1184 ? e1000 1208 ? e1000_rev_polarity_reversed
1185 : e1000 1209 : e1000_rev_polarity_normal;
1186 1210
1187 return ret_val; 1211 return ret_val;
1188 } 1212 }
1189 1213
1190 /** 1214 /**
1191 * igb_check_polarity_igp - Checks the polar !! 1215 * e1000_check_polarity_igp - Checks the polarity.
1192 * @hw: pointer to the HW structure 1216 * @hw: pointer to the HW structure
1193 * 1217 *
1194 * Success returns 0, Failure returns -E1000 1218 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1195 * 1219 *
1196 * Polarity is determined based on the PHY p 1220 * Polarity is determined based on the PHY port status register, and the
1197 * current speed (since there is no polarity 1221 * current speed (since there is no polarity at 100Mbps).
1198 **/ 1222 **/
1199 static s32 igb_check_polarity_igp(struct e100 1223 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1200 { 1224 {
1201 struct e1000_phy_info *phy = &hw->phy 1225 struct e1000_phy_info *phy = &hw->phy;
1202 s32 ret_val; 1226 s32 ret_val;
1203 u16 data, offset, mask; 1227 u16 data, offset, mask;
1204 1228
1205 /* 1229 /*
1206 * Polarity is determined based on th 1230 * Polarity is determined based on the speed of
1207 * our connection. 1231 * our connection.
1208 */ 1232 */
1209 ret_val = phy->ops.read_reg(hw, IGP01 !! 1233 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
>> 1234 &data);
1210 if (ret_val) 1235 if (ret_val)
1211 goto out; 1236 goto out;
1212 1237
1213 if ((data & IGP01E1000_PSSR_SPEED_MAS 1238 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1214 IGP01E1000_PSSR_SPEED_1000MBPS) { 1239 IGP01E1000_PSSR_SPEED_1000MBPS) {
1215 offset = IGP01E1000_PHY_PCS_ 1240 offset = IGP01E1000_PHY_PCS_INIT_REG;
1216 mask = IGP01E1000_PHY_POLA 1241 mask = IGP01E1000_PHY_POLARITY_MASK;
1217 } else { 1242 } else {
1218 /* 1243 /*
1219 * This really only applies t 1244 * This really only applies to 10Mbps since
1220 * there is no polarity for 1 1245 * there is no polarity for 100Mbps (always 0).
1221 */ 1246 */
1222 offset = IGP01E1000_PHY_PORT 1247 offset = IGP01E1000_PHY_PORT_STATUS;
1223 mask = IGP01E1000_PSSR_POL 1248 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1224 } 1249 }
1225 1250
1226 ret_val = phy->ops.read_reg(hw, offse !! 1251 ret_val = hw->phy.ops.read_phy_reg(hw, offset, &data);
1227 1252
1228 if (!ret_val) 1253 if (!ret_val)
1229 phy->cable_polarity = (data & 1254 phy->cable_polarity = (data & mask)
1230 ? e1000 1255 ? e1000_rev_polarity_reversed
1231 : e1000 1256 : e1000_rev_polarity_normal;
1232 1257
1233 out: 1258 out:
1234 return ret_val; 1259 return ret_val;
1235 } 1260 }
1236 1261
1237 /** 1262 /**
1238 * igb_wait_autoneg - Wait for auto-neg comp !! 1263 * e1000_wait_autoneg - Wait for auto-neg compeletion
1239 * @hw: pointer to the HW structure 1264 * @hw: pointer to the HW structure
1240 * 1265 *
1241 * Waits for auto-negotiation to complete or 1266 * Waits for auto-negotiation to complete or for the auto-negotiation time
1242 * limit to expire, which ever happens first 1267 * limit to expire, which ever happens first.
1243 **/ 1268 **/
1244 static s32 igb_wait_autoneg(struct e1000_hw * 1269 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1245 { 1270 {
1246 s32 ret_val = 0; 1271 s32 ret_val = 0;
1247 u16 i, phy_status; 1272 u16 i, phy_status;
1248 1273
1249 /* Break after autoneg completes or P 1274 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1250 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i 1275 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1251 ret_val = hw->phy.ops.read_re !! 1276 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1252 if (ret_val) 1277 if (ret_val)
1253 break; 1278 break;
1254 ret_val = hw->phy.ops.read_re !! 1279 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1255 if (ret_val) 1280 if (ret_val)
1256 break; 1281 break;
1257 if (phy_status & MII_SR_AUTON 1282 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1258 break; 1283 break;
1259 msleep(100); 1284 msleep(100);
1260 } 1285 }
1261 1286
1262 /* 1287 /*
1263 * PHY_AUTO_NEG_TIME expiration doesn 1288 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1264 * has completed. 1289 * has completed.
1265 */ 1290 */
1266 return ret_val; 1291 return ret_val;
1267 } 1292 }
1268 1293
1269 /** 1294 /**
1270 * igb_phy_has_link - Polls PHY for link !! 1295 * e1000_phy_has_link - Polls PHY for link
1271 * @hw: pointer to the HW structure 1296 * @hw: pointer to the HW structure
1272 * @iterations: number of times to poll for 1297 * @iterations: number of times to poll for link
1273 * @usec_interval: delay between polling att 1298 * @usec_interval: delay between polling attempts
1274 * @success: pointer to whether polling was 1299 * @success: pointer to whether polling was successful or not
1275 * 1300 *
1276 * Polls the PHY status register for link, ' 1301 * Polls the PHY status register for link, 'iterations' number of times.
1277 **/ 1302 **/
1278 s32 igb_phy_has_link(struct e1000_hw *hw, u32 1303 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1279 u32 usec_inter 1304 u32 usec_interval, bool *success)
1280 { 1305 {
1281 s32 ret_val = 0; 1306 s32 ret_val = 0;
1282 u16 i, phy_status; 1307 u16 i, phy_status;
1283 1308
1284 for (i = 0; i < iterations; i++) { 1309 for (i = 0; i < iterations; i++) {
1285 /* 1310 /*
1286 * Some PHYs require the PHY_ 1311 * Some PHYs require the PHY_STATUS register to be read
1287 * twice due to the link bit 1312 * twice due to the link bit being sticky. No harm doing
1288 * it across the board. 1313 * it across the board.
1289 */ 1314 */
1290 ret_val = hw->phy.ops.read_re !! 1315 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1291 if (ret_val) 1316 if (ret_val)
1292 break; 1317 break;
1293 ret_val = hw->phy.ops.read_re !! 1318 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1294 if (ret_val) 1319 if (ret_val)
1295 break; 1320 break;
1296 if (phy_status & MII_SR_LINK_ 1321 if (phy_status & MII_SR_LINK_STATUS)
1297 break; 1322 break;
1298 if (usec_interval >= 1000) 1323 if (usec_interval >= 1000)
1299 mdelay(usec_interval/ 1324 mdelay(usec_interval/1000);
1300 else 1325 else
1301 udelay(usec_interval) 1326 udelay(usec_interval);
1302 } 1327 }
1303 1328
1304 *success = (i < iterations) ? true : 1329 *success = (i < iterations) ? true : false;
1305 1330
1306 return ret_val; 1331 return ret_val;
1307 } 1332 }
1308 1333
1309 /** 1334 /**
1310 * igb_get_cable_length_m88 - Determine cabl !! 1335 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1311 * @hw: pointer to the HW structure 1336 * @hw: pointer to the HW structure
1312 * 1337 *
1313 * Reads the PHY specific status register to 1338 * Reads the PHY specific status register to retrieve the cable length
1314 * information. The cable length is determi 1339 * information. The cable length is determined by averaging the minimum and
1315 * maximum values to get the "average" cable 1340 * maximum values to get the "average" cable length. The m88 PHY has four
1316 * possible cable length values, which are: 1341 * possible cable length values, which are:
1317 * Register Value Cable Length 1342 * Register Value Cable Length
1318 * 0 < 50 meters 1343 * 0 < 50 meters
1319 * 1 50 - 80 meter 1344 * 1 50 - 80 meters
1320 * 2 80 - 110 mete 1345 * 2 80 - 110 meters
1321 * 3 110 - 140 met 1346 * 3 110 - 140 meters
1322 * 4 > 140 meters 1347 * 4 > 140 meters
1323 **/ 1348 **/
1324 s32 igb_get_cable_length_m88(struct e1000_hw 1349 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1325 { 1350 {
1326 struct e1000_phy_info *phy = &hw->phy 1351 struct e1000_phy_info *phy = &hw->phy;
1327 s32 ret_val; 1352 s32 ret_val;
1328 u16 phy_data, index; 1353 u16 phy_data, index;
1329 1354
1330 ret_val = phy->ops.read_reg(hw, M88E1 !! 1355 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
>> 1356 &phy_data);
1331 if (ret_val) 1357 if (ret_val)
1332 goto out; 1358 goto out;
1333 1359
1334 index = (phy_data & M88E1000_PSSR_CAB 1360 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1335 M88E1000_PSSR_CABLE_LENGTH_SH 1361 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1336 phy->min_cable_length = e1000_m88_cab 1362 phy->min_cable_length = e1000_m88_cable_length_table[index];
1337 phy->max_cable_length = e1000_m88_cab 1363 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1338 1364
1339 phy->cable_length = (phy->min_cable_l 1365 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1340 1366
1341 out: 1367 out:
1342 return ret_val; 1368 return ret_val;
1343 } 1369 }
1344 1370
1345 /** 1371 /**
1346 * igb_get_cable_length_igp_2 - Determine ca !! 1372 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1347 * @hw: pointer to the HW structure 1373 * @hw: pointer to the HW structure
1348 * 1374 *
1349 * The automatic gain control (agc) normaliz 1375 * The automatic gain control (agc) normalizes the amplitude of the
1350 * received signal, adjusting for the attenu 1376 * received signal, adjusting for the attenuation produced by the
1351 * cable. By reading the AGC registers, whi !! 1377 * cable. By reading the AGC registers, which reperesent the
1352 * combination of coarse and fine gain value !! 1378 * cobination of course and fine gain value, the value can be put
1353 * into a lookup table to obtain the approxi 1379 * into a lookup table to obtain the approximate cable length
1354 * for each channel. 1380 * for each channel.
1355 **/ 1381 **/
1356 s32 igb_get_cable_length_igp_2(struct e1000_h 1382 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1357 { 1383 {
1358 struct e1000_phy_info *phy = &hw->phy 1384 struct e1000_phy_info *phy = &hw->phy;
1359 s32 ret_val = 0; 1385 s32 ret_val = 0;
1360 u16 phy_data, i, agc_value = 0; 1386 u16 phy_data, i, agc_value = 0;
1361 u16 cur_agc_index, max_agc_index = 0; 1387 u16 cur_agc_index, max_agc_index = 0;
1362 u16 min_agc_index = IGP02E1000_CABLE_ 1388 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1363 u16 agc_reg_array[IGP02E1000_PHY_CHAN 1389 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1364 1390 {IGP02E1000_PHY_AGC_A,
1365 1391 IGP02E1000_PHY_AGC_B,
1366 1392 IGP02E1000_PHY_AGC_C,
1367 1393 IGP02E1000_PHY_AGC_D};
1368 1394
1369 /* Read the AGC registers for all cha 1395 /* Read the AGC registers for all channels */
1370 for (i = 0; i < IGP02E1000_PHY_CHANNE 1396 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1371 ret_val = phy->ops.read_reg(h !! 1397 ret_val = hw->phy.ops.read_phy_reg(hw, agc_reg_array[i],
>> 1398 &phy_data);
1372 if (ret_val) 1399 if (ret_val)
1373 goto out; 1400 goto out;
1374 1401
1375 /* 1402 /*
1376 * Getting bits 15:9, which r 1403 * Getting bits 15:9, which represent the combination of
1377 * coarse and fine gain value !! 1404 * course and fine gain values. The result is a number
1378 * that can be put into the l 1405 * that can be put into the lookup table to obtain the
1379 * approximate cable length. 1406 * approximate cable length.
1380 */ 1407 */
1381 cur_agc_index = (phy_data >> 1408 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1382 IGP02E1000_AG 1409 IGP02E1000_AGC_LENGTH_MASK;
1383 1410
1384 /* Array index bound check. * 1411 /* Array index bound check. */
1385 if ((cur_agc_index >= IGP02E1 1412 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1386 (cur_agc_index == 0)) { 1413 (cur_agc_index == 0)) {
1387 ret_val = -E1000_ERR_ 1414 ret_val = -E1000_ERR_PHY;
1388 goto out; 1415 goto out;
1389 } 1416 }
1390 1417
1391 /* Remove min & max AGC value 1418 /* Remove min & max AGC values from calculation. */
1392 if (e1000_igp_2_cable_length_ 1419 if (e1000_igp_2_cable_length_table[min_agc_index] >
1393 e1000_igp_2_cable_length_ 1420 e1000_igp_2_cable_length_table[cur_agc_index])
1394 min_agc_index = cur_a 1421 min_agc_index = cur_agc_index;
1395 if (e1000_igp_2_cable_length_ 1422 if (e1000_igp_2_cable_length_table[max_agc_index] <
1396 e1000_igp_2_cable_length_ 1423 e1000_igp_2_cable_length_table[cur_agc_index])
1397 max_agc_index = cur_a 1424 max_agc_index = cur_agc_index;
1398 1425
1399 agc_value += e1000_igp_2_cabl 1426 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1400 } 1427 }
1401 1428
1402 agc_value -= (e1000_igp_2_cable_lengt 1429 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1403 e1000_igp_2_cable_lengt 1430 e1000_igp_2_cable_length_table[max_agc_index]);
1404 agc_value /= (IGP02E1000_PHY_CHANNEL_ 1431 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1405 1432
1406 /* Calculate cable length with the er 1433 /* Calculate cable length with the error range of +/- 10 meters. */
1407 phy->min_cable_length = ((agc_value - 1434 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1408 (agc_value - 1435 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1409 phy->max_cable_length = agc_value + I 1436 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1410 1437
1411 phy->cable_length = (phy->min_cable_l 1438 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1412 1439
1413 out: 1440 out:
1414 return ret_val; 1441 return ret_val;
1415 } 1442 }
1416 1443
1417 /** 1444 /**
1418 * igb_get_phy_info_m88 - Retrieve PHY infor !! 1445 * e1000_get_phy_info_m88 - Retrieve PHY information
1419 * @hw: pointer to the HW structure 1446 * @hw: pointer to the HW structure
1420 * 1447 *
1421 * Valid for only copper links. Read the PH 1448 * Valid for only copper links. Read the PHY status register (sticky read)
1422 * to verify that link is up. Read the PHY 1449 * to verify that link is up. Read the PHY special control register to
1423 * determine the polarity and 10base-T exten 1450 * determine the polarity and 10base-T extended distance. Read the PHY
1424 * special status register to determine MDI/ 1451 * special status register to determine MDI/MDIx and current speed. If
1425 * speed is 1000, then determine cable lengt 1452 * speed is 1000, then determine cable length, local and remote receiver.
1426 **/ 1453 **/
1427 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1454 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1428 { 1455 {
1429 struct e1000_phy_info *phy = &hw->phy 1456 struct e1000_phy_info *phy = &hw->phy;
1430 s32 ret_val; 1457 s32 ret_val;
1431 u16 phy_data; 1458 u16 phy_data;
1432 bool link; 1459 bool link;
1433 1460
1434 if (phy->media_type != e1000_media_ty !! 1461 if (hw->phy.media_type != e1000_media_type_copper) {
1435 hw_dbg("Phy info is only vali !! 1462 hw_dbg(hw, "Phy info is only valid for copper media\n");
1436 ret_val = -E1000_ERR_CONFIG; 1463 ret_val = -E1000_ERR_CONFIG;
1437 goto out; 1464 goto out;
1438 } 1465 }
1439 1466
1440 ret_val = igb_phy_has_link(hw, 1, 0, 1467 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1441 if (ret_val) 1468 if (ret_val)
1442 goto out; 1469 goto out;
1443 1470
1444 if (!link) { 1471 if (!link) {
1445 hw_dbg("Phy info is only vali !! 1472 hw_dbg(hw, "Phy info is only valid if link is up\n");
1446 ret_val = -E1000_ERR_CONFIG; 1473 ret_val = -E1000_ERR_CONFIG;
1447 goto out; 1474 goto out;
1448 } 1475 }
1449 1476
1450 ret_val = phy->ops.read_reg(hw, M88E1 !! 1477 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
>> 1478 &phy_data);
1451 if (ret_val) 1479 if (ret_val)
1452 goto out; 1480 goto out;
1453 1481
1454 phy->polarity_correction = (phy_data 1482 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1455 ? true : f !! 1483 ? true
>> 1484 : false;
1456 1485
1457 ret_val = igb_check_polarity_m88(hw); 1486 ret_val = igb_check_polarity_m88(hw);
1458 if (ret_val) 1487 if (ret_val)
1459 goto out; 1488 goto out;
1460 1489
1461 ret_val = phy->ops.read_reg(hw, M88E1 !! 1490 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
>> 1491 &phy_data);
1462 if (ret_val) 1492 if (ret_val)
1463 goto out; 1493 goto out;
1464 1494
1465 phy->is_mdix = (phy_data & M88E1000_P 1495 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1466 1496
1467 if ((phy_data & M88E1000_PSSR_SPEED) 1497 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1468 ret_val = phy->ops.get_cable_ !! 1498 ret_val = hw->phy.ops.get_cable_length(hw);
1469 if (ret_val) 1499 if (ret_val)
1470 goto out; 1500 goto out;
1471 1501
1472 ret_val = phy->ops.read_reg(h !! 1502 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
>> 1503 &phy_data);
1473 if (ret_val) 1504 if (ret_val)
1474 goto out; 1505 goto out;
1475 1506
1476 phy->local_rx = (phy_data & S 1507 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1477 ? e1000_1000t 1508 ? e1000_1000t_rx_status_ok
1478 : e1000_1000t 1509 : e1000_1000t_rx_status_not_ok;
1479 1510
1480 phy->remote_rx = (phy_data & 1511 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1481 ? e1000_1000 1512 ? e1000_1000t_rx_status_ok
1482 : e1000_1000 1513 : e1000_1000t_rx_status_not_ok;
1483 } else { 1514 } else {
1484 /* Set values to "undefined" 1515 /* Set values to "undefined" */
1485 phy->cable_length = E1000_CAB 1516 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1486 phy->local_rx = e1000_1000t_r 1517 phy->local_rx = e1000_1000t_rx_status_undefined;
1487 phy->remote_rx = e1000_1000t_ 1518 phy->remote_rx = e1000_1000t_rx_status_undefined;
1488 } 1519 }
1489 1520
1490 out: 1521 out:
1491 return ret_val; 1522 return ret_val;
1492 } 1523 }
1493 1524
1494 /** 1525 /**
1495 * igb_get_phy_info_igp - Retrieve igp PHY i !! 1526 * e1000_get_phy_info_igp - Retrieve igp PHY information
1496 * @hw: pointer to the HW structure 1527 * @hw: pointer to the HW structure
1497 * 1528 *
1498 * Read PHY status to determine if link is u 1529 * Read PHY status to determine if link is up. If link is up, then
1499 * set/determine 10base-T extended distance 1530 * set/determine 10base-T extended distance and polarity correction. Read
1500 * PHY port status to determine MDI/MDIx and 1531 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1501 * determine on the cable length, local and 1532 * determine on the cable length, local and remote receiver.
1502 **/ 1533 **/
1503 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 1534 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1504 { 1535 {
1505 struct e1000_phy_info *phy = &hw->phy 1536 struct e1000_phy_info *phy = &hw->phy;
1506 s32 ret_val; 1537 s32 ret_val;
1507 u16 data; 1538 u16 data;
1508 bool link; 1539 bool link;
1509 1540
1510 ret_val = igb_phy_has_link(hw, 1, 0, 1541 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1511 if (ret_val) 1542 if (ret_val)
1512 goto out; 1543 goto out;
1513 1544
1514 if (!link) { 1545 if (!link) {
1515 hw_dbg("Phy info is only vali !! 1546 hw_dbg(hw, "Phy info is only valid if link is up\n");
1516 ret_val = -E1000_ERR_CONFIG; 1547 ret_val = -E1000_ERR_CONFIG;
1517 goto out; 1548 goto out;
1518 } 1549 }
1519 1550
1520 phy->polarity_correction = true; 1551 phy->polarity_correction = true;
1521 1552
1522 ret_val = igb_check_polarity_igp(hw); 1553 ret_val = igb_check_polarity_igp(hw);
1523 if (ret_val) 1554 if (ret_val)
1524 goto out; 1555 goto out;
1525 1556
1526 ret_val = phy->ops.read_reg(hw, IGP01 !! 1557 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
>> 1558 &data);
1527 if (ret_val) 1559 if (ret_val)
1528 goto out; 1560 goto out;
1529 1561
1530 phy->is_mdix = (data & IGP01E1000_PSS 1562 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1531 1563
1532 if ((data & IGP01E1000_PSSR_SPEED_MAS 1564 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1533 IGP01E1000_PSSR_SPEED_1000MBPS) { 1565 IGP01E1000_PSSR_SPEED_1000MBPS) {
1534 ret_val = phy->ops.get_cable_ !! 1566 ret_val = hw->phy.ops.get_cable_length(hw);
1535 if (ret_val) 1567 if (ret_val)
1536 goto out; 1568 goto out;
1537 1569
1538 ret_val = phy->ops.read_reg(h !! 1570 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
>> 1571 &data);
1539 if (ret_val) 1572 if (ret_val)
1540 goto out; 1573 goto out;
1541 1574
1542 phy->local_rx = (data & SR_10 1575 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1543 ? e1000_1000t 1576 ? e1000_1000t_rx_status_ok
1544 : e1000_1000t 1577 : e1000_1000t_rx_status_not_ok;
1545 1578
1546 phy->remote_rx = (data & SR_1 1579 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1547 ? e1000_1000 1580 ? e1000_1000t_rx_status_ok
1548 : e1000_1000 1581 : e1000_1000t_rx_status_not_ok;
1549 } else { 1582 } else {
1550 phy->cable_length = E1000_CAB 1583 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1551 phy->local_rx = e1000_1000t_r 1584 phy->local_rx = e1000_1000t_rx_status_undefined;
1552 phy->remote_rx = e1000_1000t_ 1585 phy->remote_rx = e1000_1000t_rx_status_undefined;
1553 } 1586 }
1554 1587
1555 out: 1588 out:
1556 return ret_val; 1589 return ret_val;
1557 } 1590 }
1558 1591
1559 /** 1592 /**
1560 * igb_phy_sw_reset - PHY software reset !! 1593 * e1000_phy_sw_reset - PHY software reset
1561 * @hw: pointer to the HW structure 1594 * @hw: pointer to the HW structure
1562 * 1595 *
1563 * Does a software reset of the PHY by readi 1596 * Does a software reset of the PHY by reading the PHY control register and
1564 * setting/write the control register reset 1597 * setting/write the control register reset bit to the PHY.
1565 **/ 1598 **/
1566 s32 igb_phy_sw_reset(struct e1000_hw *hw) 1599 s32 igb_phy_sw_reset(struct e1000_hw *hw)
1567 { 1600 {
1568 s32 ret_val; 1601 s32 ret_val;
1569 u16 phy_ctrl; 1602 u16 phy_ctrl;
1570 1603
1571 ret_val = hw->phy.ops.read_reg(hw, PH !! 1604 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
1572 if (ret_val) 1605 if (ret_val)
1573 goto out; 1606 goto out;
1574 1607
1575 phy_ctrl |= MII_CR_RESET; 1608 phy_ctrl |= MII_CR_RESET;
1576 ret_val = hw->phy.ops.write_reg(hw, P !! 1609 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
1577 if (ret_val) 1610 if (ret_val)
1578 goto out; 1611 goto out;
1579 1612
1580 udelay(1); 1613 udelay(1);
1581 1614
1582 out: 1615 out:
1583 return ret_val; 1616 return ret_val;
1584 } 1617 }
1585 1618
1586 /** 1619 /**
1587 * igb_phy_hw_reset - PHY hardware reset !! 1620 * e1000_phy_hw_reset - PHY hardware reset
1588 * @hw: pointer to the HW structure 1621 * @hw: pointer to the HW structure
1589 * 1622 *
1590 * Verify the reset block is not blocking us 1623 * Verify the reset block is not blocking us from resetting. Acquire
1591 * semaphore (if necessary) and read/set/wri 1624 * semaphore (if necessary) and read/set/write the device control reset
1592 * bit in the PHY. Wait the appropriate del 1625 * bit in the PHY. Wait the appropriate delay time for the device to
1593 * reset and relase the semaphore (if necess 1626 * reset and relase the semaphore (if necessary).
1594 **/ 1627 **/
1595 s32 igb_phy_hw_reset(struct e1000_hw *hw) 1628 s32 igb_phy_hw_reset(struct e1000_hw *hw)
1596 { 1629 {
1597 struct e1000_phy_info *phy = &hw->phy 1630 struct e1000_phy_info *phy = &hw->phy;
1598 s32 ret_val; 1631 s32 ret_val;
1599 u32 ctrl; 1632 u32 ctrl;
1600 1633
1601 ret_val = igb_check_reset_block(hw); 1634 ret_val = igb_check_reset_block(hw);
1602 if (ret_val) { 1635 if (ret_val) {
1603 ret_val = 0; 1636 ret_val = 0;
1604 goto out; 1637 goto out;
1605 } 1638 }
1606 1639
1607 ret_val = phy->ops.acquire(hw); !! 1640 ret_val = igb_acquire_phy(hw);
1608 if (ret_val) 1641 if (ret_val)
1609 goto out; 1642 goto out;
1610 1643
1611 ctrl = rd32(E1000_CTRL); 1644 ctrl = rd32(E1000_CTRL);
1612 wr32(E1000_CTRL, ctrl | E1000_CTRL_PH 1645 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1613 wrfl(); 1646 wrfl();
1614 1647
1615 udelay(phy->reset_delay_us); 1648 udelay(phy->reset_delay_us);
1616 1649
1617 wr32(E1000_CTRL, ctrl); 1650 wr32(E1000_CTRL, ctrl);
1618 wrfl(); 1651 wrfl();
1619 1652
1620 udelay(150); 1653 udelay(150);
1621 1654
1622 phy->ops.release(hw); !! 1655 igb_release_phy(hw);
1623 1656
1624 ret_val = phy->ops.get_cfg_done(hw); !! 1657 ret_val = igb_get_phy_cfg_done(hw);
1625 1658
1626 out: 1659 out:
1627 return ret_val; 1660 return ret_val;
1628 } 1661 }
1629 1662
>> 1663 /* Internal function pointers */
>> 1664
>> 1665 /**
>> 1666 * e1000_get_phy_cfg_done - Generic PHY configuration done
>> 1667 * @hw: pointer to the HW structure
>> 1668 *
>> 1669 * Return success if silicon family did not implement a family specific
>> 1670 * get_cfg_done function.
>> 1671 **/
>> 1672 static s32 igb_get_phy_cfg_done(struct e1000_hw *hw)
>> 1673 {
>> 1674 if (hw->phy.ops.get_cfg_done)
>> 1675 return hw->phy.ops.get_cfg_done(hw);
>> 1676
>> 1677 return 0;
>> 1678 }
>> 1679
>> 1680 /**
>> 1681 * e1000_release_phy - Generic release PHY
>> 1682 * @hw: pointer to the HW structure
>> 1683 *
>> 1684 * Return if silicon family does not require a semaphore when accessing the
>> 1685 * PHY.
>> 1686 **/
>> 1687 static void igb_release_phy(struct e1000_hw *hw)
>> 1688 {
>> 1689 if (hw->phy.ops.release_phy)
>> 1690 hw->phy.ops.release_phy(hw);
>> 1691 }
>> 1692
>> 1693 /**
>> 1694 * e1000_acquire_phy - Generic acquire PHY
>> 1695 * @hw: pointer to the HW structure
>> 1696 *
>> 1697 * Return success if silicon family does not require a semaphore when
>> 1698 * accessing the PHY.
>> 1699 **/
>> 1700 static s32 igb_acquire_phy(struct e1000_hw *hw)
>> 1701 {
>> 1702 if (hw->phy.ops.acquire_phy)
>> 1703 return hw->phy.ops.acquire_phy(hw);
>> 1704
>> 1705 return 0;
>> 1706 }
>> 1707
>> 1708 /**
>> 1709 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
>> 1710 * @hw: pointer to the HW structure
>> 1711 *
>> 1712 * When the silicon family has not implemented a forced speed/duplex
>> 1713 * function for the PHY, simply return 0.
>> 1714 **/
>> 1715 s32 igb_phy_force_speed_duplex(struct e1000_hw *hw)
>> 1716 {
>> 1717 if (hw->phy.ops.force_speed_duplex)
>> 1718 return hw->phy.ops.force_speed_duplex(hw);
>> 1719
>> 1720 return 0;
>> 1721 }
>> 1722
1630 /** 1723 /**
1631 * igb_phy_init_script_igp3 - Inits the IGP3 !! 1724 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1632 * @hw: pointer to the HW structure 1725 * @hw: pointer to the HW structure
1633 * 1726 *
1634 * Initializes a Intel Gigabit PHY3 when an 1727 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1635 **/ 1728 **/
1636 s32 igb_phy_init_script_igp3(struct e1000_hw 1729 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1637 { 1730 {
1638 hw_dbg("Running IGP 3 PHY init script !! 1731 hw_dbg(hw, "Running IGP 3 PHY init script\n");
1639 1732
1640 /* PHY init IGP 3 */ 1733 /* PHY init IGP 3 */
1641 /* Enable rise/fall, 10-mode work in 1734 /* Enable rise/fall, 10-mode work in class-A */
1642 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9 !! 1735 hw->phy.ops.write_phy_reg(hw, 0x2F5B, 0x9018);
1643 /* Remove all caps from Replica path 1736 /* Remove all caps from Replica path filter */
1644 hw->phy.ops.write_reg(hw, 0x2F52, 0x0 !! 1737 hw->phy.ops.write_phy_reg(hw, 0x2F52, 0x0000);
1645 /* Bias trimming for ADC, AFE and Dri 1738 /* Bias trimming for ADC, AFE and Driver (Default) */
1646 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8 !! 1739 hw->phy.ops.write_phy_reg(hw, 0x2FB1, 0x8B24);
1647 /* Increase Hybrid poly bias */ 1740 /* Increase Hybrid poly bias */
1648 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF !! 1741 hw->phy.ops.write_phy_reg(hw, 0x2FB2, 0xF8F0);
1649 /* Add 4% to TX amplitude in Giga mod 1742 /* Add 4% to TX amplitude in Giga mode */
1650 hw->phy.ops.write_reg(hw, 0x2010, 0x1 !! 1743 hw->phy.ops.write_phy_reg(hw, 0x2010, 0x10B0);
1651 /* Disable trimming (TTT) */ 1744 /* Disable trimming (TTT) */
1652 hw->phy.ops.write_reg(hw, 0x2011, 0x0 !! 1745 hw->phy.ops.write_phy_reg(hw, 0x2011, 0x0000);
1653 /* Poly DC correction to 94.6% + 2% f 1746 /* Poly DC correction to 94.6% + 2% for all channels */
1654 hw->phy.ops.write_reg(hw, 0x20DD, 0x2 !! 1747 hw->phy.ops.write_phy_reg(hw, 0x20DD, 0x249A);
1655 /* ABS DC correction to 95.9% */ 1748 /* ABS DC correction to 95.9% */
1656 hw->phy.ops.write_reg(hw, 0x20DE, 0x0 !! 1749 hw->phy.ops.write_phy_reg(hw, 0x20DE, 0x00D3);
1657 /* BG temp curve trim */ 1750 /* BG temp curve trim */
1658 hw->phy.ops.write_reg(hw, 0x28B4, 0x0 !! 1751 hw->phy.ops.write_phy_reg(hw, 0x28B4, 0x04CE);
1659 /* Increasing ADC OPAMP stage 1 curre 1752 /* Increasing ADC OPAMP stage 1 currents to max */
1660 hw->phy.ops.write_reg(hw, 0x2F70, 0x2 !! 1753 hw->phy.ops.write_phy_reg(hw, 0x2F70, 0x29E4);
1661 /* Force 1000 ( required for enabling 1754 /* Force 1000 ( required for enabling PHY regs configuration) */
1662 hw->phy.ops.write_reg(hw, 0x0000, 0x0 !! 1755 hw->phy.ops.write_phy_reg(hw, 0x0000, 0x0140);
1663 /* Set upd_freq to 6 */ 1756 /* Set upd_freq to 6 */
1664 hw->phy.ops.write_reg(hw, 0x1F30, 0x1 !! 1757 hw->phy.ops.write_phy_reg(hw, 0x1F30, 0x1606);
1665 /* Disable NPDFE */ 1758 /* Disable NPDFE */
1666 hw->phy.ops.write_reg(hw, 0x1F31, 0xB !! 1759 hw->phy.ops.write_phy_reg(hw, 0x1F31, 0xB814);
1667 /* Disable adaptive fixed FFE (Defaul 1760 /* Disable adaptive fixed FFE (Default) */
1668 hw->phy.ops.write_reg(hw, 0x1F35, 0x0 !! 1761 hw->phy.ops.write_phy_reg(hw, 0x1F35, 0x002A);
1669 /* Enable FFE hysteresis */ 1762 /* Enable FFE hysteresis */
1670 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0 !! 1763 hw->phy.ops.write_phy_reg(hw, 0x1F3E, 0x0067);
1671 /* Fixed FFE for short cable lengths 1764 /* Fixed FFE for short cable lengths */
1672 hw->phy.ops.write_reg(hw, 0x1F54, 0x0 !! 1765 hw->phy.ops.write_phy_reg(hw, 0x1F54, 0x0065);
1673 /* Fixed FFE for medium cable lengths 1766 /* Fixed FFE for medium cable lengths */
1674 hw->phy.ops.write_reg(hw, 0x1F55, 0x0 !! 1767 hw->phy.ops.write_phy_reg(hw, 0x1F55, 0x002A);
1675 /* Fixed FFE for long cable lengths * 1768 /* Fixed FFE for long cable lengths */
1676 hw->phy.ops.write_reg(hw, 0x1F56, 0x0 !! 1769 hw->phy.ops.write_phy_reg(hw, 0x1F56, 0x002A);
1677 /* Enable Adaptive Clip Threshold */ 1770 /* Enable Adaptive Clip Threshold */
1678 hw->phy.ops.write_reg(hw, 0x1F72, 0x3 !! 1771 hw->phy.ops.write_phy_reg(hw, 0x1F72, 0x3FB0);
1679 /* AHT reset limit to 1 */ 1772 /* AHT reset limit to 1 */
1680 hw->phy.ops.write_reg(hw, 0x1F76, 0xC !! 1773 hw->phy.ops.write_phy_reg(hw, 0x1F76, 0xC0FF);
1681 /* Set AHT master delay to 127 msec * 1774 /* Set AHT master delay to 127 msec */
1682 hw->phy.ops.write_reg(hw, 0x1F77, 0x1 !! 1775 hw->phy.ops.write_phy_reg(hw, 0x1F77, 0x1DEC);
1683 /* Set scan bits for AHT */ 1776 /* Set scan bits for AHT */
1684 hw->phy.ops.write_reg(hw, 0x1F78, 0xF !! 1777 hw->phy.ops.write_phy_reg(hw, 0x1F78, 0xF9EF);
1685 /* Set AHT Preset bits */ 1778 /* Set AHT Preset bits */
1686 hw->phy.ops.write_reg(hw, 0x1F79, 0x0 !! 1779 hw->phy.ops.write_phy_reg(hw, 0x1F79, 0x0210);
1687 /* Change integ_factor of channel A t 1780 /* Change integ_factor of channel A to 3 */
1688 hw->phy.ops.write_reg(hw, 0x1895, 0x0 !! 1781 hw->phy.ops.write_phy_reg(hw, 0x1895, 0x0003);
1689 /* Change prop_factor of channels BCD 1782 /* Change prop_factor of channels BCD to 8 */
1690 hw->phy.ops.write_reg(hw, 0x1796, 0x0 !! 1783 hw->phy.ops.write_phy_reg(hw, 0x1796, 0x0008);
1691 /* Change cg_icount + enable integbp 1784 /* Change cg_icount + enable integbp for channels BCD */
1692 hw->phy.ops.write_reg(hw, 0x1798, 0xD !! 1785 hw->phy.ops.write_phy_reg(hw, 0x1798, 0xD008);
1693 /* 1786 /*
1694 * Change cg_icount + enable integbp 1787 * Change cg_icount + enable integbp + change prop_factor_master
1695 * to 8 for channel A 1788 * to 8 for channel A
1696 */ 1789 */
1697 hw->phy.ops.write_reg(hw, 0x1898, 0xD !! 1790 hw->phy.ops.write_phy_reg(hw, 0x1898, 0xD918);
1698 /* Disable AHT in Slave mode on chann 1791 /* Disable AHT in Slave mode on channel A */
1699 hw->phy.ops.write_reg(hw, 0x187A, 0x0 !! 1792 hw->phy.ops.write_phy_reg(hw, 0x187A, 0x0800);
1700 /* 1793 /*
1701 * Enable LPLU and disable AN to 1000 1794 * Enable LPLU and disable AN to 1000 in non-D0a states,
1702 * Enable SPD+B2B 1795 * Enable SPD+B2B
1703 */ 1796 */
1704 hw->phy.ops.write_reg(hw, 0x0019, 0x0 !! 1797 hw->phy.ops.write_phy_reg(hw, 0x0019, 0x008D);
1705 /* Enable restart AN on an1000_dis ch 1798 /* Enable restart AN on an1000_dis change */
1706 hw->phy.ops.write_reg(hw, 0x001B, 0x2 !! 1799 hw->phy.ops.write_phy_reg(hw, 0x001B, 0x2080);
1707 /* Enable wh_fifo read clock in 10/10 1800 /* Enable wh_fifo read clock in 10/100 modes */
1708 hw->phy.ops.write_reg(hw, 0x0014, 0x0 !! 1801 hw->phy.ops.write_phy_reg(hw, 0x0014, 0x0045);
1709 /* Restart AN, Speed selection is 100 1802 /* Restart AN, Speed selection is 1000 */
1710 hw->phy.ops.write_reg(hw, 0x0000, 0x1 !! 1803 hw->phy.ops.write_phy_reg(hw, 0x0000, 0x1340);
1711 1804
1712 return 0; 1805 return 0;
1713 } 1806 }
1714 1807
1715 1808
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