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1 /* 1 /*
2 * Fast Ethernet Controller (FEC) driver for M 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.ne 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 * 4 *
5 * This version of the driver is specific to t 5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers 6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 tran 7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal pa 8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D. 9 * is basically all of Port D.
10 * 10 *
11 * Right now, I am very watseful with the buff !! 11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame bu 12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame 13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 1 14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will 15 * will be much more memory efficient and will easily handle lots of
16 * small packets. 16 * small packets.
17 * 17 *
18 * Much better multiple PHY support by Magnus 18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems A 19 * Copyright (c) 2000 Ericsson Radio Systems AB.
20 * 20 *
21 * Support for FEC controller of ColdFire/5270 !! 21 * Support for FEC controller of ColdFire processors.
22 * Copyrught (c) 2001-2004 Greg Ungerer (gerg@ !! 22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
>> 23 *
>> 24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
>> 25 * Copyright (c) 2004-2006 Macq Electronique SA.
23 */ 26 */
24 27
25 #include <linux/config.h> <<
26 #include <linux/module.h> 28 #include <linux/module.h>
27 #include <linux/kernel.h> 29 #include <linux/kernel.h>
28 #include <linux/string.h> 30 #include <linux/string.h>
29 #include <linux/ptrace.h> 31 #include <linux/ptrace.h>
30 #include <linux/errno.h> 32 #include <linux/errno.h>
31 #include <linux/ioport.h> 33 #include <linux/ioport.h>
32 #include <linux/slab.h> 34 #include <linux/slab.h>
33 #include <linux/interrupt.h> 35 #include <linux/interrupt.h>
34 #include <linux/pci.h> 36 #include <linux/pci.h>
35 #include <linux/init.h> 37 #include <linux/init.h>
36 #include <linux/delay.h> 38 #include <linux/delay.h>
37 #include <linux/netdevice.h> 39 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h> 40 #include <linux/etherdevice.h>
39 #include <linux/skbuff.h> 41 #include <linux/skbuff.h>
40 #include <linux/spinlock.h> 42 #include <linux/spinlock.h>
41 #include <linux/workqueue.h> 43 #include <linux/workqueue.h>
42 #include <linux/bitops.h> 44 #include <linux/bitops.h>
43 45
44 #include <asm/irq.h> 46 #include <asm/irq.h>
45 #include <asm/uaccess.h> 47 #include <asm/uaccess.h>
46 #include <asm/io.h> 48 #include <asm/io.h>
47 #include <asm/pgtable.h> 49 #include <asm/pgtable.h>
>> 50 #include <asm/cacheflush.h>
48 51
49 #if defined(CONFIG_M527x) || defined(CONFIG_M5 !! 52 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
>> 53 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
>> 54 defined(CONFIG_M520x) || defined(CONFIG_M532x)
50 #include <asm/coldfire.h> 55 #include <asm/coldfire.h>
51 #include <asm/mcfsim.h> 56 #include <asm/mcfsim.h>
52 #include "fec.h" 57 #include "fec.h"
53 #else 58 #else
54 #include <asm/8xx_immap.h> 59 #include <asm/8xx_immap.h>
55 #include <asm/mpc8xx.h> 60 #include <asm/mpc8xx.h>
56 #include "commproc.h" 61 #include "commproc.h"
57 #endif 62 #endif
58 63
59 #if defined(CONFIG_FEC2) 64 #if defined(CONFIG_FEC2)
60 #define FEC_MAX_PORTS 2 65 #define FEC_MAX_PORTS 2
61 #else 66 #else
62 #define FEC_MAX_PORTS 1 67 #define FEC_MAX_PORTS 1
63 #endif 68 #endif
64 69
65 /* 70 /*
66 * Define the fixed address of the FEC hardwar 71 * Define the fixed address of the FEC hardware.
67 */ 72 */
68 static unsigned int fec_hw[] = { 73 static unsigned int fec_hw[] = {
69 #if defined(CONFIG_M5272) 74 #if defined(CONFIG_M5272)
70 (MCF_MBAR + 0x840), 75 (MCF_MBAR + 0x840),
71 #elif defined(CONFIG_M527x) 76 #elif defined(CONFIG_M527x)
72 (MCF_MBAR + 0x1000), 77 (MCF_MBAR + 0x1000),
73 (MCF_MBAR + 0x1800), 78 (MCF_MBAR + 0x1800),
74 #elif defined(CONFIG_M528x) !! 79 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
75 (MCF_MBAR + 0x1000), 80 (MCF_MBAR + 0x1000),
>> 81 #elif defined(CONFIG_M520x)
>> 82 (MCF_MBAR+0x30000),
>> 83 #elif defined(CONFIG_M532x)
>> 84 (MCF_MBAR+0xfc030000),
76 #else 85 #else
77 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fe 86 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
78 #endif 87 #endif
79 }; 88 };
80 89
81 static unsigned char fec_mac_default[] = { 90 static unsigned char fec_mac_default[] = {
82 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
83 }; 92 };
84 93
85 /* 94 /*
86 * Some hardware gets it MAC address out of lo 95 * Some hardware gets it MAC address out of local flash memory.
87 * if this is non-zero then assume it is the a 96 * if this is non-zero then assume it is the address to get MAC from.
88 */ 97 */
89 #if defined(CONFIG_NETtel) 98 #if defined(CONFIG_NETtel)
90 #define FEC_FLASHMAC 0xf0006006 99 #define FEC_FLASHMAC 0xf0006006
91 #elif defined(CONFIG_GILBARCONAP) || defined(C 100 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
92 #define FEC_FLASHMAC 0xf0006000 101 #define FEC_FLASHMAC 0xf0006000
93 #elif defined (CONFIG_MTD_KeyTechnology) <<
94 #define FEC_FLASHMAC 0xffe04000 <<
95 #elif defined(CONFIG_CANCam) 102 #elif defined(CONFIG_CANCam)
96 #define FEC_FLASHMAC 0xf0020000 103 #define FEC_FLASHMAC 0xf0020000
>> 104 #elif defined (CONFIG_M5272C3)
>> 105 #define FEC_FLASHMAC (0xffe04000 + 4)
>> 106 #elif defined(CONFIG_MOD5272)
>> 107 #define FEC_FLASHMAC 0xffc0406b
97 #else 108 #else
98 #define FEC_FLASHMAC 0 109 #define FEC_FLASHMAC 0
99 #endif 110 #endif
100 111
101 unsigned char *fec_flashmac = (unsigned char * <<
102 <<
103 /* Forward declarations of some structures to 112 /* Forward declarations of some structures to support different PHYs
104 */ 113 */
105 114
106 typedef struct { 115 typedef struct {
107 uint mii_data; 116 uint mii_data;
108 void (*funct)(uint mii_reg, struct net 117 void (*funct)(uint mii_reg, struct net_device *dev);
109 } phy_cmd_t; 118 } phy_cmd_t;
110 119
111 typedef struct { 120 typedef struct {
112 uint id; 121 uint id;
113 char *name; 122 char *name;
114 123
115 const phy_cmd_t *config; 124 const phy_cmd_t *config;
116 const phy_cmd_t *startup; 125 const phy_cmd_t *startup;
117 const phy_cmd_t *ack_int; 126 const phy_cmd_t *ack_int;
118 const phy_cmd_t *shutdown; 127 const phy_cmd_t *shutdown;
119 } phy_info_t; 128 } phy_info_t;
120 129
121 /* The number of Tx and Rx buffers. These are 130 /* The number of Tx and Rx buffers. These are allocated from the page
122 * pool. The code may assume these are power 131 * pool. The code may assume these are power of two, so it it best
123 * to keep them that size. 132 * to keep them that size.
124 * We don't need to allocate pages for the tra 133 * We don't need to allocate pages for the transmitter. We just use
125 * the skbuffer directly. 134 * the skbuffer directly.
126 */ 135 */
127 #define FEC_ENET_RX_PAGES 8 136 #define FEC_ENET_RX_PAGES 8
128 #define FEC_ENET_RX_FRSIZE 2048 137 #define FEC_ENET_RX_FRSIZE 2048
129 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / F 138 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
130 #define RX_RING_SIZE (FEC_ENET_RX_F 139 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
131 #define FEC_ENET_TX_FRSIZE 2048 140 #define FEC_ENET_TX_FRSIZE 2048
132 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / F 141 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
133 #define TX_RING_SIZE 16 /* Mus 142 #define TX_RING_SIZE 16 /* Must be power of two */
134 #define TX_RING_MOD_MASK 15 /* f 143 #define TX_RING_MOD_MASK 15 /* for this to work */
135 144
>> 145 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
>> 146 #error "FEC: descriptor ring size constants too large"
>> 147 #endif
>> 148
136 /* Interrupt events/masks. 149 /* Interrupt events/masks.
137 */ 150 */
138 #define FEC_ENET_HBERR ((uint)0x80000000) 151 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
139 #define FEC_ENET_BABR ((uint)0x40000000) 152 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
140 #define FEC_ENET_BABT ((uint)0x20000000) 153 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
141 #define FEC_ENET_GRA ((uint)0x10000000) 154 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
142 #define FEC_ENET_TXF ((uint)0x08000000) 155 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
143 #define FEC_ENET_TXB ((uint)0x04000000) 156 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
144 #define FEC_ENET_RXF ((uint)0x02000000) 157 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
145 #define FEC_ENET_RXB ((uint)0x01000000) 158 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
146 #define FEC_ENET_MII ((uint)0x00800000) 159 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
147 #define FEC_ENET_EBERR ((uint)0x00400000) 160 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
148 161
149 /* The FEC stores dest/src/type, data, and che 162 /* The FEC stores dest/src/type, data, and checksum for receive packets.
150 */ 163 */
151 #define PKT_MAXBUF_SIZE 1518 164 #define PKT_MAXBUF_SIZE 1518
152 #define PKT_MINBUF_SIZE 64 165 #define PKT_MINBUF_SIZE 64
153 #define PKT_MAXBLR_SIZE 1520 166 #define PKT_MAXBLR_SIZE 1520
154 167
155 168
156 /* 169 /*
157 * The 5270/5271/5280/5282 RX control register !! 170 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
158 * size bits. Other FEC hardware does not, so 171 * size bits. Other FEC hardware does not, so we need to take that into
159 * account when setting it. 172 * account when setting it.
160 */ 173 */
161 #if defined(CONFIG_M527x) || defined(CONFIG_M5 !! 174 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
>> 175 defined(CONFIG_M520x) || defined(CONFIG_M532x)
162 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16 176 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
163 #else 177 #else
164 #define OPT_FRAME_SIZE 0 178 #define OPT_FRAME_SIZE 0
165 #endif 179 #endif
166 180
167 /* The FEC buffer descriptors track the ring b 181 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
168 * tx_bd_base always point to the base of the 182 * tx_bd_base always point to the base of the buffer descriptors. The
169 * cur_rx and cur_tx point to the currently av 183 * cur_rx and cur_tx point to the currently available buffer.
170 * The dirty_tx tracks the current buffer that 184 * The dirty_tx tracks the current buffer that is being sent by the
171 * controller. The cur_tx and dirty_tx are eq 185 * controller. The cur_tx and dirty_tx are equal under both completely
172 * empty and completely full conditions. The 186 * empty and completely full conditions. The empty/ready indicator in
173 * the buffer descriptor determines the actual 187 * the buffer descriptor determines the actual condition.
174 */ 188 */
175 struct fec_enet_private { 189 struct fec_enet_private {
176 /* Hardware registers of the FEC devic 190 /* Hardware registers of the FEC device */
177 volatile fec_t *hwp; 191 volatile fec_t *hwp;
178 192
>> 193 struct net_device *netdev;
>> 194
179 /* The saved address of a sent-in-plac 195 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
180 unsigned char *tx_bounce[TX_RING_SIZE] 196 unsigned char *tx_bounce[TX_RING_SIZE];
181 struct sk_buff* tx_skbuff[TX_RING_SIZ 197 struct sk_buff* tx_skbuff[TX_RING_SIZE];
182 ushort skb_cur; 198 ushort skb_cur;
183 ushort skb_dirty; 199 ushort skb_dirty;
184 200
185 /* CPM dual port RAM relative addresse 201 /* CPM dual port RAM relative addresses.
186 */ 202 */
187 cbd_t *rx_bd_base; /* Add 203 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
188 cbd_t *tx_bd_base; 204 cbd_t *tx_bd_base;
189 cbd_t *cur_rx, *cur_tx; 205 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
190 cbd_t *dirty_tx; /* The ring en 206 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
191 struct net_device_stats stats; <<
192 uint tx_full; 207 uint tx_full;
193 spinlock_t lock; 208 spinlock_t lock;
194 209
195 uint phy_id; 210 uint phy_id;
196 uint phy_id_done; 211 uint phy_id_done;
197 uint phy_status; 212 uint phy_status;
198 uint phy_speed; 213 uint phy_speed;
199 phy_info_t *phy; !! 214 phy_info_t const *phy;
200 struct work_struct phy_task; 215 struct work_struct phy_task;
201 216
202 uint sequence_done; 217 uint sequence_done;
203 uint mii_phy_task_queued; 218 uint mii_phy_task_queued;
204 219
205 uint phy_addr; 220 uint phy_addr;
206 221
207 int index; 222 int index;
208 int opened; 223 int opened;
209 int link; 224 int link;
210 int old_link; 225 int old_link;
211 int full_duplex; 226 int full_duplex;
212 unsigned char mac_addr[ETH_ALEN]; <<
213 }; 227 };
214 228
215 static int fec_enet_open(struct net_device *de 229 static int fec_enet_open(struct net_device *dev);
216 static int fec_enet_start_xmit(struct sk_buff 230 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
217 static void fec_enet_mii(struct net_device *de 231 static void fec_enet_mii(struct net_device *dev);
218 static irqreturn_t fec_enet_interrupt(int irq, !! 232 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
219 static void fec_enet_tx(struct net_device *dev 233 static void fec_enet_tx(struct net_device *dev);
220 static void fec_enet_rx(struct net_device *dev 234 static void fec_enet_rx(struct net_device *dev);
221 static int fec_enet_close(struct net_device *d 235 static int fec_enet_close(struct net_device *dev);
222 static struct net_device_stats *fec_enet_get_s <<
223 static void set_multicast_list(struct net_devi 236 static void set_multicast_list(struct net_device *dev);
224 static void fec_restart(struct net_device *dev 237 static void fec_restart(struct net_device *dev, int duplex);
225 static void fec_stop(struct net_device *dev); 238 static void fec_stop(struct net_device *dev);
226 static void fec_set_mac_address(struct net_dev 239 static void fec_set_mac_address(struct net_device *dev);
227 240
228 241
229 /* MII processing. We keep this as simple as 242 /* MII processing. We keep this as simple as possible. Requests are
230 * placed on the list (if there is room). Whe 243 * placed on the list (if there is room). When the request is finished
231 * by the MII, an optional function may be cal 244 * by the MII, an optional function may be called.
232 */ 245 */
233 typedef struct mii_list { 246 typedef struct mii_list {
234 uint mii_regval; 247 uint mii_regval;
235 void (*mii_func)(uint val, struct n 248 void (*mii_func)(uint val, struct net_device *dev);
236 struct mii_list *mii_next; 249 struct mii_list *mii_next;
237 } mii_list_t; 250 } mii_list_t;
238 251
239 #define NMII 20 252 #define NMII 20
240 mii_list_t mii_cmds[NMII]; !! 253 static mii_list_t mii_cmds[NMII];
241 mii_list_t *mii_free; !! 254 static mii_list_t *mii_free;
242 mii_list_t *mii_head; !! 255 static mii_list_t *mii_head;
243 mii_list_t *mii_tail; !! 256 static mii_list_t *mii_tail;
244 257
245 static int mii_queue(struct net_device *d !! 258 static int mii_queue(struct net_device *dev, int request,
246 void (*func)(u 259 void (*func)(uint, struct net_device *));
247 260
248 /* Make MII read/write commands for the FEC. 261 /* Make MII read/write commands for the FEC.
249 */ 262 */
250 #define mk_mii_read(REG) (0x60020000 | 263 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
251 #define mk_mii_write(REG, VAL) (0x50020000 | 264 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
252 265 (VAL & 0xffff))
253 #define mk_mii_end 0 266 #define mk_mii_end 0
254 267
255 /* Transmitter timeout. 268 /* Transmitter timeout.
256 */ 269 */
257 #define TX_TIMEOUT (2*HZ) 270 #define TX_TIMEOUT (2*HZ)
258 271
259 /* Register definitions for the PHY. 272 /* Register definitions for the PHY.
260 */ 273 */
261 274
262 #define MII_REG_CR 0 /* Control Regi 275 #define MII_REG_CR 0 /* Control Register */
263 #define MII_REG_SR 1 /* Status Regis 276 #define MII_REG_SR 1 /* Status Register */
264 #define MII_REG_PHYIR1 2 /* PHY Identifi 277 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
265 #define MII_REG_PHYIR2 3 /* PHY Identifi 278 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
266 #define MII_REG_ANAR 4 /* A-N Advertis !! 279 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
267 #define MII_REG_ANLPAR 5 /* A-N Link Par 280 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
268 #define MII_REG_ANER 6 /* A-N Expansio 281 #define MII_REG_ANER 6 /* A-N Expansion Register */
269 #define MII_REG_ANNPTR 7 /* A-N Next Pag 282 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
270 #define MII_REG_ANLPRNPR 8 /* A-N Link Par 283 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
271 284
272 /* values for phy_status */ 285 /* values for phy_status */
273 286
274 #define PHY_CONF_ANE 0x0001 /* 1 auto-nego 287 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
275 #define PHY_CONF_LOOP 0x0002 /* 1 loopback 288 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
276 #define PHY_CONF_SPMASK 0x00f0 /* mask for sp 289 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
277 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit hal 290 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
278 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit ful !! 291 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
279 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit ha 292 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
280 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit fu !! 293 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
281 294
282 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 do 295 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
283 #define PHY_STAT_FAULT 0x0200 /* 1 remote fa 296 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
284 #define PHY_STAT_ANC 0x0400 /* 1 auto-nego 297 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
285 #define PHY_STAT_SPMASK 0xf000 /* mask for sp 298 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
286 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit hal 299 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
287 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit ful !! 300 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
288 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit ha 301 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
289 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit fu !! 302 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
290 303
291 304
292 static int 305 static int
293 fec_enet_start_xmit(struct sk_buff *skb, struc 306 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
294 { 307 {
295 struct fec_enet_private *fep; 308 struct fec_enet_private *fep;
296 volatile fec_t *fecp; 309 volatile fec_t *fecp;
297 volatile cbd_t *bdp; 310 volatile cbd_t *bdp;
>> 311 unsigned short status;
298 312
299 fep = netdev_priv(dev); 313 fep = netdev_priv(dev);
300 fecp = (volatile fec_t*)dev->base_addr 314 fecp = (volatile fec_t*)dev->base_addr;
301 315
302 if (!fep->link) { 316 if (!fep->link) {
303 /* Link is down or autonegotia 317 /* Link is down or autonegotiation is in progress. */
304 return 1; 318 return 1;
305 } 319 }
306 320
307 /* Fill in a Tx ring entry */ 321 /* Fill in a Tx ring entry */
308 bdp = fep->cur_tx; 322 bdp = fep->cur_tx;
309 323
>> 324 status = bdp->cbd_sc;
310 #ifndef final_version 325 #ifndef final_version
311 if (bdp->cbd_sc & BD_ENET_TX_READY) { !! 326 if (status & BD_ENET_TX_READY) {
312 /* Ooops. All transmit buffer 327 /* Ooops. All transmit buffers are full. Bail out.
313 * This should not happen, sin 328 * This should not happen, since dev->tbusy should be set.
314 */ 329 */
315 printk("%s: tx queue full!.\n" 330 printk("%s: tx queue full!.\n", dev->name);
316 return 1; 331 return 1;
317 } 332 }
318 #endif 333 #endif
319 334
320 /* Clear all of the status flags. 335 /* Clear all of the status flags.
321 */ 336 */
322 bdp->cbd_sc &= ~BD_ENET_TX_STATS; !! 337 status &= ~BD_ENET_TX_STATS;
323 338
324 /* Set buffer length and buffer pointe 339 /* Set buffer length and buffer pointer.
325 */ 340 */
326 bdp->cbd_bufaddr = __pa(skb->data); 341 bdp->cbd_bufaddr = __pa(skb->data);
327 bdp->cbd_datlen = skb->len; 342 bdp->cbd_datlen = skb->len;
328 343
329 /* 344 /*
330 * On some FEC implementations da 345 * On some FEC implementations data must be aligned on
331 * 4-byte boundaries. Use bounce 346 * 4-byte boundaries. Use bounce buffers to copy data
332 * and get it aligned. Ugh. 347 * and get it aligned. Ugh.
333 */ 348 */
334 if (bdp->cbd_bufaddr & 0x3) { 349 if (bdp->cbd_bufaddr & 0x3) {
335 unsigned int index; 350 unsigned int index;
336 index = bdp - fep->tx_bd_base; 351 index = bdp - fep->tx_bd_base;
337 memcpy(fep->tx_bounce[index], 352 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
338 bdp->cbd_bufaddr = __pa(fep->t 353 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
339 } 354 }
340 355
341 /* Save skb pointer. 356 /* Save skb pointer.
342 */ 357 */
343 fep->tx_skbuff[fep->skb_cur] = skb; 358 fep->tx_skbuff[fep->skb_cur] = skb;
344 359
345 fep->stats.tx_bytes += skb->len; !! 360 dev->stats.tx_bytes += skb->len;
346 fep->skb_cur = (fep->skb_cur+1) & TX_R 361 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
347 !! 362
348 /* Push the data cache so the CPM does 363 /* Push the data cache so the CPM does not get stale memory
349 * data. 364 * data.
350 */ 365 */
351 flush_dcache_range((unsigned long)skb- 366 flush_dcache_range((unsigned long)skb->data,
352 (unsigned long)skb- 367 (unsigned long)skb->data + skb->len);
353 368
354 spin_lock_irq(&fep->lock); 369 spin_lock_irq(&fep->lock);
355 370
356 /* Send it on its way. Tell FEC its r !! 371 /* Send it on its way. Tell FEC it's ready, interrupt when done,
357 * its the last BD of the frame, and t !! 372 * it's the last BD of the frame, and to put the CRC on the end.
358 */ 373 */
359 374
360 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ !! 375 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
361 | BD_ENET_TX_LAST | BD 376 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
>> 377 bdp->cbd_sc = status;
362 378
363 dev->trans_start = jiffies; 379 dev->trans_start = jiffies;
364 380
365 /* Trigger transmission start */ 381 /* Trigger transmission start */
366 fecp->fec_x_des_active = 0x01000000; !! 382 fecp->fec_x_des_active = 0;
367 383
368 /* If this was the last BD in the ring 384 /* If this was the last BD in the ring, start at the beginning again.
369 */ 385 */
370 if (bdp->cbd_sc & BD_ENET_TX_WRAP) { !! 386 if (status & BD_ENET_TX_WRAP) {
371 bdp = fep->tx_bd_base; 387 bdp = fep->tx_bd_base;
372 } else { 388 } else {
373 bdp++; 389 bdp++;
374 } 390 }
375 391
376 if (bdp == fep->dirty_tx) { 392 if (bdp == fep->dirty_tx) {
377 fep->tx_full = 1; 393 fep->tx_full = 1;
378 netif_stop_queue(dev); 394 netif_stop_queue(dev);
379 } 395 }
380 396
381 fep->cur_tx = (cbd_t *)bdp; 397 fep->cur_tx = (cbd_t *)bdp;
382 398
383 spin_unlock_irq(&fep->lock); 399 spin_unlock_irq(&fep->lock);
384 400
385 return 0; 401 return 0;
386 } 402 }
387 403
388 static void 404 static void
389 fec_timeout(struct net_device *dev) 405 fec_timeout(struct net_device *dev)
390 { 406 {
391 struct fec_enet_private *fep = netdev_ 407 struct fec_enet_private *fep = netdev_priv(dev);
392 408
393 printk("%s: transmit timed out.\n", de 409 printk("%s: transmit timed out.\n", dev->name);
394 fep->stats.tx_errors++; !! 410 dev->stats.tx_errors++;
395 #ifndef final_version 411 #ifndef final_version
396 { 412 {
397 int i; 413 int i;
398 cbd_t *bdp; 414 cbd_t *bdp;
399 415
400 printk("Ring data dump: cur_tx %lx%s, 416 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
401 (unsigned long)fep->cur_tx, fep 417 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
402 (unsigned long)fep->dirty_tx, 418 (unsigned long)fep->dirty_tx,
403 (unsigned long)fep->cur_rx); 419 (unsigned long)fep->cur_rx);
404 420
405 bdp = fep->tx_bd_base; 421 bdp = fep->tx_bd_base;
406 printk(" tx: %u buffers\n", TX_RING_S 422 printk(" tx: %u buffers\n", TX_RING_SIZE);
407 for (i = 0 ; i < TX_RING_SIZE; i++) { 423 for (i = 0 ; i < TX_RING_SIZE; i++) {
408 printk(" %08x: %04x %04x %08x !! 424 printk(" %08x: %04x %04x %08x\n",
409 (uint) bdp, 425 (uint) bdp,
410 bdp->cbd_sc, 426 bdp->cbd_sc,
411 bdp->cbd_datlen, 427 bdp->cbd_datlen,
412 (int) bdp->cbd_bufaddr) 428 (int) bdp->cbd_bufaddr);
413 bdp++; 429 bdp++;
414 } 430 }
415 431
416 bdp = fep->rx_bd_base; 432 bdp = fep->rx_bd_base;
417 printk(" rx: %lu buffers\n", (unsigne 433 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
418 for (i = 0 ; i < RX_RING_SIZE; i++) { 434 for (i = 0 ; i < RX_RING_SIZE; i++) {
419 printk(" %08x: %04x %04x %08x 435 printk(" %08x: %04x %04x %08x\n",
420 (uint) bdp, 436 (uint) bdp,
421 bdp->cbd_sc, 437 bdp->cbd_sc,
422 bdp->cbd_datlen, 438 bdp->cbd_datlen,
423 (int) bdp->cbd_bufaddr) 439 (int) bdp->cbd_bufaddr);
424 bdp++; 440 bdp++;
425 } 441 }
426 } 442 }
427 #endif 443 #endif
428 fec_restart(dev, 0); !! 444 fec_restart(dev, fep->full_duplex);
429 netif_wake_queue(dev); 445 netif_wake_queue(dev);
430 } 446 }
431 447
432 /* The interrupt handler. 448 /* The interrupt handler.
433 * This is called from the MPC core interrupt. 449 * This is called from the MPC core interrupt.
434 */ 450 */
435 static irqreturn_t 451 static irqreturn_t
436 fec_enet_interrupt(int irq, void * dev_id, str !! 452 fec_enet_interrupt(int irq, void * dev_id)
437 { 453 {
438 struct net_device *dev = dev_id; 454 struct net_device *dev = dev_id;
439 volatile fec_t *fecp; 455 volatile fec_t *fecp;
440 uint int_events; 456 uint int_events;
441 int handled = 0; 457 int handled = 0;
442 458
443 fecp = (volatile fec_t*)dev->base_addr 459 fecp = (volatile fec_t*)dev->base_addr;
444 460
445 /* Get the interrupt events that cause 461 /* Get the interrupt events that caused us to be here.
446 */ 462 */
447 while ((int_events = fecp->fec_ievent) 463 while ((int_events = fecp->fec_ievent) != 0) {
448 fecp->fec_ievent = int_events; 464 fecp->fec_ievent = int_events;
449 465
450 /* Handle receive event in its 466 /* Handle receive event in its own function.
451 */ 467 */
452 if (int_events & FEC_ENET_RXF) 468 if (int_events & FEC_ENET_RXF) {
453 handled = 1; 469 handled = 1;
454 fec_enet_rx(dev); 470 fec_enet_rx(dev);
455 } 471 }
456 472
457 /* Transmit OK, or non-fatal e 473 /* Transmit OK, or non-fatal error. Update the buffer
458 descriptors. FEC handles al 474 descriptors. FEC handles all errors, we just discover
459 them as part of the transmi 475 them as part of the transmit process.
460 */ 476 */
461 if (int_events & FEC_ENET_TXF) 477 if (int_events & FEC_ENET_TXF) {
462 handled = 1; 478 handled = 1;
463 fec_enet_tx(dev); 479 fec_enet_tx(dev);
464 } 480 }
465 481
466 if (int_events & FEC_ENET_MII) 482 if (int_events & FEC_ENET_MII) {
467 handled = 1; 483 handled = 1;
468 fec_enet_mii(dev); 484 fec_enet_mii(dev);
469 } 485 }
470 !! 486
471 } 487 }
472 return IRQ_RETVAL(handled); 488 return IRQ_RETVAL(handled);
473 } 489 }
474 490
475 491
476 static void 492 static void
477 fec_enet_tx(struct net_device *dev) 493 fec_enet_tx(struct net_device *dev)
478 { 494 {
479 struct fec_enet_private *fep; 495 struct fec_enet_private *fep;
480 volatile cbd_t *bdp; 496 volatile cbd_t *bdp;
>> 497 unsigned short status;
481 struct sk_buff *skb; 498 struct sk_buff *skb;
482 499
483 fep = netdev_priv(dev); 500 fep = netdev_priv(dev);
484 spin_lock(&fep->lock); 501 spin_lock(&fep->lock);
485 bdp = fep->dirty_tx; 502 bdp = fep->dirty_tx;
486 503
487 while ((bdp->cbd_sc&BD_ENET_TX_READY) !! 504 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
488 if (bdp == fep->cur_tx && fep- 505 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
489 506
490 skb = fep->tx_skbuff[fep->skb_ 507 skb = fep->tx_skbuff[fep->skb_dirty];
491 /* Check for errors. */ 508 /* Check for errors. */
492 if (bdp->cbd_sc & (BD_ENET_TX_ !! 509 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
493 BD_ENET_TX_ 510 BD_ENET_TX_RL | BD_ENET_TX_UN |
494 BD_ENET_TX_ 511 BD_ENET_TX_CSL)) {
495 fep->stats.tx_errors++ !! 512 dev->stats.tx_errors++;
496 if (bdp->cbd_sc & BD_E !! 513 if (status & BD_ENET_TX_HB) /* No heartbeat */
497 fep->stats.tx_ !! 514 dev->stats.tx_heartbeat_errors++;
498 if (bdp->cbd_sc & BD_E !! 515 if (status & BD_ENET_TX_LC) /* Late collision */
499 fep->stats.tx_ !! 516 dev->stats.tx_window_errors++;
500 if (bdp->cbd_sc & BD_E !! 517 if (status & BD_ENET_TX_RL) /* Retrans limit */
501 fep->stats.tx_ !! 518 dev->stats.tx_aborted_errors++;
502 if (bdp->cbd_sc & BD_E !! 519 if (status & BD_ENET_TX_UN) /* Underrun */
503 fep->stats.tx_ !! 520 dev->stats.tx_fifo_errors++;
504 if (bdp->cbd_sc & BD_E !! 521 if (status & BD_ENET_TX_CSL) /* Carrier lost */
505 fep->stats.tx_ !! 522 dev->stats.tx_carrier_errors++;
506 } else { 523 } else {
507 fep->stats.tx_packets+ !! 524 dev->stats.tx_packets++;
508 } 525 }
509 526
510 #ifndef final_version 527 #ifndef final_version
511 if (bdp->cbd_sc & BD_ENET_TX_R !! 528 if (status & BD_ENET_TX_READY)
512 printk("HEY! Enet xmit 529 printk("HEY! Enet xmit interrupt and TX_READY.\n");
513 #endif 530 #endif
514 /* Deferred means some collisi 531 /* Deferred means some collisions occurred during transmit,
515 * but we eventually sent the 532 * but we eventually sent the packet OK.
516 */ 533 */
517 if (bdp->cbd_sc & BD_ENET_TX_D !! 534 if (status & BD_ENET_TX_DEF)
518 fep->stats.collisions+ !! 535 dev->stats.collisions++;
519 !! 536
520 /* Free the sk buffer associat 537 /* Free the sk buffer associated with this last transmit.
521 */ 538 */
522 dev_kfree_skb_any(skb); 539 dev_kfree_skb_any(skb);
523 fep->tx_skbuff[fep->skb_dirty] 540 fep->tx_skbuff[fep->skb_dirty] = NULL;
524 fep->skb_dirty = (fep->skb_dir 541 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
525 !! 542
526 /* Update pointer to next buff 543 /* Update pointer to next buffer descriptor to be transmitted.
527 */ 544 */
528 if (bdp->cbd_sc & BD_ENET_TX_W !! 545 if (status & BD_ENET_TX_WRAP)
529 bdp = fep->tx_bd_base; 546 bdp = fep->tx_bd_base;
530 else 547 else
531 bdp++; 548 bdp++;
532 !! 549
533 /* Since we have freed up a bu 550 /* Since we have freed up a buffer, the ring is no longer
534 * full. 551 * full.
535 */ 552 */
536 if (fep->tx_full) { 553 if (fep->tx_full) {
537 fep->tx_full = 0; 554 fep->tx_full = 0;
538 if (netif_queue_stoppe 555 if (netif_queue_stopped(dev))
539 netif_wake_que 556 netif_wake_queue(dev);
540 } 557 }
541 } 558 }
542 fep->dirty_tx = (cbd_t *)bdp; 559 fep->dirty_tx = (cbd_t *)bdp;
543 spin_unlock(&fep->lock); 560 spin_unlock(&fep->lock);
544 } 561 }
545 562
546 563
547 /* During a receive, the cur_rx points to the 564 /* During a receive, the cur_rx points to the current incoming buffer.
548 * When we update through the ring, if the nex 565 * When we update through the ring, if the next incoming buffer has
549 * not been given to the system, we just set t 566 * not been given to the system, we just set the empty indicator,
550 * effectively tossing the packet. 567 * effectively tossing the packet.
551 */ 568 */
552 static void 569 static void
553 fec_enet_rx(struct net_device *dev) 570 fec_enet_rx(struct net_device *dev)
554 { 571 {
555 struct fec_enet_private *fep; 572 struct fec_enet_private *fep;
556 volatile fec_t *fecp; 573 volatile fec_t *fecp;
557 volatile cbd_t *bdp; 574 volatile cbd_t *bdp;
>> 575 unsigned short status;
558 struct sk_buff *skb; 576 struct sk_buff *skb;
559 ushort pkt_len; 577 ushort pkt_len;
560 __u8 *data; 578 __u8 *data;
561 579
>> 580 #ifdef CONFIG_M532x
>> 581 flush_cache_all();
>> 582 #endif
>> 583
562 fep = netdev_priv(dev); 584 fep = netdev_priv(dev);
563 fecp = (volatile fec_t*)dev->base_addr 585 fecp = (volatile fec_t*)dev->base_addr;
564 586
565 /* First, grab all of the stats for th 587 /* First, grab all of the stats for the incoming packet.
566 * These get messed up if we get calle 588 * These get messed up if we get called due to a busy condition.
567 */ 589 */
568 bdp = fep->cur_rx; 590 bdp = fep->cur_rx;
569 591
570 while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) { !! 592 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
571 593
572 #ifndef final_version 594 #ifndef final_version
573 /* Since we have allocated space to ho 595 /* Since we have allocated space to hold a complete frame,
574 * the last indicator should be set. 596 * the last indicator should be set.
575 */ 597 */
576 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == !! 598 if ((status & BD_ENET_RX_LAST) == 0)
577 printk("FEC ENET: rcv is not + 599 printk("FEC ENET: rcv is not +last\n");
578 #endif 600 #endif
579 601
580 if (!fep->opened) 602 if (!fep->opened)
581 goto rx_processing_done; 603 goto rx_processing_done;
582 604
583 /* Check for errors. */ 605 /* Check for errors. */
584 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ !! 606 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
585 BD_ENET_RX_CR | BD_ 607 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
586 fep->stats.rx_errors++; !! 608 dev->stats.rx_errors++;
587 if (bdp->cbd_sc & (BD_ENET_RX_ !! 609 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
588 /* Frame too long or too short 610 /* Frame too long or too short. */
589 fep->stats.rx_length_e !! 611 dev->stats.rx_length_errors++;
590 } 612 }
591 if (bdp->cbd_sc & BD_ENET_RX_N !! 613 if (status & BD_ENET_RX_NO) /* Frame alignment */
592 fep->stats.rx_frame_er !! 614 dev->stats.rx_frame_errors++;
593 if (bdp->cbd_sc & BD_ENET_RX_C !! 615 if (status & BD_ENET_RX_CR) /* CRC Error */
594 fep->stats.rx_crc_erro !! 616 dev->stats.rx_crc_errors++;
595 if (bdp->cbd_sc & BD_ENET_RX_O !! 617 if (status & BD_ENET_RX_OV) /* FIFO overrun */
596 fep->stats.rx_crc_erro !! 618 dev->stats.rx_fifo_errors++;
597 } 619 }
598 620
599 /* Report late collisions as a frame e 621 /* Report late collisions as a frame error.
600 * On this error, the BD is closed, bu 622 * On this error, the BD is closed, but we don't know what we
601 * have in the buffer. So, just drop 623 * have in the buffer. So, just drop this frame on the floor.
602 */ 624 */
603 if (bdp->cbd_sc & BD_ENET_RX_CL) { !! 625 if (status & BD_ENET_RX_CL) {
604 fep->stats.rx_errors++; !! 626 dev->stats.rx_errors++;
605 fep->stats.rx_frame_errors++; !! 627 dev->stats.rx_frame_errors++;
606 goto rx_processing_done; 628 goto rx_processing_done;
607 } 629 }
608 630
609 /* Process the incoming frame. 631 /* Process the incoming frame.
610 */ 632 */
611 fep->stats.rx_packets++; !! 633 dev->stats.rx_packets++;
612 pkt_len = bdp->cbd_datlen; 634 pkt_len = bdp->cbd_datlen;
613 fep->stats.rx_bytes += pkt_len; !! 635 dev->stats.rx_bytes += pkt_len;
614 data = (__u8*)__va(bdp->cbd_bufaddr); 636 data = (__u8*)__va(bdp->cbd_bufaddr);
615 637
616 /* This does 16 byte alignment, exactl 638 /* This does 16 byte alignment, exactly what we need.
617 * The packet length includes FCS, but 639 * The packet length includes FCS, but we don't want to
618 * include that when passing upstream 640 * include that when passing upstream as it messes up
619 * bridging applications. 641 * bridging applications.
620 */ 642 */
621 skb = dev_alloc_skb(pkt_len-4); 643 skb = dev_alloc_skb(pkt_len-4);
622 644
623 if (skb == NULL) { 645 if (skb == NULL) {
624 printk("%s: Memory squeeze, dr 646 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
625 fep->stats.rx_dropped++; !! 647 dev->stats.rx_dropped++;
626 } else { 648 } else {
627 skb->dev = dev; <<
628 skb_put(skb,pkt_len-4); /* Mak 649 skb_put(skb,pkt_len-4); /* Make room */
629 eth_copy_and_sum(skb, !! 650 skb_copy_to_linear_data(skb, data, pkt_len-4);
630 (unsigned cha <<
631 pkt_len-4, 0) <<
632 skb->protocol=eth_type_trans(s 651 skb->protocol=eth_type_trans(skb,dev);
633 netif_rx(skb); 652 netif_rx(skb);
634 } 653 }
635 rx_processing_done: 654 rx_processing_done:
636 655
637 /* Clear the status flags for this buf 656 /* Clear the status flags for this buffer.
638 */ 657 */
639 bdp->cbd_sc &= ~BD_ENET_RX_STATS; !! 658 status &= ~BD_ENET_RX_STATS;
640 659
641 /* Mark the buffer empty. 660 /* Mark the buffer empty.
642 */ 661 */
643 bdp->cbd_sc |= BD_ENET_RX_EMPTY; !! 662 status |= BD_ENET_RX_EMPTY;
>> 663 bdp->cbd_sc = status;
644 664
645 /* Update BD pointer to next entry. 665 /* Update BD pointer to next entry.
646 */ 666 */
647 if (bdp->cbd_sc & BD_ENET_RX_WRAP) !! 667 if (status & BD_ENET_RX_WRAP)
648 bdp = fep->rx_bd_base; 668 bdp = fep->rx_bd_base;
649 else 669 else
650 bdp++; 670 bdp++;
651 !! 671
652 #if 1 672 #if 1
653 /* Doing this here will keep the FEC r 673 /* Doing this here will keep the FEC running while we process
654 * incoming frames. On a heavily load 674 * incoming frames. On a heavily loaded network, we should be
655 * able to keep up at the expense of s 675 * able to keep up at the expense of system resources.
656 */ 676 */
657 fecp->fec_r_des_active = 0x01000000; !! 677 fecp->fec_r_des_active = 0;
658 #endif 678 #endif
659 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPT !! 679 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
660 fep->cur_rx = (cbd_t *)bdp; 680 fep->cur_rx = (cbd_t *)bdp;
661 681
662 #if 0 682 #if 0
663 /* Doing this here will allow us to pr 683 /* Doing this here will allow us to process all frames in the
664 * ring before the FEC is allowed to p 684 * ring before the FEC is allowed to put more there. On a heavily
665 * loaded network, some frames may be 685 * loaded network, some frames may be lost. Unfortunately, this
666 * increases the interrupt overhead si 686 * increases the interrupt overhead since we can potentially work
667 * our way back to the interrupt retur 687 * our way back to the interrupt return only to come right back
668 * here. 688 * here.
669 */ 689 */
670 fecp->fec_r_des_active = 0x01000000; !! 690 fecp->fec_r_des_active = 0;
671 #endif 691 #endif
672 } 692 }
673 693
674 694
>> 695 /* called from interrupt context */
675 static void 696 static void
676 fec_enet_mii(struct net_device *dev) 697 fec_enet_mii(struct net_device *dev)
677 { 698 {
678 struct fec_enet_private *fep; 699 struct fec_enet_private *fep;
679 volatile fec_t *ep; 700 volatile fec_t *ep;
680 mii_list_t *mip; 701 mii_list_t *mip;
681 uint mii_reg; 702 uint mii_reg;
682 703
683 fep = netdev_priv(dev); 704 fep = netdev_priv(dev);
684 ep = fep->hwp; 705 ep = fep->hwp;
685 mii_reg = ep->fec_mii_data; 706 mii_reg = ep->fec_mii_data;
686 !! 707
>> 708 spin_lock(&fep->lock);
>> 709
687 if ((mip = mii_head) == NULL) { 710 if ((mip = mii_head) == NULL) {
688 printk("MII and no head!\n"); 711 printk("MII and no head!\n");
689 return; !! 712 goto unlock;
690 } 713 }
691 714
692 if (mip->mii_func != NULL) 715 if (mip->mii_func != NULL)
693 (*(mip->mii_func))(mii_reg, de 716 (*(mip->mii_func))(mii_reg, dev);
694 717
695 mii_head = mip->mii_next; 718 mii_head = mip->mii_next;
696 mip->mii_next = mii_free; 719 mip->mii_next = mii_free;
697 mii_free = mip; 720 mii_free = mip;
698 721
699 if ((mip = mii_head) != NULL) 722 if ((mip = mii_head) != NULL)
700 ep->fec_mii_data = mip->mii_re 723 ep->fec_mii_data = mip->mii_regval;
>> 724
>> 725 unlock:
>> 726 spin_unlock(&fep->lock);
701 } 727 }
702 728
703 static int 729 static int
704 mii_queue(struct net_device *dev, int regval, 730 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
705 { 731 {
706 struct fec_enet_private *fep; 732 struct fec_enet_private *fep;
707 unsigned long flags; 733 unsigned long flags;
708 mii_list_t *mip; 734 mii_list_t *mip;
709 int retval; 735 int retval;
710 736
711 /* Add PHY address to register command 737 /* Add PHY address to register command.
712 */ 738 */
713 fep = netdev_priv(dev); 739 fep = netdev_priv(dev);
714 regval |= fep->phy_addr << 23; 740 regval |= fep->phy_addr << 23;
715 741
716 retval = 0; 742 retval = 0;
717 743
718 save_flags(flags); !! 744 spin_lock_irqsave(&fep->lock,flags);
719 cli(); <<
720 745
721 if ((mip = mii_free) != NULL) { 746 if ((mip = mii_free) != NULL) {
722 mii_free = mip->mii_next; 747 mii_free = mip->mii_next;
723 mip->mii_regval = regval; 748 mip->mii_regval = regval;
724 mip->mii_func = func; 749 mip->mii_func = func;
725 mip->mii_next = NULL; 750 mip->mii_next = NULL;
726 if (mii_head) { 751 if (mii_head) {
727 mii_tail->mii_next = m 752 mii_tail->mii_next = mip;
728 mii_tail = mip; 753 mii_tail = mip;
729 } !! 754 } else {
730 else { <<
731 mii_head = mii_tail = 755 mii_head = mii_tail = mip;
732 fep->hwp->fec_mii_data 756 fep->hwp->fec_mii_data = regval;
733 } 757 }
734 } !! 758 } else {
735 else { <<
736 retval = 1; 759 retval = 1;
737 } 760 }
738 761
739 restore_flags(flags); !! 762 spin_unlock_irqrestore(&fep->lock,flags);
740 763
741 return(retval); 764 return(retval);
742 } 765 }
743 766
744 static void mii_do_cmd(struct net_device *dev, 767 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
745 { 768 {
746 int k; <<
747 <<
748 if(!c) 769 if(!c)
749 return; 770 return;
750 771
751 for(k = 0; (c+k)->mii_data != mk_mii_e !! 772 for (; c->mii_data != mk_mii_end; c++)
752 mii_queue(dev, (c+k)->mii_data !! 773 mii_queue(dev, c->mii_data, c->funct);
753 } <<
754 } 774 }
755 775
756 static void mii_parse_sr(uint mii_reg, struct 776 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
757 { 777 {
758 struct fec_enet_private *fep = netdev_ 778 struct fec_enet_private *fep = netdev_priv(dev);
759 volatile uint *s = &(fep->phy_status); 779 volatile uint *s = &(fep->phy_status);
>> 780 uint status;
760 781
761 *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT !! 782 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
762 783
763 if (mii_reg & 0x0004) 784 if (mii_reg & 0x0004)
764 *s |= PHY_STAT_LINK; !! 785 status |= PHY_STAT_LINK;
765 if (mii_reg & 0x0010) 786 if (mii_reg & 0x0010)
766 *s |= PHY_STAT_FAULT; !! 787 status |= PHY_STAT_FAULT;
767 if (mii_reg & 0x0020) 788 if (mii_reg & 0x0020)
768 *s |= PHY_STAT_ANC; !! 789 status |= PHY_STAT_ANC;
>> 790 *s = status;
769 } 791 }
770 792
771 static void mii_parse_cr(uint mii_reg, struct 793 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
772 { 794 {
773 struct fec_enet_private *fep = netdev_ 795 struct fec_enet_private *fep = netdev_priv(dev);
774 volatile uint *s = &(fep->phy_status); 796 volatile uint *s = &(fep->phy_status);
>> 797 uint status;
775 798
776 *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP); !! 799 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
777 800
778 if (mii_reg & 0x1000) 801 if (mii_reg & 0x1000)
779 *s |= PHY_CONF_ANE; !! 802 status |= PHY_CONF_ANE;
780 if (mii_reg & 0x4000) 803 if (mii_reg & 0x4000)
781 *s |= PHY_CONF_LOOP; !! 804 status |= PHY_CONF_LOOP;
>> 805 *s = status;
782 } 806 }
783 807
784 static void mii_parse_anar(uint mii_reg, struc 808 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
785 { 809 {
786 struct fec_enet_private *fep = netdev_ 810 struct fec_enet_private *fep = netdev_priv(dev);
787 volatile uint *s = &(fep->phy_status); 811 volatile uint *s = &(fep->phy_status);
>> 812 uint status;
788 813
789 *s &= ~(PHY_CONF_SPMASK); !! 814 status = *s & ~(PHY_CONF_SPMASK);
790 815
791 if (mii_reg & 0x0020) 816 if (mii_reg & 0x0020)
792 *s |= PHY_CONF_10HDX; !! 817 status |= PHY_CONF_10HDX;
793 if (mii_reg & 0x0040) 818 if (mii_reg & 0x0040)
794 *s |= PHY_CONF_10FDX; !! 819 status |= PHY_CONF_10FDX;
795 if (mii_reg & 0x0080) 820 if (mii_reg & 0x0080)
796 *s |= PHY_CONF_100HDX; !! 821 status |= PHY_CONF_100HDX;
797 if (mii_reg & 0x00100) 822 if (mii_reg & 0x00100)
798 *s |= PHY_CONF_100FDX; !! 823 status |= PHY_CONF_100FDX;
>> 824 *s = status;
799 } 825 }
800 826
801 /* ------------------------------------------- 827 /* ------------------------------------------------------------------------- */
802 /* The Level one LXT970 is used by many boards 828 /* The Level one LXT970 is used by many boards */
803 829
804 #define MII_LXT970_MIRROR 16 /* Mirror reg 830 #define MII_LXT970_MIRROR 16 /* Mirror register */
805 #define MII_LXT970_IER 17 /* Interrupt 831 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
806 #define MII_LXT970_ISR 18 /* Interrupt 832 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
807 #define MII_LXT970_CONFIG 19 /* Configurat 833 #define MII_LXT970_CONFIG 19 /* Configuration Register */
808 #define MII_LXT970_CSR 20 /* Chip Statu 834 #define MII_LXT970_CSR 20 /* Chip Status Register */
809 835
810 static void mii_parse_lxt970_csr(uint mii_reg, 836 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
811 { 837 {
812 struct fec_enet_private *fep = netdev_ 838 struct fec_enet_private *fep = netdev_priv(dev);
813 volatile uint *s = &(fep->phy_status); 839 volatile uint *s = &(fep->phy_status);
>> 840 uint status;
814 841
815 *s &= ~(PHY_STAT_SPMASK); !! 842 status = *s & ~(PHY_STAT_SPMASK);
816 <<
817 if (mii_reg & 0x0800) { 843 if (mii_reg & 0x0800) {
818 if (mii_reg & 0x1000) 844 if (mii_reg & 0x1000)
819 *s |= PHY_STAT_100FDX; !! 845 status |= PHY_STAT_100FDX;
820 else 846 else
821 *s |= PHY_STAT_100HDX; !! 847 status |= PHY_STAT_100HDX;
822 } else { 848 } else {
823 if (mii_reg & 0x1000) 849 if (mii_reg & 0x1000)
824 *s |= PHY_STAT_10FDX; !! 850 status |= PHY_STAT_10FDX;
825 else 851 else
826 *s |= PHY_STAT_10HDX; !! 852 status |= PHY_STAT_10HDX;
827 } 853 }
>> 854 *s = status;
828 } 855 }
829 856
830 static phy_info_t phy_info_lxt970 = { !! 857 static phy_cmd_t const phy_cmd_lxt970_config[] = {
831 0x07810000, <<
832 "LXT970", <<
833 <<
834 (const phy_cmd_t []) { /* config */ <<
835 { mk_mii_read(MII_REG_CR), mii 858 { mk_mii_read(MII_REG_CR), mii_parse_cr },
836 { mk_mii_read(MII_REG_ANAR), m 859 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
837 { mk_mii_end, } 860 { mk_mii_end, }
838 }, !! 861 };
839 (const phy_cmd_t []) { /* startup - e !! 862 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
840 { mk_mii_write(MII_LXT970_IER, 863 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
841 { mk_mii_write(MII_REG_CR, 0x1 864 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
842 { mk_mii_end, } 865 { mk_mii_end, }
843 }, !! 866 };
844 (const phy_cmd_t []) { /* ack_int */ !! 867 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
845 /* read SR and ISR to acknowle 868 /* read SR and ISR to acknowledge */
846 { mk_mii_read(MII_REG_SR), mii 869 { mk_mii_read(MII_REG_SR), mii_parse_sr },
847 { mk_mii_read(MII_LXT970_ISR), 870 { mk_mii_read(MII_LXT970_ISR), NULL },
848 871
849 /* find out the current status 872 /* find out the current status */
850 { mk_mii_read(MII_LXT970_CSR), 873 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
851 { mk_mii_end, } 874 { mk_mii_end, }
852 }, !! 875 };
853 (const phy_cmd_t []) { /* shutdown - !! 876 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
854 { mk_mii_write(MII_LXT970_IER, 877 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
855 { mk_mii_end, } 878 { mk_mii_end, }
856 }, !! 879 };
>> 880 static phy_info_t const phy_info_lxt970 = {
>> 881 .id = 0x07810000,
>> 882 .name = "LXT970",
>> 883 .config = phy_cmd_lxt970_config,
>> 884 .startup = phy_cmd_lxt970_startup,
>> 885 .ack_int = phy_cmd_lxt970_ack_int,
>> 886 .shutdown = phy_cmd_lxt970_shutdown
857 }; 887 };
858 !! 888
859 /* ------------------------------------------- 889 /* ------------------------------------------------------------------------- */
860 /* The Level one LXT971 is used on some of my 890 /* The Level one LXT971 is used on some of my custom boards */
861 891
862 /* register definitions for the 971 */ 892 /* register definitions for the 971 */
863 893
864 #define MII_LXT971_PCR 16 /* Port Contr 894 #define MII_LXT971_PCR 16 /* Port Control Register */
865 #define MII_LXT971_SR2 17 /* Status Reg 895 #define MII_LXT971_SR2 17 /* Status Register 2 */
866 #define MII_LXT971_IER 18 /* Interrupt 896 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
867 #define MII_LXT971_ISR 19 /* Interrupt 897 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
868 #define MII_LXT971_LCR 20 /* LED Contro 898 #define MII_LXT971_LCR 20 /* LED Control Register */
869 #define MII_LXT971_TCR 30 /* Transmit C 899 #define MII_LXT971_TCR 30 /* Transmit Control Register */
870 900
871 /* !! 901 /*
872 * I had some nice ideas of running the MDIO f 902 * I had some nice ideas of running the MDIO faster...
873 * The 971 should support 8MHz and I tried it, 903 * The 971 should support 8MHz and I tried it, but things acted really
874 * weird, so 2.5 MHz ought to be enough for an 904 * weird, so 2.5 MHz ought to be enough for anyone...
875 */ 905 */
876 906
877 static void mii_parse_lxt971_sr2(uint mii_reg, 907 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
878 { 908 {
879 struct fec_enet_private *fep = netdev_ 909 struct fec_enet_private *fep = netdev_priv(dev);
880 volatile uint *s = &(fep->phy_status); 910 volatile uint *s = &(fep->phy_status);
>> 911 uint status;
881 912
882 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LIN !! 913 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
883 914
884 if (mii_reg & 0x0400) { 915 if (mii_reg & 0x0400) {
885 fep->link = 1; 916 fep->link = 1;
886 *s |= PHY_STAT_LINK; !! 917 status |= PHY_STAT_LINK;
887 } else { 918 } else {
888 fep->link = 0; 919 fep->link = 0;
889 } 920 }
890 if (mii_reg & 0x0080) 921 if (mii_reg & 0x0080)
891 *s |= PHY_STAT_ANC; !! 922 status |= PHY_STAT_ANC;
892 if (mii_reg & 0x4000) { 923 if (mii_reg & 0x4000) {
893 if (mii_reg & 0x0200) 924 if (mii_reg & 0x0200)
894 *s |= PHY_STAT_100FDX; !! 925 status |= PHY_STAT_100FDX;
895 else 926 else
896 *s |= PHY_STAT_100HDX; !! 927 status |= PHY_STAT_100HDX;
897 } else { 928 } else {
898 if (mii_reg & 0x0200) 929 if (mii_reg & 0x0200)
899 *s |= PHY_STAT_10FDX; !! 930 status |= PHY_STAT_10FDX;
900 else 931 else
901 *s |= PHY_STAT_10HDX; !! 932 status |= PHY_STAT_10HDX;
902 } 933 }
903 if (mii_reg & 0x0008) 934 if (mii_reg & 0x0008)
904 *s |= PHY_STAT_FAULT; !! 935 status |= PHY_STAT_FAULT;
>> 936
>> 937 *s = status;
905 } 938 }
906 939
907 static phy_info_t phy_info_lxt971 = { !! 940 static phy_cmd_t const phy_cmd_lxt971_config[] = {
908 0x0001378e, !! 941 /* limit to 10MBit because my prototype board
909 "LXT971", <<
910 <<
911 (const phy_cmd_t []) { /* config */ <<
912 /* limit to 10MBit because my <<
913 * doesn't work with 100. */ 942 * doesn't work with 100. */
914 { mk_mii_read(MII_REG_CR), mii 943 { mk_mii_read(MII_REG_CR), mii_parse_cr },
915 { mk_mii_read(MII_REG_ANAR), m 944 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
916 { mk_mii_read(MII_LXT971_SR2), 945 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
917 { mk_mii_end, } 946 { mk_mii_end, }
918 }, !! 947 };
919 (const phy_cmd_t []) { /* startup - e !! 948 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
920 { mk_mii_write(MII_LXT971_IER, 949 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
921 { mk_mii_write(MII_REG_CR, 0x1 950 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
922 { mk_mii_write(MII_LXT971_LCR, 951 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
923 /* Somehow does the 971 tell m 952 /* Somehow does the 971 tell me that the link is down
924 * the first read after power- 953 * the first read after power-up.
925 * read here to get a valid va 954 * read here to get a valid value in ack_int */
926 { mk_mii_read(MII_REG_SR), mii !! 955 { mk_mii_read(MII_REG_SR), mii_parse_sr },
927 { mk_mii_end, } 956 { mk_mii_end, }
928 }, !! 957 };
929 (const phy_cmd_t []) { /* ack_int */ !! 958 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
>> 959 /* acknowledge the int before reading status ! */
>> 960 { mk_mii_read(MII_LXT971_ISR), NULL },
930 /* find out the current status 961 /* find out the current status */
931 { mk_mii_read(MII_REG_SR), mii 962 { mk_mii_read(MII_REG_SR), mii_parse_sr },
932 { mk_mii_read(MII_LXT971_SR2), 963 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
933 /* we only need to read ISR to <<
934 { mk_mii_read(MII_LXT971_ISR), <<
935 { mk_mii_end, } 964 { mk_mii_end, }
936 }, !! 965 };
937 (const phy_cmd_t []) { /* shutdown - !! 966 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
938 { mk_mii_write(MII_LXT971_IER, 967 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
939 { mk_mii_end, } 968 { mk_mii_end, }
940 }, !! 969 };
>> 970 static phy_info_t const phy_info_lxt971 = {
>> 971 .id = 0x0001378e,
>> 972 .name = "LXT971",
>> 973 .config = phy_cmd_lxt971_config,
>> 974 .startup = phy_cmd_lxt971_startup,
>> 975 .ack_int = phy_cmd_lxt971_ack_int,
>> 976 .shutdown = phy_cmd_lxt971_shutdown
941 }; 977 };
942 978
943 /* ------------------------------------------- 979 /* ------------------------------------------------------------------------- */
944 /* The Quality Semiconductor QS6612 is used on 980 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
945 981
946 /* register definitions */ 982 /* register definitions */
947 983
948 #define MII_QS6612_MCR 17 /* Mode Contr 984 #define MII_QS6612_MCR 17 /* Mode Control Register */
949 #define MII_QS6612_FTR 27 /* Factory Te 985 #define MII_QS6612_FTR 27 /* Factory Test Register */
950 #define MII_QS6612_MCO 28 /* Misc. Cont 986 #define MII_QS6612_MCO 28 /* Misc. Control Register */
951 #define MII_QS6612_ISR 29 /* Interrupt 987 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
952 #define MII_QS6612_IMR 30 /* Interrupt 988 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
953 #define MII_QS6612_PCR 31 /* 100BaseTx 989 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
954 990
955 static void mii_parse_qs6612_pcr(uint mii_reg, 991 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
956 { 992 {
957 struct fec_enet_private *fep = netdev_ 993 struct fec_enet_private *fep = netdev_priv(dev);
958 volatile uint *s = &(fep->phy_status); 994 volatile uint *s = &(fep->phy_status);
>> 995 uint status;
959 996
960 *s &= ~(PHY_STAT_SPMASK); !! 997 status = *s & ~(PHY_STAT_SPMASK);
961 998
962 switch((mii_reg >> 2) & 7) { 999 switch((mii_reg >> 2) & 7) {
963 case 1: *s |= PHY_STAT_10HDX; break; !! 1000 case 1: status |= PHY_STAT_10HDX; break;
964 case 2: *s |= PHY_STAT_100HDX; break; !! 1001 case 2: status |= PHY_STAT_100HDX; break;
965 case 5: *s |= PHY_STAT_10FDX; break; !! 1002 case 5: status |= PHY_STAT_10FDX; break;
966 case 6: *s |= PHY_STAT_100FDX; break; !! 1003 case 6: status |= PHY_STAT_100FDX; break;
967 } !! 1004 }
>> 1005
>> 1006 *s = status;
968 } 1007 }
969 1008
970 static phy_info_t phy_info_qs6612 = { !! 1009 static phy_cmd_t const phy_cmd_qs6612_config[] = {
971 0x00181440, !! 1010 /* The PHY powers up isolated on the RPX,
972 "QS6612", <<
973 <<
974 (const phy_cmd_t []) { /* config */ <<
975 /* The PHY powers up isolated <<
976 * so send a command to allow 1011 * so send a command to allow operation.
977 */ 1012 */
978 { mk_mii_write(MII_QS6612_PCR, 1013 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
979 1014
980 /* parse cr and anar to get so 1015 /* parse cr and anar to get some info */
981 { mk_mii_read(MII_REG_CR), mii 1016 { mk_mii_read(MII_REG_CR), mii_parse_cr },
982 { mk_mii_read(MII_REG_ANAR), m 1017 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
983 { mk_mii_end, } 1018 { mk_mii_end, }
984 }, !! 1019 };
985 (const phy_cmd_t []) { /* startup - e !! 1020 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
986 { mk_mii_write(MII_QS6612_IMR, 1021 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
987 { mk_mii_write(MII_REG_CR, 0x1 1022 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
988 { mk_mii_end, } 1023 { mk_mii_end, }
989 }, !! 1024 };
990 (const phy_cmd_t []) { /* ack_int */ !! 1025 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
991 /* we need to read ISR, SR and 1026 /* we need to read ISR, SR and ANER to acknowledge */
992 { mk_mii_read(MII_QS6612_ISR), 1027 { mk_mii_read(MII_QS6612_ISR), NULL },
993 { mk_mii_read(MII_REG_SR), mii 1028 { mk_mii_read(MII_REG_SR), mii_parse_sr },
994 { mk_mii_read(MII_REG_ANER), N 1029 { mk_mii_read(MII_REG_ANER), NULL },
995 1030
996 /* read pcr to get info */ 1031 /* read pcr to get info */
997 { mk_mii_read(MII_QS6612_PCR), 1032 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
998 { mk_mii_end, } 1033 { mk_mii_end, }
999 }, !! 1034 };
1000 (const phy_cmd_t []) { /* shutdown - !! 1035 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1001 { mk_mii_write(MII_QS6612_IMR 1036 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1002 { mk_mii_end, } 1037 { mk_mii_end, }
1003 }, !! 1038 };
>> 1039 static phy_info_t const phy_info_qs6612 = {
>> 1040 .id = 0x00181440,
>> 1041 .name = "QS6612",
>> 1042 .config = phy_cmd_qs6612_config,
>> 1043 .startup = phy_cmd_qs6612_startup,
>> 1044 .ack_int = phy_cmd_qs6612_ack_int,
>> 1045 .shutdown = phy_cmd_qs6612_shutdown
1004 }; 1046 };
1005 1047
1006 /* ------------------------------------------ 1048 /* ------------------------------------------------------------------------- */
1007 /* AMD AM79C874 phy 1049 /* AMD AM79C874 phy */
1008 1050
1009 /* register definitions for the 874 */ 1051 /* register definitions for the 874 */
1010 1052
1011 #define MII_AM79C874_MFR 16 /* Miscell 1053 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1012 #define MII_AM79C874_ICSR 17 /* Interru 1054 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1013 #define MII_AM79C874_DR 18 /* Diagnos 1055 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1014 #define MII_AM79C874_PMLR 19 /* Power a 1056 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1015 #define MII_AM79C874_MCR 21 /* ModeCon 1057 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1016 #define MII_AM79C874_DC 23 /* Disconn 1058 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1017 #define MII_AM79C874_REC 24 /* Recieve 1059 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1018 1060
1019 static void mii_parse_am79c874_dr(uint mii_re 1061 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1020 { 1062 {
1021 struct fec_enet_private *fep = netdev 1063 struct fec_enet_private *fep = netdev_priv(dev);
1022 volatile uint *s = &(fep->phy_status) 1064 volatile uint *s = &(fep->phy_status);
>> 1065 uint status;
1023 1066
1024 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_AN !! 1067 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1025 1068
1026 if (mii_reg & 0x0080) 1069 if (mii_reg & 0x0080)
1027 *s |= PHY_STAT_ANC; !! 1070 status |= PHY_STAT_ANC;
1028 if (mii_reg & 0x0400) 1071 if (mii_reg & 0x0400)
1029 *s |= ((mii_reg & 0x0800) ? P !! 1072 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1030 else 1073 else
1031 *s |= ((mii_reg & 0x0800) ? P !! 1074 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
>> 1075
>> 1076 *s = status;
1032 } 1077 }
1033 1078
1034 static phy_info_t phy_info_am79c874 = { !! 1079 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1035 0x00022561, <<
1036 "AM79C874", <<
1037 <<
1038 (const phy_cmd_t []) { /* config */ <<
1039 /* limit to 10MBit because my <<
1040 * doesn't work with 100. */ <<
1041 { mk_mii_read(MII_REG_CR), mi 1080 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1042 { mk_mii_read(MII_REG_ANAR), 1081 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1043 { mk_mii_read(MII_AM79C874_DR 1082 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1044 { mk_mii_end, } 1083 { mk_mii_end, }
1045 }, !! 1084 };
1046 (const phy_cmd_t []) { /* startup - !! 1085 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1047 { mk_mii_write(MII_AM79C874_I 1086 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1048 { mk_mii_write(MII_REG_CR, 0x 1087 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1049 { mk_mii_read(MII_REG_SR), mi !! 1088 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1050 { mk_mii_end, } 1089 { mk_mii_end, }
1051 }, !! 1090 };
1052 (const phy_cmd_t []) { /* ack_int */ !! 1091 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1053 /* find out the current statu 1092 /* find out the current status */
1054 { mk_mii_read(MII_REG_SR), mi 1093 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1055 { mk_mii_read(MII_AM79C874_DR 1094 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1056 /* we only need to read ISR t 1095 /* we only need to read ISR to acknowledge */
1057 { mk_mii_read(MII_AM79C874_IC 1096 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1058 { mk_mii_end, } 1097 { mk_mii_end, }
1059 }, !! 1098 };
1060 (const phy_cmd_t []) { /* shutdown - !! 1099 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1061 { mk_mii_write(MII_AM79C874_I 1100 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1062 { mk_mii_end, } 1101 { mk_mii_end, }
1063 }, !! 1102 };
>> 1103 static phy_info_t const phy_info_am79c874 = {
>> 1104 .id = 0x00022561,
>> 1105 .name = "AM79C874",
>> 1106 .config = phy_cmd_am79c874_config,
>> 1107 .startup = phy_cmd_am79c874_startup,
>> 1108 .ack_int = phy_cmd_am79c874_ack_int,
>> 1109 .shutdown = phy_cmd_am79c874_shutdown
1064 }; 1110 };
1065 1111
>> 1112
1066 /* ------------------------------------------ 1113 /* ------------------------------------------------------------------------- */
1067 /* Kendin KS8721BL phy 1114 /* Kendin KS8721BL phy */
1068 1115
1069 /* register definitions for the 8721 */ 1116 /* register definitions for the 8721 */
1070 1117
1071 #define MII_KS8721BL_RXERCR 21 1118 #define MII_KS8721BL_RXERCR 21
1072 #define MII_KS8721BL_ICSR 22 1119 #define MII_KS8721BL_ICSR 22
1073 #define MII_KS8721BL_PHYCR 31 1120 #define MII_KS8721BL_PHYCR 31
1074 1121
1075 static phy_info_t phy_info_ks8721bl = { !! 1122 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1076 0x00022161, <<
1077 "KS8721BL", <<
1078 <<
1079 (const phy_cmd_t []) { /* config */ <<
1080 { mk_mii_read(MII_REG_CR), mi 1123 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1081 { mk_mii_read(MII_REG_ANAR), 1124 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1082 { mk_mii_end, } 1125 { mk_mii_end, }
1083 }, !! 1126 };
1084 (const phy_cmd_t []) { /* startup */ !! 1127 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1085 { mk_mii_write(MII_KS8721BL_I 1128 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1086 { mk_mii_write(MII_REG_CR, 0x 1129 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1087 { mk_mii_read(MII_REG_SR), mi !! 1130 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1088 { mk_mii_end, } 1131 { mk_mii_end, }
1089 }, !! 1132 };
1090 (const phy_cmd_t []) { /* ack_int */ !! 1133 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1091 /* find out the current statu 1134 /* find out the current status */
1092 { mk_mii_read(MII_REG_SR), mi 1135 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1093 /* we only need to read ISR t 1136 /* we only need to read ISR to acknowledge */
1094 { mk_mii_read(MII_KS8721BL_IC 1137 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1095 { mk_mii_end, } 1138 { mk_mii_end, }
>> 1139 };
>> 1140 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
>> 1141 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
>> 1142 { mk_mii_end, }
>> 1143 };
>> 1144 static phy_info_t const phy_info_ks8721bl = {
>> 1145 .id = 0x00022161,
>> 1146 .name = "KS8721BL",
>> 1147 .config = phy_cmd_ks8721bl_config,
>> 1148 .startup = phy_cmd_ks8721bl_startup,
>> 1149 .ack_int = phy_cmd_ks8721bl_ack_int,
>> 1150 .shutdown = phy_cmd_ks8721bl_shutdown
>> 1151 };
>> 1152
>> 1153 /* ------------------------------------------------------------------------- */
>> 1154 /* register definitions for the DP83848 */
>> 1155
>> 1156 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
>> 1157
>> 1158 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
>> 1159 {
>> 1160 struct fec_enet_private *fep = dev->priv;
>> 1161 volatile uint *s = &(fep->phy_status);
>> 1162
>> 1163 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
>> 1164
>> 1165 /* Link up */
>> 1166 if (mii_reg & 0x0001) {
>> 1167 fep->link = 1;
>> 1168 *s |= PHY_STAT_LINK;
>> 1169 } else
>> 1170 fep->link = 0;
>> 1171 /* Status of link */
>> 1172 if (mii_reg & 0x0010) /* Autonegotioation complete */
>> 1173 *s |= PHY_STAT_ANC;
>> 1174 if (mii_reg & 0x0002) { /* 10MBps? */
>> 1175 if (mii_reg & 0x0004) /* Full Duplex? */
>> 1176 *s |= PHY_STAT_10FDX;
>> 1177 else
>> 1178 *s |= PHY_STAT_10HDX;
>> 1179 } else { /* 100 Mbps? */
>> 1180 if (mii_reg & 0x0004) /* Full Duplex? */
>> 1181 *s |= PHY_STAT_100FDX;
>> 1182 else
>> 1183 *s |= PHY_STAT_100HDX;
>> 1184 }
>> 1185 if (mii_reg & 0x0008)
>> 1186 *s |= PHY_STAT_FAULT;
>> 1187 }
>> 1188
>> 1189 static phy_info_t phy_info_dp83848= {
>> 1190 0x020005c9,
>> 1191 "DP83848",
>> 1192
>> 1193 (const phy_cmd_t []) { /* config */
>> 1194 { mk_mii_read(MII_REG_CR), mii_parse_cr },
>> 1195 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
>> 1196 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
>> 1197 { mk_mii_end, }
>> 1198 },
>> 1199 (const phy_cmd_t []) { /* startup - enable interrupts */
>> 1200 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
>> 1201 { mk_mii_read(MII_REG_SR), mii_parse_sr },
>> 1202 { mk_mii_end, }
>> 1203 },
>> 1204 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
>> 1205 { mk_mii_end, }
1096 }, 1206 },
1097 (const phy_cmd_t []) { /* shutdown * 1207 (const phy_cmd_t []) { /* shutdown */
1098 { mk_mii_write(MII_KS8721BL_I <<
1099 { mk_mii_end, } 1208 { mk_mii_end, }
1100 }, 1209 },
1101 }; 1210 };
1102 1211
1103 /* ------------------------------------------ 1212 /* ------------------------------------------------------------------------- */
1104 1213
1105 static phy_info_t *phy_info[] = { !! 1214 static phy_info_t const * const phy_info[] = {
1106 &phy_info_lxt970, 1215 &phy_info_lxt970,
1107 &phy_info_lxt971, 1216 &phy_info_lxt971,
1108 &phy_info_qs6612, 1217 &phy_info_qs6612,
1109 &phy_info_am79c874, 1218 &phy_info_am79c874,
1110 &phy_info_ks8721bl, 1219 &phy_info_ks8721bl,
>> 1220 &phy_info_dp83848,
1111 NULL 1221 NULL
1112 }; 1222 };
1113 1223
1114 /* ------------------------------------------ 1224 /* ------------------------------------------------------------------------- */
1115 !! 1225 #if !defined(CONFIG_M532x)
1116 #ifdef CONFIG_RPXCLASSIC 1226 #ifdef CONFIG_RPXCLASSIC
1117 static void 1227 static void
1118 mii_link_interrupt(void *dev_id); 1228 mii_link_interrupt(void *dev_id);
1119 #else 1229 #else
1120 static irqreturn_t 1230 static irqreturn_t
1121 mii_link_interrupt(int irq, void * dev_id, st !! 1231 mii_link_interrupt(int irq, void * dev_id);
>> 1232 #endif
1122 #endif 1233 #endif
1123 1234
1124 #if defined(CONFIG_M5272) 1235 #if defined(CONFIG_M5272)
1125 <<
1126 /* 1236 /*
1127 * Code specific to Coldfire 5272 setup. 1237 * Code specific to Coldfire 5272 setup.
1128 */ 1238 */
1129 static void __inline__ fec_request_intrs(stru 1239 static void __inline__ fec_request_intrs(struct net_device *dev)
1130 { 1240 {
1131 volatile unsigned long *icrp; 1241 volatile unsigned long *icrp;
>> 1242 static const struct idesc {
>> 1243 char *name;
>> 1244 unsigned short irq;
>> 1245 irq_handler_t handler;
>> 1246 } *idp, id[] = {
>> 1247 { "fec(RX)", 86, fec_enet_interrupt },
>> 1248 { "fec(TX)", 87, fec_enet_interrupt },
>> 1249 { "fec(OTHER)", 88, fec_enet_interrupt },
>> 1250 { "fec(MII)", 66, mii_link_interrupt },
>> 1251 { NULL },
>> 1252 };
1132 1253
1133 /* Setup interrupt handlers. */ 1254 /* Setup interrupt handlers. */
1134 if (request_irq(86, fec_enet_interrup !! 1255 for (idp = id; idp->name; idp++) {
1135 printk("FEC: Could not alloca !! 1256 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1136 if (request_irq(87, fec_enet_interrup !! 1257 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1137 printk("FEC: Could not alloca !! 1258 }
1138 if (request_irq(88, fec_enet_interrup <<
1139 printk("FEC: Could not alloca <<
1140 if (request_irq(66, mii_link_interrup <<
1141 printk("FEC: Could not alloca <<
1142 1259
1143 /* Unmask interrupt at ColdFire 5272 1260 /* Unmask interrupt at ColdFire 5272 SIM */
1144 icrp = (volatile unsigned long *) (MC 1261 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1145 *icrp = 0x00000ddd; 1262 *icrp = 0x00000ddd;
1146 icrp = (volatile unsigned long *) (MC 1263 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1147 *icrp = (*icrp & 0x70777777) | 0x0d00 !! 1264 *icrp = 0x0d000000;
1148 } 1265 }
1149 1266
1150 static void __inline__ fec_set_mii(struct net 1267 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1151 { 1268 {
1152 volatile fec_t *fecp; 1269 volatile fec_t *fecp;
1153 1270
1154 fecp = fep->hwp; 1271 fecp = fep->hwp;
1155 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 1272 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1156 fecp->fec_x_cntrl = 0x00; 1273 fecp->fec_x_cntrl = 0x00;
1157 1274
1158 /* 1275 /*
1159 * Set MII speed to 2.5 MHz 1276 * Set MII speed to 2.5 MHz
1160 * See 5272 manual section 11.5.8: MS 1277 * See 5272 manual section 11.5.8: MSCR
1161 */ 1278 */
1162 fep->phy_speed = ((((MCF_CLK / 4) / ( 1279 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1163 fecp->fec_mii_speed = fep->phy_speed; 1280 fecp->fec_mii_speed = fep->phy_speed;
1164 1281
1165 fec_restart(dev, 0); 1282 fec_restart(dev, 0);
1166 } 1283 }
1167 1284
1168 static void __inline__ fec_get_mac(struct net 1285 static void __inline__ fec_get_mac(struct net_device *dev)
1169 { 1286 {
1170 struct fec_enet_private *fep = netdev 1287 struct fec_enet_private *fep = netdev_priv(dev);
1171 volatile fec_t *fecp; 1288 volatile fec_t *fecp;
1172 unsigned char *iap, tmpaddr[6]; !! 1289 unsigned char *iap, tmpaddr[ETH_ALEN];
1173 int i; <<
1174 1290
1175 fecp = fep->hwp; 1291 fecp = fep->hwp;
1176 1292
1177 if (fec_flashmac) { !! 1293 if (FEC_FLASHMAC) {
1178 /* 1294 /*
1179 * Get MAC address from FLASH 1295 * Get MAC address from FLASH.
1180 * If it is all 1's or 0's, u 1296 * If it is all 1's or 0's, use the default.
1181 */ 1297 */
1182 iap = fec_flashmac; !! 1298 iap = (unsigned char *)FEC_FLASHMAC;
1183 if ((iap[0] == 0) && (iap[1] 1299 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1184 (iap[3] == 0) && (iap[4] 1300 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1185 iap = fec_mac_default 1301 iap = fec_mac_default;
1186 if ((iap[0] == 0xff) && (iap[ 1302 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1187 (iap[3] == 0xff) && (iap[ 1303 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1188 iap = fec_mac_default 1304 iap = fec_mac_default;
1189 } else { 1305 } else {
1190 *((unsigned long *) &tmpaddr[ 1306 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1191 *((unsigned short *) &tmpaddr 1307 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1192 iap = &tmpaddr[0]; 1308 iap = &tmpaddr[0];
1193 } 1309 }
1194 1310
1195 for (i=0; i<ETH_ALEN; i++) !! 1311 memcpy(dev->dev_addr, iap, ETH_ALEN);
1196 dev->dev_addr[i] = fep->mac_a <<
1197 1312
1198 /* Adjust MAC if using default MAC ad 1313 /* Adjust MAC if using default MAC address */
1199 if (iap == fec_mac_default) { !! 1314 if (iap == fec_mac_default)
1200 dev->dev_addr[ETH_ALEN-1] = f !! 1315 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1201 iap[ETH_ALEN-1] + fep <<
1202 } <<
1203 } 1316 }
1204 1317
1205 static void __inline__ fec_enable_phy_intr(vo 1318 static void __inline__ fec_enable_phy_intr(void)
1206 { 1319 {
1207 } 1320 }
1208 1321
1209 static void __inline__ fec_disable_phy_intr(v 1322 static void __inline__ fec_disable_phy_intr(void)
1210 { 1323 {
1211 volatile unsigned long *icrp; 1324 volatile unsigned long *icrp;
1212 icrp = (volatile unsigned long *) (MC 1325 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1213 *icrp = (*icrp & 0x70777777) | 0x0800 !! 1326 *icrp = 0x08000000;
1214 } 1327 }
1215 1328
1216 static void __inline__ fec_phy_ack_intr(void) 1329 static void __inline__ fec_phy_ack_intr(void)
1217 { 1330 {
1218 volatile unsigned long *icrp; 1331 volatile unsigned long *icrp;
1219 /* Acknowledge the interrupt */ 1332 /* Acknowledge the interrupt */
1220 icrp = (volatile unsigned long *) (MC 1333 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1221 *icrp = (*icrp & 0x77777777) | 0x0800 !! 1334 *icrp = 0x0d000000;
1222 } 1335 }
1223 1336
1224 static void __inline__ fec_localhw_setup(void 1337 static void __inline__ fec_localhw_setup(void)
1225 { 1338 {
1226 } 1339 }
1227 1340
1228 /* 1341 /*
1229 * Do not need to make region uncached o 1342 * Do not need to make region uncached on 5272.
1230 */ 1343 */
1231 static void __inline__ fec_uncache(unsigned l 1344 static void __inline__ fec_uncache(unsigned long addr)
1232 { 1345 {
1233 } 1346 }
1234 1347
1235 /* ------------------------------------------ 1348 /* ------------------------------------------------------------------------- */
1236 1349
1237 #elif defined(CONFIG_M527x) || defined(CONFIG !! 1350 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1238 1351
1239 /* 1352 /*
1240 * Code specific to Coldfire 5270/5271/5 !! 1353 * Code specific to Coldfire 5230/5231/5232/5234/5235,
>> 1354 * the 5270/5271/5274/5275 and 5280/5282 setups.
1241 */ 1355 */
1242 static void __inline__ fec_request_intrs(stru 1356 static void __inline__ fec_request_intrs(struct net_device *dev)
1243 { 1357 {
1244 struct fec_enet_private *fep; 1358 struct fec_enet_private *fep;
1245 int b; 1359 int b;
>> 1360 static const struct idesc {
>> 1361 char *name;
>> 1362 unsigned short irq;
>> 1363 } *idp, id[] = {
>> 1364 { "fec(TXF)", 23 },
>> 1365 { "fec(TXB)", 24 },
>> 1366 { "fec(TXFIFO)", 25 },
>> 1367 { "fec(TXCR)", 26 },
>> 1368 { "fec(RXF)", 27 },
>> 1369 { "fec(RXB)", 28 },
>> 1370 { "fec(MII)", 29 },
>> 1371 { "fec(LC)", 30 },
>> 1372 { "fec(HBERR)", 31 },
>> 1373 { "fec(GRA)", 32 },
>> 1374 { "fec(EBERR)", 33 },
>> 1375 { "fec(BABT)", 34 },
>> 1376 { "fec(BABR)", 35 },
>> 1377 { NULL },
>> 1378 };
1246 1379
1247 fep = netdev_priv(dev); 1380 fep = netdev_priv(dev);
1248 b = (fep->index) ? 128 : 64; 1381 b = (fep->index) ? 128 : 64;
1249 1382
1250 /* Setup interrupt handlers. */ 1383 /* Setup interrupt handlers. */
1251 if (request_irq(b+23, fec_enet_interr !! 1384 for (idp = id; idp->name; idp++) {
1252 printk("FEC: Could not alloca !! 1385 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1253 if (request_irq(b+24, fec_enet_interr !! 1386 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1254 printk("FEC: Could not alloca !! 1387 }
1255 if (request_irq(b+25, fec_enet_interr <<
1256 printk("FEC: Could not alloca <<
1257 if (request_irq(b+26, fec_enet_interr <<
1258 printk("FEC: Could not alloca <<
1259 <<
1260 if (request_irq(b+27, fec_enet_interr <<
1261 printk("FEC: Could not alloca <<
1262 if (request_irq(b+28, fec_enet_interr <<
1263 printk("FEC: Could not alloca <<
1264 <<
1265 if (request_irq(b+29, fec_enet_interr <<
1266 printk("FEC: Could not alloca <<
1267 if (request_irq(b+30, fec_enet_interr <<
1268 printk("FEC: Could not alloca <<
1269 if (request_irq(b+31, fec_enet_interr <<
1270 printk("FEC: Could not alloca <<
1271 if (request_irq(b+32, fec_enet_interr <<
1272 printk("FEC: Could not alloca <<
1273 if (request_irq(b+33, fec_enet_interr <<
1274 printk("FEC: Could not alloca <<
1275 if (request_irq(b+34, fec_enet_interr <<
1276 printk("FEC: Could not alloca <<
1277 if (request_irq(b+35, fec_enet_interr <<
1278 printk("FEC: Could not alloca <<
1279 1388
1280 /* Unmask interrupts at ColdFire 5280 1389 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1281 { 1390 {
1282 volatile unsigned char *icrp 1391 volatile unsigned char *icrp;
1283 volatile unsigned long *imrp 1392 volatile unsigned long *imrp;
1284 int i; !! 1393 int i, ilip;
1285 1394
1286 b = (fep->index) ? MCFICM_INT 1395 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1287 icrp = (volatile unsigned cha 1396 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1288 MCFINTC_ICR0); 1397 MCFINTC_ICR0);
1289 for (i = 23; (i < 36); i++) !! 1398 for (i = 23, ilip = 0x28; (i < 36); i++)
1290 icrp[i] = 0x23; !! 1399 icrp[i] = ilip--;
1291 1400
1292 imrp = (volatile unsigned lon 1401 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1293 MCFINTC_IMRH); 1402 MCFINTC_IMRH);
1294 *imrp &= ~0x0000000f; 1403 *imrp &= ~0x0000000f;
1295 imrp = (volatile unsigned lon 1404 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1296 MCFINTC_IMRL); 1405 MCFINTC_IMRL);
1297 *imrp &= ~0xff800001; 1406 *imrp &= ~0xff800001;
1298 } 1407 }
1299 1408
1300 #if defined(CONFIG_M528x) 1409 #if defined(CONFIG_M528x)
1301 /* Set up gpio outputs for MII lines 1410 /* Set up gpio outputs for MII lines */
1302 { 1411 {
1303 volatile unsigned short *gpio !! 1412 volatile u16 *gpio_paspar;
1304 !! 1413 volatile u8 *gpio_pehlpar;
1305 gpio_paspar = (volatile unsig !! 1414
1306 0x100056); !! 1415 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1307 *gpio_paspar = 0x0f00; !! 1416 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
>> 1417 *gpio_paspar |= 0x0f00;
>> 1418 *gpio_pehlpar = 0xc0;
1308 } 1419 }
1309 #endif 1420 #endif
>> 1421
>> 1422 #if defined(CONFIG_M527x)
>> 1423 /* Set up gpio outputs for MII lines */
>> 1424 {
>> 1425 volatile u8 *gpio_par_fec;
>> 1426 volatile u16 *gpio_par_feci2c;
>> 1427
>> 1428 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
>> 1429 /* Set up gpio outputs for FEC0 MII lines */
>> 1430 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
>> 1431
>> 1432 *gpio_par_feci2c |= 0x0f00;
>> 1433 *gpio_par_fec |= 0xc0;
>> 1434
>> 1435 #if defined(CONFIG_FEC2)
>> 1436 /* Set up gpio outputs for FEC1 MII lines */
>> 1437 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
>> 1438
>> 1439 *gpio_par_feci2c |= 0x00a0;
>> 1440 *gpio_par_fec |= 0xc0;
>> 1441 #endif /* CONFIG_FEC2 */
>> 1442 }
>> 1443 #endif /* CONFIG_M527x */
1310 } 1444 }
1311 1445
1312 static void __inline__ fec_set_mii(struct net 1446 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1313 { 1447 {
1314 volatile fec_t *fecp; 1448 volatile fec_t *fecp;
1315 1449
1316 fecp = fep->hwp; 1450 fecp = fep->hwp;
1317 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 1451 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1318 fecp->fec_x_cntrl = 0x00; 1452 fecp->fec_x_cntrl = 0x00;
1319 1453
1320 /* 1454 /*
1321 * Set MII speed to 2.5 MHz 1455 * Set MII speed to 2.5 MHz
1322 * See 5282 manual section 17.5.4.7: 1456 * See 5282 manual section 17.5.4.7: MSCR
1323 */ 1457 */
1324 fep->phy_speed = ((((MCF_CLK / 2) / ( 1458 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1325 fecp->fec_mii_speed = fep->phy_speed; 1459 fecp->fec_mii_speed = fep->phy_speed;
1326 1460
1327 fec_restart(dev, 0); 1461 fec_restart(dev, 0);
1328 } 1462 }
1329 1463
1330 static void __inline__ fec_get_mac(struct net 1464 static void __inline__ fec_get_mac(struct net_device *dev)
1331 { 1465 {
1332 struct fec_enet_private *fep = netdev 1466 struct fec_enet_private *fep = netdev_priv(dev);
1333 volatile fec_t *fecp; 1467 volatile fec_t *fecp;
1334 unsigned char *iap, tmpaddr[6]; !! 1468 unsigned char *iap, tmpaddr[ETH_ALEN];
1335 int i; <<
1336 1469
1337 fecp = fep->hwp; 1470 fecp = fep->hwp;
1338 1471
1339 if (fec_flashmac) { !! 1472 if (FEC_FLASHMAC) {
1340 /* 1473 /*
1341 * Get MAC address from FLASH 1474 * Get MAC address from FLASH.
1342 * If it is all 1's or 0's, u 1475 * If it is all 1's or 0's, use the default.
1343 */ 1476 */
1344 iap = fec_flashmac; !! 1477 iap = FEC_FLASHMAC;
1345 if ((iap[0] == 0) && (iap[1] 1478 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1346 (iap[3] == 0) && (iap[4] 1479 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1347 iap = fec_mac_default 1480 iap = fec_mac_default;
1348 if ((iap[0] == 0xff) && (iap[ 1481 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1349 (iap[3] == 0xff) && (iap[ 1482 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1350 iap = fec_mac_default 1483 iap = fec_mac_default;
1351 } else { 1484 } else {
1352 *((unsigned long *) &tmpaddr[ 1485 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1353 *((unsigned short *) &tmpaddr 1486 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1354 iap = &tmpaddr[0]; 1487 iap = &tmpaddr[0];
1355 } 1488 }
1356 1489
1357 for (i=0; i<ETH_ALEN; i++) !! 1490 memcpy(dev->dev_addr, iap, ETH_ALEN);
1358 dev->dev_addr[i] = fep->mac_a <<
1359 1491
1360 /* Adjust MAC if using default MAC ad 1492 /* Adjust MAC if using default MAC address */
1361 if (iap == fec_mac_default) { !! 1493 if (iap == fec_mac_default)
1362 dev->dev_addr[ETH_ALEN-1] = f !! 1494 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1363 iap[ETH_ALEN-1] + fep <<
1364 } <<
1365 } 1495 }
1366 1496
1367 static void __inline__ fec_enable_phy_intr(vo 1497 static void __inline__ fec_enable_phy_intr(void)
1368 { 1498 {
1369 } 1499 }
1370 1500
1371 static void __inline__ fec_disable_phy_intr(v 1501 static void __inline__ fec_disable_phy_intr(void)
1372 { 1502 {
1373 } 1503 }
1374 1504
1375 static void __inline__ fec_phy_ack_intr(void) 1505 static void __inline__ fec_phy_ack_intr(void)
1376 { 1506 {
1377 } 1507 }
1378 1508
1379 static void __inline__ fec_localhw_setup(void 1509 static void __inline__ fec_localhw_setup(void)
1380 { 1510 {
1381 } 1511 }
1382 1512
1383 /* 1513 /*
1384 * Do not need to make region uncached o 1514 * Do not need to make region uncached on 5272.
1385 */ 1515 */
1386 static void __inline__ fec_uncache(unsigned l 1516 static void __inline__ fec_uncache(unsigned long addr)
1387 { 1517 {
1388 } 1518 }
1389 1519
1390 /* ------------------------------------------ 1520 /* ------------------------------------------------------------------------- */
1391 1521
>> 1522 #elif defined(CONFIG_M520x)
>> 1523
>> 1524 /*
>> 1525 * Code specific to Coldfire 520x
>> 1526 */
>> 1527 static void __inline__ fec_request_intrs(struct net_device *dev)
>> 1528 {
>> 1529 struct fec_enet_private *fep;
>> 1530 int b;
>> 1531 static const struct idesc {
>> 1532 char *name;
>> 1533 unsigned short irq;
>> 1534 } *idp, id[] = {
>> 1535 { "fec(TXF)", 23 },
>> 1536 { "fec(TXB)", 24 },
>> 1537 { "fec(TXFIFO)", 25 },
>> 1538 { "fec(TXCR)", 26 },
>> 1539 { "fec(RXF)", 27 },
>> 1540 { "fec(RXB)", 28 },
>> 1541 { "fec(MII)", 29 },
>> 1542 { "fec(LC)", 30 },
>> 1543 { "fec(HBERR)", 31 },
>> 1544 { "fec(GRA)", 32 },
>> 1545 { "fec(EBERR)", 33 },
>> 1546 { "fec(BABT)", 34 },
>> 1547 { "fec(BABR)", 35 },
>> 1548 { NULL },
>> 1549 };
>> 1550
>> 1551 fep = netdev_priv(dev);
>> 1552 b = 64 + 13;
>> 1553
>> 1554 /* Setup interrupt handlers. */
>> 1555 for (idp = id; idp->name; idp++) {
>> 1556 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
>> 1557 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
>> 1558 }
>> 1559
>> 1560 /* Unmask interrupts at ColdFire interrupt controller */
>> 1561 {
>> 1562 volatile unsigned char *icrp;
>> 1563 volatile unsigned long *imrp;
>> 1564
>> 1565 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
>> 1566 MCFINTC_ICR0);
>> 1567 for (b = 36; (b < 49); b++)
>> 1568 icrp[b] = 0x04;
>> 1569 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
>> 1570 MCFINTC_IMRH);
>> 1571 *imrp &= ~0x0001FFF0;
>> 1572 }
>> 1573 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
>> 1574 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
>> 1575 }
>> 1576
>> 1577 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
>> 1578 {
>> 1579 volatile fec_t *fecp;
>> 1580
>> 1581 fecp = fep->hwp;
>> 1582 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
>> 1583 fecp->fec_x_cntrl = 0x00;
>> 1584
>> 1585 /*
>> 1586 * Set MII speed to 2.5 MHz
>> 1587 * See 5282 manual section 17.5.4.7: MSCR
>> 1588 */
>> 1589 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
>> 1590 fecp->fec_mii_speed = fep->phy_speed;
>> 1591
>> 1592 fec_restart(dev, 0);
>> 1593 }
>> 1594
>> 1595 static void __inline__ fec_get_mac(struct net_device *dev)
>> 1596 {
>> 1597 struct fec_enet_private *fep = netdev_priv(dev);
>> 1598 volatile fec_t *fecp;
>> 1599 unsigned char *iap, tmpaddr[ETH_ALEN];
>> 1600
>> 1601 fecp = fep->hwp;
>> 1602
>> 1603 if (FEC_FLASHMAC) {
>> 1604 /*
>> 1605 * Get MAC address from FLASH.
>> 1606 * If it is all 1's or 0's, use the default.
>> 1607 */
>> 1608 iap = FEC_FLASHMAC;
>> 1609 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
>> 1610 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
>> 1611 iap = fec_mac_default;
>> 1612 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
>> 1613 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
>> 1614 iap = fec_mac_default;
>> 1615 } else {
>> 1616 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
>> 1617 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
>> 1618 iap = &tmpaddr[0];
>> 1619 }
>> 1620
>> 1621 memcpy(dev->dev_addr, iap, ETH_ALEN);
>> 1622
>> 1623 /* Adjust MAC if using default MAC address */
>> 1624 if (iap == fec_mac_default)
>> 1625 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
>> 1626 }
>> 1627
>> 1628 static void __inline__ fec_enable_phy_intr(void)
>> 1629 {
>> 1630 }
>> 1631
>> 1632 static void __inline__ fec_disable_phy_intr(void)
>> 1633 {
>> 1634 }
>> 1635
>> 1636 static void __inline__ fec_phy_ack_intr(void)
>> 1637 {
>> 1638 }
>> 1639
>> 1640 static void __inline__ fec_localhw_setup(void)
>> 1641 {
>> 1642 }
>> 1643
>> 1644 static void __inline__ fec_uncache(unsigned long addr)
>> 1645 {
>> 1646 }
>> 1647
>> 1648 /* ------------------------------------------------------------------------- */
>> 1649
>> 1650 #elif defined(CONFIG_M532x)
>> 1651 /*
>> 1652 * Code specific for M532x
>> 1653 */
>> 1654 static void __inline__ fec_request_intrs(struct net_device *dev)
>> 1655 {
>> 1656 struct fec_enet_private *fep;
>> 1657 int b;
>> 1658 static const struct idesc {
>> 1659 char *name;
>> 1660 unsigned short irq;
>> 1661 } *idp, id[] = {
>> 1662 { "fec(TXF)", 36 },
>> 1663 { "fec(TXB)", 37 },
>> 1664 { "fec(TXFIFO)", 38 },
>> 1665 { "fec(TXCR)", 39 },
>> 1666 { "fec(RXF)", 40 },
>> 1667 { "fec(RXB)", 41 },
>> 1668 { "fec(MII)", 42 },
>> 1669 { "fec(LC)", 43 },
>> 1670 { "fec(HBERR)", 44 },
>> 1671 { "fec(GRA)", 45 },
>> 1672 { "fec(EBERR)", 46 },
>> 1673 { "fec(BABT)", 47 },
>> 1674 { "fec(BABR)", 48 },
>> 1675 { NULL },
>> 1676 };
>> 1677
>> 1678 fep = netdev_priv(dev);
>> 1679 b = (fep->index) ? 128 : 64;
>> 1680
>> 1681 /* Setup interrupt handlers. */
>> 1682 for (idp = id; idp->name; idp++) {
>> 1683 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
>> 1684 printk("FEC: Could not allocate %s IRQ(%d)!\n",
>> 1685 idp->name, b+idp->irq);
>> 1686 }
>> 1687
>> 1688 /* Unmask interrupts */
>> 1689 MCF_INTC0_ICR36 = 0x2;
>> 1690 MCF_INTC0_ICR37 = 0x2;
>> 1691 MCF_INTC0_ICR38 = 0x2;
>> 1692 MCF_INTC0_ICR39 = 0x2;
>> 1693 MCF_INTC0_ICR40 = 0x2;
>> 1694 MCF_INTC0_ICR41 = 0x2;
>> 1695 MCF_INTC0_ICR42 = 0x2;
>> 1696 MCF_INTC0_ICR43 = 0x2;
>> 1697 MCF_INTC0_ICR44 = 0x2;
>> 1698 MCF_INTC0_ICR45 = 0x2;
>> 1699 MCF_INTC0_ICR46 = 0x2;
>> 1700 MCF_INTC0_ICR47 = 0x2;
>> 1701 MCF_INTC0_ICR48 = 0x2;
>> 1702
>> 1703 MCF_INTC0_IMRH &= ~(
>> 1704 MCF_INTC_IMRH_INT_MASK36 |
>> 1705 MCF_INTC_IMRH_INT_MASK37 |
>> 1706 MCF_INTC_IMRH_INT_MASK38 |
>> 1707 MCF_INTC_IMRH_INT_MASK39 |
>> 1708 MCF_INTC_IMRH_INT_MASK40 |
>> 1709 MCF_INTC_IMRH_INT_MASK41 |
>> 1710 MCF_INTC_IMRH_INT_MASK42 |
>> 1711 MCF_INTC_IMRH_INT_MASK43 |
>> 1712 MCF_INTC_IMRH_INT_MASK44 |
>> 1713 MCF_INTC_IMRH_INT_MASK45 |
>> 1714 MCF_INTC_IMRH_INT_MASK46 |
>> 1715 MCF_INTC_IMRH_INT_MASK47 |
>> 1716 MCF_INTC_IMRH_INT_MASK48 );
>> 1717
>> 1718 /* Set up gpio outputs for MII lines */
>> 1719 MCF_GPIO_PAR_FECI2C |= (0 |
>> 1720 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
>> 1721 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
>> 1722 MCF_GPIO_PAR_FEC = (0 |
>> 1723 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
>> 1724 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
>> 1725 }
>> 1726
>> 1727 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
>> 1728 {
>> 1729 volatile fec_t *fecp;
>> 1730
>> 1731 fecp = fep->hwp;
>> 1732 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
>> 1733 fecp->fec_x_cntrl = 0x00;
>> 1734
>> 1735 /*
>> 1736 * Set MII speed to 2.5 MHz
>> 1737 */
>> 1738 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
>> 1739 fecp->fec_mii_speed = fep->phy_speed;
>> 1740
>> 1741 fec_restart(dev, 0);
>> 1742 }
>> 1743
>> 1744 static void __inline__ fec_get_mac(struct net_device *dev)
>> 1745 {
>> 1746 struct fec_enet_private *fep = netdev_priv(dev);
>> 1747 volatile fec_t *fecp;
>> 1748 unsigned char *iap, tmpaddr[ETH_ALEN];
>> 1749
>> 1750 fecp = fep->hwp;
>> 1751
>> 1752 if (FEC_FLASHMAC) {
>> 1753 /*
>> 1754 * Get MAC address from FLASH.
>> 1755 * If it is all 1's or 0's, use the default.
>> 1756 */
>> 1757 iap = FEC_FLASHMAC;
>> 1758 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
>> 1759 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
>> 1760 iap = fec_mac_default;
>> 1761 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
>> 1762 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
>> 1763 iap = fec_mac_default;
>> 1764 } else {
>> 1765 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
>> 1766 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
>> 1767 iap = &tmpaddr[0];
>> 1768 }
>> 1769
>> 1770 memcpy(dev->dev_addr, iap, ETH_ALEN);
>> 1771
>> 1772 /* Adjust MAC if using default MAC address */
>> 1773 if (iap == fec_mac_default)
>> 1774 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
>> 1775 }
>> 1776
>> 1777 static void __inline__ fec_enable_phy_intr(void)
>> 1778 {
>> 1779 }
>> 1780
>> 1781 static void __inline__ fec_disable_phy_intr(void)
>> 1782 {
>> 1783 }
>> 1784
>> 1785 static void __inline__ fec_phy_ack_intr(void)
>> 1786 {
>> 1787 }
>> 1788
>> 1789 static void __inline__ fec_localhw_setup(void)
>> 1790 {
>> 1791 }
>> 1792
>> 1793 /*
>> 1794 * Do not need to make region uncached on 532x.
>> 1795 */
>> 1796 static void __inline__ fec_uncache(unsigned long addr)
>> 1797 {
>> 1798 }
>> 1799
>> 1800 /* ------------------------------------------------------------------------- */
>> 1801
>> 1802
1392 #else 1803 #else
1393 1804
1394 /* 1805 /*
1395 * Code sepcific to the MPC860T setup. !! 1806 * Code specific to the MPC860T setup.
1396 */ 1807 */
1397 static void __inline__ fec_request_intrs(stru 1808 static void __inline__ fec_request_intrs(struct net_device *dev)
1398 { 1809 {
1399 volatile immap_t *immap; 1810 volatile immap_t *immap;
1400 1811
1401 immap = (immap_t *)IMAP_ADDR; /* po 1812 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1402 1813
1403 if (request_8xxirq(FEC_INTERRUPT, fec 1814 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1404 panic("Could not allocate FEC 1815 panic("Could not allocate FEC IRQ!");
1405 1816
1406 #ifdef CONFIG_RPXCLASSIC 1817 #ifdef CONFIG_RPXCLASSIC
1407 /* Make Port C, bit 15 an input that 1818 /* Make Port C, bit 15 an input that causes interrupts.
1408 */ 1819 */
1409 immap->im_ioport.iop_pcpar &= ~0x0001 1820 immap->im_ioport.iop_pcpar &= ~0x0001;
1410 immap->im_ioport.iop_pcdir &= ~0x0001 1821 immap->im_ioport.iop_pcdir &= ~0x0001;
1411 immap->im_ioport.iop_pcso &= ~0x0001; 1822 immap->im_ioport.iop_pcso &= ~0x0001;
1412 immap->im_ioport.iop_pcint |= 0x0001; 1823 immap->im_ioport.iop_pcint |= 0x0001;
1413 cpm_install_handler(CPMVEC_PIO_PC15, 1824 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1414 1825
1415 /* Make LEDS reflect Link status. 1826 /* Make LEDS reflect Link status.
1416 */ 1827 */
1417 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FE 1828 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1418 #endif 1829 #endif
1419 #ifdef CONFIG_FADS 1830 #ifdef CONFIG_FADS
1420 if (request_8xxirq(SIU_IRQ2, mii_link 1831 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1421 panic("Could not allocate MII 1832 panic("Could not allocate MII IRQ!");
1422 #endif 1833 #endif
1423 } 1834 }
1424 1835
1425 static void __inline__ fec_get_mac(struct net 1836 static void __inline__ fec_get_mac(struct net_device *dev)
1426 { 1837 {
1427 struct fec_enet_private *fep = netdev <<
1428 unsigned char *iap, tmpaddr[6]; <<
1429 bd_t *bd; 1838 bd_t *bd;
1430 int i; <<
1431 1839
1432 iap = bd->bi_enetaddr; <<
1433 bd = (bd_t *)__res; 1840 bd = (bd_t *)__res;
>> 1841 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1434 1842
1435 #ifdef CONFIG_RPXCLASSIC 1843 #ifdef CONFIG_RPXCLASSIC
1436 /* The Embedded Planet boards have on 1844 /* The Embedded Planet boards have only one MAC address in
1437 * the EEPROM, but can have two Ether 1845 * the EEPROM, but can have two Ethernet ports. For the
1438 * FEC port, we create another addres 1846 * FEC port, we create another address by setting one of
1439 * the address bits above something t 1847 * the address bits above something that would have (up to
1440 * now) been allocated. 1848 * now) been allocated.
1441 */ 1849 */
1442 for (i=0; i<6; i++) !! 1850 dev->dev_adrd[3] |= 0x80;
1443 tmpaddr[i] = *iap++; <<
1444 tmpaddr[3] |= 0x80; <<
1445 iap = tmpaddr; <<
1446 #endif 1851 #endif
1447 <<
1448 for (i=0; i<6; i++) <<
1449 dev->dev_addr[i] = fep->mac_a <<
1450 } 1852 }
1451 1853
1452 static void __inline__ fec_set_mii(struct net 1854 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1453 { 1855 {
1454 extern uint _get_IMMR(void); 1856 extern uint _get_IMMR(void);
1455 volatile immap_t *immap; 1857 volatile immap_t *immap;
1456 volatile fec_t *fecp; 1858 volatile fec_t *fecp;
1457 1859
1458 fecp = fep->hwp; 1860 fecp = fep->hwp;
1459 immap = (immap_t *)IMAP_ADDR; /* po 1861 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1460 1862
1461 /* Configure all of port D for MII. 1863 /* Configure all of port D for MII.
1462 */ 1864 */
1463 immap->im_ioport.iop_pdpar = 0x1fff; 1865 immap->im_ioport.iop_pdpar = 0x1fff;
1464 1866
1465 /* Bits moved from Rev. D onward. 1867 /* Bits moved from Rev. D onward.
1466 */ 1868 */
1467 if ((_get_IMMR() & 0xffff) < 0x0501) 1869 if ((_get_IMMR() & 0xffff) < 0x0501)
1468 immap->im_ioport.iop_pddir = 1870 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1469 else 1871 else
1470 immap->im_ioport.iop_pddir = 1872 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1471 !! 1873
1472 /* Set MII speed to 2.5 MHz 1874 /* Set MII speed to 2.5 MHz
1473 */ 1875 */
1474 fecp->fec_mii_speed = fep->phy_speed !! 1876 fecp->fec_mii_speed = fep->phy_speed =
1475 ((bd->bi_busfreq * 1000000) / 1877 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1476 } 1878 }
1477 1879
1478 static void __inline__ fec_enable_phy_intr(vo 1880 static void __inline__ fec_enable_phy_intr(void)
1479 { 1881 {
1480 volatile fec_t *fecp; 1882 volatile fec_t *fecp;
1481 1883
1482 fecp = fep->hwp; 1884 fecp = fep->hwp;
1483 1885
1484 /* Enable MII command finished interr !! 1886 /* Enable MII command finished interrupt
1485 */ 1887 */
1486 fecp->fec_ivec = (FEC_INTERRUPT/2) << 1888 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1487 } 1889 }
1488 1890
1489 static void __inline__ fec_disable_phy_intr(v 1891 static void __inline__ fec_disable_phy_intr(void)
1490 { 1892 {
1491 } 1893 }
1492 1894
1493 static void __inline__ fec_phy_ack_intr(void) 1895 static void __inline__ fec_phy_ack_intr(void)
1494 { 1896 {
1495 } 1897 }
1496 1898
1497 static void __inline__ fec_localhw_setup(void 1899 static void __inline__ fec_localhw_setup(void)
1498 { 1900 {
1499 volatile fec_t *fecp; 1901 volatile fec_t *fecp;
1500 1902
1501 fecp = fep->hwp; 1903 fecp = fep->hwp;
1502 fecp->fec_r_hash = PKT_MAXBUF_SIZE; 1904 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1503 /* Enable big endian and don't care a 1905 /* Enable big endian and don't care about SDMA FC.
1504 */ 1906 */
1505 fecp->fec_fun_code = 0x78000000; 1907 fecp->fec_fun_code = 0x78000000;
1506 } 1908 }
1507 1909
1508 static void __inline__ fec_uncache(unsigned l 1910 static void __inline__ fec_uncache(unsigned long addr)
1509 { 1911 {
1510 pte_t *pte; 1912 pte_t *pte;
1511 pte = va_to_pte(mem_addr); 1913 pte = va_to_pte(mem_addr);
1512 pte_val(*pte) |= _PAGE_NO_CACHE; 1914 pte_val(*pte) |= _PAGE_NO_CACHE;
1513 flush_tlb_page(init_mm.mmap, mem_addr 1915 flush_tlb_page(init_mm.mmap, mem_addr);
1514 } 1916 }
1515 1917
1516 #endif 1918 #endif
1517 1919
1518 /* ------------------------------------------ 1920 /* ------------------------------------------------------------------------- */
1519 1921
1520 static void mii_display_status(struct net_dev 1922 static void mii_display_status(struct net_device *dev)
1521 { 1923 {
1522 struct fec_enet_private *fep = netdev 1924 struct fec_enet_private *fep = netdev_priv(dev);
1523 volatile uint *s = &(fep->phy_status) 1925 volatile uint *s = &(fep->phy_status);
1524 1926
1525 if (!fep->link && !fep->old_link) { 1927 if (!fep->link && !fep->old_link) {
1526 /* Link is still down - don't 1928 /* Link is still down - don't print anything */
1527 return; 1929 return;
1528 } 1930 }
1529 1931
1530 printk("%s: status: ", dev->name); 1932 printk("%s: status: ", dev->name);
1531 1933
1532 if (!fep->link) { 1934 if (!fep->link) {
1533 printk("link down"); 1935 printk("link down");
1534 } else { 1936 } else {
1535 printk("link up"); 1937 printk("link up");
1536 1938
1537 switch(*s & PHY_STAT_SPMASK) 1939 switch(*s & PHY_STAT_SPMASK) {
1538 case PHY_STAT_100FDX: printk( 1940 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1539 case PHY_STAT_100HDX: printk( 1941 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1540 case PHY_STAT_10FDX: printk(" 1942 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1541 case PHY_STAT_10HDX: printk(" 1943 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1542 default: 1944 default:
1543 printk(", Unknown spe 1945 printk(", Unknown speed/duplex");
1544 } 1946 }
1545 1947
1546 if (*s & PHY_STAT_ANC) 1948 if (*s & PHY_STAT_ANC)
1547 printk(", auto-negoti 1949 printk(", auto-negotiation complete");
1548 } 1950 }
1549 1951
1550 if (*s & PHY_STAT_FAULT) 1952 if (*s & PHY_STAT_FAULT)
1551 printk(", remote fault"); 1953 printk(", remote fault");
1552 1954
1553 printk(".\n"); 1955 printk(".\n");
1554 } 1956 }
1555 1957
1556 static void mii_display_config(struct net_dev !! 1958 static void mii_display_config(struct work_struct *work)
1557 { 1959 {
1558 struct fec_enet_private *fep = netdev !! 1960 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1559 volatile uint *s = &(fep->phy_status) !! 1961 struct net_device *dev = fep->netdev;
>> 1962 uint status = fep->phy_status;
1560 1963
1561 /* 1964 /*
1562 ** When we get here, phy_task is alre 1965 ** When we get here, phy_task is already removed from
1563 ** the workqueue. It is thus safe to 1966 ** the workqueue. It is thus safe to allow to reuse it.
1564 */ 1967 */
1565 fep->mii_phy_task_queued = 0; 1968 fep->mii_phy_task_queued = 0;
1566 printk("%s: config: auto-negotiation 1969 printk("%s: config: auto-negotiation ", dev->name);
1567 1970
1568 if (*s & PHY_CONF_ANE) !! 1971 if (status & PHY_CONF_ANE)
1569 printk("on"); 1972 printk("on");
1570 else 1973 else
1571 printk("off"); 1974 printk("off");
1572 1975
1573 if (*s & PHY_CONF_100FDX) !! 1976 if (status & PHY_CONF_100FDX)
1574 printk(", 100FDX"); 1977 printk(", 100FDX");
1575 if (*s & PHY_CONF_100HDX) !! 1978 if (status & PHY_CONF_100HDX)
1576 printk(", 100HDX"); 1979 printk(", 100HDX");
1577 if (*s & PHY_CONF_10FDX) !! 1980 if (status & PHY_CONF_10FDX)
1578 printk(", 10FDX"); 1981 printk(", 10FDX");
1579 if (*s & PHY_CONF_10HDX) !! 1982 if (status & PHY_CONF_10HDX)
1580 printk(", 10HDX"); 1983 printk(", 10HDX");
1581 if (!(*s & PHY_CONF_SPMASK)) !! 1984 if (!(status & PHY_CONF_SPMASK))
1582 printk(", No speed/duplex sel 1985 printk(", No speed/duplex selected?");
1583 1986
1584 if (*s & PHY_CONF_LOOP) !! 1987 if (status & PHY_CONF_LOOP)
1585 printk(", loopback enabled"); 1988 printk(", loopback enabled");
1586 !! 1989
1587 printk(".\n"); 1990 printk(".\n");
1588 1991
1589 fep->sequence_done = 1; 1992 fep->sequence_done = 1;
1590 } 1993 }
1591 1994
1592 static void mii_relink(struct net_device *dev !! 1995 static void mii_relink(struct work_struct *work)
1593 { 1996 {
1594 struct fec_enet_private *fep = netdev !! 1997 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
>> 1998 struct net_device *dev = fep->netdev;
1595 int duplex; 1999 int duplex;
1596 2000
1597 /* 2001 /*
1598 ** When we get here, phy_task is alre 2002 ** When we get here, phy_task is already removed from
1599 ** the workqueue. It is thus safe to 2003 ** the workqueue. It is thus safe to allow to reuse it.
1600 */ 2004 */
1601 fep->mii_phy_task_queued = 0; 2005 fep->mii_phy_task_queued = 0;
1602 fep->link = (fep->phy_status & PHY_ST 2006 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1603 mii_display_status(dev); 2007 mii_display_status(dev);
1604 fep->old_link = fep->link; 2008 fep->old_link = fep->link;
1605 2009
1606 if (fep->link) { 2010 if (fep->link) {
1607 duplex = 0; 2011 duplex = 0;
1608 if (fep->phy_status !! 2012 if (fep->phy_status
1609 & (PHY_STAT_100FDX | PHY_ 2013 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1610 duplex = 1; 2014 duplex = 1;
1611 fec_restart(dev, duplex); 2015 fec_restart(dev, duplex);
1612 } !! 2016 } else
1613 else <<
1614 fec_stop(dev); 2017 fec_stop(dev);
1615 2018
1616 #if 0 2019 #if 0
1617 enable_irq(fep->mii_irq); 2020 enable_irq(fep->mii_irq);
1618 #endif 2021 #endif
1619 2022
1620 } 2023 }
1621 2024
1622 /* mii_queue_relink is called in interrupt co 2025 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1623 static void mii_queue_relink(uint mii_reg, st 2026 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1624 { 2027 {
1625 struct fec_enet_private *fep = netdev 2028 struct fec_enet_private *fep = netdev_priv(dev);
1626 2029
1627 /* 2030 /*
1628 ** We cannot queue phy_task twice in 2031 ** We cannot queue phy_task twice in the workqueue. It
1629 ** would cause an endless loop in the 2032 ** would cause an endless loop in the workqueue.
1630 ** Fortunately, if the last mii_relin 2033 ** Fortunately, if the last mii_relink entry has not yet been
1631 ** executed now, it will do the job f 2034 ** executed now, it will do the job for the current interrupt,
1632 ** which is just what we want. 2035 ** which is just what we want.
1633 */ 2036 */
1634 if (fep->mii_phy_task_queued) 2037 if (fep->mii_phy_task_queued)
1635 return; 2038 return;
1636 2039
1637 fep->mii_phy_task_queued = 1; 2040 fep->mii_phy_task_queued = 1;
1638 INIT_WORK(&fep->phy_task, (void*)mii_ !! 2041 INIT_WORK(&fep->phy_task, mii_relink);
1639 schedule_work(&fep->phy_task); 2042 schedule_work(&fep->phy_task);
1640 } 2043 }
1641 2044
1642 /* mii_queue_config is called in user context !! 2045 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1643 static void mii_queue_config(uint mii_reg, st 2046 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1644 { 2047 {
1645 struct fec_enet_private *fep = netdev 2048 struct fec_enet_private *fep = netdev_priv(dev);
1646 2049
1647 if (fep->mii_phy_task_queued) 2050 if (fep->mii_phy_task_queued)
1648 return; 2051 return;
1649 2052
1650 fep->mii_phy_task_queued = 1; 2053 fep->mii_phy_task_queued = 1;
1651 INIT_WORK(&fep->phy_task, (void*)mii_ !! 2054 INIT_WORK(&fep->phy_task, mii_display_config);
1652 schedule_work(&fep->phy_task); 2055 schedule_work(&fep->phy_task);
1653 } 2056 }
1654 2057
1655 !! 2058 phy_cmd_t const phy_cmd_relink[] = {
1656 !! 2059 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1657 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read( !! 2060 { mk_mii_end, }
1658 { mk_mii_end, !! 2061 };
1659 phy_cmd_t phy_cmd_config[] = { { mk_mii_read( !! 2062 phy_cmd_t const phy_cmd_config[] = {
1660 { mk_mii_end, !! 2063 { mk_mii_read(MII_REG_CR), mii_queue_config },
1661 !! 2064 { mk_mii_end, }
1662 !! 2065 };
1663 2066
1664 /* Read remainder of PHY ID. 2067 /* Read remainder of PHY ID.
1665 */ 2068 */
1666 static void 2069 static void
1667 mii_discover_phy3(uint mii_reg, struct net_de 2070 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1668 { 2071 {
1669 struct fec_enet_private *fep; 2072 struct fec_enet_private *fep;
1670 int i; 2073 int i;
1671 2074
1672 fep = netdev_priv(dev); 2075 fep = netdev_priv(dev);
1673 fep->phy_id |= (mii_reg & 0xffff); 2076 fep->phy_id |= (mii_reg & 0xffff);
1674 printk("fec: PHY @ 0x%x, ID 0x%08x", 2077 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1675 2078
1676 for(i = 0; phy_info[i]; i++) { 2079 for(i = 0; phy_info[i]; i++) {
1677 if(phy_info[i]->id == (fep->p 2080 if(phy_info[i]->id == (fep->phy_id >> 4))
1678 break; 2081 break;
1679 } 2082 }
1680 2083
1681 if (phy_info[i]) 2084 if (phy_info[i])
1682 printk(" -- %s\n", phy_info[i 2085 printk(" -- %s\n", phy_info[i]->name);
1683 else 2086 else
1684 printk(" -- unknown PHY!\n"); 2087 printk(" -- unknown PHY!\n");
1685 !! 2088
1686 fep->phy = phy_info[i]; 2089 fep->phy = phy_info[i];
1687 fep->phy_id_done = 1; 2090 fep->phy_id_done = 1;
1688 } 2091 }
1689 2092
1690 /* Scan all of the MII PHY addresses looking 2093 /* Scan all of the MII PHY addresses looking for someone to respond
1691 * with a valid ID. This usually happens qui 2094 * with a valid ID. This usually happens quickly.
1692 */ 2095 */
1693 static void 2096 static void
1694 mii_discover_phy(uint mii_reg, struct net_dev 2097 mii_discover_phy(uint mii_reg, struct net_device *dev)
1695 { 2098 {
1696 struct fec_enet_private *fep; 2099 struct fec_enet_private *fep;
1697 volatile fec_t *fecp; 2100 volatile fec_t *fecp;
1698 uint phytype; 2101 uint phytype;
1699 2102
1700 fep = netdev_priv(dev); 2103 fep = netdev_priv(dev);
1701 fecp = fep->hwp; 2104 fecp = fep->hwp;
1702 2105
1703 if (fep->phy_addr < 32) { 2106 if (fep->phy_addr < 32) {
1704 if ((phytype = (mii_reg & 0xf 2107 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1705 !! 2108
1706 /* Got first part of 2109 /* Got first part of ID, now get remainder.
1707 */ 2110 */
1708 fep->phy_id = phytype 2111 fep->phy_id = phytype << 16;
1709 mii_queue(dev, mk_mii 2112 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1710 2113 mii_discover_phy3);
1711 } !! 2114 } else {
1712 else { <<
1713 fep->phy_addr++; 2115 fep->phy_addr++;
1714 mii_queue(dev, mk_mii 2116 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1715 2117 mii_discover_phy);
1716 } 2118 }
1717 } else { 2119 } else {
1718 printk("FEC: No PHY device fo 2120 printk("FEC: No PHY device found.\n");
1719 /* Disable external MII inter 2121 /* Disable external MII interface */
1720 fecp->fec_mii_speed = fep->ph 2122 fecp->fec_mii_speed = fep->phy_speed = 0;
1721 fec_disable_phy_intr(); 2123 fec_disable_phy_intr();
1722 } 2124 }
1723 } 2125 }
1724 2126
1725 /* This interrupt occurs when the PHY detects 2127 /* This interrupt occurs when the PHY detects a link change.
1726 */ 2128 */
1727 #ifdef CONFIG_RPXCLASSIC 2129 #ifdef CONFIG_RPXCLASSIC
1728 static void 2130 static void
1729 mii_link_interrupt(void *dev_id) 2131 mii_link_interrupt(void *dev_id)
1730 #else 2132 #else
1731 static irqreturn_t 2133 static irqreturn_t
1732 mii_link_interrupt(int irq, void * dev_id, st !! 2134 mii_link_interrupt(int irq, void * dev_id)
1733 #endif 2135 #endif
1734 { 2136 {
1735 struct net_device *dev = dev_id; 2137 struct net_device *dev = dev_id;
1736 struct fec_enet_private *fep = netdev 2138 struct fec_enet_private *fep = netdev_priv(dev);
1737 2139
1738 fec_phy_ack_intr(); 2140 fec_phy_ack_intr();
1739 2141
1740 #if 0 2142 #if 0
1741 disable_irq(fep->mii_irq); /* disabl 2143 disable_irq(fep->mii_irq); /* disable now, enable later */
1742 #endif 2144 #endif
1743 2145
1744 mii_do_cmd(dev, fep->phy->ack_int); 2146 mii_do_cmd(dev, fep->phy->ack_int);
1745 mii_do_cmd(dev, phy_cmd_relink); /* 2147 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1746 2148
1747 return IRQ_HANDLED; 2149 return IRQ_HANDLED;
1748 } 2150 }
1749 2151
1750 static int 2152 static int
1751 fec_enet_open(struct net_device *dev) 2153 fec_enet_open(struct net_device *dev)
1752 { 2154 {
1753 struct fec_enet_private *fep = netdev 2155 struct fec_enet_private *fep = netdev_priv(dev);
1754 2156
1755 /* I should reset the ring buffers he 2157 /* I should reset the ring buffers here, but I don't yet know
1756 * a simple way to do that. 2158 * a simple way to do that.
1757 */ 2159 */
1758 fec_set_mac_address(dev); 2160 fec_set_mac_address(dev);
1759 2161
1760 fep->sequence_done = 0; 2162 fep->sequence_done = 0;
1761 fep->link = 0; 2163 fep->link = 0;
1762 2164
1763 if (fep->phy) { 2165 if (fep->phy) {
1764 mii_do_cmd(dev, fep->phy->ack 2166 mii_do_cmd(dev, fep->phy->ack_int);
1765 mii_do_cmd(dev, fep->phy->con 2167 mii_do_cmd(dev, fep->phy->config);
1766 mii_do_cmd(dev, phy_cmd_confi 2168 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1767 2169
1768 /* FIXME: use netif_carrier_{ !! 2170 /* Poll until the PHY tells us its configuration
1769 * until link is up which is !! 2171 * (not link state).
1770 * 30 seconds or more we are !! 2172 * Request is initiated by mii_do_cmd above, but answer
>> 2173 * comes by interrupt.
>> 2174 * This should take about 25 usec per register at 2.5 MHz,
>> 2175 * and we read approximately 5 registers.
1771 */ 2176 */
1772 while(!fep->sequence_done) 2177 while(!fep->sequence_done)
1773 schedule(); 2178 schedule();
1774 2179
1775 mii_do_cmd(dev, fep->phy->sta 2180 mii_do_cmd(dev, fep->phy->startup);
1776 2181
1777 /* Set the initial link state 2182 /* Set the initial link state to true. A lot of hardware
1778 * based on this device does 2183 * based on this device does not implement a PHY interrupt,
1779 * so we are never notified o 2184 * so we are never notified of link change.
1780 */ 2185 */
1781 fep->link = 1; 2186 fep->link = 1;
1782 } else { 2187 } else {
1783 fep->link = 1; /* lets just t 2188 fep->link = 1; /* lets just try it and see */
1784 /* no phy, go full duplex, 2189 /* no phy, go full duplex, it's most likely a hub chip */
1785 fec_restart(dev, 1); 2190 fec_restart(dev, 1);
1786 } 2191 }
1787 2192
1788 netif_start_queue(dev); 2193 netif_start_queue(dev);
1789 fep->opened = 1; 2194 fep->opened = 1;
1790 return 0; /* Success */ 2195 return 0; /* Success */
1791 } 2196 }
1792 2197
1793 static int 2198 static int
1794 fec_enet_close(struct net_device *dev) 2199 fec_enet_close(struct net_device *dev)
1795 { 2200 {
1796 struct fec_enet_private *fep = netdev 2201 struct fec_enet_private *fep = netdev_priv(dev);
1797 2202
1798 /* Don't know what to do yet. 2203 /* Don't know what to do yet.
1799 */ 2204 */
1800 fep->opened = 0; 2205 fep->opened = 0;
1801 netif_stop_queue(dev); 2206 netif_stop_queue(dev);
1802 fec_stop(dev); 2207 fec_stop(dev);
1803 2208
1804 return 0; 2209 return 0;
1805 } 2210 }
1806 2211
1807 static struct net_device_stats *fec_enet_get_ <<
1808 { <<
1809 struct fec_enet_private *fep = netdev <<
1810 <<
1811 return &fep->stats; <<
1812 } <<
1813 <<
1814 /* Set or clear the multicast filter for this 2212 /* Set or clear the multicast filter for this adaptor.
1815 * Skeleton taken from sunlance driver. 2213 * Skeleton taken from sunlance driver.
1816 * The CPM Ethernet implementation allows Mul 2214 * The CPM Ethernet implementation allows Multicast as well as individual
1817 * MAC address filtering. Some of the driver 2215 * MAC address filtering. Some of the drivers check to make sure it is
1818 * a group multicast address, and discard tho 2216 * a group multicast address, and discard those that are not. I guess I
1819 * will do the same for now, but just remove 2217 * will do the same for now, but just remove the test if you want
1820 * individual filtering as well (do the upper 2218 * individual filtering as well (do the upper net layers want or support
1821 * this kind of feature?). 2219 * this kind of feature?).
1822 */ 2220 */
1823 2221
1824 #define HASH_BITS 6 /* #b 2222 #define HASH_BITS 6 /* #bits in hash */
1825 #define CRC32_POLY 0xEDB88320 2223 #define CRC32_POLY 0xEDB88320
1826 2224
1827 static void set_multicast_list(struct net_dev 2225 static void set_multicast_list(struct net_device *dev)
1828 { 2226 {
1829 struct fec_enet_private *fep; 2227 struct fec_enet_private *fep;
1830 volatile fec_t *ep; 2228 volatile fec_t *ep;
1831 struct dev_mc_list *dmi; 2229 struct dev_mc_list *dmi;
1832 unsigned int i, j, bit, data, crc; 2230 unsigned int i, j, bit, data, crc;
1833 unsigned char hash; 2231 unsigned char hash;
1834 2232
1835 fep = netdev_priv(dev); 2233 fep = netdev_priv(dev);
1836 ep = fep->hwp; 2234 ep = fep->hwp;
1837 2235
1838 if (dev->flags&IFF_PROMISC) { 2236 if (dev->flags&IFF_PROMISC) {
1839 /* Log any net taps. */ <<
1840 printk("%s: Promiscuous mode <<
1841 ep->fec_r_cntrl |= 0x0008; 2237 ep->fec_r_cntrl |= 0x0008;
1842 } else { 2238 } else {
1843 2239
1844 ep->fec_r_cntrl &= ~0x0008; 2240 ep->fec_r_cntrl &= ~0x0008;
1845 2241
1846 if (dev->flags & IFF_ALLMULTI 2242 if (dev->flags & IFF_ALLMULTI) {
1847 /* Catch all multicas 2243 /* Catch all multicast addresses, so set the
1848 * filter to all 1's. 2244 * filter to all 1's.
1849 */ 2245 */
1850 ep->fec_hash_table_hi 2246 ep->fec_hash_table_high = 0xffffffff;
1851 ep->fec_hash_table_lo 2247 ep->fec_hash_table_low = 0xffffffff;
1852 } else { 2248 } else {
1853 /* Clear filter and a 2249 /* Clear filter and add the addresses in hash register.
1854 */ 2250 */
1855 ep->fec_hash_table_hi 2251 ep->fec_hash_table_high = 0;
1856 ep->fec_hash_table_lo 2252 ep->fec_hash_table_low = 0;
1857 !! 2253
1858 dmi = dev->mc_list; 2254 dmi = dev->mc_list;
1859 2255
1860 for (j = 0; j < dev-> 2256 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
1861 { 2257 {
1862 /* Only suppo 2258 /* Only support group multicast for now.
1863 */ 2259 */
1864 if (!(dmi->dm 2260 if (!(dmi->dmi_addr[0] & 1))
1865 conti 2261 continue;
1866 !! 2262
1867 /* calculate 2263 /* calculate crc32 value of mac address
1868 */ 2264 */
1869 crc = 0xfffff 2265 crc = 0xffffffff;
1870 2266
1871 for (i = 0; i 2267 for (i = 0; i < dmi->dmi_addrlen; i++)
1872 { 2268 {
1873 data 2269 data = dmi->dmi_addr[i];
1874 for ( 2270 for (bit = 0; bit < 8; bit++, data >>= 1)
1875 { 2271 {
1876 2272 crc = (crc >> 1) ^
1877 2273 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1878 } 2274 }
1879 } 2275 }
1880 2276
1881 /* only upper 2277 /* only upper 6 bits (HASH_BITS) are used
1882 which poin 2278 which point to specific bit in he hash registers
1883 */ 2279 */
1884 hash = (crc > 2280 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1885 !! 2281
1886 if (hash > 31 2282 if (hash > 31)
1887 ep->f 2283 ep->fec_hash_table_high |= 1 << (hash - 32);
1888 else 2284 else
1889 ep->f 2285 ep->fec_hash_table_low |= 1 << hash;
1890 } 2286 }
1891 } 2287 }
1892 } 2288 }
1893 } 2289 }
1894 2290
1895 /* Set a MAC change in hardware. 2291 /* Set a MAC change in hardware.
1896 */ 2292 */
1897 static void 2293 static void
1898 fec_set_mac_address(struct net_device *dev) 2294 fec_set_mac_address(struct net_device *dev)
1899 { 2295 {
1900 struct fec_enet_private *fep; <<
1901 volatile fec_t *fecp; 2296 volatile fec_t *fecp;
1902 2297
1903 fep = netdev_priv(dev); !! 2298 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
1904 fecp = fep->hwp; <<
1905 2299
1906 /* Set station address. */ 2300 /* Set station address. */
1907 fecp->fec_addr_low = fep->mac_addr[3] !! 2301 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
1908 (fep->mac_addr[1] << 16) | (f !! 2302 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
1909 fecp->fec_addr_high = (fep->mac_addr[ !! 2303 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
1910 (fep->mac_addr[4] << 24); !! 2304 (dev->dev_addr[4] << 24);
1911 2305
1912 } 2306 }
1913 2307
1914 /* Initialize the FEC Ethernet on 860T (or Co 2308 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
1915 */ 2309 */
1916 /* 2310 /*
1917 * XXX: We need to clean up on failure exit 2311 * XXX: We need to clean up on failure exits here.
1918 */ 2312 */
1919 int __init fec_enet_init(struct net_device *d 2313 int __init fec_enet_init(struct net_device *dev)
1920 { 2314 {
1921 struct fec_enet_private *fep = netdev 2315 struct fec_enet_private *fep = netdev_priv(dev);
1922 unsigned long mem_addr; 2316 unsigned long mem_addr;
1923 volatile cbd_t *bdp; 2317 volatile cbd_t *bdp;
1924 cbd_t *cbd_base; 2318 cbd_t *cbd_base;
1925 volatile fec_t *fecp; 2319 volatile fec_t *fecp;
1926 int i, j; 2320 int i, j;
1927 static int index = 0; 2321 static int index = 0;
1928 2322
1929 /* Only allow us to be probed once. * 2323 /* Only allow us to be probed once. */
1930 if (index >= FEC_MAX_PORTS) 2324 if (index >= FEC_MAX_PORTS)
1931 return -ENXIO; 2325 return -ENXIO;
1932 2326
>> 2327 /* Allocate memory for buffer descriptors.
>> 2328 */
>> 2329 mem_addr = __get_free_page(GFP_KERNEL);
>> 2330 if (mem_addr == 0) {
>> 2331 printk("FEC: allocate descriptor memory failed?\n");
>> 2332 return -ENOMEM;
>> 2333 }
>> 2334
1933 /* Create an Ethernet device instance 2335 /* Create an Ethernet device instance.
1934 */ 2336 */
1935 fecp = (volatile fec_t *) fec_hw[inde 2337 fecp = (volatile fec_t *) fec_hw[index];
1936 2338
1937 fep->index = index; 2339 fep->index = index;
1938 fep->hwp = fecp; 2340 fep->hwp = fecp;
>> 2341 fep->netdev = dev;
1939 2342
1940 /* Whack a reset. We should wait for 2343 /* Whack a reset. We should wait for this.
1941 */ 2344 */
1942 fecp->fec_ecntrl = 1; 2345 fecp->fec_ecntrl = 1;
1943 udelay(10); 2346 udelay(10);
1944 2347
1945 /* Clear and enable interrupts */ <<
1946 fecp->fec_ievent = 0xffc0; <<
1947 fecp->fec_imask = (FEC_ENET_TXF | FEC <<
1948 FEC_ENET_RXF | FEC_ENET_RXB | <<
1949 fecp->fec_hash_table_high = 0; <<
1950 fecp->fec_hash_table_low = 0; <<
1951 fecp->fec_r_buff_size = PKT_MAXBLR_SI <<
1952 fecp->fec_ecntrl = 2; <<
1953 fecp->fec_r_des_active = 0x01000000; <<
1954 <<
1955 /* Set the Ethernet address. If usin 2348 /* Set the Ethernet address. If using multiple Enets on the 8xx,
1956 * this needs some work to get unique 2349 * this needs some work to get unique addresses.
1957 * 2350 *
1958 * This is our default MAC address un 2351 * This is our default MAC address unless the user changes
1959 * it via eth_mac_addr (our dev->set_ 2352 * it via eth_mac_addr (our dev->set_mac_addr handler).
1960 */ 2353 */
1961 fec_get_mac(dev); 2354 fec_get_mac(dev);
1962 2355
1963 /* Allocate memory for buffer descrip <<
1964 */ <<
1965 if (((RX_RING_SIZE + TX_RING_SIZE) * <<
1966 printk("FEC init error. Need <<
1967 printk("FEC initialization fa <<
1968 return 1; <<
1969 } <<
1970 mem_addr = __get_free_page(GFP_KERNEL <<
1971 cbd_base = (cbd_t *)mem_addr; 2356 cbd_base = (cbd_t *)mem_addr;
1972 /* XXX: missing check for allocation 2357 /* XXX: missing check for allocation failure */
1973 2358
1974 fec_uncache(mem_addr); 2359 fec_uncache(mem_addr);
1975 2360
1976 /* Set receive and transmit descripto 2361 /* Set receive and transmit descriptor base.
1977 */ 2362 */
1978 fep->rx_bd_base = cbd_base; 2363 fep->rx_bd_base = cbd_base;
1979 fep->tx_bd_base = cbd_base + RX_RING_ 2364 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1980 2365
1981 fep->dirty_tx = fep->cur_tx = fep->tx 2366 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1982 fep->cur_rx = fep->rx_bd_base; 2367 fep->cur_rx = fep->rx_bd_base;
1983 2368
1984 fep->skb_cur = fep->skb_dirty = 0; 2369 fep->skb_cur = fep->skb_dirty = 0;
1985 2370
1986 /* Initialize the receive buffer desc 2371 /* Initialize the receive buffer descriptors.
1987 */ 2372 */
1988 bdp = fep->rx_bd_base; 2373 bdp = fep->rx_bd_base;
1989 for (i=0; i<FEC_ENET_RX_PAGES; i++) { 2374 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1990 2375
1991 /* Allocate a page. 2376 /* Allocate a page.
1992 */ 2377 */
1993 mem_addr = __get_free_page(GF 2378 mem_addr = __get_free_page(GFP_KERNEL);
1994 /* XXX: missing check for all 2379 /* XXX: missing check for allocation failure */
1995 2380
1996 fec_uncache(mem_addr); 2381 fec_uncache(mem_addr);
1997 2382
1998 /* Initialize the BD for ever 2383 /* Initialize the BD for every fragment in the page.
1999 */ 2384 */
2000 for (j=0; j<FEC_ENET_RX_FRPPG 2385 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2001 bdp->cbd_sc = BD_ENET 2386 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2002 bdp->cbd_bufaddr = __ 2387 bdp->cbd_bufaddr = __pa(mem_addr);
2003 mem_addr += FEC_ENET_ 2388 mem_addr += FEC_ENET_RX_FRSIZE;
2004 bdp++; 2389 bdp++;
2005 } 2390 }
2006 } 2391 }
2007 2392
2008 /* Set the last buffer to wrap. 2393 /* Set the last buffer to wrap.
2009 */ 2394 */
2010 bdp--; 2395 bdp--;
2011 bdp->cbd_sc |= BD_SC_WRAP; 2396 bdp->cbd_sc |= BD_SC_WRAP;
2012 2397
2013 /* ...and the same for transmmit. 2398 /* ...and the same for transmmit.
2014 */ 2399 */
2015 bdp = fep->tx_bd_base; 2400 bdp = fep->tx_bd_base;
2016 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_R 2401 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2017 if (j >= FEC_ENET_TX_FRPPG) { 2402 if (j >= FEC_ENET_TX_FRPPG) {
2018 mem_addr = __get_free 2403 mem_addr = __get_free_page(GFP_KERNEL);
2019 j = 1; 2404 j = 1;
2020 } else { 2405 } else {
2021 mem_addr += FEC_ENET_ 2406 mem_addr += FEC_ENET_TX_FRSIZE;
2022 j++; 2407 j++;
2023 } 2408 }
2024 fep->tx_bounce[i] = (unsigned 2409 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2025 2410
2026 /* Initialize the BD for ever 2411 /* Initialize the BD for every fragment in the page.
2027 */ 2412 */
2028 bdp->cbd_sc = 0; 2413 bdp->cbd_sc = 0;
2029 bdp->cbd_bufaddr = 0; 2414 bdp->cbd_bufaddr = 0;
2030 bdp++; 2415 bdp++;
2031 } 2416 }
2032 2417
2033 /* Set the last buffer to wrap. 2418 /* Set the last buffer to wrap.
2034 */ 2419 */
2035 bdp--; 2420 bdp--;
2036 bdp->cbd_sc |= BD_SC_WRAP; 2421 bdp->cbd_sc |= BD_SC_WRAP;
2037 2422
2038 /* Set receive and transmit descripto 2423 /* Set receive and transmit descriptor base.
2039 */ 2424 */
2040 fecp->fec_r_des_start = __pa((uint)(f 2425 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2041 fecp->fec_x_des_start = __pa((uint)(f 2426 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2042 2427
2043 /* Install our interrupt handlers. Th 2428 /* Install our interrupt handlers. This varies depending on
2044 * the architecture. 2429 * the architecture.
2045 */ 2430 */
2046 fec_request_intrs(dev); 2431 fec_request_intrs(dev);
2047 2432
>> 2433 fecp->fec_hash_table_high = 0;
>> 2434 fecp->fec_hash_table_low = 0;
>> 2435 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
>> 2436 fecp->fec_ecntrl = 2;
>> 2437 fecp->fec_r_des_active = 0;
>> 2438
2048 dev->base_addr = (unsigned long)fecp; 2439 dev->base_addr = (unsigned long)fecp;
2049 2440
2050 /* The FEC Ethernet specific entries 2441 /* The FEC Ethernet specific entries in the device structure. */
2051 dev->open = fec_enet_open; 2442 dev->open = fec_enet_open;
2052 dev->hard_start_xmit = fec_enet_start 2443 dev->hard_start_xmit = fec_enet_start_xmit;
2053 dev->tx_timeout = fec_timeout; 2444 dev->tx_timeout = fec_timeout;
2054 dev->watchdog_timeo = TX_TIMEOUT; 2445 dev->watchdog_timeo = TX_TIMEOUT;
2055 dev->stop = fec_enet_close; 2446 dev->stop = fec_enet_close;
2056 dev->get_stats = fec_enet_get_stats; <<
2057 dev->set_multicast_list = set_multica 2447 dev->set_multicast_list = set_multicast_list;
2058 2448
2059 for (i=0; i<NMII-1; i++) 2449 for (i=0; i<NMII-1; i++)
2060 mii_cmds[i].mii_next = &mii_c 2450 mii_cmds[i].mii_next = &mii_cmds[i+1];
2061 mii_free = mii_cmds; 2451 mii_free = mii_cmds;
2062 2452
2063 /* setup MII interface */ 2453 /* setup MII interface */
2064 fec_set_mii(dev, fep); 2454 fec_set_mii(dev, fep);
2065 2455
2066 printk("%s: FEC ENET Version 0.2, ", !! 2456 /* Clear and enable interrupts */
2067 for (i=0; i<5; i++) !! 2457 fecp->fec_ievent = 0xffc00000;
2068 printk("%02x:", dev->dev_addr !! 2458 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2069 printk("%02x\n", dev->dev_addr[5]); !! 2459 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2070 2460
2071 /* Queue up command to detect the PHY 2461 /* Queue up command to detect the PHY and initialize the
2072 * remainder of the interface. 2462 * remainder of the interface.
2073 */ 2463 */
2074 fep->phy_id_done = 0; 2464 fep->phy_id_done = 0;
2075 fep->phy_addr = 0; 2465 fep->phy_addr = 0;
2076 mii_queue(dev, mk_mii_read(MII_REG_PH 2466 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2077 2467
2078 index++; 2468 index++;
2079 return 0; 2469 return 0;
2080 } 2470 }
2081 2471
2082 /* This function is called to start or restar 2472 /* This function is called to start or restart the FEC during a link
2083 * change. This only happens when switching 2473 * change. This only happens when switching between half and full
2084 * duplex. 2474 * duplex.
2085 */ 2475 */
2086 static void 2476 static void
2087 fec_restart(struct net_device *dev, int duple 2477 fec_restart(struct net_device *dev, int duplex)
2088 { 2478 {
2089 struct fec_enet_private *fep; 2479 struct fec_enet_private *fep;
2090 volatile cbd_t *bdp; 2480 volatile cbd_t *bdp;
2091 volatile fec_t *fecp; 2481 volatile fec_t *fecp;
2092 int i; 2482 int i;
2093 2483
2094 fep = netdev_priv(dev); 2484 fep = netdev_priv(dev);
2095 fecp = fep->hwp; 2485 fecp = fep->hwp;
2096 2486
2097 /* Whack a reset. We should wait for 2487 /* Whack a reset. We should wait for this.
2098 */ 2488 */
2099 fecp->fec_ecntrl = 1; 2489 fecp->fec_ecntrl = 1;
2100 udelay(10); 2490 udelay(10);
2101 2491
2102 /* Enable interrupts we wish to servi <<
2103 */ <<
2104 fecp->fec_imask = (FEC_ENET_TXF | FEC <<
2105 FEC_ENET_RXF <<
2106 <<
2107 /* Clear any outstanding interrupt. 2492 /* Clear any outstanding interrupt.
2108 */ 2493 */
2109 fecp->fec_ievent = 0xffc0; !! 2494 fecp->fec_ievent = 0xffc00000;
2110 fec_enable_phy_intr(); 2495 fec_enable_phy_intr();
2111 2496
2112 /* Set station address. 2497 /* Set station address.
2113 */ 2498 */
2114 fecp->fec_addr_low = fep->mac_addr[3] !! 2499 fec_set_mac_address(dev);
2115 (fep->mac_addr[1] << 16) | (f <<
2116 fecp->fec_addr_high = (fep->mac_addr[ <<
2117 (fep->mac_addr[4] << 24); <<
2118 <<
2119 for (i=0; i<ETH_ALEN; i++) <<
2120 dev->dev_addr[i] = fep->mac_a <<
2121 2500
2122 /* Reset all multicast. 2501 /* Reset all multicast.
2123 */ 2502 */
2124 fecp->fec_hash_table_high = 0; 2503 fecp->fec_hash_table_high = 0;
2125 fecp->fec_hash_table_low = 0; 2504 fecp->fec_hash_table_low = 0;
2126 2505
2127 /* Set maximum receive buffer size. 2506 /* Set maximum receive buffer size.
2128 */ 2507 */
2129 fecp->fec_r_buff_size = PKT_MAXBLR_SI 2508 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2130 2509
2131 fec_localhw_setup(); 2510 fec_localhw_setup();
2132 2511
2133 /* Set receive and transmit descripto 2512 /* Set receive and transmit descriptor base.
2134 */ 2513 */
2135 fecp->fec_r_des_start = __pa((uint)(f 2514 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2136 fecp->fec_x_des_start = __pa((uint)(f 2515 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2137 2516
2138 fep->dirty_tx = fep->cur_tx = fep->tx 2517 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2139 fep->cur_rx = fep->rx_bd_base; 2518 fep->cur_rx = fep->rx_bd_base;
2140 2519
2141 /* Reset SKB transmit buffers. 2520 /* Reset SKB transmit buffers.
2142 */ 2521 */
2143 fep->skb_cur = fep->skb_dirty = 0; 2522 fep->skb_cur = fep->skb_dirty = 0;
2144 for (i=0; i<=TX_RING_MOD_MASK; i++) { 2523 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2145 if (fep->tx_skbuff[i] != NULL 2524 if (fep->tx_skbuff[i] != NULL) {
2146 dev_kfree_skb_any(fep 2525 dev_kfree_skb_any(fep->tx_skbuff[i]);
2147 fep->tx_skbuff[i] = N 2526 fep->tx_skbuff[i] = NULL;
2148 } 2527 }
2149 } 2528 }
2150 2529
2151 /* Initialize the receive buffer desc 2530 /* Initialize the receive buffer descriptors.
2152 */ 2531 */
2153 bdp = fep->rx_bd_base; 2532 bdp = fep->rx_bd_base;
2154 for (i=0; i<RX_RING_SIZE; i++) { 2533 for (i=0; i<RX_RING_SIZE; i++) {
2155 2534
2156 /* Initialize the BD for ever 2535 /* Initialize the BD for every fragment in the page.
2157 */ 2536 */
2158 bdp->cbd_sc = BD_ENET_RX_EMPT 2537 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2159 bdp++; 2538 bdp++;
2160 } 2539 }
2161 2540
2162 /* Set the last buffer to wrap. 2541 /* Set the last buffer to wrap.
2163 */ 2542 */
2164 bdp--; 2543 bdp--;
2165 bdp->cbd_sc |= BD_SC_WRAP; 2544 bdp->cbd_sc |= BD_SC_WRAP;
2166 2545
2167 /* ...and the same for transmmit. 2546 /* ...and the same for transmmit.
2168 */ 2547 */
2169 bdp = fep->tx_bd_base; 2548 bdp = fep->tx_bd_base;
2170 for (i=0; i<TX_RING_SIZE; i++) { 2549 for (i=0; i<TX_RING_SIZE; i++) {
2171 2550
2172 /* Initialize the BD for ever 2551 /* Initialize the BD for every fragment in the page.
2173 */ 2552 */
2174 bdp->cbd_sc = 0; 2553 bdp->cbd_sc = 0;
2175 bdp->cbd_bufaddr = 0; 2554 bdp->cbd_bufaddr = 0;
2176 bdp++; 2555 bdp++;
2177 } 2556 }
2178 2557
2179 /* Set the last buffer to wrap. 2558 /* Set the last buffer to wrap.
2180 */ 2559 */
2181 bdp--; 2560 bdp--;
2182 bdp->cbd_sc |= BD_SC_WRAP; 2561 bdp->cbd_sc |= BD_SC_WRAP;
2183 2562
2184 /* Enable MII mode. 2563 /* Enable MII mode.
2185 */ 2564 */
2186 if (duplex) { 2565 if (duplex) {
2187 fecp->fec_r_cntrl = OPT_FRAME 2566 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2188 fecp->fec_x_cntrl = 0x04; 2567 fecp->fec_x_cntrl = 0x04; /* FD enable */
2189 } !! 2568 } else {
2190 else { <<
2191 /* MII enable|No Rcv on Xmit 2569 /* MII enable|No Rcv on Xmit */
2192 fecp->fec_r_cntrl = OPT_FRAME 2570 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2193 fecp->fec_x_cntrl = 0x00; 2571 fecp->fec_x_cntrl = 0x00;
2194 } 2572 }
2195 fep->full_duplex = duplex; 2573 fep->full_duplex = duplex;
2196 2574
2197 /* Set MII speed. 2575 /* Set MII speed.
2198 */ 2576 */
2199 fecp->fec_mii_speed = fep->phy_speed; 2577 fecp->fec_mii_speed = fep->phy_speed;
2200 2578
2201 /* And last, enable the transmit and 2579 /* And last, enable the transmit and receive processing.
2202 */ 2580 */
2203 fecp->fec_ecntrl = 2; 2581 fecp->fec_ecntrl = 2;
2204 fecp->fec_r_des_active = 0x01000000; !! 2582 fecp->fec_r_des_active = 0;
>> 2583
>> 2584 /* Enable interrupts we wish to service.
>> 2585 */
>> 2586 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
>> 2587 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2205 } 2588 }
2206 2589
2207 static void 2590 static void
2208 fec_stop(struct net_device *dev) 2591 fec_stop(struct net_device *dev)
2209 { 2592 {
2210 volatile fec_t *fecp; 2593 volatile fec_t *fecp;
2211 struct fec_enet_private *fep; 2594 struct fec_enet_private *fep;
2212 2595
2213 fep = netdev_priv(dev); 2596 fep = netdev_priv(dev);
2214 fecp = fep->hwp; 2597 fecp = fep->hwp;
2215 2598
2216 fecp->fec_x_cntrl = 0x01; /* Gr !! 2599 /*
2217 !! 2600 ** We cannot expect a graceful transmit stop without link !!!
2218 while(!(fecp->fec_ievent & 0x10000000 !! 2601 */
>> 2602 if (fep->link)
>> 2603 {
>> 2604 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
>> 2605 udelay(10);
>> 2606 if (!(fecp->fec_ievent & FEC_ENET_GRA))
>> 2607 printk("fec_stop : Graceful transmit stop did not complete !\n");
>> 2608 }
2219 2609
2220 /* Whack a reset. We should wait for 2610 /* Whack a reset. We should wait for this.
2221 */ 2611 */
2222 fecp->fec_ecntrl = 1; 2612 fecp->fec_ecntrl = 1;
2223 udelay(10); 2613 udelay(10);
2224 2614
2225 /* Clear outstanding MII command inte 2615 /* Clear outstanding MII command interrupts.
2226 */ 2616 */
2227 fecp->fec_ievent = FEC_ENET_MII; 2617 fecp->fec_ievent = FEC_ENET_MII;
2228 fec_enable_phy_intr(); 2618 fec_enable_phy_intr();
2229 2619
2230 fecp->fec_imask = FEC_ENET_MII; 2620 fecp->fec_imask = FEC_ENET_MII;
2231 fecp->fec_mii_speed = fep->phy_speed; 2621 fecp->fec_mii_speed = fep->phy_speed;
2232 } 2622 }
2233 2623
2234 static int __init fec_enet_module_init(void) 2624 static int __init fec_enet_module_init(void)
2235 { 2625 {
2236 struct net_device *dev; 2626 struct net_device *dev;
2237 int i, err; !! 2627 int i, j, err;
>> 2628 DECLARE_MAC_BUF(mac);
>> 2629
>> 2630 printk("FEC ENET Version 0.2\n");
2238 2631
2239 for (i = 0; (i < FEC_MAX_PORTS); i++) 2632 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2240 dev = alloc_etherdev(sizeof(s 2633 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2241 if (!dev) 2634 if (!dev)
2242 return -ENOMEM; 2635 return -ENOMEM;
2243 err = fec_enet_init(dev); 2636 err = fec_enet_init(dev);
2244 if (err) { 2637 if (err) {
2245 free_netdev(dev); 2638 free_netdev(dev);
2246 continue; 2639 continue;
2247 } 2640 }
2248 if (register_netdev(dev) != 0 2641 if (register_netdev(dev) != 0) {
2249 /* XXX: missing clean 2642 /* XXX: missing cleanup here */
2250 free_netdev(dev); 2643 free_netdev(dev);
2251 return -EIO; 2644 return -EIO;
2252 } 2645 }
>> 2646
>> 2647 printk("%s: ethernet %s\n",
>> 2648 dev->name, print_mac(mac, dev->dev_addr));
2253 } 2649 }
2254 return 0; 2650 return 0;
2255 } 2651 }
2256 2652
2257 module_init(fec_enet_module_init); 2653 module_init(fec_enet_module_init);
2258 2654
2259 MODULE_LICENSE("GPL"); 2655 MODULE_LICENSE("GPL");
2260 2656
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