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1 /********************************************* 1 /*******************************************************************************
2 2
3 Intel PRO/1000 Linux driver 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation. !! 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redis 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU Ge 7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software 8 version 2, as published by the Free Software Foundation.
9 9
10 This program is distributed in the hope it w 10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warra 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the G 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details. 13 more details.
14 14
15 You should have received a copy of the GNU G 15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Soft 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 021 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 18
19 The full GNU General Public License is inclu 19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING". 20 the file called "COPYING".
21 21
22 Contact Information: 22 Contact Information:
23 Linux NICS <linux.nics@intel.com> 23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists. 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Park 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 26
27 ********************************************** 27 *******************************************************************************/
28 28
29 #ifndef _E1000_HW_H_ 29 #ifndef _E1000_HW_H_
30 #define _E1000_HW_H_ 30 #define _E1000_HW_H_
31 31
32 #include <linux/types.h> 32 #include <linux/types.h>
33 33
34 struct e1000_hw; 34 struct e1000_hw;
35 struct e1000_adapter; 35 struct e1000_adapter;
36 36
37 #include "defines.h" 37 #include "defines.h"
38 38
39 #define er32(reg) __er32(hw, E1000_##reg 39 #define er32(reg) __er32(hw, E1000_##reg)
40 #define ew32(reg,val) __ew32(hw, E1000_##reg 40 #define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41 #define e1e_flush() er32(STATUS) 41 #define e1e_flush() er32(STATUS)
42 42
43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, 43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + 44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45 45
46 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 46 #define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) 47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48 48
49 enum e1e_registers { 49 enum e1e_registers {
50 E1000_CTRL = 0x00000, /* Device Co 50 E1000_CTRL = 0x00000, /* Device Control - RW */
51 E1000_STATUS = 0x00008, /* Device St 51 E1000_STATUS = 0x00008, /* Device Status - RO */
52 E1000_EECD = 0x00010, /* EEPROM/Fl 52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
53 E1000_EERD = 0x00014, /* EEPROM Re 53 E1000_EERD = 0x00014, /* EEPROM Read - RW */
54 E1000_CTRL_EXT = 0x00018, /* Extended 54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
55 E1000_FLA = 0x0001C, /* Flash Acc 55 E1000_FLA = 0x0001C, /* Flash Access - RW */
56 E1000_MDIC = 0x00020, /* MDI Contr 56 E1000_MDIC = 0x00020, /* MDI Control - RW */
57 E1000_SCTL = 0x00024, /* SerDes Co 57 E1000_SCTL = 0x00024, /* SerDes Control - RW */
58 E1000_FCAL = 0x00028, /* Flow Cont 58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
59 E1000_FCAH = 0x0002C, /* Flow Cont 59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
60 E1000_FEXTNVM = 0x00028, /* Future Ex 60 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
61 E1000_FCT = 0x00030, /* Flow Cont 61 E1000_FCT = 0x00030, /* Flow Control Type - RW */
62 E1000_VET = 0x00038, /* VLAN Ethe 62 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
63 E1000_ICR = 0x000C0, /* Interrupt 63 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
64 E1000_ITR = 0x000C4, /* Interrupt 64 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
65 E1000_ICS = 0x000C8, /* Interrupt 65 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
66 E1000_IMS = 0x000D0, /* Interrupt 66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt 67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
>> 68 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
68 E1000_IAM = 0x000E0, /* Interrupt 69 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
69 E1000_RCTL = 0x00100, /* RX Contro !! 70 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
>> 71 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
>> 72 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
>> 73 E1000_RCTL = 0x00100, /* Rx Control - RW */
70 E1000_FCTTV = 0x00170, /* Flow Cont 74 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
71 E1000_TXCW = 0x00178, /* TX Config !! 75 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
72 E1000_RXCW = 0x00180, /* RX Config !! 76 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
73 E1000_TCTL = 0x00400, /* TX Contro !! 77 E1000_TCTL = 0x00400, /* Tx Control - RW */
74 E1000_TCTL_EXT = 0x00404, /* Extended !! 78 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
75 E1000_TIPG = 0x00410, /* TX Inter- !! 79 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
76 E1000_AIT = 0x00458, /* Adaptive !! 80 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
77 E1000_LEDCTL = 0x00E00, /* LED Contr 81 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
78 E1000_EXTCNF_CTRL = 0x00F00, /* Exten 82 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
79 E1000_EXTCNF_SIZE = 0x00F08, /* Exten 83 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
80 E1000_PHY_CTRL = 0x00F10, /* PHY C 84 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
81 E1000_PBA = 0x01000, /* Packet Bu 85 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
82 E1000_PBS = 0x01008, /* Packet Bu 86 E1000_PBS = 0x01008, /* Packet Buffer Size */
83 E1000_EEMNGCTL = 0x01010, /* MNG EEpro 87 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
84 E1000_EEWR = 0x0102C, /* EEPROM Wr 88 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
85 E1000_FLOP = 0x0103C, /* FLASH Opc 89 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
>> 90 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
86 E1000_ERT = 0x02008, /* Early Rx 91 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
87 E1000_FCRTL = 0x02160, /* Flow Cont 92 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
88 E1000_FCRTH = 0x02168, /* Flow Cont 93 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
89 E1000_PSRCTL = 0x02170, /* Packet Sp 94 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
90 E1000_RDBAL = 0x02800, /* RX Descri !! 95 E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
91 E1000_RDBAH = 0x02804, /* RX Descri !! 96 E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
92 E1000_RDLEN = 0x02808, /* RX Descri !! 97 E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
93 E1000_RDH = 0x02810, /* RX Descri !! 98 E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
94 E1000_RDT = 0x02818, /* RX Descri !! 99 E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
95 E1000_RDTR = 0x02820, /* RX Delay !! 100 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
>> 101 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
>> 102 #define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
96 E1000_RADV = 0x0282C, /* RX Interr 103 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
97 104
98 /* Convenience macros 105 /* Convenience macros
99 * 106 *
100 * Note: "_n" is the queue number of the regis 107 * Note: "_n" is the queue number of the register to be written to.
101 * 108 *
102 * Example usage: 109 * Example usage:
103 * E1000_RDBAL_REG(current_rx_queue) 110 * E1000_RDBAL_REG(current_rx_queue)
104 * 111 *
105 */ 112 */
106 #define E1000_RDBAL_REG(_n) (E1000_RDBAL + ( 113 #define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
107 E1000_KABGTXD = 0x03004, /* AFE Band 114 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
108 E1000_TDBAL = 0x03800, /* TX Descri !! 115 E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
109 E1000_TDBAH = 0x03804, /* TX Descri !! 116 E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
110 E1000_TDLEN = 0x03808, /* TX Descri !! 117 E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
111 E1000_TDH = 0x03810, /* TX Descri !! 118 E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
112 E1000_TDT = 0x03818, /* TX Descri !! 119 E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
113 E1000_TIDV = 0x03820, /* TX Interr !! 120 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
114 E1000_TXDCTL = 0x03828, /* TX Descri !! 121 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
115 E1000_TADV = 0x0382C, /* TX Interr !! 122 #define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
116 E1000_TARC0 = 0x03840, /* TX Arbitr !! 123 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
117 E1000_TXDCTL1 = 0x03928, /* TX Descri !! 124 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
118 E1000_TARC1 = 0x03940, /* TX Arbitr !! 125 #define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
119 E1000_CRCERRS = 0x04000, /* CRC Error 126 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
120 E1000_ALGNERRC = 0x04004, /* Alignment 127 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
121 E1000_SYMERRS = 0x04008, /* Symbol Er 128 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
122 E1000_RXERRC = 0x0400C, /* Receive E 129 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
123 E1000_MPC = 0x04010, /* Missed Pa 130 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
124 E1000_SCC = 0x04014, /* Single Co 131 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
125 E1000_ECOL = 0x04018, /* Excessive 132 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
126 E1000_MCC = 0x0401C, /* Multiple 133 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
127 E1000_LATECOL = 0x04020, /* Late Coll 134 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
128 E1000_COLC = 0x04028, /* Collision 135 E1000_COLC = 0x04028, /* Collision Count - R/clr */
129 E1000_DC = 0x04030, /* Defer Cou 136 E1000_DC = 0x04030, /* Defer Count - R/clr */
130 E1000_TNCRS = 0x04034, /* TX-No CRS !! 137 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
131 E1000_SEC = 0x04038, /* Sequence 138 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
132 E1000_CEXTERR = 0x0403C, /* Carrier E 139 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
133 E1000_RLEC = 0x04040, /* Receive L 140 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
134 E1000_XONRXC = 0x04048, /* XON RX Co !! 141 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
135 E1000_XONTXC = 0x0404C, /* XON TX Co !! 142 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
136 E1000_XOFFRXC = 0x04050, /* XOFF RX C !! 143 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
137 E1000_XOFFTXC = 0x04054, /* XOFF TX C !! 144 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
138 E1000_FCRUC = 0x04058, /* Flow Cont !! 145 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
139 E1000_PRC64 = 0x0405C, /* Packets R !! 146 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
140 E1000_PRC127 = 0x04060, /* Packets R !! 147 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
141 E1000_PRC255 = 0x04064, /* Packets R !! 148 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
142 E1000_PRC511 = 0x04068, /* Packets R !! 149 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
143 E1000_PRC1023 = 0x0406C, /* Packets R !! 150 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
144 E1000_PRC1522 = 0x04070, /* Packets R !! 151 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
145 E1000_GPRC = 0x04074, /* Good Pack !! 152 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
146 E1000_BPRC = 0x04078, /* Broadcast !! 153 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
147 E1000_MPRC = 0x0407C, /* Multicast !! 154 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
148 E1000_GPTC = 0x04080, /* Good Pack !! 155 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
149 E1000_GORCL = 0x04088, /* Good Octe !! 156 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
150 E1000_GORCH = 0x0408C, /* Good Octe !! 157 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
151 E1000_GOTCL = 0x04090, /* Good Octe !! 158 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
152 E1000_GOTCH = 0x04094, /* Good Octe !! 159 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
153 E1000_RNBC = 0x040A0, /* RX No Buf !! 160 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
154 E1000_RUC = 0x040A4, /* RX Unders !! 161 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
155 E1000_RFC = 0x040A8, /* RX Fragme !! 162 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
156 E1000_ROC = 0x040AC, /* RX Oversi !! 163 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
157 E1000_RJC = 0x040B0, /* RX Jabber !! 164 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
158 E1000_MGTPRC = 0x040B4, /* Managemen !! 165 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
159 E1000_MGTPDC = 0x040B8, /* Managemen 166 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
160 E1000_MGTPTC = 0x040BC, /* Managemen !! 167 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
161 E1000_TORL = 0x040C0, /* Total Oct !! 168 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
162 E1000_TORH = 0x040C4, /* Total Oct !! 169 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
163 E1000_TOTL = 0x040C8, /* Total Oct !! 170 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
164 E1000_TOTH = 0x040CC, /* Total Oct !! 171 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
165 E1000_TPR = 0x040D0, /* Total Pac !! 172 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
166 E1000_TPT = 0x040D4, /* Total Pac !! 173 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
167 E1000_PTC64 = 0x040D8, /* Packets T !! 174 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
168 E1000_PTC127 = 0x040DC, /* Packets T !! 175 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
169 E1000_PTC255 = 0x040E0, /* Packets T !! 176 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
170 E1000_PTC511 = 0x040E4, /* Packets T !! 177 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
171 E1000_PTC1023 = 0x040E8, /* Packets T !! 178 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
172 E1000_PTC1522 = 0x040EC, /* Packets T !! 179 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
173 E1000_MPTC = 0x040F0, /* Multicast !! 180 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
174 E1000_BPTC = 0x040F4, /* Broadcast !! 181 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
175 E1000_TSCTC = 0x040F8, /* TCP Segme !! 182 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
176 E1000_TSCTFC = 0x040FC, /* TCP Segme !! 183 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
177 E1000_IAC = 0x04100, /* Interrupt 184 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
178 E1000_ICRXPTC = 0x04104, /* Irq Cause 185 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
179 E1000_ICRXATC = 0x04108, /* Irq Cause 186 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
180 E1000_ICTXPTC = 0x0410C, /* Irq Cause 187 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
181 E1000_ICTXATC = 0x04110, /* Irq Cause 188 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
182 E1000_ICTXQEC = 0x04118, /* Irq Cause 189 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
183 E1000_ICTXQMTC = 0x0411C, /* Irq Cause 190 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
184 E1000_ICRXDMTC = 0x04120, /* Irq Cause 191 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
185 E1000_ICRXOC = 0x04124, /* Irq Cause 192 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
186 E1000_RXCSUM = 0x05000, /* RX Checks !! 193 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
187 E1000_RFCTL = 0x05008, /* Receive F 194 E1000_RFCTL = 0x05008, /* Receive Filter Control */
188 E1000_MTA = 0x05200, /* Multicast 195 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
189 E1000_RA = 0x05400, /* Receive A !! 196 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
>> 197 #define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
>> 198 #define E1000_RA (E1000_RAL(0))
>> 199 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
>> 200 #define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
190 E1000_VFTA = 0x05600, /* VLAN Filt 201 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
191 E1000_WUC = 0x05800, /* Wakeup Co 202 E1000_WUC = 0x05800, /* Wakeup Control - RW */
192 E1000_WUFC = 0x05808, /* Wakeup Fi 203 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
193 E1000_WUS = 0x05810, /* Wakeup St 204 E1000_WUS = 0x05810, /* Wakeup Status - RO */
194 E1000_MANC = 0x05820, /* Managemen 205 E1000_MANC = 0x05820, /* Management Control - RW */
195 E1000_FFLT = 0x05F00, /* Flexible 206 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
196 E1000_HOST_IF = 0x08800, /* Host Inte 207 E1000_HOST_IF = 0x08800, /* Host Interface */
197 208
198 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PH 209 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
199 E1000_MANC2H = 0x05860, /* Manageme 210 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
200 E1000_SW_FW_SYNC = 0x05B5C, /* Softwar 211 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
201 E1000_GCR = 0x05B00, /* PCI-Ex C 212 E1000_GCR = 0x05B00, /* PCI-Ex Control */
>> 213 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
202 E1000_FACTPS = 0x05B30, /* Function 214 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
203 E1000_SWSM = 0x05B50, /* SW Semap 215 E1000_SWSM = 0x05B50, /* SW Semaphore */
204 E1000_FWSM = 0x05B54, /* FW Semap 216 E1000_FWSM = 0x05B54, /* FW Semaphore */
>> 217 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
>> 218 E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
205 E1000_HICR = 0x08F00, /* Host Int 219 E1000_HICR = 0x08F00, /* Host Interface Control */
206 }; 220 };
207 221
208 /* RSS registers */ 222 /* RSS registers */
209 223
210 /* IGP01E1000 Specific Registers */ 224 /* IGP01E1000 Specific Registers */
211 #define IGP01E1000_PHY_PORT_CONFIG 0x10 / 225 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
212 #define IGP01E1000_PHY_PORT_STATUS 0x11 / 226 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
213 #define IGP01E1000_PHY_PORT_CTRL 0x12 / 227 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
214 #define IGP01E1000_PHY_LINK_HEALTH 0x13 / 228 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
215 #define IGP02E1000_PHY_POWER_MGMT 0x19 / 229 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
216 #define IGP01E1000_PHY_PAGE_SELECT 0x1F / 230 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
>> 231 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
>> 232 #define IGP_PAGE_SHIFT 5
>> 233 #define PHY_REG_MASK 0x1F
>> 234
>> 235 #define BM_WUC_PAGE 800
>> 236 #define BM_WUC_ADDRESS_OPCODE 0x11
>> 237 #define BM_WUC_DATA_OPCODE 0x12
>> 238 #define BM_WUC_ENABLE_PAGE 769
>> 239 #define BM_WUC_ENABLE_REG 17
>> 240 #define BM_WUC_ENABLE_BIT (1 << 2)
>> 241 #define BM_WUC_HOST_WU_BIT (1 << 4)
>> 242
>> 243 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
>> 244 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
>> 245 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
217 246
218 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 247 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
219 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 248 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
220 249
221 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 250 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
222 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 251 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
223 252
224 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 253 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
225 254
226 #define IGP02E1000_PM_SPD 0x0001 255 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
227 #define IGP02E1000_PM_D0_LPLU 0x0002 256 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
228 #define IGP02E1000_PM_D3_LPLU 0x0004 257 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
229 258
230 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 259 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
231 260
232 #define IGP01E1000_PSSR_POLARITY_REVERSED 261 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
233 #define IGP01E1000_PSSR_MDIX !! 262 #define IGP01E1000_PSSR_MDIX 0x0800
234 #define IGP01E1000_PSSR_SPEED_MASK 263 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
235 #define IGP01E1000_PSSR_SPEED_1000MBPS 264 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
236 265
237 #define IGP02E1000_PHY_CHANNEL_NUM 266 #define IGP02E1000_PHY_CHANNEL_NUM 4
238 #define IGP02E1000_PHY_AGC_A 267 #define IGP02E1000_PHY_AGC_A 0x11B1
239 #define IGP02E1000_PHY_AGC_B 268 #define IGP02E1000_PHY_AGC_B 0x12B1
240 #define IGP02E1000_PHY_AGC_C 269 #define IGP02E1000_PHY_AGC_C 0x14B1
241 #define IGP02E1000_PHY_AGC_D 270 #define IGP02E1000_PHY_AGC_D 0x18B1
242 271
243 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* C 272 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
244 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 273 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
245 #define IGP02E1000_AGC_RANGE 15 274 #define IGP02E1000_AGC_RANGE 15
246 275
247 /* manage.c */ 276 /* manage.c */
248 #define E1000_VFTA_ENTRY_SHIFT 5 277 #define E1000_VFTA_ENTRY_SHIFT 5
249 #define E1000_VFTA_ENTRY_MASK 0x7F 278 #define E1000_VFTA_ENTRY_MASK 0x7F
250 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 279 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
251 280
252 #define E1000_HICR_EN 0x01 281 #define E1000_HICR_EN 0x01 /* Enable bit - RO */
253 #define E1000_HICR_C 0x02 !! 282 /* Driver sets this bit when done to put command in RAM */
254 !! 283 #define E1000_HICR_C 0x02
255 #define E1000_HICR_FW_RESET_ENABLE 0x40 284 #define E1000_HICR_FW_RESET_ENABLE 0x40
256 #define E1000_HICR_FW_RESET 0x80 285 #define E1000_HICR_FW_RESET 0x80
257 286
258 #define E1000_FWSM_MODE_MASK 0xE 287 #define E1000_FWSM_MODE_MASK 0xE
259 #define E1000_FWSM_MODE_SHIFT 1 288 #define E1000_FWSM_MODE_SHIFT 1
260 289
261 #define E1000_MNG_IAMT_MODE 0x3 290 #define E1000_MNG_IAMT_MODE 0x3
262 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 291 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
263 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 292 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
264 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 293 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
265 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 294 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
266 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 295 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
267 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 296 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
268 297
269 /* nvm.c */ 298 /* nvm.c */
270 #define E1000_STM_OPCODE 0xDB00 299 #define E1000_STM_OPCODE 0xDB00
271 300
272 #define E1000_KMRNCTRLSTA_OFFSET 0x001F 301 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
273 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 302 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
274 #define E1000_KMRNCTRLSTA_REN 0x0020 303 #define E1000_KMRNCTRLSTA_REN 0x00200000
275 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 304 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
276 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 305 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
>> 306 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
>> 307 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x140E
>> 308 #define E1000_KMRNCTRLSTA_K1_DISABLE 0x1400
277 309
278 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 310 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
279 #define IFE_PHY_SPECIAL_CONTROL 0x11 / 311 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
280 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B / 312 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
281 #define IFE_PHY_MDIX_CONTROL 0x1C / 313 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
282 314
283 /* IFE PHY Extended Status Control */ 315 /* IFE PHY Extended Status Control */
284 #define IFE_PESC_POLARITY_REVERSED 0x0100 316 #define IFE_PESC_POLARITY_REVERSED 0x0100
285 317
286 /* IFE PHY Special Control */ 318 /* IFE PHY Special Control */
287 #define IFE_PSC_AUTO_POLARITY_DISABLE 319 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
288 #define IFE_PSC_FORCE_POLARITY 320 #define IFE_PSC_FORCE_POLARITY 0x0020
289 321
290 /* IFE PHY Special Control and LED Control */ 322 /* IFE PHY Special Control and LED Control */
291 #define IFE_PSCL_PROBE_MODE 0x0020 323 #define IFE_PSCL_PROBE_MODE 0x0020
292 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 324 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
293 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 325 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
294 326
295 /* IFE PHY MDIX Control */ 327 /* IFE PHY MDIX Control */
296 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MD 328 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
297 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=fo 329 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
298 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=en 330 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
299 331
300 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 332 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
301 333
302 #define E1000_DEV_ID_82571EB_COPPER 334 #define E1000_DEV_ID_82571EB_COPPER 0x105E
303 #define E1000_DEV_ID_82571EB_FIBER 335 #define E1000_DEV_ID_82571EB_FIBER 0x105F
304 #define E1000_DEV_ID_82571EB_SERDES 336 #define E1000_DEV_ID_82571EB_SERDES 0x1060
305 #define E1000_DEV_ID_82571EB_QUAD_COPPER 337 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
306 #define E1000_DEV_ID_82571PT_QUAD_COPPER 338 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
307 #define E1000_DEV_ID_82571EB_QUAD_FIBER 339 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
308 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 340 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
309 #define E1000_DEV_ID_82571EB_SERDES_DUAL 341 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
310 #define E1000_DEV_ID_82571EB_SERDES_QUAD 342 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
311 #define E1000_DEV_ID_82572EI_COPPER 343 #define E1000_DEV_ID_82572EI_COPPER 0x107D
312 #define E1000_DEV_ID_82572EI_FIBER 344 #define E1000_DEV_ID_82572EI_FIBER 0x107E
313 #define E1000_DEV_ID_82572EI_SERDES 345 #define E1000_DEV_ID_82572EI_SERDES 0x107F
314 #define E1000_DEV_ID_82572EI 346 #define E1000_DEV_ID_82572EI 0x10B9
315 #define E1000_DEV_ID_82573E 347 #define E1000_DEV_ID_82573E 0x108B
316 #define E1000_DEV_ID_82573E_IAMT 348 #define E1000_DEV_ID_82573E_IAMT 0x108C
317 #define E1000_DEV_ID_82573L 349 #define E1000_DEV_ID_82573L 0x109A
>> 350 #define E1000_DEV_ID_82574L 0x10D3
>> 351 #define E1000_DEV_ID_82574LA 0x10F6
>> 352 #define E1000_DEV_ID_82583V 0x150C
318 353
319 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 354 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
320 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 355 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
321 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 356 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
322 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 357 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
323 358
324 #define E1000_DEV_ID_ICH8_IGP_M_AMT 359 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
325 #define E1000_DEV_ID_ICH8_IGP_AMT 360 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
326 #define E1000_DEV_ID_ICH8_IGP_C 361 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
327 #define E1000_DEV_ID_ICH8_IFE 362 #define E1000_DEV_ID_ICH8_IFE 0x104C
328 #define E1000_DEV_ID_ICH8_IFE_GT 363 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
329 #define E1000_DEV_ID_ICH8_IFE_G 364 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
330 #define E1000_DEV_ID_ICH8_IGP_M 365 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
331 #define E1000_DEV_ID_ICH9_IGP_AMT 366 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
>> 367 #define E1000_DEV_ID_ICH9_BM 0x10E5
>> 368 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
>> 369 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
>> 370 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
332 #define E1000_DEV_ID_ICH9_IGP_C 371 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
333 #define E1000_DEV_ID_ICH9_IFE 372 #define E1000_DEV_ID_ICH9_IFE 0x10C0
334 #define E1000_DEV_ID_ICH9_IFE_GT 373 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
335 #define E1000_DEV_ID_ICH9_IFE_G 374 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
>> 375 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
>> 376 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
>> 377 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
>> 378 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
>> 379 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
>> 380 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
>> 381 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
>> 382 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
>> 383 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
>> 384
>> 385 #define E1000_REVISION_4 4
336 386
337 #define E1000_FUNC_1 1 387 #define E1000_FUNC_1 1
338 388
339 enum e1000_mac_type { 389 enum e1000_mac_type {
340 e1000_82571, 390 e1000_82571,
341 e1000_82572, 391 e1000_82572,
342 e1000_82573, 392 e1000_82573,
>> 393 e1000_82574,
>> 394 e1000_82583,
343 e1000_80003es2lan, 395 e1000_80003es2lan,
344 e1000_ich8lan, 396 e1000_ich8lan,
345 e1000_ich9lan, 397 e1000_ich9lan,
>> 398 e1000_ich10lan,
>> 399 e1000_pchlan,
346 }; 400 };
347 401
348 enum e1000_media_type { 402 enum e1000_media_type {
349 e1000_media_type_unknown = 0, 403 e1000_media_type_unknown = 0,
350 e1000_media_type_copper = 1, 404 e1000_media_type_copper = 1,
351 e1000_media_type_fiber = 2, 405 e1000_media_type_fiber = 2,
352 e1000_media_type_internal_serdes = 3, 406 e1000_media_type_internal_serdes = 3,
353 e1000_num_media_types 407 e1000_num_media_types
354 }; 408 };
355 409
356 enum e1000_nvm_type { 410 enum e1000_nvm_type {
357 e1000_nvm_unknown = 0, 411 e1000_nvm_unknown = 0,
358 e1000_nvm_none, 412 e1000_nvm_none,
359 e1000_nvm_eeprom_spi, 413 e1000_nvm_eeprom_spi,
360 e1000_nvm_flash_hw, 414 e1000_nvm_flash_hw,
361 e1000_nvm_flash_sw 415 e1000_nvm_flash_sw
362 }; 416 };
363 417
364 enum e1000_nvm_override { 418 enum e1000_nvm_override {
365 e1000_nvm_override_none = 0, 419 e1000_nvm_override_none = 0,
366 e1000_nvm_override_spi_small, 420 e1000_nvm_override_spi_small,
367 e1000_nvm_override_spi_large 421 e1000_nvm_override_spi_large
368 }; 422 };
369 423
370 enum e1000_phy_type { 424 enum e1000_phy_type {
371 e1000_phy_unknown = 0, 425 e1000_phy_unknown = 0,
372 e1000_phy_none, 426 e1000_phy_none,
373 e1000_phy_m88, 427 e1000_phy_m88,
374 e1000_phy_igp, 428 e1000_phy_igp,
375 e1000_phy_igp_2, 429 e1000_phy_igp_2,
376 e1000_phy_gg82563, 430 e1000_phy_gg82563,
377 e1000_phy_igp_3, 431 e1000_phy_igp_3,
378 e1000_phy_ife, 432 e1000_phy_ife,
>> 433 e1000_phy_bm,
>> 434 e1000_phy_82578,
>> 435 e1000_phy_82577,
379 }; 436 };
380 437
381 enum e1000_bus_width { 438 enum e1000_bus_width {
382 e1000_bus_width_unknown = 0, 439 e1000_bus_width_unknown = 0,
383 e1000_bus_width_pcie_x1, 440 e1000_bus_width_pcie_x1,
384 e1000_bus_width_pcie_x2, 441 e1000_bus_width_pcie_x2,
385 e1000_bus_width_pcie_x4 = 4, 442 e1000_bus_width_pcie_x4 = 4,
386 e1000_bus_width_32, 443 e1000_bus_width_32,
387 e1000_bus_width_64, 444 e1000_bus_width_64,
388 e1000_bus_width_reserved 445 e1000_bus_width_reserved
389 }; 446 };
390 447
391 enum e1000_1000t_rx_status { 448 enum e1000_1000t_rx_status {
392 e1000_1000t_rx_status_not_ok = 0, 449 e1000_1000t_rx_status_not_ok = 0,
393 e1000_1000t_rx_status_ok, 450 e1000_1000t_rx_status_ok,
394 e1000_1000t_rx_status_undefined = 0xFF 451 e1000_1000t_rx_status_undefined = 0xFF
395 }; 452 };
396 453
397 enum e1000_rev_polarity{ 454 enum e1000_rev_polarity{
398 e1000_rev_polarity_normal = 0, 455 e1000_rev_polarity_normal = 0,
399 e1000_rev_polarity_reversed, 456 e1000_rev_polarity_reversed,
400 e1000_rev_polarity_undefined = 0xFF 457 e1000_rev_polarity_undefined = 0xFF
401 }; 458 };
402 459
403 enum e1000_fc_mode { 460 enum e1000_fc_mode {
404 e1000_fc_none = 0, 461 e1000_fc_none = 0,
405 e1000_fc_rx_pause, 462 e1000_fc_rx_pause,
406 e1000_fc_tx_pause, 463 e1000_fc_tx_pause,
407 e1000_fc_full, 464 e1000_fc_full,
408 e1000_fc_default = 0xFF 465 e1000_fc_default = 0xFF
409 }; 466 };
410 467
411 enum e1000_ms_type { 468 enum e1000_ms_type {
412 e1000_ms_hw_default = 0, 469 e1000_ms_hw_default = 0,
413 e1000_ms_force_master, 470 e1000_ms_force_master,
414 e1000_ms_force_slave, 471 e1000_ms_force_slave,
415 e1000_ms_auto 472 e1000_ms_auto
416 }; 473 };
417 474
418 enum e1000_smart_speed { 475 enum e1000_smart_speed {
419 e1000_smart_speed_default = 0, 476 e1000_smart_speed_default = 0,
420 e1000_smart_speed_on, 477 e1000_smart_speed_on,
421 e1000_smart_speed_off 478 e1000_smart_speed_off
422 }; 479 };
423 480
>> 481 enum e1000_serdes_link_state {
>> 482 e1000_serdes_link_down = 0,
>> 483 e1000_serdes_link_autoneg_progress,
>> 484 e1000_serdes_link_autoneg_complete,
>> 485 e1000_serdes_link_forced_up
>> 486 };
>> 487
424 /* Receive Descriptor */ 488 /* Receive Descriptor */
425 struct e1000_rx_desc { 489 struct e1000_rx_desc {
426 __le64 buffer_addr; /* Address of the 490 __le64 buffer_addr; /* Address of the descriptor's data buffer */
427 __le16 length; /* Length of data 491 __le16 length; /* Length of data DMAed into data buffer */
428 __le16 csum; /* Packet checksum */ 492 __le16 csum; /* Packet checksum */
429 u8 status; /* Descriptor status 493 u8 status; /* Descriptor status */
430 u8 errors; /* Descriptor Errors 494 u8 errors; /* Descriptor Errors */
431 __le16 special; 495 __le16 special;
432 }; 496 };
433 497
434 /* Receive Descriptor - Extended */ 498 /* Receive Descriptor - Extended */
435 union e1000_rx_desc_extended { 499 union e1000_rx_desc_extended {
436 struct { 500 struct {
437 __le64 buffer_addr; 501 __le64 buffer_addr;
438 __le64 reserved; 502 __le64 reserved;
439 } read; 503 } read;
440 struct { 504 struct {
441 struct { 505 struct {
442 __le32 mrq; 506 __le32 mrq; /* Multiple Rx Queues */
443 union { 507 union {
444 __le32 rss; 508 __le32 rss; /* RSS Hash */
445 struct { 509 struct {
446 __le16 510 __le16 ip_id; /* IP id */
447 __le16 511 __le16 csum; /* Packet Checksum */
448 } csum_ip; 512 } csum_ip;
449 } hi_dword; 513 } hi_dword;
450 } lower; 514 } lower;
451 struct { 515 struct {
452 __le32 status_error; 516 __le32 status_error; /* ext status/error */
453 __le16 length; 517 __le16 length;
454 __le16 vlan; / 518 __le16 vlan; /* VLAN tag */
455 } upper; 519 } upper;
456 } wb; /* writeback */ 520 } wb; /* writeback */
457 }; 521 };
458 522
459 #define MAX_PS_BUFFERS 4 523 #define MAX_PS_BUFFERS 4
460 /* Receive Descriptor - Packet Split */ 524 /* Receive Descriptor - Packet Split */
461 union e1000_rx_desc_packet_split { 525 union e1000_rx_desc_packet_split {
462 struct { 526 struct {
463 /* one buffer for protocol hea 527 /* one buffer for protocol header(s), three data buffers */
464 __le64 buffer_addr[MAX_PS_BUFF 528 __le64 buffer_addr[MAX_PS_BUFFERS];
465 } read; 529 } read;
466 struct { 530 struct {
467 struct { 531 struct {
468 __le32 mrq; 532 __le32 mrq; /* Multiple Rx Queues */
469 union { 533 union {
470 __le32 rss; 534 __le32 rss; /* RSS Hash */
471 struct { 535 struct {
472 __le16 536 __le16 ip_id; /* IP id */
473 __le16 537 __le16 csum; /* Packet Checksum */
474 } csum_ip; 538 } csum_ip;
475 } hi_dword; 539 } hi_dword;
476 } lower; 540 } lower;
477 struct { 541 struct {
478 __le32 status_error; 542 __le32 status_error; /* ext status/error */
479 __le16 length0; /* l 543 __le16 length0; /* length of buffer 0 */
480 __le16 vlan; / 544 __le16 vlan; /* VLAN tag */
481 } middle; 545 } middle;
482 struct { 546 struct {
483 __le16 header_status; 547 __le16 header_status;
484 __le16 length[3]; 548 __le16 length[3]; /* length of buffers 1-3 */
485 } upper; 549 } upper;
486 __le64 reserved; 550 __le64 reserved;
487 } wb; /* writeback */ 551 } wb; /* writeback */
488 }; 552 };
489 553
490 /* Transmit Descriptor */ 554 /* Transmit Descriptor */
491 struct e1000_tx_desc { 555 struct e1000_tx_desc {
492 __le64 buffer_addr; /* Address of 556 __le64 buffer_addr; /* Address of the descriptor's data buffer */
493 union { 557 union {
494 __le32 data; 558 __le32 data;
495 struct { 559 struct {
496 __le16 length; /* D 560 __le16 length; /* Data buffer length */
497 u8 cso; /* Checksum of 561 u8 cso; /* Checksum offset */
498 u8 cmd; /* Descriptor 562 u8 cmd; /* Descriptor control */
499 } flags; 563 } flags;
500 } lower; 564 } lower;
501 union { 565 union {
502 __le32 data; 566 __le32 data;
503 struct { 567 struct {
504 u8 status; /* Desc 568 u8 status; /* Descriptor status */
505 u8 css; /* Checksum st 569 u8 css; /* Checksum start */
506 __le16 special; 570 __le16 special;
507 } fields; 571 } fields;
508 } upper; 572 } upper;
509 }; 573 };
510 574
511 /* Offload Context Descriptor */ 575 /* Offload Context Descriptor */
512 struct e1000_context_desc { 576 struct e1000_context_desc {
513 union { 577 union {
514 __le32 ip_config; 578 __le32 ip_config;
515 struct { 579 struct {
516 u8 ipcss; /* IP c 580 u8 ipcss; /* IP checksum start */
517 u8 ipcso; /* IP c 581 u8 ipcso; /* IP checksum offset */
518 __le16 ipcse; /* I 582 __le16 ipcse; /* IP checksum end */
519 } ip_fields; 583 } ip_fields;
520 } lower_setup; 584 } lower_setup;
521 union { 585 union {
522 __le32 tcp_config; 586 __le32 tcp_config;
523 struct { 587 struct {
524 u8 tucss; /* TCP 588 u8 tucss; /* TCP checksum start */
525 u8 tucso; /* TCP 589 u8 tucso; /* TCP checksum offset */
526 __le16 tucse; /* T 590 __le16 tucse; /* TCP checksum end */
527 } tcp_fields; 591 } tcp_fields;
528 } upper_setup; 592 } upper_setup;
529 __le32 cmd_and_length; 593 __le32 cmd_and_length;
530 union { 594 union {
531 __le32 data; 595 __le32 data;
532 struct { 596 struct {
533 u8 status; /* Desc 597 u8 status; /* Descriptor status */
534 u8 hdr_len; /* Head 598 u8 hdr_len; /* Header length */
535 __le16 mss; /* M 599 __le16 mss; /* Maximum segment size */
536 } fields; 600 } fields;
537 } tcp_seg_setup; 601 } tcp_seg_setup;
538 }; 602 };
539 603
540 /* Offload data descriptor */ 604 /* Offload data descriptor */
541 struct e1000_data_desc { 605 struct e1000_data_desc {
542 __le64 buffer_addr; /* Address of th 606 __le64 buffer_addr; /* Address of the descriptor's buffer address */
543 union { 607 union {
544 __le32 data; 608 __le32 data;
545 struct { 609 struct {
546 __le16 length; /* D 610 __le16 length; /* Data buffer length */
547 u8 typ_len_ext; 611 u8 typ_len_ext;
548 u8 cmd; 612 u8 cmd;
549 } flags; 613 } flags;
550 } lower; 614 } lower;
551 union { 615 union {
552 __le32 data; 616 __le32 data;
553 struct { 617 struct {
554 u8 status; /* Desc 618 u8 status; /* Descriptor status */
555 u8 popts; /* Pack 619 u8 popts; /* Packet Options */
556 __le16 special; /* * 620 __le16 special; /* */
557 } fields; 621 } fields;
558 } upper; 622 } upper;
559 }; 623 };
560 624
561 /* Statistics counters collected by the MAC */ 625 /* Statistics counters collected by the MAC */
562 struct e1000_hw_stats { 626 struct e1000_hw_stats {
563 u64 crcerrs; 627 u64 crcerrs;
564 u64 algnerrc; 628 u64 algnerrc;
565 u64 symerrs; 629 u64 symerrs;
566 u64 rxerrc; 630 u64 rxerrc;
567 u64 mpc; 631 u64 mpc;
568 u64 scc; 632 u64 scc;
569 u64 ecol; 633 u64 ecol;
570 u64 mcc; 634 u64 mcc;
571 u64 latecol; 635 u64 latecol;
572 u64 colc; 636 u64 colc;
573 u64 dc; 637 u64 dc;
574 u64 tncrs; 638 u64 tncrs;
575 u64 sec; 639 u64 sec;
576 u64 cexterr; 640 u64 cexterr;
577 u64 rlec; 641 u64 rlec;
578 u64 xonrxc; 642 u64 xonrxc;
579 u64 xontxc; 643 u64 xontxc;
580 u64 xoffrxc; 644 u64 xoffrxc;
581 u64 xofftxc; 645 u64 xofftxc;
582 u64 fcruc; 646 u64 fcruc;
583 u64 prc64; 647 u64 prc64;
584 u64 prc127; 648 u64 prc127;
585 u64 prc255; 649 u64 prc255;
586 u64 prc511; 650 u64 prc511;
587 u64 prc1023; 651 u64 prc1023;
588 u64 prc1522; 652 u64 prc1522;
589 u64 gprc; 653 u64 gprc;
590 u64 bprc; 654 u64 bprc;
591 u64 mprc; 655 u64 mprc;
592 u64 gptc; 656 u64 gptc;
593 u64 gorcl; !! 657 u64 gorc;
594 u64 gorch; !! 658 u64 gotc;
595 u64 gotcl; <<
596 u64 gotch; <<
597 u64 rnbc; 659 u64 rnbc;
598 u64 ruc; 660 u64 ruc;
599 u64 rfc; 661 u64 rfc;
600 u64 roc; 662 u64 roc;
601 u64 rjc; 663 u64 rjc;
602 u64 mgprc; 664 u64 mgprc;
603 u64 mgpdc; 665 u64 mgpdc;
604 u64 mgptc; 666 u64 mgptc;
605 u64 torl; !! 667 u64 tor;
606 u64 torh; !! 668 u64 tot;
607 u64 totl; <<
608 u64 toth; <<
609 u64 tpr; 669 u64 tpr;
610 u64 tpt; 670 u64 tpt;
611 u64 ptc64; 671 u64 ptc64;
612 u64 ptc127; 672 u64 ptc127;
613 u64 ptc255; 673 u64 ptc255;
614 u64 ptc511; 674 u64 ptc511;
615 u64 ptc1023; 675 u64 ptc1023;
616 u64 ptc1522; 676 u64 ptc1522;
617 u64 mptc; 677 u64 mptc;
618 u64 bptc; 678 u64 bptc;
619 u64 tsctc; 679 u64 tsctc;
620 u64 tsctfc; 680 u64 tsctfc;
621 u64 iac; 681 u64 iac;
622 u64 icrxptc; 682 u64 icrxptc;
623 u64 icrxatc; 683 u64 icrxatc;
624 u64 ictxptc; 684 u64 ictxptc;
625 u64 ictxatc; 685 u64 ictxatc;
626 u64 ictxqec; 686 u64 ictxqec;
627 u64 ictxqmtc; 687 u64 ictxqmtc;
628 u64 icrxdmtc; 688 u64 icrxdmtc;
629 u64 icrxoc; 689 u64 icrxoc;
630 }; 690 };
631 691
632 struct e1000_phy_stats { 692 struct e1000_phy_stats {
633 u32 idle_errors; 693 u32 idle_errors;
634 u32 receive_errors; 694 u32 receive_errors;
635 }; 695 };
636 696
637 struct e1000_host_mng_dhcp_cookie { 697 struct e1000_host_mng_dhcp_cookie {
638 u32 signature; 698 u32 signature;
639 u8 status; 699 u8 status;
640 u8 reserved0; 700 u8 reserved0;
641 u16 vlan_id; 701 u16 vlan_id;
642 u32 reserved1; 702 u32 reserved1;
643 u16 reserved2; 703 u16 reserved2;
644 u8 reserved3; 704 u8 reserved3;
645 u8 checksum; 705 u8 checksum;
646 }; 706 };
647 707
648 /* Host Interface "Rev 1" */ 708 /* Host Interface "Rev 1" */
649 struct e1000_host_command_header { 709 struct e1000_host_command_header {
650 u8 command_id; 710 u8 command_id;
651 u8 command_length; 711 u8 command_length;
652 u8 command_options; 712 u8 command_options;
653 u8 checksum; 713 u8 checksum;
654 }; 714 };
655 715
656 #define E1000_HI_MAX_DATA_LENGTH 252 716 #define E1000_HI_MAX_DATA_LENGTH 252
657 struct e1000_host_command_info { 717 struct e1000_host_command_info {
658 struct e1000_host_command_header comma 718 struct e1000_host_command_header command_header;
659 u8 command_data[E1000_HI_MAX_DATA_LENG 719 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
660 }; 720 };
661 721
662 /* Host Interface "Rev 2" */ 722 /* Host Interface "Rev 2" */
663 struct e1000_host_mng_command_header { 723 struct e1000_host_mng_command_header {
664 u8 command_id; 724 u8 command_id;
665 u8 checksum; 725 u8 checksum;
666 u16 reserved1; 726 u16 reserved1;
667 u16 reserved2; 727 u16 reserved2;
668 u16 command_length; 728 u16 command_length;
669 }; 729 };
670 730
671 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 731 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
672 struct e1000_host_mng_command_info { 732 struct e1000_host_mng_command_info {
673 struct e1000_host_mng_command_header c 733 struct e1000_host_mng_command_header command_header;
674 u8 command_data[E1000_HI_MAX_MNG_DATA_ 734 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
675 }; 735 };
676 736
677 /* Function pointers and static data for the M 737 /* Function pointers and static data for the MAC. */
678 struct e1000_mac_operations { 738 struct e1000_mac_operations {
679 u32 mng_mode_enab; !! 739 s32 (*id_led_init)(struct e1000_hw *);
680 !! 740 bool (*check_mng_mode)(struct e1000_hw *);
681 s32 (*check_for_link)(struct e1000_hw 741 s32 (*check_for_link)(struct e1000_hw *);
682 s32 (*cleanup_led)(struct e1000_hw *) 742 s32 (*cleanup_led)(struct e1000_hw *);
683 void (*clear_hw_cntrs)(struct e1000_hw 743 void (*clear_hw_cntrs)(struct e1000_hw *);
684 s32 (*get_bus_info)(struct e1000_hw * 744 s32 (*get_bus_info)(struct e1000_hw *);
685 s32 (*get_link_up_info)(struct e1000_ 745 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
686 s32 (*led_on)(struct e1000_hw *); 746 s32 (*led_on)(struct e1000_hw *);
687 s32 (*led_off)(struct e1000_hw *); 747 s32 (*led_off)(struct e1000_hw *);
688 void (*mc_addr_list_update)(struct e10 !! 748 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
689 u32); <<
690 s32 (*reset_hw)(struct e1000_hw *); 749 s32 (*reset_hw)(struct e1000_hw *);
691 s32 (*init_hw)(struct e1000_hw *); 750 s32 (*init_hw)(struct e1000_hw *);
692 s32 (*setup_link)(struct e1000_hw *); 751 s32 (*setup_link)(struct e1000_hw *);
693 s32 (*setup_physical_interface)(struc 752 s32 (*setup_physical_interface)(struct e1000_hw *);
>> 753 s32 (*setup_led)(struct e1000_hw *);
694 }; 754 };
695 755
696 /* Function pointers for the PHY. */ 756 /* Function pointers for the PHY. */
697 struct e1000_phy_operations { 757 struct e1000_phy_operations {
698 s32 (*acquire_phy)(struct e1000_hw *) 758 s32 (*acquire_phy)(struct e1000_hw *);
>> 759 s32 (*check_polarity)(struct e1000_hw *);
699 s32 (*check_reset_block)(struct e1000 760 s32 (*check_reset_block)(struct e1000_hw *);
700 s32 (*commit_phy)(struct e1000_hw *); 761 s32 (*commit_phy)(struct e1000_hw *);
701 s32 (*force_speed_duplex)(struct e100 762 s32 (*force_speed_duplex)(struct e1000_hw *);
702 s32 (*get_cfg_done)(struct e1000_hw * 763 s32 (*get_cfg_done)(struct e1000_hw *hw);
703 s32 (*get_cable_length)(struct e1000_ 764 s32 (*get_cable_length)(struct e1000_hw *);
704 s32 (*get_phy_info)(struct e1000_hw * 765 s32 (*get_phy_info)(struct e1000_hw *);
705 s32 (*read_phy_reg)(struct e1000_hw * 766 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
706 void (*release_phy)(struct e1000_hw *) 767 void (*release_phy)(struct e1000_hw *);
707 s32 (*reset_phy)(struct e1000_hw *); 768 s32 (*reset_phy)(struct e1000_hw *);
708 s32 (*set_d0_lplu_state)(struct e1000 769 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
709 s32 (*set_d3_lplu_state)(struct e1000 770 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
710 s32 (*write_phy_reg)(struct e1000_hw 771 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
>> 772 s32 (*cfg_on_link_up)(struct e1000_hw *);
711 }; 773 };
712 774
713 /* Function pointers for the NVM. */ 775 /* Function pointers for the NVM. */
714 struct e1000_nvm_operations { 776 struct e1000_nvm_operations {
715 s32 (*acquire_nvm)(struct e1000_hw *) 777 s32 (*acquire_nvm)(struct e1000_hw *);
716 s32 (*read_nvm)(struct e1000_hw *, u1 778 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
717 void (*release_nvm)(struct e1000_hw *) 779 void (*release_nvm)(struct e1000_hw *);
718 s32 (*update_nvm)(struct e1000_hw *); 780 s32 (*update_nvm)(struct e1000_hw *);
719 s32 (*valid_led_default)(struct e1000 781 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
720 s32 (*validate_nvm)(struct e1000_hw * 782 s32 (*validate_nvm)(struct e1000_hw *);
721 s32 (*write_nvm)(struct e1000_hw *, u 783 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
722 }; 784 };
723 785
724 struct e1000_mac_info { 786 struct e1000_mac_info {
725 struct e1000_mac_operations ops; 787 struct e1000_mac_operations ops;
726 788
727 u8 addr[6]; 789 u8 addr[6];
728 u8 perm_addr[6]; 790 u8 perm_addr[6];
729 791
730 enum e1000_mac_type type; 792 enum e1000_mac_type type;
731 enum e1000_fc_mode fc; <<
732 enum e1000_fc_mode original_fc; <<
733 793
734 u32 collision_delta; 794 u32 collision_delta;
735 u32 ledctl_default; 795 u32 ledctl_default;
736 u32 ledctl_mode1; 796 u32 ledctl_mode1;
737 u32 ledctl_mode2; 797 u32 ledctl_mode2;
738 u32 max_frame_size; <<
739 u32 mc_filter_type; 798 u32 mc_filter_type;
740 u32 min_frame_size; <<
741 u32 tx_packet_delta; 799 u32 tx_packet_delta;
742 u32 txcw; 800 u32 txcw;
743 801
744 u16 current_ifs_val; 802 u16 current_ifs_val;
745 u16 ifs_max_val; 803 u16 ifs_max_val;
746 u16 ifs_min_val; 804 u16 ifs_min_val;
747 u16 ifs_ratio; 805 u16 ifs_ratio;
748 u16 ifs_step_size; 806 u16 ifs_step_size;
749 u16 mta_reg_count; 807 u16 mta_reg_count;
750 u16 rar_entry_count; 808 u16 rar_entry_count;
751 u16 fc_high_water; <<
752 u16 fc_low_water; <<
753 u16 fc_pause_time; <<
754 809
755 u8 forced_speed_duplex; 810 u8 forced_speed_duplex;
756 811
757 bool arc_subsystem_valid; 812 bool arc_subsystem_valid;
758 bool autoneg; 813 bool autoneg;
759 bool autoneg_failed; 814 bool autoneg_failed;
760 bool get_link_status; 815 bool get_link_status;
761 bool in_ifs_mode; 816 bool in_ifs_mode;
762 bool serdes_has_link; 817 bool serdes_has_link;
763 bool tx_pkt_filtering; 818 bool tx_pkt_filtering;
>> 819 enum e1000_serdes_link_state serdes_link_state;
764 }; 820 };
765 821
766 struct e1000_phy_info { 822 struct e1000_phy_info {
767 struct e1000_phy_operations ops; 823 struct e1000_phy_operations ops;
768 824
769 enum e1000_phy_type type; 825 enum e1000_phy_type type;
770 826
771 enum e1000_1000t_rx_status local_rx; 827 enum e1000_1000t_rx_status local_rx;
772 enum e1000_1000t_rx_status remote_rx; 828 enum e1000_1000t_rx_status remote_rx;
773 enum e1000_ms_type ms_type; 829 enum e1000_ms_type ms_type;
774 enum e1000_ms_type original_ms_type; 830 enum e1000_ms_type original_ms_type;
775 enum e1000_rev_polarity cable_polarity 831 enum e1000_rev_polarity cable_polarity;
776 enum e1000_smart_speed smart_speed; 832 enum e1000_smart_speed smart_speed;
777 833
778 u32 addr; 834 u32 addr;
779 u32 id; 835 u32 id;
780 u32 reset_delay_us; /* in usec */ 836 u32 reset_delay_us; /* in usec */
781 u32 revision; 837 u32 revision;
782 838
>> 839 enum e1000_media_type media_type;
>> 840
783 u16 autoneg_advertised; 841 u16 autoneg_advertised;
784 u16 autoneg_mask; 842 u16 autoneg_mask;
785 u16 cable_length; 843 u16 cable_length;
786 u16 max_cable_length; 844 u16 max_cable_length;
787 u16 min_cable_length; 845 u16 min_cable_length;
788 846
789 u8 mdix; 847 u8 mdix;
790 848
791 bool disable_polarity_correction; 849 bool disable_polarity_correction;
792 bool is_mdix; 850 bool is_mdix;
793 bool polarity_correction; 851 bool polarity_correction;
794 bool speed_downgraded; 852 bool speed_downgraded;
795 bool wait_for_link; !! 853 bool autoneg_wait_to_complete;
796 }; 854 };
797 855
798 struct e1000_nvm_info { 856 struct e1000_nvm_info {
799 struct e1000_nvm_operations ops; 857 struct e1000_nvm_operations ops;
800 858
801 enum e1000_nvm_type type; 859 enum e1000_nvm_type type;
802 enum e1000_nvm_override override; 860 enum e1000_nvm_override override;
803 861
804 u32 flash_bank_size; 862 u32 flash_bank_size;
805 u32 flash_base_addr; 863 u32 flash_base_addr;
806 864
807 u16 word_size; 865 u16 word_size;
808 u16 delay_usec; 866 u16 delay_usec;
809 u16 address_bits; 867 u16 address_bits;
810 u16 opcode_bits; 868 u16 opcode_bits;
811 u16 page_size; 869 u16 page_size;
812 }; 870 };
813 871
814 struct e1000_bus_info { 872 struct e1000_bus_info {
815 enum e1000_bus_width width; 873 enum e1000_bus_width width;
816 874
817 u16 func; 875 u16 func;
818 }; 876 };
819 877
>> 878 struct e1000_fc_info {
>> 879 u32 high_water; /* Flow control high-water mark */
>> 880 u32 low_water; /* Flow control low-water mark */
>> 881 u16 pause_time; /* Flow control pause timer */
>> 882 bool send_xon; /* Flow control send XON */
>> 883 bool strict_ieee; /* Strict IEEE mode */
>> 884 enum e1000_fc_mode current_mode; /* FC mode in effect */
>> 885 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
>> 886 };
>> 887
820 struct e1000_dev_spec_82571 { 888 struct e1000_dev_spec_82571 {
821 bool laa_is_present; 889 bool laa_is_present;
822 bool alt_mac_addr_is_present; 890 bool alt_mac_addr_is_present;
>> 891 u32 smb_counter;
823 }; 892 };
824 893
825 struct e1000_shadow_ram { 894 struct e1000_shadow_ram {
826 u16 value; 895 u16 value;
827 bool modified; 896 bool modified;
828 }; 897 };
829 898
830 #define E1000_ICH8_SHADOW_RAM_WORDS 899 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
831 900
832 struct e1000_dev_spec_ich8lan { 901 struct e1000_dev_spec_ich8lan {
833 bool kmrn_lock_loss_workaround_enabled 902 bool kmrn_lock_loss_workaround_enabled;
834 struct e1000_shadow_ram shadow_ram[E10 903 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
835 }; 904 };
836 905
837 struct e1000_hw { 906 struct e1000_hw {
838 struct e1000_adapter *adapter; 907 struct e1000_adapter *adapter;
839 908
840 u8 __iomem *hw_addr; 909 u8 __iomem *hw_addr;
841 u8 __iomem *flash_address; 910 u8 __iomem *flash_address;
842 911
843 struct e1000_mac_info mac; 912 struct e1000_mac_info mac;
>> 913 struct e1000_fc_info fc;
844 struct e1000_phy_info phy; 914 struct e1000_phy_info phy;
845 struct e1000_nvm_info nvm; 915 struct e1000_nvm_info nvm;
846 struct e1000_bus_info bus; 916 struct e1000_bus_info bus;
847 struct e1000_host_mng_dhcp_cookie mng_ 917 struct e1000_host_mng_dhcp_cookie mng_cookie;
848 918
849 union { 919 union {
850 struct e1000_dev_spec_82571 920 struct e1000_dev_spec_82571 e82571;
851 struct e1000_dev_spec_ich8lan 921 struct e1000_dev_spec_ich8lan ich8lan;
852 } dev_spec; 922 } dev_spec;
853 <<
854 enum e1000_media_type media_type; <<
855 }; 923 };
856 924
857 #ifdef DEBUG 925 #ifdef DEBUG
858 #define hw_dbg(hw, format, arg...) \ 926 #define hw_dbg(hw, format, arg...) \
859 printk(KERN_DEBUG "%s: " format, e1000 927 printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
860 #else 928 #else
861 static inline int __attribute__ ((format (prin 929 static inline int __attribute__ ((format (printf, 2, 3)))
862 hw_dbg(struct e1000_hw *hw, const char *format 930 hw_dbg(struct e1000_hw *hw, const char *format, ...)
863 { 931 {
864 return 0; 932 return 0;
865 } 933 }
866 #endif 934 #endif
867 935
868 #endif 936 #endif
869 937
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