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1 /********************************************* 1 /*******************************************************************************
2 2
3 Intel PRO/1000 Linux driver 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation. 4 Copyright(c) 1999 - 2007 Intel Corporation.
5 5
6 This program is free software; you can redis 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU Ge 7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software 8 version 2, as published by the Free Software Foundation.
9 9
10 This program is distributed in the hope it w 10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warra 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the G 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details. 13 more details.
14 14
15 You should have received a copy of the GNU G 15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Soft 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 021 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 18
19 The full GNU General Public License is inclu 19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING". 20 the file called "COPYING".
21 21
22 Contact Information: 22 Contact Information:
23 Linux NICS <linux.nics@intel.com> 23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists. 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Park 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 26
27 ********************************************** 27 *******************************************************************************/
28 28
29 #ifndef _E1000_HW_H_ 29 #ifndef _E1000_HW_H_
30 #define _E1000_HW_H_ 30 #define _E1000_HW_H_
31 31
32 #include <linux/types.h> 32 #include <linux/types.h>
33 33
34 struct e1000_hw; 34 struct e1000_hw;
35 struct e1000_adapter; 35 struct e1000_adapter;
36 36
37 #include "defines.h" 37 #include "defines.h"
38 38
39 #define er32(reg) __er32(hw, E1000_##reg 39 #define er32(reg) __er32(hw, E1000_##reg)
40 #define ew32(reg,val) __ew32(hw, E1000_##reg 40 #define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41 #define e1e_flush() er32(STATUS) 41 #define e1e_flush() er32(STATUS)
42 42
43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, 43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + 44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45 45
46 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 46 #define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) 47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48 48
49 enum e1e_registers { 49 enum e1e_registers {
50 E1000_CTRL = 0x00000, /* Device Co 50 E1000_CTRL = 0x00000, /* Device Control - RW */
51 E1000_STATUS = 0x00008, /* Device St 51 E1000_STATUS = 0x00008, /* Device Status - RO */
52 E1000_EECD = 0x00010, /* EEPROM/Fl 52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
53 E1000_EERD = 0x00014, /* EEPROM Re 53 E1000_EERD = 0x00014, /* EEPROM Read - RW */
54 E1000_CTRL_EXT = 0x00018, /* Extended 54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
55 E1000_FLA = 0x0001C, /* Flash Acc 55 E1000_FLA = 0x0001C, /* Flash Access - RW */
56 E1000_MDIC = 0x00020, /* MDI Contr 56 E1000_MDIC = 0x00020, /* MDI Control - RW */
57 E1000_SCTL = 0x00024, /* SerDes Co 57 E1000_SCTL = 0x00024, /* SerDes Control - RW */
58 E1000_FCAL = 0x00028, /* Flow Cont 58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
59 E1000_FCAH = 0x0002C, /* Flow Cont 59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
60 E1000_FEXTNVM = 0x00028, /* Future Ex 60 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
61 E1000_FCT = 0x00030, /* Flow Cont 61 E1000_FCT = 0x00030, /* Flow Control Type - RW */
62 E1000_VET = 0x00038, /* VLAN Ethe 62 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
63 E1000_ICR = 0x000C0, /* Interrupt 63 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
64 E1000_ITR = 0x000C4, /* Interrupt 64 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
65 E1000_ICS = 0x000C8, /* Interrupt 65 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
66 E1000_IMS = 0x000D0, /* Interrupt 66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt 67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
68 E1000_IAM = 0x000E0, /* Interrupt 68 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
69 E1000_RCTL = 0x00100, /* RX Contro 69 E1000_RCTL = 0x00100, /* RX Control - RW */
70 E1000_FCTTV = 0x00170, /* Flow Cont 70 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
71 E1000_TXCW = 0x00178, /* TX Config 71 E1000_TXCW = 0x00178, /* TX Configuration Word - RW */
72 E1000_RXCW = 0x00180, /* RX Config 72 E1000_RXCW = 0x00180, /* RX Configuration Word - RO */
73 E1000_TCTL = 0x00400, /* TX Contro 73 E1000_TCTL = 0x00400, /* TX Control - RW */
74 E1000_TCTL_EXT = 0x00404, /* Extended 74 E1000_TCTL_EXT = 0x00404, /* Extended TX Control - RW */
75 E1000_TIPG = 0x00410, /* TX Inter- 75 E1000_TIPG = 0x00410, /* TX Inter-packet gap -RW */
76 E1000_AIT = 0x00458, /* Adaptive 76 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle - RW */
77 E1000_LEDCTL = 0x00E00, /* LED Contr 77 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
78 E1000_EXTCNF_CTRL = 0x00F00, /* Exten 78 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
79 E1000_EXTCNF_SIZE = 0x00F08, /* Exten 79 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
80 E1000_PHY_CTRL = 0x00F10, /* PHY C 80 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
81 E1000_PBA = 0x01000, /* Packet Bu 81 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
82 E1000_PBS = 0x01008, /* Packet Bu 82 E1000_PBS = 0x01008, /* Packet Buffer Size */
83 E1000_EEMNGCTL = 0x01010, /* MNG EEpro 83 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
84 E1000_EEWR = 0x0102C, /* EEPROM Wr 84 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
85 E1000_FLOP = 0x0103C, /* FLASH Opc 85 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
86 E1000_ERT = 0x02008, /* Early Rx 86 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
87 E1000_FCRTL = 0x02160, /* Flow Cont 87 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
88 E1000_FCRTH = 0x02168, /* Flow Cont 88 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
89 E1000_PSRCTL = 0x02170, /* Packet Sp 89 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
90 E1000_RDBAL = 0x02800, /* RX Descri 90 E1000_RDBAL = 0x02800, /* RX Descriptor Base Address Low - RW */
91 E1000_RDBAH = 0x02804, /* RX Descri 91 E1000_RDBAH = 0x02804, /* RX Descriptor Base Address High - RW */
92 E1000_RDLEN = 0x02808, /* RX Descri 92 E1000_RDLEN = 0x02808, /* RX Descriptor Length - RW */
93 E1000_RDH = 0x02810, /* RX Descri 93 E1000_RDH = 0x02810, /* RX Descriptor Head - RW */
94 E1000_RDT = 0x02818, /* RX Descri 94 E1000_RDT = 0x02818, /* RX Descriptor Tail - RW */
95 E1000_RDTR = 0x02820, /* RX Delay 95 E1000_RDTR = 0x02820, /* RX Delay Timer - RW */
96 E1000_RADV = 0x0282C, /* RX Interr 96 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
97 97
98 /* Convenience macros 98 /* Convenience macros
99 * 99 *
100 * Note: "_n" is the queue number of the regis 100 * Note: "_n" is the queue number of the register to be written to.
101 * 101 *
102 * Example usage: 102 * Example usage:
103 * E1000_RDBAL_REG(current_rx_queue) 103 * E1000_RDBAL_REG(current_rx_queue)
104 * 104 *
105 */ 105 */
106 #define E1000_RDBAL_REG(_n) (E1000_RDBAL + ( 106 #define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
107 E1000_KABGTXD = 0x03004, /* AFE Band 107 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
108 E1000_TDBAL = 0x03800, /* TX Descri 108 E1000_TDBAL = 0x03800, /* TX Descriptor Base Address Low - RW */
109 E1000_TDBAH = 0x03804, /* TX Descri 109 E1000_TDBAH = 0x03804, /* TX Descriptor Base Address High - RW */
110 E1000_TDLEN = 0x03808, /* TX Descri 110 E1000_TDLEN = 0x03808, /* TX Descriptor Length - RW */
111 E1000_TDH = 0x03810, /* TX Descri 111 E1000_TDH = 0x03810, /* TX Descriptor Head - RW */
112 E1000_TDT = 0x03818, /* TX Descri 112 E1000_TDT = 0x03818, /* TX Descriptor Tail - RW */
113 E1000_TIDV = 0x03820, /* TX Interr 113 E1000_TIDV = 0x03820, /* TX Interrupt Delay Value - RW */
114 E1000_TXDCTL = 0x03828, /* TX Descri 114 E1000_TXDCTL = 0x03828, /* TX Descriptor Control - RW */
115 E1000_TADV = 0x0382C, /* TX Interr 115 E1000_TADV = 0x0382C, /* TX Interrupt Absolute Delay Val - RW */
116 E1000_TARC0 = 0x03840, /* TX Arbitr 116 E1000_TARC0 = 0x03840, /* TX Arbitration Count (0) */
117 E1000_TXDCTL1 = 0x03928, /* TX Descri 117 E1000_TXDCTL1 = 0x03928, /* TX Descriptor Control (1) - RW */
118 E1000_TARC1 = 0x03940, /* TX Arbitr 118 E1000_TARC1 = 0x03940, /* TX Arbitration Count (1) */
119 E1000_CRCERRS = 0x04000, /* CRC Error 119 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
120 E1000_ALGNERRC = 0x04004, /* Alignment 120 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
121 E1000_SYMERRS = 0x04008, /* Symbol Er 121 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
122 E1000_RXERRC = 0x0400C, /* Receive E 122 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
123 E1000_MPC = 0x04010, /* Missed Pa 123 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
124 E1000_SCC = 0x04014, /* Single Co 124 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
125 E1000_ECOL = 0x04018, /* Excessive 125 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
126 E1000_MCC = 0x0401C, /* Multiple 126 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
127 E1000_LATECOL = 0x04020, /* Late Coll 127 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
128 E1000_COLC = 0x04028, /* Collision 128 E1000_COLC = 0x04028, /* Collision Count - R/clr */
129 E1000_DC = 0x04030, /* Defer Cou 129 E1000_DC = 0x04030, /* Defer Count - R/clr */
130 E1000_TNCRS = 0x04034, /* TX-No CRS 130 E1000_TNCRS = 0x04034, /* TX-No CRS - R/clr */
131 E1000_SEC = 0x04038, /* Sequence 131 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
132 E1000_CEXTERR = 0x0403C, /* Carrier E 132 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
133 E1000_RLEC = 0x04040, /* Receive L 133 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
134 E1000_XONRXC = 0x04048, /* XON RX Co 134 E1000_XONRXC = 0x04048, /* XON RX Count - R/clr */
135 E1000_XONTXC = 0x0404C, /* XON TX Co 135 E1000_XONTXC = 0x0404C, /* XON TX Count - R/clr */
136 E1000_XOFFRXC = 0x04050, /* XOFF RX C 136 E1000_XOFFRXC = 0x04050, /* XOFF RX Count - R/clr */
137 E1000_XOFFTXC = 0x04054, /* XOFF TX C 137 E1000_XOFFTXC = 0x04054, /* XOFF TX Count - R/clr */
138 E1000_FCRUC = 0x04058, /* Flow Cont 138 E1000_FCRUC = 0x04058, /* Flow Control RX Unsupported Count- R/clr */
139 E1000_PRC64 = 0x0405C, /* Packets R 139 E1000_PRC64 = 0x0405C, /* Packets RX (64 bytes) - R/clr */
140 E1000_PRC127 = 0x04060, /* Packets R 140 E1000_PRC127 = 0x04060, /* Packets RX (65-127 bytes) - R/clr */
141 E1000_PRC255 = 0x04064, /* Packets R 141 E1000_PRC255 = 0x04064, /* Packets RX (128-255 bytes) - R/clr */
142 E1000_PRC511 = 0x04068, /* Packets R 142 E1000_PRC511 = 0x04068, /* Packets RX (255-511 bytes) - R/clr */
143 E1000_PRC1023 = 0x0406C, /* Packets R 143 E1000_PRC1023 = 0x0406C, /* Packets RX (512-1023 bytes) - R/clr */
144 E1000_PRC1522 = 0x04070, /* Packets R 144 E1000_PRC1522 = 0x04070, /* Packets RX (1024-1522 bytes) - R/clr */
145 E1000_GPRC = 0x04074, /* Good Pack 145 E1000_GPRC = 0x04074, /* Good Packets RX Count - R/clr */
146 E1000_BPRC = 0x04078, /* Broadcast 146 E1000_BPRC = 0x04078, /* Broadcast Packets RX Count - R/clr */
147 E1000_MPRC = 0x0407C, /* Multicast 147 E1000_MPRC = 0x0407C, /* Multicast Packets RX Count - R/clr */
148 E1000_GPTC = 0x04080, /* Good Pack 148 E1000_GPTC = 0x04080, /* Good Packets TX Count - R/clr */
149 E1000_GORCL = 0x04088, /* Good Octe 149 E1000_GORCL = 0x04088, /* Good Octets RX Count Low - R/clr */
150 E1000_GORCH = 0x0408C, /* Good Octe 150 E1000_GORCH = 0x0408C, /* Good Octets RX Count High - R/clr */
151 E1000_GOTCL = 0x04090, /* Good Octe 151 E1000_GOTCL = 0x04090, /* Good Octets TX Count Low - R/clr */
152 E1000_GOTCH = 0x04094, /* Good Octe 152 E1000_GOTCH = 0x04094, /* Good Octets TX Count High - R/clr */
153 E1000_RNBC = 0x040A0, /* RX No Buf 153 E1000_RNBC = 0x040A0, /* RX No Buffers Count - R/clr */
154 E1000_RUC = 0x040A4, /* RX Unders 154 E1000_RUC = 0x040A4, /* RX Undersize Count - R/clr */
155 E1000_RFC = 0x040A8, /* RX Fragme 155 E1000_RFC = 0x040A8, /* RX Fragment Count - R/clr */
156 E1000_ROC = 0x040AC, /* RX Oversi 156 E1000_ROC = 0x040AC, /* RX Oversize Count - R/clr */
157 E1000_RJC = 0x040B0, /* RX Jabber 157 E1000_RJC = 0x040B0, /* RX Jabber Count - R/clr */
158 E1000_MGTPRC = 0x040B4, /* Managemen 158 E1000_MGTPRC = 0x040B4, /* Management Packets RX Count - R/clr */
159 E1000_MGTPDC = 0x040B8, /* Managemen 159 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
160 E1000_MGTPTC = 0x040BC, /* Managemen 160 E1000_MGTPTC = 0x040BC, /* Management Packets TX Count - R/clr */
161 E1000_TORL = 0x040C0, /* Total Oct 161 E1000_TORL = 0x040C0, /* Total Octets RX Low - R/clr */
162 E1000_TORH = 0x040C4, /* Total Oct 162 E1000_TORH = 0x040C4, /* Total Octets RX High - R/clr */
163 E1000_TOTL = 0x040C8, /* Total Oct 163 E1000_TOTL = 0x040C8, /* Total Octets TX Low - R/clr */
164 E1000_TOTH = 0x040CC, /* Total Oct 164 E1000_TOTH = 0x040CC, /* Total Octets TX High - R/clr */
165 E1000_TPR = 0x040D0, /* Total Pac 165 E1000_TPR = 0x040D0, /* Total Packets RX - R/clr */
166 E1000_TPT = 0x040D4, /* Total Pac 166 E1000_TPT = 0x040D4, /* Total Packets TX - R/clr */
167 E1000_PTC64 = 0x040D8, /* Packets T 167 E1000_PTC64 = 0x040D8, /* Packets TX (64 bytes) - R/clr */
168 E1000_PTC127 = 0x040DC, /* Packets T 168 E1000_PTC127 = 0x040DC, /* Packets TX (65-127 bytes) - R/clr */
169 E1000_PTC255 = 0x040E0, /* Packets T 169 E1000_PTC255 = 0x040E0, /* Packets TX (128-255 bytes) - R/clr */
170 E1000_PTC511 = 0x040E4, /* Packets T 170 E1000_PTC511 = 0x040E4, /* Packets TX (256-511 bytes) - R/clr */
171 E1000_PTC1023 = 0x040E8, /* Packets T 171 E1000_PTC1023 = 0x040E8, /* Packets TX (512-1023 bytes) - R/clr */
172 E1000_PTC1522 = 0x040EC, /* Packets T 172 E1000_PTC1522 = 0x040EC, /* Packets TX (1024-1522 Bytes) - R/clr */
173 E1000_MPTC = 0x040F0, /* Multicast 173 E1000_MPTC = 0x040F0, /* Multicast Packets TX Count - R/clr */
174 E1000_BPTC = 0x040F4, /* Broadcast 174 E1000_BPTC = 0x040F4, /* Broadcast Packets TX Count - R/clr */
175 E1000_TSCTC = 0x040F8, /* TCP Segme 175 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context TX - R/clr */
176 E1000_TSCTFC = 0x040FC, /* TCP Segme 176 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context TX Fail - R/clr */
177 E1000_IAC = 0x04100, /* Interrupt 177 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
178 E1000_ICRXPTC = 0x04104, /* Irq Cause 178 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
179 E1000_ICRXATC = 0x04108, /* Irq Cause 179 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
180 E1000_ICTXPTC = 0x0410C, /* Irq Cause 180 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
181 E1000_ICTXATC = 0x04110, /* Irq Cause 181 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
182 E1000_ICTXQEC = 0x04118, /* Irq Cause 182 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
183 E1000_ICTXQMTC = 0x0411C, /* Irq Cause 183 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
184 E1000_ICRXDMTC = 0x04120, /* Irq Cause 184 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
185 E1000_ICRXOC = 0x04124, /* Irq Cause 185 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
186 E1000_RXCSUM = 0x05000, /* RX Checks 186 E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */
187 E1000_RFCTL = 0x05008, /* Receive F 187 E1000_RFCTL = 0x05008, /* Receive Filter Control */
188 E1000_MTA = 0x05200, /* Multicast 188 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
189 E1000_RA = 0x05400, /* Receive A 189 E1000_RA = 0x05400, /* Receive Address - RW Array */
190 E1000_VFTA = 0x05600, /* VLAN Filt 190 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
191 E1000_WUC = 0x05800, /* Wakeup Co 191 E1000_WUC = 0x05800, /* Wakeup Control - RW */
192 E1000_WUFC = 0x05808, /* Wakeup Fi 192 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
193 E1000_WUS = 0x05810, /* Wakeup St 193 E1000_WUS = 0x05810, /* Wakeup Status - RO */
194 E1000_MANC = 0x05820, /* Managemen 194 E1000_MANC = 0x05820, /* Management Control - RW */
195 E1000_FFLT = 0x05F00, /* Flexible 195 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
196 E1000_HOST_IF = 0x08800, /* Host Inte 196 E1000_HOST_IF = 0x08800, /* Host Interface */
197 197
198 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PH 198 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
199 E1000_MANC2H = 0x05860, /* Manageme 199 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
200 E1000_SW_FW_SYNC = 0x05B5C, /* Softwar 200 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
201 E1000_GCR = 0x05B00, /* PCI-Ex C 201 E1000_GCR = 0x05B00, /* PCI-Ex Control */
202 E1000_FACTPS = 0x05B30, /* Function 202 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
203 E1000_SWSM = 0x05B50, /* SW Semap 203 E1000_SWSM = 0x05B50, /* SW Semaphore */
204 E1000_FWSM = 0x05B54, /* FW Semap 204 E1000_FWSM = 0x05B54, /* FW Semaphore */
205 E1000_HICR = 0x08F00, /* Host Int 205 E1000_HICR = 0x08F00, /* Host Interface Control */
206 }; 206 };
207 207
208 /* RSS registers */ 208 /* RSS registers */
209 209
210 /* IGP01E1000 Specific Registers */ 210 /* IGP01E1000 Specific Registers */
211 #define IGP01E1000_PHY_PORT_CONFIG 0x10 / 211 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
212 #define IGP01E1000_PHY_PORT_STATUS 0x11 / 212 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
213 #define IGP01E1000_PHY_PORT_CTRL 0x12 / 213 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
214 #define IGP01E1000_PHY_LINK_HEALTH 0x13 / 214 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
215 #define IGP02E1000_PHY_POWER_MGMT 0x19 / 215 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
216 #define IGP01E1000_PHY_PAGE_SELECT 0x1F / 216 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
217 217
218 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 218 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
219 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 219 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
220 220
221 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 221 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
222 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 222 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
223 223
224 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 224 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
225 225
226 #define IGP02E1000_PM_SPD 0x0001 226 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
227 #define IGP02E1000_PM_D0_LPLU 0x0002 227 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
228 #define IGP02E1000_PM_D3_LPLU 0x0004 228 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
229 229
230 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 230 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
231 231
232 #define IGP01E1000_PSSR_POLARITY_REVERSED 232 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
233 #define IGP01E1000_PSSR_MDIX 233 #define IGP01E1000_PSSR_MDIX 0x0008
234 #define IGP01E1000_PSSR_SPEED_MASK 234 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
235 #define IGP01E1000_PSSR_SPEED_1000MBPS 235 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
236 236
237 #define IGP02E1000_PHY_CHANNEL_NUM 237 #define IGP02E1000_PHY_CHANNEL_NUM 4
238 #define IGP02E1000_PHY_AGC_A 238 #define IGP02E1000_PHY_AGC_A 0x11B1
239 #define IGP02E1000_PHY_AGC_B 239 #define IGP02E1000_PHY_AGC_B 0x12B1
240 #define IGP02E1000_PHY_AGC_C 240 #define IGP02E1000_PHY_AGC_C 0x14B1
241 #define IGP02E1000_PHY_AGC_D 241 #define IGP02E1000_PHY_AGC_D 0x18B1
242 242
243 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* C 243 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
244 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 244 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
245 #define IGP02E1000_AGC_RANGE 15 245 #define IGP02E1000_AGC_RANGE 15
246 246
247 /* manage.c */ 247 /* manage.c */
248 #define E1000_VFTA_ENTRY_SHIFT 5 248 #define E1000_VFTA_ENTRY_SHIFT 5
249 #define E1000_VFTA_ENTRY_MASK 0x7F 249 #define E1000_VFTA_ENTRY_MASK 0x7F
250 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 250 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
251 251
252 #define E1000_HICR_EN 0x01 252 #define E1000_HICR_EN 0x01 /* Enable bit - RO */
253 #define E1000_HICR_C 0x02 253 #define E1000_HICR_C 0x02 /* Driver sets this bit when done
254 254 * to put command in RAM */
255 #define E1000_HICR_FW_RESET_ENABLE 0x40 255 #define E1000_HICR_FW_RESET_ENABLE 0x40
256 #define E1000_HICR_FW_RESET 0x80 256 #define E1000_HICR_FW_RESET 0x80
257 257
258 #define E1000_FWSM_MODE_MASK 0xE 258 #define E1000_FWSM_MODE_MASK 0xE
259 #define E1000_FWSM_MODE_SHIFT 1 259 #define E1000_FWSM_MODE_SHIFT 1
260 260
261 #define E1000_MNG_IAMT_MODE 0x3 261 #define E1000_MNG_IAMT_MODE 0x3
262 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 262 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
263 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 263 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
264 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 264 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
265 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 265 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
266 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 266 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
267 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 267 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
268 268
269 /* nvm.c */ 269 /* nvm.c */
270 #define E1000_STM_OPCODE 0xDB00 270 #define E1000_STM_OPCODE 0xDB00
271 271
272 #define E1000_KMRNCTRLSTA_OFFSET 0x001F 272 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
273 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 273 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
274 #define E1000_KMRNCTRLSTA_REN 0x0020 274 #define E1000_KMRNCTRLSTA_REN 0x00200000
275 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 275 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
276 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 276 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
277 277
278 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 278 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
279 #define IFE_PHY_SPECIAL_CONTROL 0x11 / 279 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
280 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B / 280 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
281 #define IFE_PHY_MDIX_CONTROL 0x1C / 281 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
282 282
283 /* IFE PHY Extended Status Control */ 283 /* IFE PHY Extended Status Control */
284 #define IFE_PESC_POLARITY_REVERSED 0x0100 284 #define IFE_PESC_POLARITY_REVERSED 0x0100
285 285
286 /* IFE PHY Special Control */ 286 /* IFE PHY Special Control */
287 #define IFE_PSC_AUTO_POLARITY_DISABLE 287 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
288 #define IFE_PSC_FORCE_POLARITY 288 #define IFE_PSC_FORCE_POLARITY 0x0020
289 289
290 /* IFE PHY Special Control and LED Control */ 290 /* IFE PHY Special Control and LED Control */
291 #define IFE_PSCL_PROBE_MODE 0x0020 291 #define IFE_PSCL_PROBE_MODE 0x0020
292 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 292 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
293 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 293 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
294 294
295 /* IFE PHY MDIX Control */ 295 /* IFE PHY MDIX Control */
296 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MD 296 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
297 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=fo 297 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
298 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=en 298 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
299 299
300 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 300 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
301 301
302 #define E1000_DEV_ID_82571EB_COPPER 302 #define E1000_DEV_ID_82571EB_COPPER 0x105E
303 #define E1000_DEV_ID_82571EB_FIBER 303 #define E1000_DEV_ID_82571EB_FIBER 0x105F
304 #define E1000_DEV_ID_82571EB_SERDES 304 #define E1000_DEV_ID_82571EB_SERDES 0x1060
305 #define E1000_DEV_ID_82571EB_QUAD_COPPER 305 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
306 #define E1000_DEV_ID_82571PT_QUAD_COPPER 306 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
307 #define E1000_DEV_ID_82571EB_QUAD_FIBER 307 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
308 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 308 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
309 #define E1000_DEV_ID_82571EB_SERDES_DUAL 309 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
310 #define E1000_DEV_ID_82571EB_SERDES_QUAD 310 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
311 #define E1000_DEV_ID_82572EI_COPPER 311 #define E1000_DEV_ID_82572EI_COPPER 0x107D
312 #define E1000_DEV_ID_82572EI_FIBER 312 #define E1000_DEV_ID_82572EI_FIBER 0x107E
313 #define E1000_DEV_ID_82572EI_SERDES 313 #define E1000_DEV_ID_82572EI_SERDES 0x107F
314 #define E1000_DEV_ID_82572EI 314 #define E1000_DEV_ID_82572EI 0x10B9
315 #define E1000_DEV_ID_82573E 315 #define E1000_DEV_ID_82573E 0x108B
316 #define E1000_DEV_ID_82573E_IAMT 316 #define E1000_DEV_ID_82573E_IAMT 0x108C
317 #define E1000_DEV_ID_82573L 317 #define E1000_DEV_ID_82573L 0x109A
318 318
319 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 319 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
320 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 320 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
321 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 321 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
322 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 322 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
323 323
324 #define E1000_DEV_ID_ICH8_IGP_M_AMT 324 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
325 #define E1000_DEV_ID_ICH8_IGP_AMT 325 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
326 #define E1000_DEV_ID_ICH8_IGP_C 326 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
327 #define E1000_DEV_ID_ICH8_IFE 327 #define E1000_DEV_ID_ICH8_IFE 0x104C
328 #define E1000_DEV_ID_ICH8_IFE_GT 328 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
329 #define E1000_DEV_ID_ICH8_IFE_G 329 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
330 #define E1000_DEV_ID_ICH8_IGP_M 330 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
331 #define E1000_DEV_ID_ICH9_IGP_AMT 331 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
332 #define E1000_DEV_ID_ICH9_IGP_C 332 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
333 #define E1000_DEV_ID_ICH9_IFE 333 #define E1000_DEV_ID_ICH9_IFE 0x10C0
334 #define E1000_DEV_ID_ICH9_IFE_GT 334 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
335 #define E1000_DEV_ID_ICH9_IFE_G 335 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
336 336
337 #define E1000_FUNC_1 1 337 #define E1000_FUNC_1 1
338 338
339 enum e1000_mac_type { 339 enum e1000_mac_type {
340 e1000_82571, 340 e1000_82571,
341 e1000_82572, 341 e1000_82572,
342 e1000_82573, 342 e1000_82573,
343 e1000_80003es2lan, 343 e1000_80003es2lan,
344 e1000_ich8lan, 344 e1000_ich8lan,
345 e1000_ich9lan, 345 e1000_ich9lan,
346 }; 346 };
347 347
348 enum e1000_media_type { 348 enum e1000_media_type {
349 e1000_media_type_unknown = 0, 349 e1000_media_type_unknown = 0,
350 e1000_media_type_copper = 1, 350 e1000_media_type_copper = 1,
351 e1000_media_type_fiber = 2, 351 e1000_media_type_fiber = 2,
352 e1000_media_type_internal_serdes = 3, 352 e1000_media_type_internal_serdes = 3,
353 e1000_num_media_types 353 e1000_num_media_types
354 }; 354 };
355 355
356 enum e1000_nvm_type { 356 enum e1000_nvm_type {
357 e1000_nvm_unknown = 0, 357 e1000_nvm_unknown = 0,
358 e1000_nvm_none, 358 e1000_nvm_none,
359 e1000_nvm_eeprom_spi, 359 e1000_nvm_eeprom_spi,
360 e1000_nvm_flash_hw, 360 e1000_nvm_flash_hw,
361 e1000_nvm_flash_sw 361 e1000_nvm_flash_sw
362 }; 362 };
363 363
364 enum e1000_nvm_override { 364 enum e1000_nvm_override {
365 e1000_nvm_override_none = 0, 365 e1000_nvm_override_none = 0,
366 e1000_nvm_override_spi_small, 366 e1000_nvm_override_spi_small,
367 e1000_nvm_override_spi_large 367 e1000_nvm_override_spi_large
368 }; 368 };
369 369
370 enum e1000_phy_type { 370 enum e1000_phy_type {
371 e1000_phy_unknown = 0, 371 e1000_phy_unknown = 0,
372 e1000_phy_none, 372 e1000_phy_none,
373 e1000_phy_m88, 373 e1000_phy_m88,
374 e1000_phy_igp, 374 e1000_phy_igp,
375 e1000_phy_igp_2, 375 e1000_phy_igp_2,
376 e1000_phy_gg82563, 376 e1000_phy_gg82563,
377 e1000_phy_igp_3, 377 e1000_phy_igp_3,
378 e1000_phy_ife, 378 e1000_phy_ife,
379 }; 379 };
380 380
381 enum e1000_bus_width { 381 enum e1000_bus_width {
382 e1000_bus_width_unknown = 0, 382 e1000_bus_width_unknown = 0,
383 e1000_bus_width_pcie_x1, 383 e1000_bus_width_pcie_x1,
384 e1000_bus_width_pcie_x2, 384 e1000_bus_width_pcie_x2,
385 e1000_bus_width_pcie_x4 = 4, 385 e1000_bus_width_pcie_x4 = 4,
386 e1000_bus_width_32, 386 e1000_bus_width_32,
387 e1000_bus_width_64, 387 e1000_bus_width_64,
388 e1000_bus_width_reserved 388 e1000_bus_width_reserved
389 }; 389 };
390 390
391 enum e1000_1000t_rx_status { 391 enum e1000_1000t_rx_status {
392 e1000_1000t_rx_status_not_ok = 0, 392 e1000_1000t_rx_status_not_ok = 0,
393 e1000_1000t_rx_status_ok, 393 e1000_1000t_rx_status_ok,
394 e1000_1000t_rx_status_undefined = 0xFF 394 e1000_1000t_rx_status_undefined = 0xFF
395 }; 395 };
396 396
397 enum e1000_rev_polarity{ 397 enum e1000_rev_polarity{
398 e1000_rev_polarity_normal = 0, 398 e1000_rev_polarity_normal = 0,
399 e1000_rev_polarity_reversed, 399 e1000_rev_polarity_reversed,
400 e1000_rev_polarity_undefined = 0xFF 400 e1000_rev_polarity_undefined = 0xFF
401 }; 401 };
402 402
403 enum e1000_fc_mode { 403 enum e1000_fc_mode {
404 e1000_fc_none = 0, 404 e1000_fc_none = 0,
405 e1000_fc_rx_pause, 405 e1000_fc_rx_pause,
406 e1000_fc_tx_pause, 406 e1000_fc_tx_pause,
407 e1000_fc_full, 407 e1000_fc_full,
408 e1000_fc_default = 0xFF 408 e1000_fc_default = 0xFF
409 }; 409 };
410 410
411 enum e1000_ms_type { 411 enum e1000_ms_type {
412 e1000_ms_hw_default = 0, 412 e1000_ms_hw_default = 0,
413 e1000_ms_force_master, 413 e1000_ms_force_master,
414 e1000_ms_force_slave, 414 e1000_ms_force_slave,
415 e1000_ms_auto 415 e1000_ms_auto
416 }; 416 };
417 417
418 enum e1000_smart_speed { 418 enum e1000_smart_speed {
419 e1000_smart_speed_default = 0, 419 e1000_smart_speed_default = 0,
420 e1000_smart_speed_on, 420 e1000_smart_speed_on,
421 e1000_smart_speed_off 421 e1000_smart_speed_off
422 }; 422 };
423 423
424 /* Receive Descriptor */ 424 /* Receive Descriptor */
425 struct e1000_rx_desc { 425 struct e1000_rx_desc {
426 __le64 buffer_addr; /* Address of the 426 __le64 buffer_addr; /* Address of the descriptor's data buffer */
427 __le16 length; /* Length of data 427 __le16 length; /* Length of data DMAed into data buffer */
428 __le16 csum; /* Packet checksum */ 428 __le16 csum; /* Packet checksum */
429 u8 status; /* Descriptor status 429 u8 status; /* Descriptor status */
430 u8 errors; /* Descriptor Errors 430 u8 errors; /* Descriptor Errors */
431 __le16 special; 431 __le16 special;
432 }; 432 };
433 433
434 /* Receive Descriptor - Extended */ 434 /* Receive Descriptor - Extended */
435 union e1000_rx_desc_extended { 435 union e1000_rx_desc_extended {
436 struct { 436 struct {
437 __le64 buffer_addr; 437 __le64 buffer_addr;
438 __le64 reserved; 438 __le64 reserved;
439 } read; 439 } read;
440 struct { 440 struct {
441 struct { 441 struct {
442 __le32 mrq; 442 __le32 mrq; /* Multiple Rx Queues */
443 union { 443 union {
444 __le32 rss; 444 __le32 rss; /* RSS Hash */
445 struct { 445 struct {
446 __le16 446 __le16 ip_id; /* IP id */
447 __le16 447 __le16 csum; /* Packet Checksum */
448 } csum_ip; 448 } csum_ip;
449 } hi_dword; 449 } hi_dword;
450 } lower; 450 } lower;
451 struct { 451 struct {
452 __le32 status_error; 452 __le32 status_error; /* ext status/error */
453 __le16 length; 453 __le16 length;
454 __le16 vlan; / 454 __le16 vlan; /* VLAN tag */
455 } upper; 455 } upper;
456 } wb; /* writeback */ 456 } wb; /* writeback */
457 }; 457 };
458 458
459 #define MAX_PS_BUFFERS 4 459 #define MAX_PS_BUFFERS 4
460 /* Receive Descriptor - Packet Split */ 460 /* Receive Descriptor - Packet Split */
461 union e1000_rx_desc_packet_split { 461 union e1000_rx_desc_packet_split {
462 struct { 462 struct {
463 /* one buffer for protocol hea 463 /* one buffer for protocol header(s), three data buffers */
464 __le64 buffer_addr[MAX_PS_BUFF 464 __le64 buffer_addr[MAX_PS_BUFFERS];
465 } read; 465 } read;
466 struct { 466 struct {
467 struct { 467 struct {
468 __le32 mrq; 468 __le32 mrq; /* Multiple Rx Queues */
469 union { 469 union {
470 __le32 rss; 470 __le32 rss; /* RSS Hash */
471 struct { 471 struct {
472 __le16 472 __le16 ip_id; /* IP id */
473 __le16 473 __le16 csum; /* Packet Checksum */
474 } csum_ip; 474 } csum_ip;
475 } hi_dword; 475 } hi_dword;
476 } lower; 476 } lower;
477 struct { 477 struct {
478 __le32 status_error; 478 __le32 status_error; /* ext status/error */
479 __le16 length0; /* l 479 __le16 length0; /* length of buffer 0 */
480 __le16 vlan; / 480 __le16 vlan; /* VLAN tag */
481 } middle; 481 } middle;
482 struct { 482 struct {
483 __le16 header_status; 483 __le16 header_status;
484 __le16 length[3]; 484 __le16 length[3]; /* length of buffers 1-3 */
485 } upper; 485 } upper;
486 __le64 reserved; 486 __le64 reserved;
487 } wb; /* writeback */ 487 } wb; /* writeback */
488 }; 488 };
489 489
490 /* Transmit Descriptor */ 490 /* Transmit Descriptor */
491 struct e1000_tx_desc { 491 struct e1000_tx_desc {
492 __le64 buffer_addr; /* Address of 492 __le64 buffer_addr; /* Address of the descriptor's data buffer */
493 union { 493 union {
494 __le32 data; 494 __le32 data;
495 struct { 495 struct {
496 __le16 length; /* D 496 __le16 length; /* Data buffer length */
497 u8 cso; /* Checksum of 497 u8 cso; /* Checksum offset */
498 u8 cmd; /* Descriptor 498 u8 cmd; /* Descriptor control */
499 } flags; 499 } flags;
500 } lower; 500 } lower;
501 union { 501 union {
502 __le32 data; 502 __le32 data;
503 struct { 503 struct {
504 u8 status; /* Desc 504 u8 status; /* Descriptor status */
505 u8 css; /* Checksum st 505 u8 css; /* Checksum start */
506 __le16 special; 506 __le16 special;
507 } fields; 507 } fields;
508 } upper; 508 } upper;
509 }; 509 };
510 510
511 /* Offload Context Descriptor */ 511 /* Offload Context Descriptor */
512 struct e1000_context_desc { 512 struct e1000_context_desc {
513 union { 513 union {
514 __le32 ip_config; 514 __le32 ip_config;
515 struct { 515 struct {
516 u8 ipcss; /* IP c 516 u8 ipcss; /* IP checksum start */
517 u8 ipcso; /* IP c 517 u8 ipcso; /* IP checksum offset */
518 __le16 ipcse; /* I 518 __le16 ipcse; /* IP checksum end */
519 } ip_fields; 519 } ip_fields;
520 } lower_setup; 520 } lower_setup;
521 union { 521 union {
522 __le32 tcp_config; 522 __le32 tcp_config;
523 struct { 523 struct {
524 u8 tucss; /* TCP 524 u8 tucss; /* TCP checksum start */
525 u8 tucso; /* TCP 525 u8 tucso; /* TCP checksum offset */
526 __le16 tucse; /* T 526 __le16 tucse; /* TCP checksum end */
527 } tcp_fields; 527 } tcp_fields;
528 } upper_setup; 528 } upper_setup;
529 __le32 cmd_and_length; 529 __le32 cmd_and_length;
530 union { 530 union {
531 __le32 data; 531 __le32 data;
532 struct { 532 struct {
533 u8 status; /* Desc 533 u8 status; /* Descriptor status */
534 u8 hdr_len; /* Head 534 u8 hdr_len; /* Header length */
535 __le16 mss; /* M 535 __le16 mss; /* Maximum segment size */
536 } fields; 536 } fields;
537 } tcp_seg_setup; 537 } tcp_seg_setup;
538 }; 538 };
539 539
540 /* Offload data descriptor */ 540 /* Offload data descriptor */
541 struct e1000_data_desc { 541 struct e1000_data_desc {
542 __le64 buffer_addr; /* Address of th 542 __le64 buffer_addr; /* Address of the descriptor's buffer address */
543 union { 543 union {
544 __le32 data; 544 __le32 data;
545 struct { 545 struct {
546 __le16 length; /* D 546 __le16 length; /* Data buffer length */
547 u8 typ_len_ext; 547 u8 typ_len_ext;
548 u8 cmd; 548 u8 cmd;
549 } flags; 549 } flags;
550 } lower; 550 } lower;
551 union { 551 union {
552 __le32 data; 552 __le32 data;
553 struct { 553 struct {
554 u8 status; /* Desc 554 u8 status; /* Descriptor status */
555 u8 popts; /* Pack 555 u8 popts; /* Packet Options */
556 __le16 special; /* * 556 __le16 special; /* */
557 } fields; 557 } fields;
558 } upper; 558 } upper;
559 }; 559 };
560 560
561 /* Statistics counters collected by the MAC */ 561 /* Statistics counters collected by the MAC */
562 struct e1000_hw_stats { 562 struct e1000_hw_stats {
563 u64 crcerrs; 563 u64 crcerrs;
564 u64 algnerrc; 564 u64 algnerrc;
565 u64 symerrs; 565 u64 symerrs;
566 u64 rxerrc; 566 u64 rxerrc;
567 u64 mpc; 567 u64 mpc;
568 u64 scc; 568 u64 scc;
569 u64 ecol; 569 u64 ecol;
570 u64 mcc; 570 u64 mcc;
571 u64 latecol; 571 u64 latecol;
572 u64 colc; 572 u64 colc;
573 u64 dc; 573 u64 dc;
574 u64 tncrs; 574 u64 tncrs;
575 u64 sec; 575 u64 sec;
576 u64 cexterr; 576 u64 cexterr;
577 u64 rlec; 577 u64 rlec;
578 u64 xonrxc; 578 u64 xonrxc;
579 u64 xontxc; 579 u64 xontxc;
580 u64 xoffrxc; 580 u64 xoffrxc;
581 u64 xofftxc; 581 u64 xofftxc;
582 u64 fcruc; 582 u64 fcruc;
583 u64 prc64; 583 u64 prc64;
584 u64 prc127; 584 u64 prc127;
585 u64 prc255; 585 u64 prc255;
586 u64 prc511; 586 u64 prc511;
587 u64 prc1023; 587 u64 prc1023;
588 u64 prc1522; 588 u64 prc1522;
589 u64 gprc; 589 u64 gprc;
590 u64 bprc; 590 u64 bprc;
591 u64 mprc; 591 u64 mprc;
592 u64 gptc; 592 u64 gptc;
593 u64 gorcl; 593 u64 gorcl;
594 u64 gorch; 594 u64 gorch;
595 u64 gotcl; 595 u64 gotcl;
596 u64 gotch; 596 u64 gotch;
597 u64 rnbc; 597 u64 rnbc;
598 u64 ruc; 598 u64 ruc;
599 u64 rfc; 599 u64 rfc;
600 u64 roc; 600 u64 roc;
601 u64 rjc; 601 u64 rjc;
602 u64 mgprc; 602 u64 mgprc;
603 u64 mgpdc; 603 u64 mgpdc;
604 u64 mgptc; 604 u64 mgptc;
605 u64 torl; 605 u64 torl;
606 u64 torh; 606 u64 torh;
607 u64 totl; 607 u64 totl;
608 u64 toth; 608 u64 toth;
609 u64 tpr; 609 u64 tpr;
610 u64 tpt; 610 u64 tpt;
611 u64 ptc64; 611 u64 ptc64;
612 u64 ptc127; 612 u64 ptc127;
613 u64 ptc255; 613 u64 ptc255;
614 u64 ptc511; 614 u64 ptc511;
615 u64 ptc1023; 615 u64 ptc1023;
616 u64 ptc1522; 616 u64 ptc1522;
617 u64 mptc; 617 u64 mptc;
618 u64 bptc; 618 u64 bptc;
619 u64 tsctc; 619 u64 tsctc;
620 u64 tsctfc; 620 u64 tsctfc;
621 u64 iac; 621 u64 iac;
622 u64 icrxptc; 622 u64 icrxptc;
623 u64 icrxatc; 623 u64 icrxatc;
624 u64 ictxptc; 624 u64 ictxptc;
625 u64 ictxatc; 625 u64 ictxatc;
626 u64 ictxqec; 626 u64 ictxqec;
627 u64 ictxqmtc; 627 u64 ictxqmtc;
628 u64 icrxdmtc; 628 u64 icrxdmtc;
629 u64 icrxoc; 629 u64 icrxoc;
630 }; 630 };
631 631
632 struct e1000_phy_stats { 632 struct e1000_phy_stats {
633 u32 idle_errors; 633 u32 idle_errors;
634 u32 receive_errors; 634 u32 receive_errors;
635 }; 635 };
636 636
637 struct e1000_host_mng_dhcp_cookie { 637 struct e1000_host_mng_dhcp_cookie {
638 u32 signature; 638 u32 signature;
639 u8 status; 639 u8 status;
640 u8 reserved0; 640 u8 reserved0;
641 u16 vlan_id; 641 u16 vlan_id;
642 u32 reserved1; 642 u32 reserved1;
643 u16 reserved2; 643 u16 reserved2;
644 u8 reserved3; 644 u8 reserved3;
645 u8 checksum; 645 u8 checksum;
646 }; 646 };
647 647
648 /* Host Interface "Rev 1" */ 648 /* Host Interface "Rev 1" */
649 struct e1000_host_command_header { 649 struct e1000_host_command_header {
650 u8 command_id; 650 u8 command_id;
651 u8 command_length; 651 u8 command_length;
652 u8 command_options; 652 u8 command_options;
653 u8 checksum; 653 u8 checksum;
654 }; 654 };
655 655
656 #define E1000_HI_MAX_DATA_LENGTH 252 656 #define E1000_HI_MAX_DATA_LENGTH 252
657 struct e1000_host_command_info { 657 struct e1000_host_command_info {
658 struct e1000_host_command_header comma 658 struct e1000_host_command_header command_header;
659 u8 command_data[E1000_HI_MAX_DATA_LENG 659 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
660 }; 660 };
661 661
662 /* Host Interface "Rev 2" */ 662 /* Host Interface "Rev 2" */
663 struct e1000_host_mng_command_header { 663 struct e1000_host_mng_command_header {
664 u8 command_id; 664 u8 command_id;
665 u8 checksum; 665 u8 checksum;
666 u16 reserved1; 666 u16 reserved1;
667 u16 reserved2; 667 u16 reserved2;
668 u16 command_length; 668 u16 command_length;
669 }; 669 };
670 670
671 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 671 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
672 struct e1000_host_mng_command_info { 672 struct e1000_host_mng_command_info {
673 struct e1000_host_mng_command_header c 673 struct e1000_host_mng_command_header command_header;
674 u8 command_data[E1000_HI_MAX_MNG_DATA_ 674 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
675 }; 675 };
676 676
677 /* Function pointers and static data for the M 677 /* Function pointers and static data for the MAC. */
678 struct e1000_mac_operations { 678 struct e1000_mac_operations {
679 u32 mng_mode_enab; 679 u32 mng_mode_enab;
680 680
681 s32 (*check_for_link)(struct e1000_hw 681 s32 (*check_for_link)(struct e1000_hw *);
682 s32 (*cleanup_led)(struct e1000_hw *) 682 s32 (*cleanup_led)(struct e1000_hw *);
683 void (*clear_hw_cntrs)(struct e1000_hw 683 void (*clear_hw_cntrs)(struct e1000_hw *);
684 s32 (*get_bus_info)(struct e1000_hw * 684 s32 (*get_bus_info)(struct e1000_hw *);
685 s32 (*get_link_up_info)(struct e1000_ 685 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
686 s32 (*led_on)(struct e1000_hw *); 686 s32 (*led_on)(struct e1000_hw *);
687 s32 (*led_off)(struct e1000_hw *); 687 s32 (*led_off)(struct e1000_hw *);
688 void (*mc_addr_list_update)(struct e10 688 void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32,
689 u32); 689 u32);
690 s32 (*reset_hw)(struct e1000_hw *); 690 s32 (*reset_hw)(struct e1000_hw *);
691 s32 (*init_hw)(struct e1000_hw *); 691 s32 (*init_hw)(struct e1000_hw *);
692 s32 (*setup_link)(struct e1000_hw *); 692 s32 (*setup_link)(struct e1000_hw *);
693 s32 (*setup_physical_interface)(struc 693 s32 (*setup_physical_interface)(struct e1000_hw *);
694 }; 694 };
695 695
696 /* Function pointers for the PHY. */ 696 /* Function pointers for the PHY. */
697 struct e1000_phy_operations { 697 struct e1000_phy_operations {
698 s32 (*acquire_phy)(struct e1000_hw *) 698 s32 (*acquire_phy)(struct e1000_hw *);
699 s32 (*check_reset_block)(struct e1000 699 s32 (*check_reset_block)(struct e1000_hw *);
700 s32 (*commit_phy)(struct e1000_hw *); 700 s32 (*commit_phy)(struct e1000_hw *);
701 s32 (*force_speed_duplex)(struct e100 701 s32 (*force_speed_duplex)(struct e1000_hw *);
702 s32 (*get_cfg_done)(struct e1000_hw * 702 s32 (*get_cfg_done)(struct e1000_hw *hw);
703 s32 (*get_cable_length)(struct e1000_ 703 s32 (*get_cable_length)(struct e1000_hw *);
704 s32 (*get_phy_info)(struct e1000_hw * 704 s32 (*get_phy_info)(struct e1000_hw *);
705 s32 (*read_phy_reg)(struct e1000_hw * 705 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
706 void (*release_phy)(struct e1000_hw *) 706 void (*release_phy)(struct e1000_hw *);
707 s32 (*reset_phy)(struct e1000_hw *); 707 s32 (*reset_phy)(struct e1000_hw *);
708 s32 (*set_d0_lplu_state)(struct e1000 708 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
709 s32 (*set_d3_lplu_state)(struct e1000 709 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
710 s32 (*write_phy_reg)(struct e1000_hw 710 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
711 }; 711 };
712 712
713 /* Function pointers for the NVM. */ 713 /* Function pointers for the NVM. */
714 struct e1000_nvm_operations { 714 struct e1000_nvm_operations {
715 s32 (*acquire_nvm)(struct e1000_hw *) 715 s32 (*acquire_nvm)(struct e1000_hw *);
716 s32 (*read_nvm)(struct e1000_hw *, u1 716 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
717 void (*release_nvm)(struct e1000_hw *) 717 void (*release_nvm)(struct e1000_hw *);
718 s32 (*update_nvm)(struct e1000_hw *); 718 s32 (*update_nvm)(struct e1000_hw *);
719 s32 (*valid_led_default)(struct e1000 719 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
720 s32 (*validate_nvm)(struct e1000_hw * 720 s32 (*validate_nvm)(struct e1000_hw *);
721 s32 (*write_nvm)(struct e1000_hw *, u 721 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
722 }; 722 };
723 723
724 struct e1000_mac_info { 724 struct e1000_mac_info {
725 struct e1000_mac_operations ops; 725 struct e1000_mac_operations ops;
726 726
727 u8 addr[6]; 727 u8 addr[6];
728 u8 perm_addr[6]; 728 u8 perm_addr[6];
729 729
730 enum e1000_mac_type type; 730 enum e1000_mac_type type;
731 enum e1000_fc_mode fc; 731 enum e1000_fc_mode fc;
732 enum e1000_fc_mode original_fc; 732 enum e1000_fc_mode original_fc;
733 733
734 u32 collision_delta; 734 u32 collision_delta;
735 u32 ledctl_default; 735 u32 ledctl_default;
736 u32 ledctl_mode1; 736 u32 ledctl_mode1;
737 u32 ledctl_mode2; 737 u32 ledctl_mode2;
738 u32 max_frame_size; 738 u32 max_frame_size;
739 u32 mc_filter_type; 739 u32 mc_filter_type;
740 u32 min_frame_size; 740 u32 min_frame_size;
741 u32 tx_packet_delta; 741 u32 tx_packet_delta;
742 u32 txcw; 742 u32 txcw;
743 743
744 u16 current_ifs_val; 744 u16 current_ifs_val;
745 u16 ifs_max_val; 745 u16 ifs_max_val;
746 u16 ifs_min_val; 746 u16 ifs_min_val;
747 u16 ifs_ratio; 747 u16 ifs_ratio;
748 u16 ifs_step_size; 748 u16 ifs_step_size;
749 u16 mta_reg_count; 749 u16 mta_reg_count;
750 u16 rar_entry_count; 750 u16 rar_entry_count;
751 u16 fc_high_water; 751 u16 fc_high_water;
752 u16 fc_low_water; 752 u16 fc_low_water;
753 u16 fc_pause_time; 753 u16 fc_pause_time;
754 754
755 u8 forced_speed_duplex; 755 u8 forced_speed_duplex;
756 756
757 bool arc_subsystem_valid; 757 bool arc_subsystem_valid;
758 bool autoneg; 758 bool autoneg;
759 bool autoneg_failed; 759 bool autoneg_failed;
760 bool get_link_status; 760 bool get_link_status;
761 bool in_ifs_mode; 761 bool in_ifs_mode;
762 bool serdes_has_link; 762 bool serdes_has_link;
763 bool tx_pkt_filtering; 763 bool tx_pkt_filtering;
764 }; 764 };
765 765
766 struct e1000_phy_info { 766 struct e1000_phy_info {
767 struct e1000_phy_operations ops; 767 struct e1000_phy_operations ops;
768 768
769 enum e1000_phy_type type; 769 enum e1000_phy_type type;
770 770
771 enum e1000_1000t_rx_status local_rx; 771 enum e1000_1000t_rx_status local_rx;
772 enum e1000_1000t_rx_status remote_rx; 772 enum e1000_1000t_rx_status remote_rx;
773 enum e1000_ms_type ms_type; 773 enum e1000_ms_type ms_type;
774 enum e1000_ms_type original_ms_type; 774 enum e1000_ms_type original_ms_type;
775 enum e1000_rev_polarity cable_polarity 775 enum e1000_rev_polarity cable_polarity;
776 enum e1000_smart_speed smart_speed; 776 enum e1000_smart_speed smart_speed;
777 777
778 u32 addr; 778 u32 addr;
779 u32 id; 779 u32 id;
780 u32 reset_delay_us; /* in usec */ 780 u32 reset_delay_us; /* in usec */
781 u32 revision; 781 u32 revision;
782 782
783 u16 autoneg_advertised; 783 u16 autoneg_advertised;
784 u16 autoneg_mask; 784 u16 autoneg_mask;
785 u16 cable_length; 785 u16 cable_length;
786 u16 max_cable_length; 786 u16 max_cable_length;
787 u16 min_cable_length; 787 u16 min_cable_length;
788 788
789 u8 mdix; 789 u8 mdix;
790 790
791 bool disable_polarity_correction; 791 bool disable_polarity_correction;
792 bool is_mdix; 792 bool is_mdix;
793 bool polarity_correction; 793 bool polarity_correction;
794 bool speed_downgraded; 794 bool speed_downgraded;
795 bool wait_for_link; 795 bool wait_for_link;
796 }; 796 };
797 797
798 struct e1000_nvm_info { 798 struct e1000_nvm_info {
799 struct e1000_nvm_operations ops; 799 struct e1000_nvm_operations ops;
800 800
801 enum e1000_nvm_type type; 801 enum e1000_nvm_type type;
802 enum e1000_nvm_override override; 802 enum e1000_nvm_override override;
803 803
804 u32 flash_bank_size; 804 u32 flash_bank_size;
805 u32 flash_base_addr; 805 u32 flash_base_addr;
806 806
807 u16 word_size; 807 u16 word_size;
808 u16 delay_usec; 808 u16 delay_usec;
809 u16 address_bits; 809 u16 address_bits;
810 u16 opcode_bits; 810 u16 opcode_bits;
811 u16 page_size; 811 u16 page_size;
812 }; 812 };
813 813
814 struct e1000_bus_info { 814 struct e1000_bus_info {
815 enum e1000_bus_width width; 815 enum e1000_bus_width width;
816 816
817 u16 func; 817 u16 func;
818 }; 818 };
819 819
820 struct e1000_dev_spec_82571 { 820 struct e1000_dev_spec_82571 {
821 bool laa_is_present; 821 bool laa_is_present;
822 bool alt_mac_addr_is_present; 822 bool alt_mac_addr_is_present;
823 }; 823 };
824 824
825 struct e1000_shadow_ram { 825 struct e1000_shadow_ram {
826 u16 value; 826 u16 value;
827 bool modified; 827 bool modified;
828 }; 828 };
829 829
830 #define E1000_ICH8_SHADOW_RAM_WORDS 830 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
831 831
832 struct e1000_dev_spec_ich8lan { 832 struct e1000_dev_spec_ich8lan {
833 bool kmrn_lock_loss_workaround_enabled 833 bool kmrn_lock_loss_workaround_enabled;
834 struct e1000_shadow_ram shadow_ram[E10 834 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
835 }; 835 };
836 836
837 struct e1000_hw { 837 struct e1000_hw {
838 struct e1000_adapter *adapter; 838 struct e1000_adapter *adapter;
839 839
840 u8 __iomem *hw_addr; 840 u8 __iomem *hw_addr;
841 u8 __iomem *flash_address; 841 u8 __iomem *flash_address;
842 842
843 struct e1000_mac_info mac; 843 struct e1000_mac_info mac;
844 struct e1000_phy_info phy; 844 struct e1000_phy_info phy;
845 struct e1000_nvm_info nvm; 845 struct e1000_nvm_info nvm;
846 struct e1000_bus_info bus; 846 struct e1000_bus_info bus;
847 struct e1000_host_mng_dhcp_cookie mng_ 847 struct e1000_host_mng_dhcp_cookie mng_cookie;
848 848
849 union { 849 union {
850 struct e1000_dev_spec_82571 850 struct e1000_dev_spec_82571 e82571;
851 struct e1000_dev_spec_ich8lan 851 struct e1000_dev_spec_ich8lan ich8lan;
852 } dev_spec; 852 } dev_spec;
853 853
854 enum e1000_media_type media_type; 854 enum e1000_media_type media_type;
855 }; 855 };
856 856
857 #ifdef DEBUG 857 #ifdef DEBUG
858 #define hw_dbg(hw, format, arg...) \ 858 #define hw_dbg(hw, format, arg...) \
859 printk(KERN_DEBUG "%s: " format, e1000 859 printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
860 #else 860 #else
861 static inline int __attribute__ ((format (prin 861 static inline int __attribute__ ((format (printf, 2, 3)))
862 hw_dbg(struct e1000_hw *hw, const char *format 862 hw_dbg(struct e1000_hw *hw, const char *format, ...)
863 { 863 {
864 return 0; 864 return 0;
865 } 865 }
866 #endif 866 #endif
867 867
868 #endif 868 #endif
869 869
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