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1 /* 1 /*
2 * Colour AR M64278(VGA) driver for Video4Linu 2 * Colour AR M64278(VGA) driver for Video4Linux
3 * 3 *
4 * Copyright (C) 2003 Takeo Takahashi <takah 4 * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com>
5 * 5 *
6 * This program is free software; you can redi 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Genera 7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundatio 8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any l 9 * 2 of the License, or (at your option) any later version.
10 * 10 *
11 * Some code is taken from AR driver sample pr 11 * Some code is taken from AR driver sample program for M3T-M32700UT.
12 * 12 *
13 * AR driver sample (M32R SDK): 13 * AR driver sample (M32R SDK):
14 * Copyright (c) 2003 RENESAS TECHNOROGY C 14 * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION
15 * AND RENESAS SOLUTIONS CORPORATION 15 * AND RENESAS SOLUTIONS CORPORATION
16 * All Rights Reserved. 16 * All Rights Reserved.
17 * 17 *
18 * 2003-09-01: Support w3cam by Takeo Takahas 18 * 2003-09-01: Support w3cam by Takeo Takahashi
19 */ 19 */
20 20
21 #include <linux/init.h> 21 #include <linux/init.h>
22 #include <linux/module.h> 22 #include <linux/module.h>
23 #include <linux/delay.h> 23 #include <linux/delay.h>
24 #include <linux/errno.h> 24 #include <linux/errno.h>
25 #include <linux/fs.h> 25 #include <linux/fs.h>
26 #include <linux/kernel.h> 26 #include <linux/kernel.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/mm.h> 28 #include <linux/mm.h>
29 #include <linux/sched.h> 29 #include <linux/sched.h>
30 #include <linux/videodev.h> 30 #include <linux/videodev.h>
31 #include <media/v4l2-common.h> 31 #include <media/v4l2-common.h>
32 #include <media/v4l2-ioctl.h> <<
33 #include <linux/mutex.h> 32 #include <linux/mutex.h>
34 33
35 #include <asm/uaccess.h> 34 #include <asm/uaccess.h>
36 #include <asm/m32r.h> 35 #include <asm/m32r.h>
37 #include <asm/io.h> 36 #include <asm/io.h>
38 #include <asm/dma.h> 37 #include <asm/dma.h>
39 #include <asm/byteorder.h> 38 #include <asm/byteorder.h>
40 39
41 #if 0 40 #if 0
42 #define DEBUG(n, args...) printk(args) 41 #define DEBUG(n, args...) printk(args)
43 #define CHECK_LOST 1 42 #define CHECK_LOST 1
44 #else 43 #else
45 #define DEBUG(n, args...) 44 #define DEBUG(n, args...)
46 #define CHECK_LOST 0 45 #define CHECK_LOST 0
47 #endif 46 #endif
48 47
49 /* 48 /*
50 * USE_INT is always 0, interrupt mode is not 49 * USE_INT is always 0, interrupt mode is not available
51 * on linux due to lack of speed 50 * on linux due to lack of speed
52 */ 51 */
53 #define USE_INT 0 /* Don't modif 52 #define USE_INT 0 /* Don't modify */
54 53
55 #define VERSION "0.03" 54 #define VERSION "0.03"
56 55
57 #define ar_inl(addr) inl((unsigned 56 #define ar_inl(addr) inl((unsigned long)(addr))
58 #define ar_outl(val, addr) outl((unsigned 57 #define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr))
59 58
60 extern struct cpuinfo_m32r boot_cpu_data; 59 extern struct cpuinfo_m32r boot_cpu_data;
61 60
62 /* 61 /*
63 * CCD pixel size 62 * CCD pixel size
64 * Note that M32700UT does not support CI 63 * Note that M32700UT does not support CIF mode, but QVGA is
65 * supported by M32700UT hardware using V 64 * supported by M32700UT hardware using VGA mode of AR LSI.
66 * 65 *
67 * Supported: VGA (Normal mode, Interlac 66 * Supported: VGA (Normal mode, Interlace mode)
68 * QVGA (Always Interlace mode 67 * QVGA (Always Interlace mode of VGA)
69 * 68 *
70 */ 69 */
71 #define AR_WIDTH_VGA 640 70 #define AR_WIDTH_VGA 640
72 #define AR_HEIGHT_VGA 480 71 #define AR_HEIGHT_VGA 480
73 #define AR_WIDTH_QVGA 320 72 #define AR_WIDTH_QVGA 320
74 #define AR_HEIGHT_QVGA 240 73 #define AR_HEIGHT_QVGA 240
75 #define MIN_AR_WIDTH AR_WIDTH_QVGA 74 #define MIN_AR_WIDTH AR_WIDTH_QVGA
76 #define MIN_AR_HEIGHT AR_HEIGHT_QVGA 75 #define MIN_AR_HEIGHT AR_HEIGHT_QVGA
77 #define MAX_AR_WIDTH AR_WIDTH_VGA 76 #define MAX_AR_WIDTH AR_WIDTH_VGA
78 #define MAX_AR_HEIGHT AR_HEIGHT_VGA 77 #define MAX_AR_HEIGHT AR_HEIGHT_VGA
79 78
80 /* bits & bytes per pixel */ 79 /* bits & bytes per pixel */
81 #define AR_BITS_PER_PIXEL 16 80 #define AR_BITS_PER_PIXEL 16
82 #define AR_BYTES_PER_PIXEL (AR_BITS_PER_P 81 #define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8)
83 82
84 /* line buffer size */ 83 /* line buffer size */
85 #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA 84 #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL)
86 #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA 85 #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL)
87 #define MAX_AR_LINE_BYTES AR_LINE_BYTES_ 86 #define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA
88 87
89 /* frame size & type */ 88 /* frame size & type */
90 #define AR_FRAME_BYTES_VGA \ 89 #define AR_FRAME_BYTES_VGA \
91 (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYT 90 (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL)
92 #define AR_FRAME_BYTES_QVGA \ 91 #define AR_FRAME_BYTES_QVGA \
93 (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_B 92 (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL)
94 #define MAX_AR_FRAME_BYTES \ 93 #define MAX_AR_FRAME_BYTES \
95 (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYT 94 (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL)
96 95
97 #define AR_MAX_FRAME 15 96 #define AR_MAX_FRAME 15
98 97
99 /* capture size */ 98 /* capture size */
100 #define AR_SIZE_VGA 0 99 #define AR_SIZE_VGA 0
101 #define AR_SIZE_QVGA 1 100 #define AR_SIZE_QVGA 1
102 101
103 /* capture mode */ 102 /* capture mode */
104 #define AR_MODE_INTERLACE 0 103 #define AR_MODE_INTERLACE 0
105 #define AR_MODE_NORMAL 1 104 #define AR_MODE_NORMAL 1
106 105
107 struct ar_device { 106 struct ar_device {
108 struct video_device *vdev; 107 struct video_device *vdev;
109 unsigned int start_capture; /* dua 108 unsigned int start_capture; /* duaring capture in INT. mode. */
110 #if USE_INT 109 #if USE_INT
111 unsigned char *line_buff; /* DMA 110 unsigned char *line_buff; /* DMA line buffer */
112 #endif 111 #endif
113 unsigned char *frame[MAX_AR_HEIGHT]; 112 unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */
114 short size; /* cap 113 short size; /* capture size */
115 short mode; /* cap 114 short mode; /* capture mode */
116 int width, height; 115 int width, height;
117 int frame_bytes, line_bytes; 116 int frame_bytes, line_bytes;
118 wait_queue_head_t wait; 117 wait_queue_head_t wait;
119 unsigned long in_use; <<
120 struct mutex lock; 118 struct mutex lock;
121 }; 119 };
122 120
123 static int video_nr = -1; /* video devic 121 static int video_nr = -1; /* video device number (first free) */
124 static unsigned char yuv[MAX_AR_FRAME_BYTES 122 static unsigned char yuv[MAX_AR_FRAME_BYTES];
125 123
126 /* module parameters */ 124 /* module parameters */
127 /* default frequency */ 125 /* default frequency */
128 #define DEFAULT_FREQ 50 /* 50 or 75 (M 126 #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */
129 static int freq = DEFAULT_FREQ; /* BCLK: avail 127 static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */
130 static int vga; /* default mod !! 128 static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */
131 static int vga_interlace; /* 0 is normal !! 129 static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */
132 module_param(freq, int, 0); 130 module_param(freq, int, 0);
133 module_param(vga, int, 0); 131 module_param(vga, int, 0);
134 module_param(vga_interlace, int, 0); 132 module_param(vga_interlace, int, 0);
135 133
136 static int ar_initialize(struct video_device * 134 static int ar_initialize(struct video_device *dev);
137 135
138 static inline void wait_for_vsync(void) 136 static inline void wait_for_vsync(void)
139 { 137 {
140 while (ar_inl(ARVCR0) & ARVCR0_VDS) 138 while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */
141 cpu_relax(); 139 cpu_relax();
142 while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) 140 while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */
143 cpu_relax(); 141 cpu_relax();
144 } 142 }
145 143
146 static inline void wait_acknowledge(void) 144 static inline void wait_acknowledge(void)
147 { 145 {
148 int i; 146 int i;
149 147
150 for (i = 0; i < 1000; i++) 148 for (i = 0; i < 1000; i++)
151 cpu_relax(); 149 cpu_relax();
152 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_N 150 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK)
153 cpu_relax(); 151 cpu_relax();
154 } 152 }
155 153
156 /********************************************* 154 /*******************************************************************
157 * I2C functions 155 * I2C functions
158 ********************************************* 156 *******************************************************************/
159 void iic(int n, unsigned long addr, unsigned l 157 void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2,
160 unsigned long data3) 158 unsigned long data3)
161 { 159 {
162 int i; 160 int i;
163 161
164 /* Slave Address */ 162 /* Slave Address */
165 ar_outl(addr, PLDI2CDATA); 163 ar_outl(addr, PLDI2CDATA);
166 wait_for_vsync(); 164 wait_for_vsync();
167 165
168 /* Start */ 166 /* Start */
169 ar_outl(1, PLDI2CCND); 167 ar_outl(1, PLDI2CCND);
170 wait_acknowledge(); 168 wait_acknowledge();
171 169
172 /* Transfer data 1 */ 170 /* Transfer data 1 */
173 ar_outl(data1, PLDI2CDATA); 171 ar_outl(data1, PLDI2CDATA);
174 wait_for_vsync(); 172 wait_for_vsync();
175 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); 173 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
176 wait_acknowledge(); 174 wait_acknowledge();
177 175
178 /* Transfer data 2 */ 176 /* Transfer data 2 */
179 ar_outl(data2, PLDI2CDATA); 177 ar_outl(data2, PLDI2CDATA);
180 wait_for_vsync(); 178 wait_for_vsync();
181 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); 179 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
182 wait_acknowledge(); 180 wait_acknowledge();
183 181
184 if (n == 3) { 182 if (n == 3) {
185 /* Transfer data 3 */ 183 /* Transfer data 3 */
186 ar_outl(data3, PLDI2CDATA); 184 ar_outl(data3, PLDI2CDATA);
187 wait_for_vsync(); 185 wait_for_vsync();
188 ar_outl(PLDI2CSTEN_STEN, PLDI2 186 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
189 wait_acknowledge(); 187 wait_acknowledge();
190 } 188 }
191 189
192 /* Stop */ 190 /* Stop */
193 for (i = 0; i < 100; i++) 191 for (i = 0; i < 100; i++)
194 cpu_relax(); 192 cpu_relax();
195 ar_outl(2, PLDI2CCND); 193 ar_outl(2, PLDI2CCND);
196 ar_outl(2, PLDI2CCND); 194 ar_outl(2, PLDI2CCND);
197 195
198 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_B 196 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB)
199 cpu_relax(); 197 cpu_relax();
200 } 198 }
201 199
202 200
203 void init_iic(void) 201 void init_iic(void)
204 { 202 {
205 DEBUG(1, "init_iic:\n"); 203 DEBUG(1, "init_iic:\n");
206 204
207 /* 205 /*
208 * ICU Setting (iic) 206 * ICU Setting (iic)
209 */ 207 */
210 /* I2C Setting */ 208 /* I2C Setting */
211 ar_outl(0x0, PLDI2CCR); /* I2C 209 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
212 ar_outl(0x0300, PLDI2CMOD); /* I2C 210 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
213 ar_outl(0x1, PLDI2CACK); /* I2C 211 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
214 212
215 /* I2C CLK */ 213 /* I2C CLK */
216 /* 50MH-100k */ 214 /* 50MH-100k */
217 if (freq == 75) { 215 if (freq == 75) {
218 ar_outl(369, PLDI2CFREQ); 216 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
219 } else if (freq == 50) { 217 } else if (freq == 50) {
220 ar_outl(244, PLDI2CFREQ); 218 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
221 } else { 219 } else {
222 ar_outl(244, PLDI2CFREQ); 220 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
223 } 221 }
224 ar_outl(0x1, PLDI2CCR); /* I2C 222 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
225 } 223 }
226 224
227 /********************************************* 225 /**************************************************************************
228 * 226 *
229 * Video4Linux Interface functions 227 * Video4Linux Interface functions
230 * 228 *
231 ********************************************* 229 **************************************************************************/
232 230
233 static inline void disable_dma(void) 231 static inline void disable_dma(void)
234 { 232 {
235 ar_outl(0x8000, M32R_DMAEN_PORTL); 233 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
236 } 234 }
237 235
238 static inline void enable_dma(void) 236 static inline void enable_dma(void)
239 { 237 {
240 ar_outl(0x8080, M32R_DMAEN_PORTL); 238 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
241 } 239 }
242 240
243 static inline void clear_dma_status(void) 241 static inline void clear_dma_status(void)
244 { 242 {
245 ar_outl(0x8000, M32R_DMAEDET_PORTL); 243 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
246 } 244 }
247 245
248 static inline void wait_for_vertical_sync(int 246 static inline void wait_for_vertical_sync(int exp_line)
249 { 247 {
250 #if CHECK_LOST 248 #if CHECK_LOST
251 int tmout = 10000; /* FIXME */ 249 int tmout = 10000; /* FIXME */
252 int l; 250 int l;
253 251
254 /* 252 /*
255 * check HCOUNT because we cannot chec 253 * check HCOUNT because we cannot check vertical sync.
256 */ 254 */
257 for (; tmout >= 0; tmout--) { 255 for (; tmout >= 0; tmout--) {
258 l = ar_inl(ARVHCOUNT); 256 l = ar_inl(ARVHCOUNT);
259 if (l == exp_line) 257 if (l == exp_line)
260 break; 258 break;
261 } 259 }
262 if (tmout < 0) 260 if (tmout < 0)
263 printk("arv: lost %d -> %d\n", 261 printk("arv: lost %d -> %d\n", exp_line, l);
264 #else 262 #else
265 while (ar_inl(ARVHCOUNT) != exp_line) 263 while (ar_inl(ARVHCOUNT) != exp_line)
266 cpu_relax(); 264 cpu_relax();
267 #endif 265 #endif
268 } 266 }
269 267
270 static ssize_t ar_read(struct file *file, char 268 static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos)
271 { 269 {
272 struct video_device *v = video_devdata 270 struct video_device *v = video_devdata(file);
273 struct ar_device *ar = video_get_drvda !! 271 struct ar_device *ar = v->priv;
274 long ret = ar->frame_bytes; 272 long ret = ar->frame_bytes; /* return read bytes */
275 unsigned long arvcr1 = 0; 273 unsigned long arvcr1 = 0;
276 unsigned long flags; 274 unsigned long flags;
277 unsigned char *p; 275 unsigned char *p;
278 int h, w; 276 int h, w;
279 unsigned char *py, *pu, *pv; 277 unsigned char *py, *pu, *pv;
280 #if ! USE_INT 278 #if ! USE_INT
281 int l; 279 int l;
282 #endif 280 #endif
283 281
284 DEBUG(1, "ar_read()\n"); 282 DEBUG(1, "ar_read()\n");
285 283
286 if (ar->size == AR_SIZE_QVGA) 284 if (ar->size == AR_SIZE_QVGA)
287 arvcr1 |= ARVCR1_QVGA; 285 arvcr1 |= ARVCR1_QVGA;
288 if (ar->mode == AR_MODE_NORMAL) 286 if (ar->mode == AR_MODE_NORMAL)
289 arvcr1 |= ARVCR1_NORMAL; 287 arvcr1 |= ARVCR1_NORMAL;
290 288
291 mutex_lock(&ar->lock); 289 mutex_lock(&ar->lock);
292 290
293 #if USE_INT 291 #if USE_INT
294 local_irq_save(flags); 292 local_irq_save(flags);
295 disable_dma(); 293 disable_dma();
296 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL 294 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
297 ar_outl(0x01000000, M32R_DMA0CR1_PORTL 295 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
298 296
299 /* set AR FIFO address as source(BSEL5 297 /* set AR FIFO address as source(BSEL5) */
300 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); 298 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
301 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); 299 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
302 ar_outl(ar->line_buff, M32R_DMA0CDA_PO 300 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
303 ar_outl(ar->line_buff, M32R_DMA0RDA_PO 301 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
304 ar_outl(ar->line_bytes, M32R_DMA0CBCUT 302 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
305 ar_outl(ar->line_bytes, M32R_DMA0RBCUT 303 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
306 304
307 /* 305 /*
308 * Okey , kicks AR LSI to invoke an in 306 * Okey , kicks AR LSI to invoke an interrupt
309 */ 307 */
310 ar->start_capture = 0; 308 ar->start_capture = 0;
311 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); 309 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
312 local_irq_restore(flags); 310 local_irq_restore(flags);
313 /* .... AR interrupts .... */ 311 /* .... AR interrupts .... */
314 interruptible_sleep_on(&ar->wait); 312 interruptible_sleep_on(&ar->wait);
315 if (signal_pending(current)) { 313 if (signal_pending(current)) {
316 printk("arv: interrupted while 314 printk("arv: interrupted while get frame data.\n");
317 ret = -EINTR; 315 ret = -EINTR;
318 goto out_up; 316 goto out_up;
319 } 317 }
320 #else /* ! USE_INT */ 318 #else /* ! USE_INT */
321 /* polling */ 319 /* polling */
322 ar_outl(arvcr1, ARVCR1); 320 ar_outl(arvcr1, ARVCR1);
323 disable_dma(); 321 disable_dma();
324 ar_outl(0x8000, M32R_DMAEDET_PORTL); 322 ar_outl(0x8000, M32R_DMAEDET_PORTL);
325 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL 323 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
326 ar_outl(0x01000000, M32R_DMA0CR1_PORTL 324 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
327 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); 325 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
328 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); 326 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
329 ar_outl(ar->line_bytes, M32R_DMA0CBCUT 327 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
330 ar_outl(ar->line_bytes, M32R_DMA0RBCUT 328 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
331 329
332 local_irq_save(flags); 330 local_irq_save(flags);
333 while (ar_inl(ARVHCOUNT) != 0) 331 while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */
334 cpu_relax(); 332 cpu_relax();
335 if (ar->mode == AR_MODE_INTERLACE && a 333 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
336 for (h = 0; h < ar->height; h+ 334 for (h = 0; h < ar->height; h++) {
337 wait_for_vertical_sync 335 wait_for_vertical_sync(h);
338 if (h < (AR_HEIGHT_VGA 336 if (h < (AR_HEIGHT_VGA/2))
339 l = h << 1; 337 l = h << 1;
340 else 338 else
341 l = (((h - (AR 339 l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1);
342 ar_outl(virt_to_phys(a 340 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
343 enable_dma(); 341 enable_dma();
344 while (!(ar_inl(M32R_D 342 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
345 cpu_relax(); 343 cpu_relax();
346 disable_dma(); 344 disable_dma();
347 clear_dma_status(); 345 clear_dma_status();
348 ar_outl(0xa0861300, M3 346 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
349 } 347 }
350 } else { 348 } else {
351 for (h = 0; h < ar->height; h+ 349 for (h = 0; h < ar->height; h++) {
352 wait_for_vertical_sync 350 wait_for_vertical_sync(h);
353 ar_outl(virt_to_phys(a 351 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
354 enable_dma(); 352 enable_dma();
355 while (!(ar_inl(M32R_D 353 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
356 cpu_relax(); 354 cpu_relax();
357 disable_dma(); 355 disable_dma();
358 clear_dma_status(); 356 clear_dma_status();
359 ar_outl(0xa0861300, M3 357 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
360 } 358 }
361 } 359 }
362 local_irq_restore(flags); 360 local_irq_restore(flags);
363 #endif /* ! USE_INT */ 361 #endif /* ! USE_INT */
364 362
365 /* 363 /*
366 * convert YUV422 to YUV422P 364 * convert YUV422 to YUV422P
367 * +--------------------+ 365 * +--------------------+
368 * | Y0,Y1,... | 366 * | Y0,Y1,... |
369 * | ..............Yn | 367 * | ..............Yn |
370 * +--------------------+ 368 * +--------------------+
371 * | U0,U1,........Un | 369 * | U0,U1,........Un |
372 * +--------------------+ 370 * +--------------------+
373 * | V0,V1,........Vn | 371 * | V0,V1,........Vn |
374 * +--------------------+ 372 * +--------------------+
375 */ 373 */
376 py = yuv; 374 py = yuv;
377 pu = py + (ar->frame_bytes / 2); 375 pu = py + (ar->frame_bytes / 2);
378 pv = pu + (ar->frame_bytes / 4); 376 pv = pu + (ar->frame_bytes / 4);
379 for (h = 0; h < ar->height; h++) { 377 for (h = 0; h < ar->height; h++) {
380 p = ar->frame[h]; 378 p = ar->frame[h];
381 for (w = 0; w < ar->line_bytes 379 for (w = 0; w < ar->line_bytes; w += 4) {
382 *py++ = *p++; 380 *py++ = *p++;
383 *pu++ = *p++; 381 *pu++ = *p++;
384 *py++ = *p++; 382 *py++ = *p++;
385 *pv++ = *p++; 383 *pv++ = *p++;
386 } 384 }
387 } 385 }
388 if (copy_to_user(buf, yuv, ar->frame_b 386 if (copy_to_user(buf, yuv, ar->frame_bytes)) {
389 printk("arv: failed while copy 387 printk("arv: failed while copy_to_user yuv.\n");
390 ret = -EFAULT; 388 ret = -EFAULT;
391 goto out_up; 389 goto out_up;
392 } 390 }
393 DEBUG(1, "ret = %d\n", ret); 391 DEBUG(1, "ret = %d\n", ret);
394 out_up: 392 out_up:
395 mutex_unlock(&ar->lock); 393 mutex_unlock(&ar->lock);
396 return ret; 394 return ret;
397 } 395 }
398 396
399 static long ar_do_ioctl(struct file *file, uns !! 397 static int ar_do_ioctl(struct inode *inode, struct file *file,
>> 398 unsigned int cmd, void *arg)
400 { 399 {
401 struct video_device *dev = video_devda 400 struct video_device *dev = video_devdata(file);
402 struct ar_device *ar = video_get_drvda !! 401 struct ar_device *ar = dev->priv;
403 402
404 DEBUG(1, "ar_ioctl()\n"); 403 DEBUG(1, "ar_ioctl()\n");
405 switch(cmd) { 404 switch(cmd) {
406 case VIDIOCGCAP: 405 case VIDIOCGCAP:
407 { 406 {
408 struct video_capability *b = a 407 struct video_capability *b = arg;
409 DEBUG(1, "VIDIOCGCAP:\n"); 408 DEBUG(1, "VIDIOCGCAP:\n");
410 strcpy(b->name, ar->vdev->name 409 strcpy(b->name, ar->vdev->name);
411 b->type = VID_TYPE_CAPTURE; 410 b->type = VID_TYPE_CAPTURE;
412 b->channels = 0; 411 b->channels = 0;
413 b->audios = 0; 412 b->audios = 0;
414 b->maxwidth = MAX_AR_WIDTH; 413 b->maxwidth = MAX_AR_WIDTH;
415 b->maxheight = MAX_AR_HEIGHT; 414 b->maxheight = MAX_AR_HEIGHT;
416 b->minwidth = MIN_AR_WIDTH; 415 b->minwidth = MIN_AR_WIDTH;
417 b->minheight = MIN_AR_HEIGHT; 416 b->minheight = MIN_AR_HEIGHT;
418 return 0; 417 return 0;
419 } 418 }
420 case VIDIOCGCHAN: 419 case VIDIOCGCHAN:
421 DEBUG(1, "VIDIOCGCHAN:\n"); 420 DEBUG(1, "VIDIOCGCHAN:\n");
422 return 0; 421 return 0;
423 case VIDIOCSCHAN: 422 case VIDIOCSCHAN:
424 DEBUG(1, "VIDIOCSCHAN:\n"); 423 DEBUG(1, "VIDIOCSCHAN:\n");
425 return 0; 424 return 0;
426 case VIDIOCGTUNER: 425 case VIDIOCGTUNER:
427 DEBUG(1, "VIDIOCGTUNER:\n"); 426 DEBUG(1, "VIDIOCGTUNER:\n");
428 return 0; 427 return 0;
429 case VIDIOCSTUNER: 428 case VIDIOCSTUNER:
430 DEBUG(1, "VIDIOCSTUNER:\n"); 429 DEBUG(1, "VIDIOCSTUNER:\n");
431 return 0; 430 return 0;
432 case VIDIOCGPICT: 431 case VIDIOCGPICT:
433 DEBUG(1, "VIDIOCGPICT:\n"); 432 DEBUG(1, "VIDIOCGPICT:\n");
434 return 0; 433 return 0;
435 case VIDIOCSPICT: 434 case VIDIOCSPICT:
436 DEBUG(1, "VIDIOCSPICT:\n"); 435 DEBUG(1, "VIDIOCSPICT:\n");
437 return 0; 436 return 0;
438 case VIDIOCCAPTURE: 437 case VIDIOCCAPTURE:
439 DEBUG(1, "VIDIOCCAPTURE:\n"); 438 DEBUG(1, "VIDIOCCAPTURE:\n");
440 return -EINVAL; 439 return -EINVAL;
441 case VIDIOCGWIN: 440 case VIDIOCGWIN:
442 { 441 {
443 struct video_window *w = arg; 442 struct video_window *w = arg;
444 DEBUG(1, "VIDIOCGWIN:\n"); 443 DEBUG(1, "VIDIOCGWIN:\n");
445 memset(w, 0, sizeof(*w)); 444 memset(w, 0, sizeof(*w));
446 w->width = ar->width; 445 w->width = ar->width;
447 w->height = ar->height; 446 w->height = ar->height;
448 return 0; 447 return 0;
449 } 448 }
450 case VIDIOCSWIN: 449 case VIDIOCSWIN:
451 { 450 {
452 struct video_window *w = arg; 451 struct video_window *w = arg;
453 DEBUG(1, "VIDIOCSWIN:\n"); 452 DEBUG(1, "VIDIOCSWIN:\n");
454 if ((w->width != AR_WIDTH_VGA 453 if ((w->width != AR_WIDTH_VGA || w->height != AR_HEIGHT_VGA) &&
455 (w->width != AR_WIDTH_QVGA 454 (w->width != AR_WIDTH_QVGA || w->height != AR_HEIGHT_QVGA))
456 return -EINVAL 455 return -EINVAL;
457 456
458 mutex_lock(&ar->lock); 457 mutex_lock(&ar->lock);
459 ar->width = w->width; 458 ar->width = w->width;
460 ar->height = w->height; 459 ar->height = w->height;
461 if (ar->width == AR_WIDTH_VGA) 460 if (ar->width == AR_WIDTH_VGA) {
462 ar->size = AR_SIZE_VGA 461 ar->size = AR_SIZE_VGA;
463 ar->frame_bytes = AR_F 462 ar->frame_bytes = AR_FRAME_BYTES_VGA;
464 ar->line_bytes = AR_LI 463 ar->line_bytes = AR_LINE_BYTES_VGA;
465 if (vga_interlace) 464 if (vga_interlace)
466 ar->mode = AR_ 465 ar->mode = AR_MODE_INTERLACE;
467 else 466 else
468 ar->mode = AR_ 467 ar->mode = AR_MODE_NORMAL;
469 } else { 468 } else {
470 ar->size = AR_SIZE_QVG 469 ar->size = AR_SIZE_QVGA;
471 ar->frame_bytes = AR_F 470 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
472 ar->line_bytes = AR_LI 471 ar->line_bytes = AR_LINE_BYTES_QVGA;
473 ar->mode = AR_MODE_INT 472 ar->mode = AR_MODE_INTERLACE;
474 } 473 }
475 mutex_unlock(&ar->lock); 474 mutex_unlock(&ar->lock);
476 return 0; 475 return 0;
477 } 476 }
478 case VIDIOCGFBUF: 477 case VIDIOCGFBUF:
479 DEBUG(1, "VIDIOCGFBUF:\n"); 478 DEBUG(1, "VIDIOCGFBUF:\n");
480 return -EINVAL; 479 return -EINVAL;
481 case VIDIOCSFBUF: 480 case VIDIOCSFBUF:
482 DEBUG(1, "VIDIOCSFBUF:\n"); 481 DEBUG(1, "VIDIOCSFBUF:\n");
483 return -EINVAL; 482 return -EINVAL;
484 case VIDIOCKEY: 483 case VIDIOCKEY:
485 DEBUG(1, "VIDIOCKEY:\n"); 484 DEBUG(1, "VIDIOCKEY:\n");
486 return 0; 485 return 0;
487 case VIDIOCGFREQ: 486 case VIDIOCGFREQ:
488 DEBUG(1, "VIDIOCGFREQ:\n"); 487 DEBUG(1, "VIDIOCGFREQ:\n");
489 return -EINVAL; 488 return -EINVAL;
490 case VIDIOCSFREQ: 489 case VIDIOCSFREQ:
491 DEBUG(1, "VIDIOCSFREQ:\n"); 490 DEBUG(1, "VIDIOCSFREQ:\n");
492 return -EINVAL; 491 return -EINVAL;
493 case VIDIOCGAUDIO: 492 case VIDIOCGAUDIO:
494 DEBUG(1, "VIDIOCGAUDIO:\n"); 493 DEBUG(1, "VIDIOCGAUDIO:\n");
495 return -EINVAL; 494 return -EINVAL;
496 case VIDIOCSAUDIO: 495 case VIDIOCSAUDIO:
497 DEBUG(1, "VIDIOCSAUDIO:\n"); 496 DEBUG(1, "VIDIOCSAUDIO:\n");
498 return -EINVAL; 497 return -EINVAL;
499 case VIDIOCSYNC: 498 case VIDIOCSYNC:
500 DEBUG(1, "VIDIOCSYNC:\n"); 499 DEBUG(1, "VIDIOCSYNC:\n");
501 return -EINVAL; 500 return -EINVAL;
502 case VIDIOCMCAPTURE: 501 case VIDIOCMCAPTURE:
503 DEBUG(1, "VIDIOCMCAPTURE:\n"); 502 DEBUG(1, "VIDIOCMCAPTURE:\n");
504 return -EINVAL; 503 return -EINVAL;
505 case VIDIOCGMBUF: 504 case VIDIOCGMBUF:
506 DEBUG(1, "VIDIOCGMBUF:\n"); 505 DEBUG(1, "VIDIOCGMBUF:\n");
507 return -EINVAL; 506 return -EINVAL;
508 case VIDIOCGUNIT: 507 case VIDIOCGUNIT:
509 DEBUG(1, "VIDIOCGUNIT:\n"); 508 DEBUG(1, "VIDIOCGUNIT:\n");
510 return -EINVAL; 509 return -EINVAL;
511 case VIDIOCGCAPTURE: 510 case VIDIOCGCAPTURE:
512 DEBUG(1, "VIDIOCGCAPTURE:\n"); 511 DEBUG(1, "VIDIOCGCAPTURE:\n");
513 return -EINVAL; 512 return -EINVAL;
514 case VIDIOCSCAPTURE: 513 case VIDIOCSCAPTURE:
515 DEBUG(1, "VIDIOCSCAPTURE:\n"); 514 DEBUG(1, "VIDIOCSCAPTURE:\n");
516 return -EINVAL; 515 return -EINVAL;
517 case VIDIOCSPLAYMODE: 516 case VIDIOCSPLAYMODE:
518 DEBUG(1, "VIDIOCSPLAYMODE:\n") 517 DEBUG(1, "VIDIOCSPLAYMODE:\n");
519 return -EINVAL; 518 return -EINVAL;
520 case VIDIOCSWRITEMODE: 519 case VIDIOCSWRITEMODE:
521 DEBUG(1, "VIDIOCSWRITEMODE:\n" 520 DEBUG(1, "VIDIOCSWRITEMODE:\n");
522 return -EINVAL; 521 return -EINVAL;
523 case VIDIOCGPLAYINFO: 522 case VIDIOCGPLAYINFO:
524 DEBUG(1, "VIDIOCGPLAYINFO:\n") 523 DEBUG(1, "VIDIOCGPLAYINFO:\n");
525 return -EINVAL; 524 return -EINVAL;
526 case VIDIOCSMICROCODE: 525 case VIDIOCSMICROCODE:
527 DEBUG(1, "VIDIOCSMICROCODE:\n" 526 DEBUG(1, "VIDIOCSMICROCODE:\n");
528 return -EINVAL; 527 return -EINVAL;
529 case VIDIOCGVBIFMT: 528 case VIDIOCGVBIFMT:
530 DEBUG(1, "VIDIOCGVBIFMT:\n"); 529 DEBUG(1, "VIDIOCGVBIFMT:\n");
531 return -EINVAL; 530 return -EINVAL;
532 case VIDIOCSVBIFMT: 531 case VIDIOCSVBIFMT:
533 DEBUG(1, "VIDIOCSVBIFMT:\n"); 532 DEBUG(1, "VIDIOCSVBIFMT:\n");
534 return -EINVAL; 533 return -EINVAL;
535 default: 534 default:
536 DEBUG(1, "Unknown ioctl(0x%08x 535 DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd);
537 return -ENOIOCTLCMD; 536 return -ENOIOCTLCMD;
538 } 537 }
539 return 0; 538 return 0;
540 } 539 }
541 540
542 static long ar_ioctl(struct file *file, unsign !! 541 static int ar_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
543 unsigned long arg) 542 unsigned long arg)
544 { 543 {
545 return video_usercopy(file, cmd, arg, !! 544 return video_usercopy(inode, file, cmd, arg, ar_do_ioctl);
546 } 545 }
547 546
548 #if USE_INT 547 #if USE_INT
549 /* 548 /*
550 * Interrupt handler 549 * Interrupt handler
551 */ 550 */
552 static void ar_interrupt(int irq, void *dev) 551 static void ar_interrupt(int irq, void *dev)
553 { 552 {
554 struct ar_device *ar = dev; 553 struct ar_device *ar = dev;
555 unsigned int line_count; 554 unsigned int line_count;
556 unsigned int line_number; 555 unsigned int line_number;
557 unsigned int arvcr1; 556 unsigned int arvcr1;
558 557
559 line_count = ar_inl(ARVHCOUNT); 558 line_count = ar_inl(ARVHCOUNT); /* line number */
560 if (ar->mode == AR_MODE_INTERLACE && a 559 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
561 /* operations for interlace mo 560 /* operations for interlace mode */
562 if ( line_count < (AR_HEIGHT_V 561 if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */
563 line_number = (line_co 562 line_number = (line_count << 1);
564 else 563 else /* odd line */
565 line_number = 564 line_number =
566 (((line_count - (AR_HE 565 (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1);
567 } else { 566 } else {
568 line_number = line_count; 567 line_number = line_count;
569 } 568 }
570 569
571 if (line_number == 0) { 570 if (line_number == 0) {
572 /* 571 /*
573 * It is an interrupt for line 572 * It is an interrupt for line 0.
574 * we have to start capture. 573 * we have to start capture.
575 */ 574 */
576 disable_dma(); 575 disable_dma();
577 #if 0 576 #if 0
578 ar_outl(ar->line_buff, M32R_DM 577 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */
579 #endif 578 #endif
580 memcpy(ar->frame[0], ar->line_ 579 memcpy(ar->frame[0], ar->line_buff, ar->line_bytes);
581 #if 0 580 #if 0
582 ar_outl(0xa1861300, M32R_DMA0C 581 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
583 #endif 582 #endif
584 enable_dma(); 583 enable_dma();
585 ar->start_capture = 1; 584 ar->start_capture = 1; /* during capture */
586 return; 585 return;
587 } 586 }
588 587
589 if (ar->start_capture == 1 && line_num 588 if (ar->start_capture == 1 && line_number <= (ar->height - 1)) {
590 disable_dma(); 589 disable_dma();
591 memcpy(ar->frame[line_number], 590 memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes);
592 591
593 /* 592 /*
594 * if captured all line of a f 593 * if captured all line of a frame, disable AR interrupt
595 * and wake a process up. 594 * and wake a process up.
596 */ 595 */
597 if (line_number == (ar->height 596 if (line_number == (ar->height - 1)) { /* end of line */
598 597
599 ar->start_capture = 0; 598 ar->start_capture = 0;
600 599
601 /* disable AR interrup 600 /* disable AR interrupt request */
602 arvcr1 = ar_inl(ARVCR1 601 arvcr1 = ar_inl(ARVCR1);
603 arvcr1 &= ~ARVCR1_HIEN 602 arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */
604 ar_outl(arvcr1, ARVCR1 603 ar_outl(arvcr1, ARVCR1); /* disable */
605 wake_up_interruptible( 604 wake_up_interruptible(&ar->wait);
606 } else { 605 } else {
607 #if 0 606 #if 0
608 ar_outl(ar->line_buff, 607 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL);
609 ar_outl(0xa1861300, M3 608 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
610 #endif 609 #endif
611 enable_dma(); 610 enable_dma();
612 } 611 }
613 } 612 }
614 } 613 }
615 #endif 614 #endif
616 615
617 /* 616 /*
618 * ar_initialize() 617 * ar_initialize()
619 * ar_initialize() is called by video_reg 618 * ar_initialize() is called by video_register_device() and
620 * initializes AR LSI and peripherals. 619 * initializes AR LSI and peripherals.
621 * 620 *
622 * -1 is returned in all failures. 621 * -1 is returned in all failures.
623 * 0 is returned in success. 622 * 0 is returned in success.
624 * 623 *
625 */ 624 */
626 static int ar_initialize(struct video_device * 625 static int ar_initialize(struct video_device *dev)
627 { 626 {
628 struct ar_device *ar = video_get_drvda !! 627 struct ar_device *ar = dev->priv;
629 unsigned long cr = 0; 628 unsigned long cr = 0;
630 int i,found=0; 629 int i,found=0;
631 630
632 DEBUG(1, "ar_initialize:\n"); 631 DEBUG(1, "ar_initialize:\n");
633 632
634 /* 633 /*
635 * initialize AR LSI 634 * initialize AR LSI
636 */ 635 */
637 ar_outl(0, ARVCR0); /* ass 636 ar_outl(0, ARVCR0); /* assert reset of AR LSI */
638 for (i = 0; i < 0x18; i++) /* wai 637 for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */
639 cpu_relax(); 638 cpu_relax();
640 ar_outl(ARVCR0_RST, ARVCR0); /* neg 639 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
641 for (i = 0; i < 0x40d; i++) /* wai 640 for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */
642 cpu_relax(); 641 cpu_relax();
643 642
644 /* AR uses INT3 of CPU as interrupt pi 643 /* AR uses INT3 of CPU as interrupt pin. */
645 ar_outl(ARINTSEL_INT3, ARINTSEL); 644 ar_outl(ARINTSEL_INT3, ARINTSEL);
646 645
647 if (ar->size == AR_SIZE_QVGA) 646 if (ar->size == AR_SIZE_QVGA)
648 cr |= ARVCR1_QVGA; 647 cr |= ARVCR1_QVGA;
649 if (ar->mode == AR_MODE_NORMAL) 648 if (ar->mode == AR_MODE_NORMAL)
650 cr |= ARVCR1_NORMAL; 649 cr |= ARVCR1_NORMAL;
651 ar_outl(cr, ARVCR1); 650 ar_outl(cr, ARVCR1);
652 651
653 /* 652 /*
654 * Initialize IIC so that CPU can comm 653 * Initialize IIC so that CPU can communicate with AR LSI,
655 * and send boot commands to AR LSI. 654 * and send boot commands to AR LSI.
656 */ 655 */
657 init_iic(); 656 init_iic();
658 657
659 for (i = 0; i < 0x100000; i++) { 658 for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */
660 if ((ar_inl(ARVCR0) & ARVCR0_V 659 if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */
661 found = 1; 660 found = 1;
662 break; 661 break;
663 } 662 }
664 } 663 }
665 664
666 if (found == 0) 665 if (found == 0)
667 return -ENODEV; 666 return -ENODEV;
668 667
669 printk("arv: Initializing "); 668 printk("arv: Initializing ");
670 669
671 iic(2,0x78,0x11,0x01,0x00); /* sta 670 iic(2,0x78,0x11,0x01,0x00); /* start */
672 iic(3,0x78,0x12,0x00,0x06); 671 iic(3,0x78,0x12,0x00,0x06);
673 iic(3,0x78,0x12,0x12,0x30); 672 iic(3,0x78,0x12,0x12,0x30);
674 iic(3,0x78,0x12,0x15,0x58); 673 iic(3,0x78,0x12,0x15,0x58);
675 iic(3,0x78,0x12,0x17,0x30); 674 iic(3,0x78,0x12,0x17,0x30);
676 printk("."); 675 printk(".");
677 iic(3,0x78,0x12,0x1a,0x97); 676 iic(3,0x78,0x12,0x1a,0x97);
678 iic(3,0x78,0x12,0x1b,0xff); 677 iic(3,0x78,0x12,0x1b,0xff);
679 iic(3,0x78,0x12,0x1c,0xff); 678 iic(3,0x78,0x12,0x1c,0xff);
680 iic(3,0x78,0x12,0x26,0x10); 679 iic(3,0x78,0x12,0x26,0x10);
681 iic(3,0x78,0x12,0x27,0x00); 680 iic(3,0x78,0x12,0x27,0x00);
682 printk("."); 681 printk(".");
683 iic(2,0x78,0x34,0x02,0x00); 682 iic(2,0x78,0x34,0x02,0x00);
684 iic(2,0x78,0x7a,0x10,0x00); 683 iic(2,0x78,0x7a,0x10,0x00);
685 iic(2,0x78,0x80,0x39,0x00); 684 iic(2,0x78,0x80,0x39,0x00);
686 iic(2,0x78,0x81,0xe6,0x00); 685 iic(2,0x78,0x81,0xe6,0x00);
687 iic(2,0x78,0x8d,0x00,0x00); 686 iic(2,0x78,0x8d,0x00,0x00);
688 printk("."); 687 printk(".");
689 iic(2,0x78,0x8e,0x0c,0x00); 688 iic(2,0x78,0x8e,0x0c,0x00);
690 iic(2,0x78,0x8f,0x00,0x00); 689 iic(2,0x78,0x8f,0x00,0x00);
691 #if 0 690 #if 0
692 iic(2,0x78,0x90,0x00,0x00); /* AWB 691 iic(2,0x78,0x90,0x00,0x00); /* AWB on=1 off=0 */
693 #endif 692 #endif
694 iic(2,0x78,0x93,0x01,0x00); 693 iic(2,0x78,0x93,0x01,0x00);
695 iic(2,0x78,0x94,0xcd,0x00); 694 iic(2,0x78,0x94,0xcd,0x00);
696 iic(2,0x78,0x95,0x00,0x00); 695 iic(2,0x78,0x95,0x00,0x00);
697 printk("."); 696 printk(".");
698 iic(2,0x78,0x96,0xa0,0x00); 697 iic(2,0x78,0x96,0xa0,0x00);
699 iic(2,0x78,0x97,0x00,0x00); 698 iic(2,0x78,0x97,0x00,0x00);
700 iic(2,0x78,0x98,0x60,0x00); 699 iic(2,0x78,0x98,0x60,0x00);
701 iic(2,0x78,0x99,0x01,0x00); 700 iic(2,0x78,0x99,0x01,0x00);
702 iic(2,0x78,0x9a,0x19,0x00); 701 iic(2,0x78,0x9a,0x19,0x00);
703 printk("."); 702 printk(".");
704 iic(2,0x78,0x9b,0x02,0x00); 703 iic(2,0x78,0x9b,0x02,0x00);
705 iic(2,0x78,0x9c,0xe8,0x00); 704 iic(2,0x78,0x9c,0xe8,0x00);
706 iic(2,0x78,0x9d,0x02,0x00); 705 iic(2,0x78,0x9d,0x02,0x00);
707 iic(2,0x78,0x9e,0x2e,0x00); 706 iic(2,0x78,0x9e,0x2e,0x00);
708 iic(2,0x78,0xb8,0x78,0x00); 707 iic(2,0x78,0xb8,0x78,0x00);
709 iic(2,0x78,0xba,0x05,0x00); 708 iic(2,0x78,0xba,0x05,0x00);
710 #if 0 709 #if 0
711 iic(2,0x78,0x83,0x8c,0x00); /* bri 710 iic(2,0x78,0x83,0x8c,0x00); /* brightness */
712 #endif 711 #endif
713 printk("."); 712 printk(".");
714 713
715 /* color correction */ 714 /* color correction */
716 iic(3,0x78,0x49,0x00,0x95); /* a 715 iic(3,0x78,0x49,0x00,0x95); /* a */
717 iic(3,0x78,0x49,0x01,0x96); /* b 716 iic(3,0x78,0x49,0x01,0x96); /* b */
718 iic(3,0x78,0x49,0x03,0x85); /* c 717 iic(3,0x78,0x49,0x03,0x85); /* c */
719 iic(3,0x78,0x49,0x04,0x97); /* d 718 iic(3,0x78,0x49,0x04,0x97); /* d */
720 iic(3,0x78,0x49,0x02,0x7e); /* e(L 719 iic(3,0x78,0x49,0x02,0x7e); /* e(Lo) */
721 iic(3,0x78,0x49,0x05,0xa4); /* f(L 720 iic(3,0x78,0x49,0x05,0xa4); /* f(Lo) */
722 iic(3,0x78,0x49,0x06,0x04); /* e(H 721 iic(3,0x78,0x49,0x06,0x04); /* e(Hi) */
723 iic(3,0x78,0x49,0x07,0x04); /* e(H 722 iic(3,0x78,0x49,0x07,0x04); /* e(Hi) */
724 iic(2,0x78,0x48,0x01,0x00); /* on= 723 iic(2,0x78,0x48,0x01,0x00); /* on=1 off=0 */
725 724
726 printk("."); 725 printk(".");
727 iic(2,0x78,0x11,0x00,0x00); /* end 726 iic(2,0x78,0x11,0x00,0x00); /* end */
728 printk(" done\n"); 727 printk(" done\n");
729 return 0; 728 return 0;
730 } 729 }
731 730
732 731
733 void ar_release(struct video_device *vfd) 732 void ar_release(struct video_device *vfd)
734 { 733 {
735 struct ar_device *ar = video_get_drvda !! 734 struct ar_device *ar = vfd->priv;
736 mutex_lock(&ar->lock); 735 mutex_lock(&ar->lock);
737 video_device_release(vfd); 736 video_device_release(vfd);
738 } 737 }
739 738
740 /********************************************* 739 /****************************************************************************
741 * 740 *
742 * Video4Linux Module functions 741 * Video4Linux Module functions
743 * 742 *
744 ********************************************* 743 ****************************************************************************/
745 static struct ar_device ardev; !! 744 static const struct file_operations ar_fops = {
746 <<
747 static int ar_exclusive_open(struct file *file <<
748 { <<
749 return test_and_set_bit(0, &ardev.in_u <<
750 } <<
751 <<
752 static int ar_exclusive_release(struct file *f <<
753 { <<
754 clear_bit(0, &ardev.in_use); <<
755 return 0; <<
756 } <<
757 <<
758 static const struct v4l2_file_operations ar_fo <<
759 .owner = THIS_MODULE, 745 .owner = THIS_MODULE,
760 .open = ar_exclusive_open, !! 746 .open = video_exclusive_open,
761 .release = ar_exclusive_release !! 747 .release = video_exclusive_release,
762 .read = ar_read, 748 .read = ar_read,
763 .ioctl = ar_ioctl, 749 .ioctl = ar_ioctl,
>> 750 .compat_ioctl = v4l_compat_ioctl32,
>> 751 .llseek = no_llseek,
764 }; 752 };
765 753
766 static struct video_device ar_template = { 754 static struct video_device ar_template = {
>> 755 .owner = THIS_MODULE,
767 .name = "Colour AR VGA", 756 .name = "Colour AR VGA",
>> 757 .type = VID_TYPE_CAPTURE,
768 .fops = &ar_fops, 758 .fops = &ar_fops,
769 .release = ar_release, 759 .release = ar_release,
770 .minor = -1, 760 .minor = -1,
771 }; 761 };
772 762
773 #define ALIGN4(x) ((((int)(x)) & 0x3) == 763 #define ALIGN4(x) ((((int)(x)) & 0x3) == 0)
>> 764 static struct ar_device ardev;
774 765
775 static int __init ar_init(void) 766 static int __init ar_init(void)
776 { 767 {
777 struct ar_device *ar; 768 struct ar_device *ar;
778 int ret; 769 int ret;
779 int i; 770 int i;
780 771
781 DEBUG(1, "ar_init:\n"); 772 DEBUG(1, "ar_init:\n");
782 ret = -EIO; 773 ret = -EIO;
783 printk(KERN_INFO "arv: Colour AR VGA d 774 printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION);
784 775
785 ar = &ardev; 776 ar = &ardev;
786 memset(ar, 0, sizeof(struct ar_device) 777 memset(ar, 0, sizeof(struct ar_device));
787 778
788 #if USE_INT 779 #if USE_INT
789 /* allocate a DMA buffer for 1 line. 780 /* allocate a DMA buffer for 1 line. */
790 ar->line_buff = kmalloc(MAX_AR_LINE_BY 781 ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA);
791 if (ar->line_buff == NULL || ! ALIGN4( 782 if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) {
792 printk("arv: buffer allocation 783 printk("arv: buffer allocation failed for DMA.\n");
793 ret = -ENOMEM; 784 ret = -ENOMEM;
794 goto out_end; 785 goto out_end;
795 } 786 }
796 #endif 787 #endif
797 /* allocate buffers for a frame */ 788 /* allocate buffers for a frame */
798 for (i = 0; i < MAX_AR_HEIGHT; i++) { 789 for (i = 0; i < MAX_AR_HEIGHT; i++) {
799 ar->frame[i] = kmalloc(MAX_AR_ 790 ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL);
800 if (ar->frame[i] == NULL || ! 791 if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) {
801 printk("arv: buffer al 792 printk("arv: buffer allocation failed for frame.\n");
802 ret = -ENOMEM; 793 ret = -ENOMEM;
803 goto out_line_buff; 794 goto out_line_buff;
804 } 795 }
805 } 796 }
806 797
807 ar->vdev = video_device_alloc(); 798 ar->vdev = video_device_alloc();
808 if (!ar->vdev) { 799 if (!ar->vdev) {
809 printk(KERN_ERR "arv: video_de 800 printk(KERN_ERR "arv: video_device_alloc() failed\n");
810 return -ENOMEM; 801 return -ENOMEM;
811 } 802 }
812 memcpy(ar->vdev, &ar_template, sizeof( 803 memcpy(ar->vdev, &ar_template, sizeof(ar_template));
813 video_set_drvdata(ar->vdev, ar); !! 804 ar->vdev->priv = ar;
814 805
815 if (vga) { 806 if (vga) {
816 ar->width = AR_WIDTH_VGA 807 ar->width = AR_WIDTH_VGA;
817 ar->height = AR_HEIGHT_VG 808 ar->height = AR_HEIGHT_VGA;
818 ar->size = AR_SIZE_VGA; 809 ar->size = AR_SIZE_VGA;
819 ar->frame_bytes = AR_FRAME_BYT 810 ar->frame_bytes = AR_FRAME_BYTES_VGA;
820 ar->line_bytes = AR_LINE_BYTE 811 ar->line_bytes = AR_LINE_BYTES_VGA;
821 if (vga_interlace) 812 if (vga_interlace)
822 ar->mode = AR_MODE_INT 813 ar->mode = AR_MODE_INTERLACE;
823 else 814 else
824 ar->mode = AR_MODE_NOR 815 ar->mode = AR_MODE_NORMAL;
825 } else { 816 } else {
826 ar->width = AR_WIDTH_QVG 817 ar->width = AR_WIDTH_QVGA;
827 ar->height = AR_HEIGHT_QV 818 ar->height = AR_HEIGHT_QVGA;
828 ar->size = AR_SIZE_QVGA 819 ar->size = AR_SIZE_QVGA;
829 ar->frame_bytes = AR_FRAME_BYT 820 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
830 ar->line_bytes = AR_LINE_BYTE 821 ar->line_bytes = AR_LINE_BYTES_QVGA;
831 ar->mode = AR_MODE_INTE 822 ar->mode = AR_MODE_INTERLACE;
832 } 823 }
833 mutex_init(&ar->lock); 824 mutex_init(&ar->lock);
834 init_waitqueue_head(&ar->wait); 825 init_waitqueue_head(&ar->wait);
835 826
836 #if USE_INT 827 #if USE_INT
837 if (request_irq(M32R_IRQ_INT3, ar_inte 828 if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) {
838 printk("arv: request_irq(%d) f 829 printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3);
839 ret = -EIO; 830 ret = -EIO;
840 goto out_irq; 831 goto out_irq;
841 } 832 }
842 #endif 833 #endif
843 834
844 if (ar_initialize(ar->vdev) != 0) { 835 if (ar_initialize(ar->vdev) != 0) {
845 printk("arv: M64278 not found. 836 printk("arv: M64278 not found.\n");
846 ret = -ENODEV; 837 ret = -ENODEV;
847 goto out_dev; 838 goto out_dev;
848 } 839 }
849 840
850 /* 841 /*
851 * ok, we can initialize h/w according 842 * ok, we can initialize h/w according to parameters,
852 * so register video device as a frame 843 * so register video device as a frame grabber type.
853 * device is named "video[0-64]". 844 * device is named "video[0-64]".
854 * video_register_device() initializes 845 * video_register_device() initializes h/w using ar_initialize().
855 */ 846 */
856 if (video_register_device(ar->vdev, VF 847 if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) {
857 /* return -1, -ENFILE(full) or 848 /* return -1, -ENFILE(full) or others */
858 printk("arv: register video (C 849 printk("arv: register video (Colour AR) failed.\n");
859 ret = -ENODEV; 850 ret = -ENODEV;
860 goto out_dev; 851 goto out_dev;
861 } 852 }
862 853
863 printk("video%d: Found M64278 VGA (IRQ 854 printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n",
864 ar->vdev->num, M32R_IRQ_INT3, !! 855 ar->vdev->minor, M32R_IRQ_INT3, freq);
865 856
866 return 0; 857 return 0;
867 858
868 out_dev: 859 out_dev:
869 #if USE_INT 860 #if USE_INT
870 free_irq(M32R_IRQ_INT3, ar); 861 free_irq(M32R_IRQ_INT3, ar);
871 862
872 out_irq: 863 out_irq:
873 #endif 864 #endif
874 for (i = 0; i < MAX_AR_HEIGHT; i++) 865 for (i = 0; i < MAX_AR_HEIGHT; i++)
875 kfree(ar->frame[i]); 866 kfree(ar->frame[i]);
876 867
877 out_line_buff: 868 out_line_buff:
878 #if USE_INT 869 #if USE_INT
879 kfree(ar->line_buff); 870 kfree(ar->line_buff);
880 871
881 out_end: 872 out_end:
882 #endif 873 #endif
883 return ret; 874 return ret;
884 } 875 }
885 876
886 877
887 static int __init ar_init_module(void) 878 static int __init ar_init_module(void)
888 { 879 {
889 freq = (boot_cpu_data.bus_clock / 1000 880 freq = (boot_cpu_data.bus_clock / 1000000);
890 printk("arv: Bus clock %d\n", freq); 881 printk("arv: Bus clock %d\n", freq);
891 if (freq != 50 && freq != 75) 882 if (freq != 50 && freq != 75)
892 freq = DEFAULT_FREQ; 883 freq = DEFAULT_FREQ;
893 return ar_init(); 884 return ar_init();
894 } 885 }
895 886
896 static void __exit ar_cleanup_module(void) 887 static void __exit ar_cleanup_module(void)
897 { 888 {
898 struct ar_device *ar; 889 struct ar_device *ar;
899 int i; 890 int i;
900 891
901 ar = &ardev; 892 ar = &ardev;
902 video_unregister_device(ar->vdev); 893 video_unregister_device(ar->vdev);
903 #if USE_INT 894 #if USE_INT
904 free_irq(M32R_IRQ_INT3, ar); 895 free_irq(M32R_IRQ_INT3, ar);
905 #endif 896 #endif
906 for (i = 0; i < MAX_AR_HEIGHT; i++) 897 for (i = 0; i < MAX_AR_HEIGHT; i++)
907 kfree(ar->frame[i]); 898 kfree(ar->frame[i]);
908 #if USE_INT 899 #if USE_INT
909 kfree(ar->line_buff); 900 kfree(ar->line_buff);
910 #endif 901 #endif
911 } 902 }
912 903
913 module_init(ar_init_module); 904 module_init(ar_init_module);
914 module_exit(ar_cleanup_module); 905 module_exit(ar_cleanup_module);
915 906
916 MODULE_AUTHOR("Takeo Takahashi <takahashi.take 907 MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>");
917 MODULE_DESCRIPTION("Colour AR M64278(VGA) for 908 MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux");
918 MODULE_LICENSE("GPL"); 909 MODULE_LICENSE("GPL");
919 910
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