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1 /* 1 /*
2 * Copyright (c) 1997-1998 Mark Lord !! 2 * linux/drivers/ide/pci/trm290.c Version 1.02 Mar. 18, 2000
3 * Copyright (c) 2007 MontaVista Softwa <<
4 * 3 *
>> 4 * Copyright (c) 1997-1998 Mark Lord
5 * May be copied or modified under the terms 5 * May be copied or modified under the terms of the GNU General Public License
6 * 6 *
7 * June 22, 2004 - get rid of check_region 7 * June 22, 2004 - get rid of check_region
8 * - Jesper Juhl !! 8 * Jesper Juhl <juhl-lkml@dif.dk>
9 * 9 *
10 */ 10 */
11 11
12 /* 12 /*
13 * This module provides support for the bus-ma 13 * This module provides support for the bus-master IDE DMA function
14 * of the Tekram TRM290 chip, used on a variet 14 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
15 * including a "Precision Instruments" board. 15 * including a "Precision Instruments" board. The TRM290 pre-dates
16 * the sff-8038 standard (ide-dma.c) by a few 16 * the sff-8038 standard (ide-dma.c) by a few months, and differs
17 * significantly enough to warrant separate ro 17 * significantly enough to warrant separate routines for some functions,
18 * while re-using others from ide-dma.c. 18 * while re-using others from ide-dma.c.
19 * 19 *
20 * EXPERIMENTAL! It works for me (a sample of 20 * EXPERIMENTAL! It works for me (a sample of one).
21 * 21 *
22 * Works reliably for me in DMA mode (READs on 22 * Works reliably for me in DMA mode (READs only),
23 * DMA WRITEs are disabled by default (see #de 23 * DMA WRITEs are disabled by default (see #define below);
24 * 24 *
25 * DMA is not enabled automatically for this c 25 * DMA is not enabled automatically for this chipset,
26 * but can be turned on manually (with "hdparm 26 * but can be turned on manually (with "hdparm -d1") at run time.
27 * 27 *
28 * I need volunteers with "spare" drives for f 28 * I need volunteers with "spare" drives for further testing
29 * and development, and maybe to help figure o 29 * and development, and maybe to help figure out the peculiarities.
30 * Even knowing the registers (below), some th 30 * Even knowing the registers (below), some things behave strangely.
31 */ 31 */
32 32
33 #define TRM290_NO_DMA_WRITES /* DMA writes 33 #define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
34 34
35 /* 35 /*
36 * TRM-290 PCI-IDE2 Bus Master Chip 36 * TRM-290 PCI-IDE2 Bus Master Chip
37 * ================================ 37 * ================================
38 * The configuration registers are addressed i 38 * The configuration registers are addressed in normal I/O port space
39 * and are used as follows: 39 * and are used as follows:
40 * 40 *
41 * trm290_base depends on jumper settings, and 41 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
42 * 42 *
43 * trm290_base+2 when WRITTEN: chiptest regist 43 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
44 * bit7 must always be written as "1" 44 * bit7 must always be written as "1"
45 * bits6-2 undefined 45 * bits6-2 undefined
46 * bit1 1=legacy_compatible_mode, 0=nativ 46 * bit1 1=legacy_compatible_mode, 0=native_pci_mode
47 * bit0 1=test_mode, 0=normal(default) 47 * bit0 1=test_mode, 0=normal(default)
48 * 48 *
49 * trm290_base+2 when READ: status register (b 49 * trm290_base+2 when READ: status register (byte, read-only)
50 * bits7-2 undefined 50 * bits7-2 undefined
51 * bit1 channel0 busmaster interrupt stat 51 * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
52 * bit0 channel0 interrupt status 0=none, 52 * bit0 channel0 interrupt status 0=none, 1=asserted
53 * 53 *
54 * trm290_base+3 Interrupt mask register 54 * trm290_base+3 Interrupt mask register
55 * bits7-5 undefined 55 * bits7-5 undefined
56 * bit4 legacy_header: 1=present, 0=absen 56 * bit4 legacy_header: 1=present, 0=absent
57 * bit3 channel1 busmaster interrupt stat 57 * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
58 * bit2 channel1 interrupt status 0=none, 58 * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
59 * bit1 channel1 interrupt mask: 1=masked 59 * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
60 * bit0 channel0 interrupt mask: 1=masked 60 * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
61 * 61 *
62 * trm290_base+1 "CPR" Config Pointer Register 62 * trm290_base+1 "CPR" Config Pointer Register (byte)
63 * bit7 1=autoincrement CPR bits 2-0 afte 63 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
64 * bit6 1=min. 1 wait-state posted write 64 * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
65 * bit5 0=enabled master burst access (de 65 * bit5 0=enabled master burst access (default), 1=disable (write only)
66 * bit4 PCI DEVSEL# timing select: 1=medi 66 * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
67 * bit3 0=primary IDE channel, 1=secondar 67 * bit3 0=primary IDE channel, 1=secondary IDE channel
68 * bits2-0 register index for accesses th 68 * bits2-0 register index for accesses through CDR port
69 * 69 *
70 * trm290_base+0 "CDR" Config Data Register (w 70 * trm290_base+0 "CDR" Config Data Register (word)
71 * two sets of seven config registers, 71 * two sets of seven config registers,
72 * selected by CPR bit 3 (channel) and CP 72 * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
73 * each index defined below: 73 * each index defined below:
74 * 74 *
75 * Index-0 Base address register for command b 75 * Index-0 Base address register for command block (word)
76 * defaults: 0x1f0 for primary, 0x170 for 76 * defaults: 0x1f0 for primary, 0x170 for secondary
77 * 77 *
78 * Index-1 general config register (byte) 78 * Index-1 general config register (byte)
79 * bit7 1=DMA enable, 0=DMA disable 79 * bit7 1=DMA enable, 0=DMA disable
80 * bit6 1=activate IDE_RESET, 0=no action 80 * bit6 1=activate IDE_RESET, 0=no action (default)
81 * bit5 1=enable IORDY, 0=disable IORDY ( 81 * bit5 1=enable IORDY, 0=disable IORDY (default)
82 * bit4 0=16-bit data port(default), 1=8- 82 * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83 * bit3 interrupt polarity: 1=active_low, 83 * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84 * bit2 power-saving-mode(?): 1=enable, 0 84 * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85 * bit1 bus_master_mode(?): 1=enable, 0=d 85 * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86 * bit0 enable_io_ports: 1=enable(default 86 * bit0 enable_io_ports: 1=enable(default), 0=disable
87 * 87 *
88 * Index-2 read-ahead counter preload bits 0-7 88 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89 * bits7-0 bits7-0 of readahead count 89 * bits7-0 bits7-0 of readahead count
90 * 90 *
91 * Index-3 read-ahead config register (byte, w 91 * Index-3 read-ahead config register (byte, write only)
92 * bit7 1=enable_readahead, 0=disable_rea 92 * bit7 1=enable_readahead, 0=disable_readahead(default)
93 * bit6 1=clear_FIFO, 0=no_action 93 * bit6 1=clear_FIFO, 0=no_action
94 * bit5 undefined 94 * bit5 undefined
95 * bit4 mode4 timing control: 1=enable, 0 95 * bit4 mode4 timing control: 1=enable, 0=disable(default)
96 * bit3 undefined 96 * bit3 undefined
97 * bit2 undefined 97 * bit2 undefined
98 * bits1-0 bits9-8 of read-ahead count 98 * bits1-0 bits9-8 of read-ahead count
99 * 99 *
100 * Index-4 base address register for control b 100 * Index-4 base address register for control block (word)
101 * defaults: 0x3f6 for primary, 0x376 for 101 * defaults: 0x3f6 for primary, 0x376 for secondary
102 * 102 *
103 * Index-5 data port timings (shared by both d 103 * Index-5 data port timings (shared by both drives) (byte)
104 * standard PCI "clk" (clock) counts, def 104 * standard PCI "clk" (clock) counts, default value = 0xf5
105 * 105 *
106 * bits7-6 setup time: 00=1clk, 01=2clk, 106 * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
107 * bits5-3 hold time: 000=1clk, 001= 107 * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
108 * 011=4clk, 100= 108 * 011=4clk, 100=5clk, 101=6clk,
109 * 110=8clk, 111= 109 * 110=8clk, 111=12clk
110 * bits2-0 active time: 000=2clk, 001= 110 * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
111 * 011=5clk, 100= 111 * 011=5clk, 100=6clk, 101=8clk,
112 * 110=12clk, 111 112 * 110=12clk, 111=16clk
113 * 113 *
114 * Index-6 command/control port timings (share 114 * Index-6 command/control port timings (shared by both drives) (byte)
115 * same layout as Index-5, default value 115 * same layout as Index-5, default value = 0xde
116 * 116 *
117 * Suggested CDR programming for PIO mode0 (60 117 * Suggested CDR programming for PIO mode0 (600ns):
118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde 118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
119 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde 119 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
120 * 120 *
121 * Suggested CDR programming for PIO mode3 (18 121 * Suggested CDR programming for PIO mode3 (180ns):
122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde 122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
123 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde 123 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
124 * 124 *
125 * Suggested CDR programming for PIO mode4 (12 125 * Suggested CDR programming for PIO mode4 (120ns):
126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde 126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
127 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde 127 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
128 * 128 *
129 */ 129 */
130 130
>> 131 #include <linux/config.h>
131 #include <linux/types.h> 132 #include <linux/types.h>
132 #include <linux/module.h> 133 #include <linux/module.h>
133 #include <linux/kernel.h> 134 #include <linux/kernel.h>
>> 135 #include <linux/mm.h>
134 #include <linux/ioport.h> 136 #include <linux/ioport.h>
135 #include <linux/interrupt.h> 137 #include <linux/interrupt.h>
136 #include <linux/blkdev.h> 138 #include <linux/blkdev.h>
137 #include <linux/init.h> 139 #include <linux/init.h>
138 #include <linux/hdreg.h> 140 #include <linux/hdreg.h>
139 #include <linux/pci.h> 141 #include <linux/pci.h>
>> 142 #include <linux/delay.h>
140 #include <linux/ide.h> 143 #include <linux/ide.h>
141 144
142 #include <asm/io.h> 145 #include <asm/io.h>
143 146
144 static void trm290_prepare_drive (ide_drive_t 147 static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
145 { 148 {
146 ide_hwif_t *hwif = HWIF(drive); 149 ide_hwif_t *hwif = HWIF(drive);
147 u16 reg = 0; 150 u16 reg = 0;
148 unsigned long flags; 151 unsigned long flags;
149 152
150 /* select PIO or DMA */ 153 /* select PIO or DMA */
151 reg = use_dma ? (0x21 | 0x82) : (0x21 154 reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
152 155
153 local_irq_save(flags); 156 local_irq_save(flags);
154 157
155 if (reg != hwif->select_data) { 158 if (reg != hwif->select_data) {
156 hwif->select_data = reg; 159 hwif->select_data = reg;
157 /* set PIO/DMA */ 160 /* set PIO/DMA */
158 outb(0x51 | (hwif->channel << !! 161 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
159 outw(reg & 0xff, hwif->config_ !! 162 hwif->OUTW(reg & 0xff, hwif->config_data);
160 } 163 }
161 164
162 /* enable IRQ if not probing */ 165 /* enable IRQ if not probing */
163 if (drive->present) { 166 if (drive->present) {
164 reg = inw(hwif->config_data + !! 167 reg = hwif->INW(hwif->config_data + 3);
165 reg &= 0x13; 168 reg &= 0x13;
166 reg &= ~(1 << hwif->channel); 169 reg &= ~(1 << hwif->channel);
167 outw(reg, hwif->config_data + !! 170 hwif->OUTW(reg, hwif->config_data+3);
168 } 171 }
169 172
170 local_irq_restore(flags); 173 local_irq_restore(flags);
171 } 174 }
172 175
173 static void trm290_selectproc (ide_drive_t *dr 176 static void trm290_selectproc (ide_drive_t *drive)
174 { 177 {
175 trm290_prepare_drive(drive, drive->usi 178 trm290_prepare_drive(drive, drive->using_dma);
176 } 179 }
177 180
178 static void trm290_dma_exec_cmd(ide_drive_t *d !! 181 #ifdef CONFIG_BLK_DEV_IDEDMA
>> 182 static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
179 { 183 {
180 ide_execute_command(drive, command, &i !! 184 ide_hwif_t *hwif = HWIF(drive);
>> 185
>> 186 if (HWGROUP(drive)->handler != NULL) /* paranoia check */
>> 187 BUG();
>> 188 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
>> 189 /* issue cmd to drive */
>> 190 hwif->OUTB(command, IDE_COMMAND_REG);
181 } 191 }
182 192
183 static int trm290_dma_setup(ide_drive_t *drive !! 193 static int trm290_ide_dma_setup(ide_drive_t *drive)
184 { 194 {
185 ide_hwif_t *hwif = drive->hwif; 195 ide_hwif_t *hwif = drive->hwif;
186 struct request *rq = hwif->hwgroup->rq 196 struct request *rq = hwif->hwgroup->rq;
187 unsigned int count, rw; 197 unsigned int count, rw;
188 198
189 if (rq_data_dir(rq)) { 199 if (rq_data_dir(rq)) {
190 #ifdef TRM290_NO_DMA_WRITES 200 #ifdef TRM290_NO_DMA_WRITES
191 /* always use PIO for writes * 201 /* always use PIO for writes */
192 trm290_prepare_drive(drive, 0) 202 trm290_prepare_drive(drive, 0); /* select PIO xfer */
193 return 1; 203 return 1;
194 #endif 204 #endif
195 rw = 1; 205 rw = 1;
196 } else 206 } else
197 rw = 2; 207 rw = 2;
198 208
199 if (!(count = ide_build_dmatable(drive 209 if (!(count = ide_build_dmatable(drive, rq))) {
200 /* try PIO instead of DMA */ 210 /* try PIO instead of DMA */
201 trm290_prepare_drive(drive, 0) 211 trm290_prepare_drive(drive, 0); /* select PIO xfer */
202 return 1; 212 return 1;
203 } 213 }
204 /* select DMA xfer */ 214 /* select DMA xfer */
205 trm290_prepare_drive(drive, 1); 215 trm290_prepare_drive(drive, 1);
206 outl(hwif->dmatable_dma | rw, hwif->dm !! 216 hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
207 drive->waiting_for_dma = 1; 217 drive->waiting_for_dma = 1;
208 /* start DMA */ 218 /* start DMA */
209 outw(count * 2 - 1, hwif->dma_base + 2 !! 219 hwif->OUTW((count * 2) - 1, hwif->dma_status);
210 return 0; 220 return 0;
211 } 221 }
212 222
213 static void trm290_dma_start(ide_drive_t *driv !! 223 static void trm290_ide_dma_start(ide_drive_t *drive)
214 { 224 {
215 } 225 }
216 226
217 static int trm290_ide_dma_end (ide_drive_t *dr 227 static int trm290_ide_dma_end (ide_drive_t *drive)
218 { 228 {
219 u16 status; !! 229 ide_hwif_t *hwif = HWIF(drive);
>> 230 u16 status = 0;
220 231
221 drive->waiting_for_dma = 0; 232 drive->waiting_for_dma = 0;
222 /* purge DMA mappings */ 233 /* purge DMA mappings */
223 ide_destroy_dmatable(drive); 234 ide_destroy_dmatable(drive);
224 status = inw(HWIF(drive)->dma_base + 2 !! 235 status = hwif->INW(hwif->dma_status);
225 return status != 0x00ff; !! 236 return (status != 0x00ff);
226 } 237 }
227 238
228 static int trm290_ide_dma_test_irq (ide_drive_ 239 static int trm290_ide_dma_test_irq (ide_drive_t *drive)
229 { 240 {
230 u16 status; !! 241 ide_hwif_t *hwif = HWIF(drive);
231 !! 242 u16 status = 0;
232 status = inw(HWIF(drive)->dma_base + 2 <<
233 return status == 0x00ff; <<
234 } <<
235 243
236 static void trm290_dma_host_set(ide_drive_t *d !! 244 status = hwif->INW(hwif->dma_status);
237 { !! 245 return (status == 0x00ff);
238 } 246 }
>> 247 #endif /* CONFIG_BLK_DEV_IDEDMA */
239 248
>> 249 /*
>> 250 * Invoked from ide-dma.c at boot time.
>> 251 */
240 static void __devinit init_hwif_trm290(ide_hwi 252 static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
241 { 253 {
242 struct pci_dev *dev = to_pci_dev(h !! 254 unsigned int cfgbase = 0;
243 unsigned int cfg_base = pci_resource <<
244 unsigned long flags; 255 unsigned long flags;
245 u8 reg = 0; 256 u8 reg = 0;
>> 257 struct pci_dev *dev = hwif->pci_dev;
246 258
247 if ((dev->class & 5) && cfg_base) !! 259 hwif->no_lba48 = 1;
248 printk(KERN_INFO "TRM290: chip !! 260 hwif->chipset = ide_trm290;
249 else { !! 261 cfgbase = pci_resource_start(dev, 4);
250 cfg_base = 0x3df0; !! 262 if ((dev->class & 5) && cfgbase) {
251 printk(KERN_INFO "TRM290: usin !! 263 hwif->config_data = cfgbase;
252 } !! 264 printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
253 printk(KERN_CONT " config base at 0x%0 !! 265 hwif->config_data);
254 hwif->config_data = cfg_base; !! 266 } else {
255 hwif->dma_base = (cfg_base + 4) ^ (hwi !! 267 hwif->config_data = 0x3df0;
256 !! 268 printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
257 printk(KERN_INFO " %s: BM-DMA at 0x !! 269 hwif->config_data);
258 hwif->name, hwif->dma_base, hwi <<
259 <<
260 if (!request_region(hwif->dma_base, 4, <<
261 printk(KERN_CONT " -- Error, p <<
262 return; <<
263 } 270 }
264 271
265 hwif->dmatable_cpu = pci_alloc_consist <<
266 <<
267 if (!hwif->dmatable_cpu) { <<
268 printk(KERN_CONT " -- Error, u <<
269 release_region(hwif->dma_base, <<
270 return; <<
271 } <<
272 printk(KERN_CONT "\n"); <<
273 <<
274 local_irq_save(flags); 272 local_irq_save(flags);
275 /* put config reg into first byte of h 273 /* put config reg into first byte of hwif->select_data */
276 outb(0x51 | (hwif->channel << 3), hwif !! 274 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
277 /* select PIO as default */ 275 /* select PIO as default */
278 hwif->select_data = 0x21; 276 hwif->select_data = 0x21;
279 outb(hwif->select_data, hwif->config_d !! 277 hwif->OUTB(hwif->select_data, hwif->config_data);
280 /* get IRQ info */ 278 /* get IRQ info */
281 reg = inb(hwif->config_data + 3); !! 279 reg = hwif->INB(hwif->config_data+3);
282 /* mask IRQs for both ports */ 280 /* mask IRQs for both ports */
283 reg = (reg & 0x10) | 0x03; 281 reg = (reg & 0x10) | 0x03;
284 outb(reg, hwif->config_data + 3); !! 282 hwif->OUTB(reg, hwif->config_data+3);
285 local_irq_restore(flags); 283 local_irq_restore(flags);
286 284
287 if (reg & 0x10) !! 285 if ((reg & 0x10))
288 /* legacy mode */ 286 /* legacy mode */
289 hwif->irq = hwif->channel ? 15 287 hwif->irq = hwif->channel ? 15 : 14;
290 else if (!hwif->irq && hwif->mate && h 288 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
291 /* sharing IRQ with mate */ 289 /* sharing IRQ with mate */
292 hwif->irq = hwif->mate->irq; 290 hwif->irq = hwif->mate->irq;
293 291
294 hwif->dma_host_set = &trm290_dma_ !! 292 ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
295 hwif->dma_setup = &trm290_dma_ !! 293
296 hwif->dma_exec_cmd = &trm290_dma_ !! 294 #ifdef CONFIG_BLK_DEV_IDEDMA
297 hwif->dma_start = &trm290_dma_ !! 295 hwif->dma_setup = &trm290_ide_dma_setup;
298 hwif->ide_dma_end = &trm290_ide_ !! 296 hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd;
299 hwif->ide_dma_test_irq = &trm290_ide_ !! 297 hwif->dma_start = &trm290_ide_dma_start;
>> 298 hwif->ide_dma_end = &trm290_ide_dma_end;
>> 299 hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
>> 300 #endif /* CONFIG_BLK_DEV_IDEDMA */
300 301
301 hwif->selectproc = &trm290_selectproc; 302 hwif->selectproc = &trm290_selectproc;
>> 303 hwif->autodma = 0; /* play it safe for now */
>> 304 hwif->drives[0].autodma = hwif->autodma;
>> 305 hwif->drives[1].autodma = hwif->autodma;
302 #if 1 306 #if 1
303 { 307 {
304 /* 308 /*
305 * My trm290-based card doesn't seem t 309 * My trm290-based card doesn't seem to work with all possible values
306 * for the control basereg, so this kl 310 * for the control basereg, so this kludge ensures that we use only
307 * values that are known to work. Ugh 311 * values that are known to work. Ugh. -ml
308 */ 312 */
309 u16 new, old, compat = hwif->c 313 u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
310 static u16 next_offset = 0; 314 static u16 next_offset = 0;
311 u8 old_mask; 315 u8 old_mask;
312 316
313 outb(0x54 | (hwif->channel << !! 317 hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
314 old = inw(hwif->config_data); !! 318 old = hwif->INW(hwif->config_data);
315 old &= ~1; 319 old &= ~1;
316 old_mask = inb(old + 2); !! 320 old_mask = hwif->INB(old+2);
317 if (old != compat && old_mask 321 if (old != compat && old_mask == 0xff) {
318 /* leave lower 10 bits 322 /* leave lower 10 bits untouched */
319 compat += (next_offset 323 compat += (next_offset += 0x400);
320 hwif->io_ports[IDE_CON 324 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
321 outw(compat | 1, hwif- !! 325 hwif->OUTW(compat|1, hwif->config_data);
322 new = inw(hwif->config !! 326 new = hwif->INW(hwif->config_data);
323 printk(KERN_INFO "%s: 327 printk(KERN_INFO "%s: control basereg workaround: "
324 "old=0x%04x, n 328 "old=0x%04x, new=0x%04x\n",
325 hwif->name, ol 329 hwif->name, old, new & ~1);
326 } 330 }
327 } 331 }
328 #endif 332 #endif
329 } 333 }
330 334
331 static const struct ide_port_info trm290_chips !! 335 static ide_pci_device_t trm290_chipset __devinitdata = {
332 .name = "TRM290", 336 .name = "TRM290",
333 .init_hwif = init_hwif_trm290, 337 .init_hwif = init_hwif_trm290,
334 .chipset = ide_trm290, !! 338 .channels = 2,
335 .host_flags = IDE_HFLAG_NO_ATAPI_D !! 339 .autodma = NOAUTODMA,
336 #if 0 /* play it safe for now */ !! 340 .bootable = ON_BOARD,
337 IDE_HFLAG_TRUST_BIOS <<
338 #endif <<
339 IDE_HFLAG_NO_AUTODMA <<
340 IDE_HFLAG_BOOTABLE | <<
341 IDE_HFLAG_NO_LBA48, <<
342 }; 341 };
343 342
344 static int __devinit trm290_init_one(struct pc 343 static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
345 { 344 {
346 return ide_setup_pci_device(dev, &trm2 345 return ide_setup_pci_device(dev, &trm290_chipset);
347 } 346 }
348 347
349 static const struct pci_device_id trm290_pci_t !! 348 static struct pci_device_id trm290_pci_tbl[] = {
350 { PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TE !! 349 { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 { 0, }, 350 { 0, },
352 }; 351 };
353 MODULE_DEVICE_TABLE(pci, trm290_pci_tbl); 352 MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
354 353
355 static struct pci_driver driver = { 354 static struct pci_driver driver = {
356 .name = "TRM290_IDE", 355 .name = "TRM290_IDE",
357 .id_table = trm290_pci_tbl, 356 .id_table = trm290_pci_tbl,
358 .probe = trm290_init_one, 357 .probe = trm290_init_one,
359 }; 358 };
360 359
361 static int __init trm290_ide_init(void) !! 360 static int trm290_ide_init(void)
362 { 361 {
363 return ide_pci_register_driver(&driver 362 return ide_pci_register_driver(&driver);
364 } 363 }
365 364
366 module_init(trm290_ide_init); 365 module_init(trm290_ide_init);
367 366
368 MODULE_AUTHOR("Mark Lord"); 367 MODULE_AUTHOR("Mark Lord");
369 MODULE_DESCRIPTION("PCI driver module for Tekr 368 MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
370 MODULE_LICENSE("GPL"); 369 MODULE_LICENSE("GPL");
371 370
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