Diff markup
1 /* 1 /*
2 * i2c_adap_pxa.c 2 * i2c_adap_pxa.c
3 * 3 *
4 * I2C adapter for the PXA I2C bus access. 4 * I2C adapter for the PXA I2C bus access.
5 * 5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc. 6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solution 7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 * 8 *
9 * This program is free software; you can red 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Publ 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 * History: 13 * History:
14 * Apr 2002: Initial version [CS] 14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [ 15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning 16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling 17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficie 18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and s 19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RM 20 * Feb 2005: Rework slave mode handling [RMK]
21 */ 21 */
22 #include <linux/kernel.h> 22 #include <linux/kernel.h>
23 #include <linux/module.h> 23 #include <linux/module.h>
24 #include <linux/i2c.h> 24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h> 25 #include <linux/i2c-id.h>
26 #include <linux/init.h> 26 #include <linux/init.h>
27 #include <linux/time.h> 27 #include <linux/time.h>
28 #include <linux/sched.h> 28 #include <linux/sched.h>
29 #include <linux/delay.h> 29 #include <linux/delay.h>
30 #include <linux/errno.h> 30 #include <linux/errno.h>
31 #include <linux/interrupt.h> 31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h> 32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h> 33 #include <linux/platform_device.h>
34 #include <linux/err.h> 34 #include <linux/err.h>
35 #include <linux/clk.h> 35 #include <linux/clk.h>
36 36
>> 37 #include <asm/hardware.h>
37 #include <asm/irq.h> 38 #include <asm/irq.h>
38 #include <asm/io.h> 39 #include <asm/io.h>
39 #include <plat/i2c.h> !! 40 #include <asm/arch/i2c.h>
40 !! 41 #include <asm/arch/pxa-regs.h>
41 /* <<
42 * I2C register offsets will be shifted 0 or 1 <<
43 * different SoCs <<
44 */ <<
45 #define REG_SHIFT_0 (0 << 0) <<
46 #define REG_SHIFT_1 (1 << 0) <<
47 #define REG_SHIFT(d) ((d) & 0x1) <<
48 <<
49 static const struct platform_device_id i2c_pxa <<
50 { "pxa2xx-i2c", REG_SHIFT_1 }, <<
51 { "pxa3xx-pwri2c", REG_SHIFT_0 }, <<
52 { }, <<
53 }; <<
54 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table <<
55 <<
56 /* <<
57 * I2C registers and bit definitions <<
58 */ <<
59 #define IBMR (0x00) <<
60 #define IDBR (0x08) <<
61 #define ICR (0x10) <<
62 #define ISR (0x18) <<
63 #define ISAR (0x20) <<
64 <<
65 #define ICR_START (1 << 0) /* <<
66 #define ICR_STOP (1 << 1) /* <<
67 #define ICR_ACKNAK (1 << 2) /* <<
68 #define ICR_TB (1 << 3) /* <<
69 #define ICR_MA (1 << 4) /* <<
70 #define ICR_SCLE (1 << 5) /* <<
71 #define ICR_IUE (1 << 6) /* <<
72 #define ICR_GCD (1 << 7) /* <<
73 #define ICR_ITEIE (1 << 8) /* <<
74 #define ICR_IRFIE (1 << 9) /* <<
75 #define ICR_BEIE (1 << 10) /* <<
76 #define ICR_SSDIE (1 << 11) /* <<
77 #define ICR_ALDIE (1 << 12) /* <<
78 #define ICR_SADIE (1 << 13) /* <<
79 #define ICR_UR (1 << 14) /* <<
80 #define ICR_FM (1 << 15) /* <<
81 <<
82 #define ISR_RWM (1 << 0) /* <<
83 #define ISR_ACKNAK (1 << 1) /* <<
84 #define ISR_UB (1 << 2) /* <<
85 #define ISR_IBB (1 << 3) /* <<
86 #define ISR_SSD (1 << 4) /* <<
87 #define ISR_ALD (1 << 5) /* <<
88 #define ISR_ITE (1 << 6) /* <<
89 #define ISR_IRF (1 << 7) /* <<
90 #define ISR_GCAD (1 << 8) /* <<
91 #define ISR_SAD (1 << 9) /* <<
92 #define ISR_BED (1 << 10) /* <<
93 42
94 struct pxa_i2c { 43 struct pxa_i2c {
95 spinlock_t lock; 44 spinlock_t lock;
96 wait_queue_head_t wait; 45 wait_queue_head_t wait;
97 struct i2c_msg *msg; 46 struct i2c_msg *msg;
98 unsigned int msg_num; 47 unsigned int msg_num;
99 unsigned int msg_idx; 48 unsigned int msg_idx;
100 unsigned int msg_ptr; 49 unsigned int msg_ptr;
101 unsigned int slave_addr; 50 unsigned int slave_addr;
102 51
103 struct i2c_adapter adap; 52 struct i2c_adapter adap;
104 struct clk *clk; 53 struct clk *clk;
105 #ifdef CONFIG_I2C_PXA_SLAVE 54 #ifdef CONFIG_I2C_PXA_SLAVE
106 struct i2c_slave_client *slave; 55 struct i2c_slave_client *slave;
107 #endif 56 #endif
108 57
109 unsigned int irqlogidx; 58 unsigned int irqlogidx;
110 u32 isrlog[32]; 59 u32 isrlog[32];
111 u32 icrlog[32]; 60 u32 icrlog[32];
112 61
113 void __iomem *reg_base; 62 void __iomem *reg_base;
114 unsigned int reg_shift; <<
115 63
116 unsigned long iobase; 64 unsigned long iobase;
117 unsigned long iosize; 65 unsigned long iosize;
118 66
119 int irq; 67 int irq;
120 unsigned int use_pio :1; !! 68 int use_pio;
121 unsigned int fast_mode :1; <<
122 }; 69 };
123 70
124 #define _IBMR(i2c) ((i2c)->reg_base + (0x !! 71 #define _IBMR(i2c) ((i2c)->reg_base + 0)
125 #define _IDBR(i2c) ((i2c)->reg_base + (0x !! 72 #define _IDBR(i2c) ((i2c)->reg_base + 8)
126 #define _ICR(i2c) ((i2c)->reg_base + (0x !! 73 #define _ICR(i2c) ((i2c)->reg_base + 0x10)
127 #define _ISR(i2c) ((i2c)->reg_base + (0x !! 74 #define _ISR(i2c) ((i2c)->reg_base + 0x18)
128 #define _ISAR(i2c) ((i2c)->reg_base + (0x !! 75 #define _ISAR(i2c) ((i2c)->reg_base + 0x20)
129 76
130 /* 77 /*
131 * I2C Slave mode address 78 * I2C Slave mode address
132 */ 79 */
133 #define I2C_PXA_SLAVE_ADDR 0x1 80 #define I2C_PXA_SLAVE_ADDR 0x1
134 81
135 #ifdef DEBUG 82 #ifdef DEBUG
136 83
137 struct bits { 84 struct bits {
138 u32 mask; 85 u32 mask;
139 const char *set; 86 const char *set;
140 const char *unset; 87 const char *unset;
141 }; 88 };
142 #define PXA_BIT(m, s, u) { .mask = m, . 89 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
143 90
144 static inline void 91 static inline void
145 decode_bits(const char *prefix, const struct b 92 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
146 { 93 {
147 printk("%s %08x: ", prefix, val); 94 printk("%s %08x: ", prefix, val);
148 while (num--) { 95 while (num--) {
149 const char *str = val & bits-> 96 const char *str = val & bits->mask ? bits->set : bits->unset;
150 if (str) 97 if (str)
151 printk("%s ", str); 98 printk("%s ", str);
152 bits++; 99 bits++;
153 } 100 }
154 } 101 }
155 102
156 static const struct bits isr_bits[] = { 103 static const struct bits isr_bits[] = {
157 PXA_BIT(ISR_RWM, "RX", 104 PXA_BIT(ISR_RWM, "RX", "TX"),
158 PXA_BIT(ISR_ACKNAK, "NAK", 105 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
159 PXA_BIT(ISR_UB, "Bsy", 106 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
160 PXA_BIT(ISR_IBB, "BusBsy", 107 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
161 PXA_BIT(ISR_SSD, "SlaveStop", 108 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
162 PXA_BIT(ISR_ALD, "ALD", 109 PXA_BIT(ISR_ALD, "ALD", NULL),
163 PXA_BIT(ISR_ITE, "TxEmpty", 110 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
164 PXA_BIT(ISR_IRF, "RxFull", 111 PXA_BIT(ISR_IRF, "RxFull", NULL),
165 PXA_BIT(ISR_GCAD, "GenCall", 112 PXA_BIT(ISR_GCAD, "GenCall", NULL),
166 PXA_BIT(ISR_SAD, "SlaveAddr", 113 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
167 PXA_BIT(ISR_BED, "BusErr", 114 PXA_BIT(ISR_BED, "BusErr", NULL),
168 }; 115 };
169 116
170 static void decode_ISR(unsigned int val) 117 static void decode_ISR(unsigned int val)
171 { 118 {
172 decode_bits(KERN_DEBUG "ISR", isr_bits 119 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
173 printk("\n"); 120 printk("\n");
174 } 121 }
175 122
176 static const struct bits icr_bits[] = { 123 static const struct bits icr_bits[] = {
177 PXA_BIT(ICR_START, "START", NULL), 124 PXA_BIT(ICR_START, "START", NULL),
178 PXA_BIT(ICR_STOP, "STOP", NULL), 125 PXA_BIT(ICR_STOP, "STOP", NULL),
179 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), 126 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
180 PXA_BIT(ICR_TB, "TB", NULL), 127 PXA_BIT(ICR_TB, "TB", NULL),
181 PXA_BIT(ICR_MA, "MA", NULL), 128 PXA_BIT(ICR_MA, "MA", NULL),
182 PXA_BIT(ICR_SCLE, "SCLE", "scle" 129 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
183 PXA_BIT(ICR_IUE, "IUE", "iue") 130 PXA_BIT(ICR_IUE, "IUE", "iue"),
184 PXA_BIT(ICR_GCD, "GCD", NULL), 131 PXA_BIT(ICR_GCD, "GCD", NULL),
185 PXA_BIT(ICR_ITEIE, "ITEIE", NULL), 132 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
186 PXA_BIT(ICR_IRFIE, "IRFIE", NULL), 133 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
187 PXA_BIT(ICR_BEIE, "BEIE", NULL), 134 PXA_BIT(ICR_BEIE, "BEIE", NULL),
188 PXA_BIT(ICR_SSDIE, "SSDIE", NULL), 135 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
189 PXA_BIT(ICR_ALDIE, "ALDIE", NULL), 136 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
190 PXA_BIT(ICR_SADIE, "SADIE", NULL), 137 PXA_BIT(ICR_SADIE, "SADIE", NULL),
191 PXA_BIT(ICR_UR, "UR", 138 PXA_BIT(ICR_UR, "UR", "ur"),
192 }; 139 };
193 140
194 #ifdef CONFIG_I2C_PXA_SLAVE 141 #ifdef CONFIG_I2C_PXA_SLAVE
195 static void decode_ICR(unsigned int val) 142 static void decode_ICR(unsigned int val)
196 { 143 {
197 decode_bits(KERN_DEBUG "ICR", icr_bits 144 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
198 printk("\n"); 145 printk("\n");
199 } 146 }
200 #endif 147 #endif
201 148
202 static unsigned int i2c_debug = DEBUG; 149 static unsigned int i2c_debug = DEBUG;
203 150
204 static void i2c_pxa_show_state(struct pxa_i2c 151 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
205 { 152 {
206 dev_dbg(&i2c->adap.dev, "state:%s:%d: 153 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
207 readl(_ISR(i2c)), readl(_ICR(i 154 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
208 } 155 }
209 156
210 #define show_state(i2c) i2c_pxa_show_state(i2c !! 157 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
211 #else 158 #else
212 #define i2c_debug 0 159 #define i2c_debug 0
213 160
214 #define show_state(i2c) do { } while (0) 161 #define show_state(i2c) do { } while (0)
215 #define decode_ISR(val) do { } while (0) 162 #define decode_ISR(val) do { } while (0)
216 #define decode_ICR(val) do { } while (0) 163 #define decode_ICR(val) do { } while (0)
217 #endif 164 #endif
218 165
219 #define eedbg(lvl, x...) do { if ((lvl) < 1) { 166 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
220 167
221 static void i2c_pxa_master_complete(struct pxa 168 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
222 static irqreturn_t i2c_pxa_handler(int this_ir 169 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
223 170
224 static void i2c_pxa_scream_blue_murder(struct 171 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
225 { 172 {
226 unsigned int i; 173 unsigned int i;
227 printk(KERN_ERR "i2c: error: %s\n", wh !! 174 printk("i2c: error: %s\n", why);
228 printk(KERN_ERR "i2c: msg_num: %d msg_ !! 175 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
229 i2c->msg_num, i2c->msg_idx, i2 176 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
230 printk(KERN_ERR "i2c: ICR: %08x ISR: % !! 177 printk("i2c: ICR: %08x ISR: %08x\n"
231 readl(_ICR(i2c)), readl(_ISR(i2 !! 178 "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
232 printk(KERN_DEBUG "i2c: log: "); <<
233 for (i = 0; i < i2c->irqlogidx; i++) 179 for (i = 0; i < i2c->irqlogidx; i++)
234 printk("[%08x:%08x] ", i2c->is 180 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
235 printk("\n"); 181 printk("\n");
236 } 182 }
237 183
238 static inline int i2c_pxa_is_slavemode(struct 184 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
239 { 185 {
240 return !(readl(_ICR(i2c)) & ICR_SCLE); 186 return !(readl(_ICR(i2c)) & ICR_SCLE);
241 } 187 }
242 188
243 static void i2c_pxa_abort(struct pxa_i2c *i2c) 189 static void i2c_pxa_abort(struct pxa_i2c *i2c)
244 { 190 {
245 int i = 250; !! 191 unsigned long timeout = jiffies + HZ/4;
246 192
247 if (i2c_pxa_is_slavemode(i2c)) { 193 if (i2c_pxa_is_slavemode(i2c)) {
248 dev_dbg(&i2c->adap.dev, "%s: c 194 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
249 return; 195 return;
250 } 196 }
251 197
252 while ((i > 0) && (readl(_IBMR(i2c)) & !! 198 while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
253 unsigned long icr = readl(_ICR 199 unsigned long icr = readl(_ICR(i2c));
254 200
255 icr &= ~ICR_START; 201 icr &= ~ICR_START;
256 icr |= ICR_ACKNAK | ICR_STOP | 202 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
257 203
258 writel(icr, _ICR(i2c)); 204 writel(icr, _ICR(i2c));
259 205
260 show_state(i2c); 206 show_state(i2c);
261 207
262 mdelay(1); !! 208 msleep(1);
263 i --; <<
264 } 209 }
265 210
266 writel(readl(_ICR(i2c)) & ~(ICR_MA | I 211 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
267 _ICR(i2c)); 212 _ICR(i2c));
268 } 213 }
269 214
270 static int i2c_pxa_wait_bus_not_busy(struct px 215 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
271 { 216 {
272 int timeout = DEF_TIMEOUT; 217 int timeout = DEF_TIMEOUT;
273 218
274 while (timeout-- && readl(_ISR(i2c)) & 219 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
275 if ((readl(_ISR(i2c)) & ISR_SA 220 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
276 timeout += 4; 221 timeout += 4;
277 222
278 msleep(2); 223 msleep(2);
279 show_state(i2c); 224 show_state(i2c);
280 } 225 }
281 226
282 if (timeout < 0) !! 227 if (timeout <= 0)
283 show_state(i2c); 228 show_state(i2c);
284 229
285 return timeout < 0 ? I2C_RETRY : 0; !! 230 return timeout <= 0 ? I2C_RETRY : 0;
286 } 231 }
287 232
288 static int i2c_pxa_wait_master(struct pxa_i2c 233 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
289 { 234 {
290 unsigned long timeout = jiffies + HZ*4 235 unsigned long timeout = jiffies + HZ*4;
291 236
292 while (time_before(jiffies, timeout)) 237 while (time_before(jiffies, timeout)) {
293 if (i2c_debug > 1) 238 if (i2c_debug > 1)
294 dev_dbg(&i2c->adap.dev 239 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
295 __func__, (lon 240 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
296 241
297 if (readl(_ISR(i2c)) & ISR_SAD 242 if (readl(_ISR(i2c)) & ISR_SAD) {
298 if (i2c_debug > 0) 243 if (i2c_debug > 0)
299 dev_dbg(&i2c-> 244 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
300 goto out; 245 goto out;
301 } 246 }
302 247
303 /* wait for unit and bus being 248 /* wait for unit and bus being not busy, and we also do a
304 * quick check of the i2c line 249 * quick check of the i2c lines themselves to ensure they've
305 * gone high... 250 * gone high...
306 */ 251 */
307 if ((readl(_ISR(i2c)) & (ISR_U 252 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
308 if (i2c_debug > 0) 253 if (i2c_debug > 0)
309 dev_dbg(&i2c-> 254 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
310 return 1; 255 return 1;
311 } 256 }
312 257
313 msleep(1); 258 msleep(1);
314 } 259 }
315 260
316 if (i2c_debug > 0) 261 if (i2c_debug > 0)
317 dev_dbg(&i2c->adap.dev, "%s: d 262 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
318 out: 263 out:
319 return 0; 264 return 0;
320 } 265 }
321 266
322 static int i2c_pxa_set_master(struct pxa_i2c * 267 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
323 { 268 {
324 if (i2c_debug) 269 if (i2c_debug)
325 dev_dbg(&i2c->adap.dev, "setti 270 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
326 271
327 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_ 272 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
328 dev_dbg(&i2c->adap.dev, "%s: u 273 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
329 if (!i2c_pxa_wait_master(i2c)) 274 if (!i2c_pxa_wait_master(i2c)) {
330 dev_dbg(&i2c->adap.dev 275 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
331 return I2C_RETRY; 276 return I2C_RETRY;
332 } 277 }
333 } 278 }
334 279
335 writel(readl(_ICR(i2c)) | ICR_SCLE, _I 280 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
336 return 0; 281 return 0;
337 } 282 }
338 283
339 #ifdef CONFIG_I2C_PXA_SLAVE 284 #ifdef CONFIG_I2C_PXA_SLAVE
340 static int i2c_pxa_wait_slave(struct pxa_i2c * 285 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
341 { 286 {
342 unsigned long timeout = jiffies + HZ*1 287 unsigned long timeout = jiffies + HZ*1;
343 288
344 /* wait for stop */ 289 /* wait for stop */
345 290
346 show_state(i2c); 291 show_state(i2c);
347 292
348 while (time_before(jiffies, timeout)) 293 while (time_before(jiffies, timeout)) {
349 if (i2c_debug > 1) 294 if (i2c_debug > 1)
350 dev_dbg(&i2c->adap.dev 295 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
351 __func__, (lon 296 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
352 297
353 if ((readl(_ISR(i2c)) & (ISR_U 298 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
354 (readl(_ISR(i2c)) & ISR_SA 299 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
355 (readl(_ICR(i2c)) & ICR_SC 300 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
356 if (i2c_debug > 1) 301 if (i2c_debug > 1)
357 dev_dbg(&i2c-> 302 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
358 return 1; 303 return 1;
359 } 304 }
360 305
361 msleep(1); 306 msleep(1);
362 } 307 }
363 308
364 if (i2c_debug > 0) 309 if (i2c_debug > 0)
365 dev_dbg(&i2c->adap.dev, "%s: d 310 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
366 return 0; 311 return 0;
367 } 312 }
368 313
369 /* 314 /*
370 * clear the hold on the bus, and take of anyt 315 * clear the hold on the bus, and take of anything else
371 * that has been configured 316 * that has been configured
372 */ 317 */
373 static void i2c_pxa_set_slave(struct pxa_i2c * 318 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
374 { 319 {
375 show_state(i2c); 320 show_state(i2c);
376 321
377 if (errcode < 0) { 322 if (errcode < 0) {
378 udelay(100); /* simple delay 323 udelay(100); /* simple delay */
379 } else { 324 } else {
380 /* we need to wait for the sto 325 /* we need to wait for the stop condition to end */
381 326
382 /* if we where in stop, then c 327 /* if we where in stop, then clear... */
383 if (readl(_ICR(i2c)) & ICR_STO 328 if (readl(_ICR(i2c)) & ICR_STOP) {
384 udelay(100); 329 udelay(100);
385 writel(readl(_ICR(i2c) 330 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
386 } 331 }
387 332
388 if (!i2c_pxa_wait_slave(i2c)) 333 if (!i2c_pxa_wait_slave(i2c)) {
389 dev_err(&i2c->adap.dev 334 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
390 __func__); 335 __func__);
391 return; 336 return;
392 } 337 }
393 } 338 }
394 339
395 writel(readl(_ICR(i2c)) & ~(ICR_STOP|I 340 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
396 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ 341 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
397 342
398 if (i2c_debug) { 343 if (i2c_debug) {
399 dev_dbg(&i2c->adap.dev, "ICR n 344 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
400 decode_ICR(readl(_ICR(i2c))); 345 decode_ICR(readl(_ICR(i2c)));
401 } 346 }
402 } 347 }
403 #else 348 #else
404 #define i2c_pxa_set_slave(i2c, err) do { } 349 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
405 #endif 350 #endif
406 351
407 static void i2c_pxa_reset(struct pxa_i2c *i2c) 352 static void i2c_pxa_reset(struct pxa_i2c *i2c)
408 { 353 {
409 pr_debug("Resetting I2C Controller Uni 354 pr_debug("Resetting I2C Controller Unit\n");
410 355
411 /* abort any transfer currently under 356 /* abort any transfer currently under way */
412 i2c_pxa_abort(i2c); 357 i2c_pxa_abort(i2c);
413 358
414 /* reset according to 9.8 */ 359 /* reset according to 9.8 */
415 writel(ICR_UR, _ICR(i2c)); 360 writel(ICR_UR, _ICR(i2c));
416 writel(I2C_ISR_INIT, _ISR(i2c)); 361 writel(I2C_ISR_INIT, _ISR(i2c));
417 writel(readl(_ICR(i2c)) & ~ICR_UR, _IC 362 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
418 363
419 writel(i2c->slave_addr, _ISAR(i2c)); 364 writel(i2c->slave_addr, _ISAR(i2c));
420 365
421 /* set control register values */ 366 /* set control register values */
422 writel(I2C_ICR_INIT | (i2c->fast_mode !! 367 writel(I2C_ICR_INIT, _ICR(i2c));
423 368
424 #ifdef CONFIG_I2C_PXA_SLAVE 369 #ifdef CONFIG_I2C_PXA_SLAVE
425 dev_info(&i2c->adap.dev, "Enabling sla 370 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
426 writel(readl(_ICR(i2c)) | ICR_SADIE | 371 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
427 #endif 372 #endif
428 373
429 i2c_pxa_set_slave(i2c, 0); 374 i2c_pxa_set_slave(i2c, 0);
430 375
431 /* enable unit */ 376 /* enable unit */
432 writel(readl(_ICR(i2c)) | ICR_IUE, _IC 377 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
433 udelay(100); 378 udelay(100);
434 } 379 }
435 380
436 381
437 #ifdef CONFIG_I2C_PXA_SLAVE 382 #ifdef CONFIG_I2C_PXA_SLAVE
438 /* 383 /*
439 * PXA I2C Slave mode 384 * PXA I2C Slave mode
440 */ 385 */
441 386
442 static void i2c_pxa_slave_txempty(struct pxa_i 387 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
443 { 388 {
444 if (isr & ISR_BED) { 389 if (isr & ISR_BED) {
445 /* what should we do here? */ 390 /* what should we do here? */
446 } else { 391 } else {
447 int ret = 0; 392 int ret = 0;
448 393
449 if (i2c->slave != NULL) 394 if (i2c->slave != NULL)
450 ret = i2c->slave->read 395 ret = i2c->slave->read(i2c->slave->data);
451 396
452 writel(ret, _IDBR(i2c)); 397 writel(ret, _IDBR(i2c));
453 writel(readl(_ICR(i2c)) | ICR_ 398 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
454 } 399 }
455 } 400 }
456 401
457 static void i2c_pxa_slave_rxfull(struct pxa_i2 402 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
458 { 403 {
459 unsigned int byte = readl(_IDBR(i2c)); 404 unsigned int byte = readl(_IDBR(i2c));
460 405
461 if (i2c->slave != NULL) 406 if (i2c->slave != NULL)
462 i2c->slave->write(i2c->slave-> 407 i2c->slave->write(i2c->slave->data, byte);
463 408
464 writel(readl(_ICR(i2c)) | ICR_TB, _ICR 409 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
465 } 410 }
466 411
467 static void i2c_pxa_slave_start(struct pxa_i2c 412 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
468 { 413 {
469 int timeout; 414 int timeout;
470 415
471 if (i2c_debug > 0) 416 if (i2c_debug > 0)
472 dev_dbg(&i2c->adap.dev, "SAD, 417 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
473 (isr & ISR_RWM) ? 'r' : 418 (isr & ISR_RWM) ? 'r' : 't');
474 419
475 if (i2c->slave != NULL) 420 if (i2c->slave != NULL)
476 i2c->slave->event(i2c->slave-> 421 i2c->slave->event(i2c->slave->data,
477 (isr & ISR_RW 422 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
478 423
479 /* 424 /*
480 * slave could interrupt in the middle 425 * slave could interrupt in the middle of us generating a
481 * start condition... if this happens, 426 * start condition... if this happens, we'd better back off
482 * and stop holding the poor thing up 427 * and stop holding the poor thing up
483 */ 428 */
484 writel(readl(_ICR(i2c)) & ~(ICR_START| 429 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
485 writel(readl(_ICR(i2c)) | ICR_TB, _ICR 430 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
486 431
487 timeout = 0x10000; 432 timeout = 0x10000;
488 433
489 while (1) { 434 while (1) {
490 if ((readl(_IBMR(i2c)) & 2) == 435 if ((readl(_IBMR(i2c)) & 2) == 2)
491 break; 436 break;
492 437
493 timeout--; 438 timeout--;
494 439
495 if (timeout <= 0) { 440 if (timeout <= 0) {
496 dev_err(&i2c->adap.dev 441 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
497 break; 442 break;
498 } 443 }
499 } 444 }
500 445
501 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ 446 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
502 } 447 }
503 448
504 static void i2c_pxa_slave_stop(struct pxa_i2c 449 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
505 { 450 {
506 if (i2c_debug > 2) 451 if (i2c_debug > 2)
507 dev_dbg(&i2c->adap.dev, "ISR: 452 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
508 453
509 if (i2c->slave != NULL) 454 if (i2c->slave != NULL)
510 i2c->slave->event(i2c->slave-> 455 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
511 456
512 if (i2c_debug > 2) 457 if (i2c_debug > 2)
513 dev_dbg(&i2c->adap.dev, "ISR: 458 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
514 459
515 /* 460 /*
516 * If we have a master-mode message wa 461 * If we have a master-mode message waiting,
517 * kick it off now that the slave has 462 * kick it off now that the slave has completed.
518 */ 463 */
519 if (i2c->msg) 464 if (i2c->msg)
520 i2c_pxa_master_complete(i2c, I 465 i2c_pxa_master_complete(i2c, I2C_RETRY);
521 } 466 }
522 #else 467 #else
523 static void i2c_pxa_slave_txempty(struct pxa_i 468 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
524 { 469 {
525 if (isr & ISR_BED) { 470 if (isr & ISR_BED) {
526 /* what should we do here? */ 471 /* what should we do here? */
527 } else { 472 } else {
528 writel(0, _IDBR(i2c)); 473 writel(0, _IDBR(i2c));
529 writel(readl(_ICR(i2c)) | ICR_ 474 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
530 } 475 }
531 } 476 }
532 477
533 static void i2c_pxa_slave_rxfull(struct pxa_i2 478 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
534 { 479 {
535 writel(readl(_ICR(i2c)) | ICR_TB | ICR 480 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
536 } 481 }
537 482
538 static void i2c_pxa_slave_start(struct pxa_i2c 483 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
539 { 484 {
540 int timeout; 485 int timeout;
541 486
542 /* 487 /*
543 * slave could interrupt in the middle 488 * slave could interrupt in the middle of us generating a
544 * start condition... if this happens, 489 * start condition... if this happens, we'd better back off
545 * and stop holding the poor thing up 490 * and stop holding the poor thing up
546 */ 491 */
547 writel(readl(_ICR(i2c)) & ~(ICR_START| 492 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
548 writel(readl(_ICR(i2c)) | ICR_TB | ICR 493 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
549 494
550 timeout = 0x10000; 495 timeout = 0x10000;
551 496
552 while (1) { 497 while (1) {
553 if ((readl(_IBMR(i2c)) & 2) == 498 if ((readl(_IBMR(i2c)) & 2) == 2)
554 break; 499 break;
555 500
556 timeout--; 501 timeout--;
557 502
558 if (timeout <= 0) { 503 if (timeout <= 0) {
559 dev_err(&i2c->adap.dev 504 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
560 break; 505 break;
561 } 506 }
562 } 507 }
563 508
564 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ 509 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
565 } 510 }
566 511
567 static void i2c_pxa_slave_stop(struct pxa_i2c 512 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
568 { 513 {
569 if (i2c->msg) 514 if (i2c->msg)
570 i2c_pxa_master_complete(i2c, I 515 i2c_pxa_master_complete(i2c, I2C_RETRY);
571 } 516 }
572 #endif 517 #endif
573 518
574 /* 519 /*
575 * PXA I2C Master mode 520 * PXA I2C Master mode
576 */ 521 */
577 522
578 static inline unsigned int i2c_pxa_addr_byte(s 523 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
579 { 524 {
580 unsigned int addr = (msg->addr & 0x7f) 525 unsigned int addr = (msg->addr & 0x7f) << 1;
581 526
582 if (msg->flags & I2C_M_RD) 527 if (msg->flags & I2C_M_RD)
583 addr |= 1; 528 addr |= 1;
584 529
585 return addr; 530 return addr;
586 } 531 }
587 532
588 static inline void i2c_pxa_start_message(struc 533 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
589 { 534 {
590 u32 icr; 535 u32 icr;
591 536
592 /* 537 /*
593 * Step 1: target slave address into I 538 * Step 1: target slave address into IDBR
594 */ 539 */
595 writel(i2c_pxa_addr_byte(i2c->msg), _I 540 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
596 541
597 /* 542 /*
598 * Step 2: initiate the write. 543 * Step 2: initiate the write.
599 */ 544 */
600 icr = readl(_ICR(i2c)) & ~(ICR_STOP | 545 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
601 writel(icr | ICR_START | ICR_TB, _ICR( 546 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
602 } 547 }
603 548
604 static inline void i2c_pxa_stop_message(struct 549 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
605 { 550 {
606 u32 icr; 551 u32 icr;
607 552
608 /* 553 /*
609 * Clear the STOP and ACK flags 554 * Clear the STOP and ACK flags
610 */ 555 */
611 icr = readl(_ICR(i2c)); 556 icr = readl(_ICR(i2c));
612 icr &= ~(ICR_STOP | ICR_ACKNAK); 557 icr &= ~(ICR_STOP | ICR_ACKNAK);
613 writel(icr, _ICR(i2c)); 558 writel(icr, _ICR(i2c));
614 } 559 }
615 560
616 static int i2c_pxa_pio_set_master(struct pxa_i 561 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
617 { 562 {
618 /* make timeout the same as for interr 563 /* make timeout the same as for interrupt based functions */
619 long timeout = 2 * DEF_TIMEOUT; 564 long timeout = 2 * DEF_TIMEOUT;
620 565
621 /* 566 /*
622 * Wait for the bus to become free. 567 * Wait for the bus to become free.
623 */ 568 */
624 while (timeout-- && readl(_ISR(i2c)) & 569 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
625 udelay(1000); 570 udelay(1000);
626 show_state(i2c); 571 show_state(i2c);
627 } 572 }
628 573
629 if (timeout < 0) { !! 574 if (timeout <= 0) {
630 show_state(i2c); 575 show_state(i2c);
631 dev_err(&i2c->adap.dev, 576 dev_err(&i2c->adap.dev,
632 "i2c_pxa: timeout wait 577 "i2c_pxa: timeout waiting for bus free\n");
633 return I2C_RETRY; 578 return I2C_RETRY;
634 } 579 }
635 580
636 /* 581 /*
637 * Set master mode. 582 * Set master mode.
638 */ 583 */
639 writel(readl(_ICR(i2c)) | ICR_SCLE, _I 584 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
640 585
641 return 0; 586 return 0;
642 } 587 }
643 588
644 static int i2c_pxa_do_pio_xfer(struct pxa_i2c 589 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
645 struct i2c_msg 590 struct i2c_msg *msg, int num)
646 { 591 {
647 unsigned long timeout = 500000; /* 5 s 592 unsigned long timeout = 500000; /* 5 seconds */
648 int ret = 0; 593 int ret = 0;
649 594
650 ret = i2c_pxa_pio_set_master(i2c); 595 ret = i2c_pxa_pio_set_master(i2c);
651 if (ret) 596 if (ret)
652 goto out; 597 goto out;
653 598
654 i2c->msg = msg; 599 i2c->msg = msg;
655 i2c->msg_num = num; 600 i2c->msg_num = num;
656 i2c->msg_idx = 0; 601 i2c->msg_idx = 0;
657 i2c->msg_ptr = 0; 602 i2c->msg_ptr = 0;
658 i2c->irqlogidx = 0; 603 i2c->irqlogidx = 0;
659 604
660 i2c_pxa_start_message(i2c); 605 i2c_pxa_start_message(i2c);
661 606
662 while (i2c->msg_num > 0 && --timeout) !! 607 while (timeout-- && i2c->msg_num > 0) {
663 i2c_pxa_handler(0, i2c); 608 i2c_pxa_handler(0, i2c);
664 udelay(10); 609 udelay(10);
665 } 610 }
666 611
667 i2c_pxa_stop_message(i2c); 612 i2c_pxa_stop_message(i2c);
668 613
669 /* 614 /*
670 * We place the return code in i2c->ms 615 * We place the return code in i2c->msg_idx.
671 */ 616 */
672 ret = i2c->msg_idx; 617 ret = i2c->msg_idx;
673 618
674 out: 619 out:
675 if (timeout == 0) 620 if (timeout == 0)
676 i2c_pxa_scream_blue_murder(i2c 621 i2c_pxa_scream_blue_murder(i2c, "timeout");
677 622
678 return ret; 623 return ret;
679 } 624 }
680 625
681 /* 626 /*
682 * We are protected by the adapter bus mutex. 627 * We are protected by the adapter bus mutex.
683 */ 628 */
684 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c 629 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
685 { 630 {
686 long timeout; 631 long timeout;
687 int ret; 632 int ret;
688 633
689 /* 634 /*
690 * Wait for the bus to become free. 635 * Wait for the bus to become free.
691 */ 636 */
692 ret = i2c_pxa_wait_bus_not_busy(i2c); 637 ret = i2c_pxa_wait_bus_not_busy(i2c);
693 if (ret) { 638 if (ret) {
694 dev_err(&i2c->adap.dev, "i2c_p 639 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
695 goto out; 640 goto out;
696 } 641 }
697 642
698 /* 643 /*
699 * Set master mode. 644 * Set master mode.
700 */ 645 */
701 ret = i2c_pxa_set_master(i2c); 646 ret = i2c_pxa_set_master(i2c);
702 if (ret) { 647 if (ret) {
703 dev_err(&i2c->adap.dev, "i2c_p 648 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
704 goto out; 649 goto out;
705 } 650 }
706 651
707 spin_lock_irq(&i2c->lock); 652 spin_lock_irq(&i2c->lock);
708 653
709 i2c->msg = msg; 654 i2c->msg = msg;
710 i2c->msg_num = num; 655 i2c->msg_num = num;
711 i2c->msg_idx = 0; 656 i2c->msg_idx = 0;
712 i2c->msg_ptr = 0; 657 i2c->msg_ptr = 0;
713 i2c->irqlogidx = 0; 658 i2c->irqlogidx = 0;
714 659
715 i2c_pxa_start_message(i2c); 660 i2c_pxa_start_message(i2c);
716 661
717 spin_unlock_irq(&i2c->lock); 662 spin_unlock_irq(&i2c->lock);
718 663
719 /* 664 /*
720 * The rest of the processing occurs i 665 * The rest of the processing occurs in the interrupt handler.
721 */ 666 */
722 timeout = wait_event_timeout(i2c->wait 667 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
723 i2c_pxa_stop_message(i2c); 668 i2c_pxa_stop_message(i2c);
724 669
725 /* 670 /*
726 * We place the return code in i2c->ms 671 * We place the return code in i2c->msg_idx.
727 */ 672 */
728 ret = i2c->msg_idx; 673 ret = i2c->msg_idx;
729 674
730 if (timeout == 0) 675 if (timeout == 0)
731 i2c_pxa_scream_blue_murder(i2c 676 i2c_pxa_scream_blue_murder(i2c, "timeout");
732 677
733 out: 678 out:
734 return ret; 679 return ret;
735 } 680 }
736 681
737 static int i2c_pxa_pio_xfer(struct i2c_adapter 682 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
738 struct i2c_msg msg 683 struct i2c_msg msgs[], int num)
739 { 684 {
740 struct pxa_i2c *i2c = adap->algo_data; 685 struct pxa_i2c *i2c = adap->algo_data;
741 int ret, i; 686 int ret, i;
742 687
743 /* If the I2C controller is disabled w 688 /* If the I2C controller is disabled we need to reset it
744 (probably due to a suspend/resume de 689 (probably due to a suspend/resume destroying state). We do
745 this here as we can then avoid worry 690 this here as we can then avoid worrying about resuming the
746 controller before its users. */ 691 controller before its users. */
747 if (!(readl(_ICR(i2c)) & ICR_IUE)) 692 if (!(readl(_ICR(i2c)) & ICR_IUE))
748 i2c_pxa_reset(i2c); 693 i2c_pxa_reset(i2c);
749 694
750 for (i = adap->retries; i >= 0; i--) { 695 for (i = adap->retries; i >= 0; i--) {
751 ret = i2c_pxa_do_pio_xfer(i2c, 696 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
752 if (ret != I2C_RETRY) 697 if (ret != I2C_RETRY)
753 goto out; 698 goto out;
754 699
755 if (i2c_debug) 700 if (i2c_debug)
756 dev_dbg(&adap->dev, "R 701 dev_dbg(&adap->dev, "Retrying transmission\n");
757 udelay(100); 702 udelay(100);
758 } 703 }
759 i2c_pxa_scream_blue_murder(i2c, "exhau 704 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
760 ret = -EREMOTEIO; 705 ret = -EREMOTEIO;
761 out: 706 out:
762 i2c_pxa_set_slave(i2c, ret); 707 i2c_pxa_set_slave(i2c, ret);
763 return ret; 708 return ret;
764 } 709 }
765 710
766 /* 711 /*
767 * i2c_pxa_master_complete - complete the mess 712 * i2c_pxa_master_complete - complete the message and wake up.
768 */ 713 */
769 static void i2c_pxa_master_complete(struct pxa 714 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
770 { 715 {
771 i2c->msg_ptr = 0; 716 i2c->msg_ptr = 0;
772 i2c->msg = NULL; 717 i2c->msg = NULL;
773 i2c->msg_idx ++; 718 i2c->msg_idx ++;
774 i2c->msg_num = 0; 719 i2c->msg_num = 0;
775 if (ret) 720 if (ret)
776 i2c->msg_idx = ret; 721 i2c->msg_idx = ret;
777 if (!i2c->use_pio) 722 if (!i2c->use_pio)
778 wake_up(&i2c->wait); 723 wake_up(&i2c->wait);
779 } 724 }
780 725
781 static void i2c_pxa_irq_txempty(struct pxa_i2c 726 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
782 { 727 {
783 u32 icr = readl(_ICR(i2c)) & ~(ICR_STA 728 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
784 729
785 again: 730 again:
786 /* 731 /*
787 * If ISR_ALD is set, we lost arbitrat 732 * If ISR_ALD is set, we lost arbitration.
788 */ 733 */
789 if (isr & ISR_ALD) { 734 if (isr & ISR_ALD) {
790 /* 735 /*
791 * Do we need to do anything h 736 * Do we need to do anything here? The PXA docs
792 * are vague about what happen 737 * are vague about what happens.
793 */ 738 */
794 i2c_pxa_scream_blue_murder(i2c 739 i2c_pxa_scream_blue_murder(i2c, "ALD set");
795 740
796 /* 741 /*
797 * We ignore this error. We s 742 * We ignore this error. We seem to see spurious ALDs
798 * for seemingly no reason. I 743 * for seemingly no reason. If we handle them as I think
799 * they should, we end up caus 744 * they should, we end up causing an I2C error, which
800 * is painful for some systems 745 * is painful for some systems.
801 */ 746 */
802 return; /* ignore */ 747 return; /* ignore */
803 } 748 }
804 749
805 if (isr & ISR_BED) { 750 if (isr & ISR_BED) {
806 int ret = BUS_ERROR; 751 int ret = BUS_ERROR;
807 752
808 /* 753 /*
809 * I2C bus error - either the 754 * I2C bus error - either the device NAK'd us, or
810 * something more serious happ 755 * something more serious happened. If we were NAK'd
811 * on the initial address phas 756 * on the initial address phase, we can retry.
812 */ 757 */
813 if (isr & ISR_ACKNAK) { 758 if (isr & ISR_ACKNAK) {
814 if (i2c->msg_ptr == 0 759 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
815 ret = I2C_RETR 760 ret = I2C_RETRY;
816 else 761 else
817 ret = XFER_NAK 762 ret = XFER_NAKED;
818 } 763 }
819 i2c_pxa_master_complete(i2c, r 764 i2c_pxa_master_complete(i2c, ret);
820 } else if (isr & ISR_RWM) { 765 } else if (isr & ISR_RWM) {
821 /* 766 /*
822 * Read mode. We have just se 767 * Read mode. We have just sent the address byte, and
823 * now we must initiate the tr 768 * now we must initiate the transfer.
824 */ 769 */
825 if (i2c->msg_ptr == i2c->msg-> 770 if (i2c->msg_ptr == i2c->msg->len - 1 &&
826 i2c->msg_idx == i2c->msg_n 771 i2c->msg_idx == i2c->msg_num - 1)
827 icr |= ICR_STOP | ICR_ 772 icr |= ICR_STOP | ICR_ACKNAK;
828 773
829 icr |= ICR_ALDIE | ICR_TB; 774 icr |= ICR_ALDIE | ICR_TB;
830 } else if (i2c->msg_ptr < i2c->msg->le 775 } else if (i2c->msg_ptr < i2c->msg->len) {
831 /* 776 /*
832 * Write mode. Write the next 777 * Write mode. Write the next data byte.
833 */ 778 */
834 writel(i2c->msg->buf[i2c->msg_ 779 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
835 780
836 icr |= ICR_ALDIE | ICR_TB; 781 icr |= ICR_ALDIE | ICR_TB;
837 782
838 /* 783 /*
839 * If this is the last byte of 784 * If this is the last byte of the last message, send
840 * a STOP. 785 * a STOP.
841 */ 786 */
842 if (i2c->msg_ptr == i2c->msg-> 787 if (i2c->msg_ptr == i2c->msg->len &&
843 i2c->msg_idx == i2c->msg_n 788 i2c->msg_idx == i2c->msg_num - 1)
844 icr |= ICR_STOP; 789 icr |= ICR_STOP;
845 } else if (i2c->msg_idx < i2c->msg_num 790 } else if (i2c->msg_idx < i2c->msg_num - 1) {
846 /* 791 /*
847 * Next segment of the message 792 * Next segment of the message.
848 */ 793 */
849 i2c->msg_ptr = 0; 794 i2c->msg_ptr = 0;
850 i2c->msg_idx ++; 795 i2c->msg_idx ++;
851 i2c->msg++; 796 i2c->msg++;
852 797
853 /* 798 /*
854 * If we aren't doing a repeat 799 * If we aren't doing a repeated start and address,
855 * go back and try to send the 800 * go back and try to send the next byte. Note that
856 * we do not support switching 801 * we do not support switching the R/W direction here.
857 */ 802 */
858 if (i2c->msg->flags & I2C_M_NO 803 if (i2c->msg->flags & I2C_M_NOSTART)
859 goto again; 804 goto again;
860 805
861 /* 806 /*
862 * Write the next address. 807 * Write the next address.
863 */ 808 */
864 writel(i2c_pxa_addr_byte(i2c-> 809 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
865 810
866 /* 811 /*
867 * And trigger a repeated star 812 * And trigger a repeated start, and send the byte.
868 */ 813 */
869 icr &= ~ICR_ALDIE; 814 icr &= ~ICR_ALDIE;
870 icr |= ICR_START | ICR_TB; 815 icr |= ICR_START | ICR_TB;
871 } else { 816 } else {
872 if (i2c->msg->len == 0) { 817 if (i2c->msg->len == 0) {
873 /* 818 /*
874 * Device probes have 819 * Device probes have a message length of zero
875 * and need the bus to 820 * and need the bus to be reset before it can
876 * be used again. 821 * be used again.
877 */ 822 */
878 i2c_pxa_reset(i2c); 823 i2c_pxa_reset(i2c);
879 } 824 }
880 i2c_pxa_master_complete(i2c, 0 825 i2c_pxa_master_complete(i2c, 0);
881 } 826 }
882 827
883 i2c->icrlog[i2c->irqlogidx-1] = icr; 828 i2c->icrlog[i2c->irqlogidx-1] = icr;
884 829
885 writel(icr, _ICR(i2c)); 830 writel(icr, _ICR(i2c));
886 show_state(i2c); 831 show_state(i2c);
887 } 832 }
888 833
889 static void i2c_pxa_irq_rxfull(struct pxa_i2c 834 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
890 { 835 {
891 u32 icr = readl(_ICR(i2c)) & ~(ICR_STA 836 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
892 837
893 /* 838 /*
894 * Read the byte. 839 * Read the byte.
895 */ 840 */
896 i2c->msg->buf[i2c->msg_ptr++] = readl( 841 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
897 842
898 if (i2c->msg_ptr < i2c->msg->len) { 843 if (i2c->msg_ptr < i2c->msg->len) {
899 /* 844 /*
900 * If this is the last byte of 845 * If this is the last byte of the last
901 * message, send a STOP. 846 * message, send a STOP.
902 */ 847 */
903 if (i2c->msg_ptr == i2c->msg-> 848 if (i2c->msg_ptr == i2c->msg->len - 1)
904 icr |= ICR_STOP | ICR_ 849 icr |= ICR_STOP | ICR_ACKNAK;
905 850
906 icr |= ICR_ALDIE | ICR_TB; 851 icr |= ICR_ALDIE | ICR_TB;
907 } else { 852 } else {
908 i2c_pxa_master_complete(i2c, 0 853 i2c_pxa_master_complete(i2c, 0);
909 } 854 }
910 855
911 i2c->icrlog[i2c->irqlogidx-1] = icr; 856 i2c->icrlog[i2c->irqlogidx-1] = icr;
912 857
913 writel(icr, _ICR(i2c)); 858 writel(icr, _ICR(i2c));
914 } 859 }
915 860
916 static irqreturn_t i2c_pxa_handler(int this_ir 861 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
917 { 862 {
918 struct pxa_i2c *i2c = dev_id; 863 struct pxa_i2c *i2c = dev_id;
919 u32 isr = readl(_ISR(i2c)); 864 u32 isr = readl(_ISR(i2c));
920 865
921 if (i2c_debug > 2 && 0) { 866 if (i2c_debug > 2 && 0) {
922 dev_dbg(&i2c->adap.dev, "%s: I 867 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
923 __func__, isr, readl(_ 868 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
924 decode_ISR(isr); 869 decode_ISR(isr);
925 } 870 }
926 871
927 if (i2c->irqlogidx < ARRAY_SIZE(i2c->i 872 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
928 i2c->isrlog[i2c->irqlogidx++] 873 i2c->isrlog[i2c->irqlogidx++] = isr;
929 874
930 show_state(i2c); 875 show_state(i2c);
931 876
932 /* 877 /*
933 * Always clear all pending IRQs. 878 * Always clear all pending IRQs.
934 */ 879 */
935 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE| 880 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
936 881
937 if (isr & ISR_SAD) 882 if (isr & ISR_SAD)
938 i2c_pxa_slave_start(i2c, isr); 883 i2c_pxa_slave_start(i2c, isr);
939 if (isr & ISR_SSD) 884 if (isr & ISR_SSD)
940 i2c_pxa_slave_stop(i2c); 885 i2c_pxa_slave_stop(i2c);
941 886
942 if (i2c_pxa_is_slavemode(i2c)) { 887 if (i2c_pxa_is_slavemode(i2c)) {
943 if (isr & ISR_ITE) 888 if (isr & ISR_ITE)
944 i2c_pxa_slave_txempty( 889 i2c_pxa_slave_txempty(i2c, isr);
945 if (isr & ISR_IRF) 890 if (isr & ISR_IRF)
946 i2c_pxa_slave_rxfull(i 891 i2c_pxa_slave_rxfull(i2c, isr);
947 } else if (i2c->msg) { 892 } else if (i2c->msg) {
948 if (isr & ISR_ITE) 893 if (isr & ISR_ITE)
949 i2c_pxa_irq_txempty(i2 894 i2c_pxa_irq_txempty(i2c, isr);
950 if (isr & ISR_IRF) 895 if (isr & ISR_IRF)
951 i2c_pxa_irq_rxfull(i2c 896 i2c_pxa_irq_rxfull(i2c, isr);
952 } else { 897 } else {
953 i2c_pxa_scream_blue_murder(i2c 898 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
954 } 899 }
955 900
956 return IRQ_HANDLED; 901 return IRQ_HANDLED;
957 } 902 }
958 903
959 904
960 static int i2c_pxa_xfer(struct i2c_adapter *ad 905 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
961 { 906 {
962 struct pxa_i2c *i2c = adap->algo_data; 907 struct pxa_i2c *i2c = adap->algo_data;
963 int ret, i; 908 int ret, i;
964 909
>> 910 /* If the I2C controller is disabled we need to reset it (probably due
>> 911 to a suspend/resume destroying state). We do this here as we can then
>> 912 avoid worrying about resuming the controller before its users. */
>> 913 if (!(readl(_ICR(i2c)) & ICR_IUE))
>> 914 i2c_pxa_reset(i2c);
>> 915
965 for (i = adap->retries; i >= 0; i--) { 916 for (i = adap->retries; i >= 0; i--) {
966 ret = i2c_pxa_do_xfer(i2c, msg 917 ret = i2c_pxa_do_xfer(i2c, msgs, num);
967 if (ret != I2C_RETRY) 918 if (ret != I2C_RETRY)
968 goto out; 919 goto out;
969 920
970 if (i2c_debug) 921 if (i2c_debug)
971 dev_dbg(&adap->dev, "R 922 dev_dbg(&adap->dev, "Retrying transmission\n");
972 udelay(100); 923 udelay(100);
973 } 924 }
974 i2c_pxa_scream_blue_murder(i2c, "exhau 925 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
975 ret = -EREMOTEIO; 926 ret = -EREMOTEIO;
976 out: 927 out:
977 i2c_pxa_set_slave(i2c, ret); 928 i2c_pxa_set_slave(i2c, ret);
978 return ret; 929 return ret;
979 } 930 }
980 931
981 static u32 i2c_pxa_functionality(struct i2c_ad 932 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
982 { 933 {
983 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_E 934 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
984 } 935 }
985 936
986 static const struct i2c_algorithm i2c_pxa_algo 937 static const struct i2c_algorithm i2c_pxa_algorithm = {
987 .master_xfer = i2c_pxa_xfer, 938 .master_xfer = i2c_pxa_xfer,
988 .functionality = i2c_pxa_functionalit 939 .functionality = i2c_pxa_functionality,
989 }; 940 };
990 941
991 static const struct i2c_algorithm i2c_pxa_pio_ 942 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
992 .master_xfer = i2c_pxa_pio_xfer, 943 .master_xfer = i2c_pxa_pio_xfer,
993 .functionality = i2c_pxa_functionalit 944 .functionality = i2c_pxa_functionality,
994 }; 945 };
995 946
>> 947 static void i2c_pxa_enable(struct platform_device *dev)
>> 948 {
>> 949 if (cpu_is_pxa27x()) {
>> 950 switch (dev->id) {
>> 951 case 0:
>> 952 pxa_gpio_mode(GPIO117_I2CSCL_MD);
>> 953 pxa_gpio_mode(GPIO118_I2CSDA_MD);
>> 954 break;
>> 955 case 1:
>> 956 local_irq_disable();
>> 957 PCFR |= PCFR_PI2CEN;
>> 958 local_irq_enable();
>> 959 break;
>> 960 }
>> 961 }
>> 962 }
>> 963
>> 964 static void i2c_pxa_disable(struct platform_device *dev)
>> 965 {
>> 966 if (cpu_is_pxa27x() && dev->id == 1) {
>> 967 local_irq_disable();
>> 968 PCFR &= ~PCFR_PI2CEN;
>> 969 local_irq_enable();
>> 970 }
>> 971 }
>> 972
>> 973 #define res_len(r) ((r)->end - (r)->start + 1)
996 static int i2c_pxa_probe(struct platform_devic 974 static int i2c_pxa_probe(struct platform_device *dev)
997 { 975 {
998 struct pxa_i2c *i2c; 976 struct pxa_i2c *i2c;
999 struct resource *res; 977 struct resource *res;
1000 struct i2c_pxa_platform_data *plat = 978 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1001 struct platform_device_id *id = platf <<
1002 int ret; 979 int ret;
1003 int irq; 980 int irq;
1004 981
1005 res = platform_get_resource(dev, IORE 982 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1006 irq = platform_get_irq(dev, 0); 983 irq = platform_get_irq(dev, 0);
1007 if (res == NULL || irq < 0) 984 if (res == NULL || irq < 0)
1008 return -ENODEV; 985 return -ENODEV;
1009 986
1010 if (!request_mem_region(res->start, r !! 987 if (!request_mem_region(res->start, res_len(res), res->name))
1011 return -ENOMEM; 988 return -ENOMEM;
1012 989
1013 i2c = kzalloc(sizeof(struct pxa_i2c), 990 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1014 if (!i2c) { 991 if (!i2c) {
1015 ret = -ENOMEM; 992 ret = -ENOMEM;
1016 goto emalloc; 993 goto emalloc;
1017 } 994 }
1018 995
1019 i2c->adap.owner = THIS_MODULE; 996 i2c->adap.owner = THIS_MODULE;
1020 i2c->adap.retries = 5; 997 i2c->adap.retries = 5;
1021 998
1022 spin_lock_init(&i2c->lock); 999 spin_lock_init(&i2c->lock);
1023 init_waitqueue_head(&i2c->wait); 1000 init_waitqueue_head(&i2c->wait);
1024 1001
1025 /* 1002 /*
1026 * If "dev->id" is negative we consid 1003 * If "dev->id" is negative we consider it as zero.
1027 * The reason to do so is to avoid sy 1004 * The reason to do so is to avoid sysfs names that only make
1028 * sense when there are multiple adap 1005 * sense when there are multiple adapters.
1029 */ 1006 */
1030 i2c->adap.nr = dev->id != -1 ? dev->i 1007 i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1031 snprintf(i2c->adap.name, sizeof(i2c-> 1008 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1032 i2c->adap.nr); 1009 i2c->adap.nr);
1033 1010
1034 i2c->clk = clk_get(&dev->dev, NULL); !! 1011 i2c->clk = clk_get(&dev->dev, "I2CCLK");
1035 if (IS_ERR(i2c->clk)) { 1012 if (IS_ERR(i2c->clk)) {
1036 ret = PTR_ERR(i2c->clk); 1013 ret = PTR_ERR(i2c->clk);
1037 goto eclk; 1014 goto eclk;
1038 } 1015 }
1039 1016
1040 i2c->reg_base = ioremap(res->start, r !! 1017 i2c->reg_base = ioremap(res->start, res_len(res));
1041 if (!i2c->reg_base) { 1018 if (!i2c->reg_base) {
1042 ret = -EIO; 1019 ret = -EIO;
1043 goto eremap; 1020 goto eremap;
1044 } 1021 }
1045 i2c->reg_shift = REG_SHIFT(id->driver <<
1046 1022
1047 i2c->iobase = res->start; 1023 i2c->iobase = res->start;
1048 i2c->iosize = resource_size(res); !! 1024 i2c->iosize = res_len(res);
1049 1025
1050 i2c->irq = irq; 1026 i2c->irq = irq;
1051 1027
1052 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 1028 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1053 1029
1054 #ifdef CONFIG_I2C_PXA_SLAVE 1030 #ifdef CONFIG_I2C_PXA_SLAVE
1055 if (plat) { 1031 if (plat) {
1056 i2c->slave_addr = plat->slave 1032 i2c->slave_addr = plat->slave_addr;
1057 i2c->slave = plat->slave; 1033 i2c->slave = plat->slave;
1058 } 1034 }
1059 #endif 1035 #endif
1060 1036
1061 clk_enable(i2c->clk); 1037 clk_enable(i2c->clk);
>> 1038 i2c_pxa_enable(dev);
1062 1039
1063 if (plat) { 1040 if (plat) {
1064 i2c->adap.class = plat->class 1041 i2c->adap.class = plat->class;
1065 i2c->use_pio = plat->use_pio; 1042 i2c->use_pio = plat->use_pio;
1066 i2c->fast_mode = plat->fast_m <<
1067 } 1043 }
1068 1044
1069 if (i2c->use_pio) { 1045 if (i2c->use_pio) {
1070 i2c->adap.algo = &i2c_pxa_pio 1046 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1071 } else { 1047 } else {
1072 i2c->adap.algo = &i2c_pxa_alg 1048 i2c->adap.algo = &i2c_pxa_algorithm;
1073 ret = request_irq(irq, i2c_px 1049 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1074 i2c->adap.n 1050 i2c->adap.name, i2c);
1075 if (ret) 1051 if (ret)
1076 goto ereqirq; 1052 goto ereqirq;
1077 } 1053 }
1078 1054
1079 i2c_pxa_reset(i2c); 1055 i2c_pxa_reset(i2c);
1080 1056
1081 i2c->adap.algo_data = i2c; 1057 i2c->adap.algo_data = i2c;
1082 i2c->adap.dev.parent = &dev->dev; 1058 i2c->adap.dev.parent = &dev->dev;
1083 1059
1084 ret = i2c_add_numbered_adapter(&i2c-> 1060 ret = i2c_add_numbered_adapter(&i2c->adap);
1085 if (ret < 0) { 1061 if (ret < 0) {
1086 printk(KERN_INFO "I2C: Failed 1062 printk(KERN_INFO "I2C: Failed to add bus\n");
1087 goto eadapt; 1063 goto eadapt;
1088 } 1064 }
1089 1065
1090 platform_set_drvdata(dev, i2c); 1066 platform_set_drvdata(dev, i2c);
1091 1067
1092 #ifdef CONFIG_I2C_PXA_SLAVE 1068 #ifdef CONFIG_I2C_PXA_SLAVE
1093 printk(KERN_INFO "I2C: %s: PXA I2C ad 1069 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1094 dev_name(&i2c->adap.dev), i2c- !! 1070 i2c->adap.dev.bus_id, i2c->slave_addr);
1095 #else 1071 #else
1096 printk(KERN_INFO "I2C: %s: PXA I2C ad 1072 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1097 dev_name(&i2c->adap.dev)); !! 1073 i2c->adap.dev.bus_id);
1098 #endif 1074 #endif
1099 return 0; 1075 return 0;
1100 1076
1101 eadapt: 1077 eadapt:
1102 if (!i2c->use_pio) 1078 if (!i2c->use_pio)
1103 free_irq(irq, i2c); 1079 free_irq(irq, i2c);
1104 ereqirq: 1080 ereqirq:
1105 clk_disable(i2c->clk); 1081 clk_disable(i2c->clk);
>> 1082 i2c_pxa_disable(dev);
1106 iounmap(i2c->reg_base); 1083 iounmap(i2c->reg_base);
1107 eremap: 1084 eremap:
1108 clk_put(i2c->clk); 1085 clk_put(i2c->clk);
1109 eclk: 1086 eclk:
1110 kfree(i2c); 1087 kfree(i2c);
1111 emalloc: 1088 emalloc:
1112 release_mem_region(res->start, resour !! 1089 release_mem_region(res->start, res_len(res));
1113 return ret; 1090 return ret;
1114 } 1091 }
1115 1092
1116 static int __exit i2c_pxa_remove(struct platf 1093 static int __exit i2c_pxa_remove(struct platform_device *dev)
1117 { 1094 {
1118 struct pxa_i2c *i2c = platform_get_dr 1095 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1119 1096
1120 platform_set_drvdata(dev, NULL); 1097 platform_set_drvdata(dev, NULL);
1121 1098
1122 i2c_del_adapter(&i2c->adap); 1099 i2c_del_adapter(&i2c->adap);
1123 if (!i2c->use_pio) 1100 if (!i2c->use_pio)
1124 free_irq(i2c->irq, i2c); 1101 free_irq(i2c->irq, i2c);
1125 1102
1126 clk_disable(i2c->clk); 1103 clk_disable(i2c->clk);
1127 clk_put(i2c->clk); 1104 clk_put(i2c->clk);
>> 1105 i2c_pxa_disable(dev);
1128 1106
1129 iounmap(i2c->reg_base); 1107 iounmap(i2c->reg_base);
1130 release_mem_region(i2c->iobase, i2c-> 1108 release_mem_region(i2c->iobase, i2c->iosize);
1131 kfree(i2c); 1109 kfree(i2c);
1132 1110
1133 return 0; 1111 return 0;
1134 } 1112 }
1135 1113
1136 #ifdef CONFIG_PM <<
1137 static int i2c_pxa_suspend_late(struct platfo <<
1138 { <<
1139 struct pxa_i2c *i2c = platform_get_dr <<
1140 clk_disable(i2c->clk); <<
1141 return 0; <<
1142 } <<
1143 <<
1144 static int i2c_pxa_resume_early(struct platfo <<
1145 { <<
1146 struct pxa_i2c *i2c = platform_get_dr <<
1147 <<
1148 clk_enable(i2c->clk); <<
1149 i2c_pxa_reset(i2c); <<
1150 <<
1151 return 0; <<
1152 } <<
1153 #else <<
1154 #define i2c_pxa_suspend_late NULL <<
1155 #define i2c_pxa_resume_early NULL <<
1156 #endif <<
1157 <<
1158 static struct platform_driver i2c_pxa_driver 1114 static struct platform_driver i2c_pxa_driver = {
1159 .probe = i2c_pxa_probe, 1115 .probe = i2c_pxa_probe,
1160 .remove = __exit_p(i2c_pxa_re 1116 .remove = __exit_p(i2c_pxa_remove),
1161 .suspend_late = i2c_pxa_suspend_lat <<
1162 .resume_early = i2c_pxa_resume_earl <<
1163 .driver = { 1117 .driver = {
1164 .name = "pxa2xx-i2c", 1118 .name = "pxa2xx-i2c",
1165 .owner = THIS_MODULE, 1119 .owner = THIS_MODULE,
1166 }, 1120 },
1167 .id_table = i2c_pxa_id_table, <<
1168 }; 1121 };
1169 1122
1170 static int __init i2c_adap_pxa_init(void) 1123 static int __init i2c_adap_pxa_init(void)
1171 { 1124 {
1172 return platform_driver_register(&i2c_ 1125 return platform_driver_register(&i2c_pxa_driver);
1173 } 1126 }
1174 1127
1175 static void __exit i2c_adap_pxa_exit(void) 1128 static void __exit i2c_adap_pxa_exit(void)
1176 { 1129 {
1177 platform_driver_unregister(&i2c_pxa_d 1130 platform_driver_unregister(&i2c_pxa_driver);
1178 } 1131 }
1179 1132
1180 MODULE_LICENSE("GPL"); 1133 MODULE_LICENSE("GPL");
1181 MODULE_ALIAS("platform:pxa2xx-i2c"); <<
1182 1134
1183 subsys_initcall(i2c_adap_pxa_init); !! 1135 module_init(i2c_adap_pxa_init);
1184 module_exit(i2c_adap_pxa_exit); 1136 module_exit(i2c_adap_pxa_exit);
1185 1137
|
This page was automatically generated by the
LXR engine.
|