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1 /* 1 /*
2 i801.c - Part of lm_sensors, Linux kernel !! 2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring 3 monitoring
4 Copyright (c) 1998 - 2002 Frodo Looijaard 4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and 5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6 <mdsxyz123@yahoo.com> 6 <mdsxyz123@yahoo.com>
>> 7 Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
7 8
8 This program is free software; you can red 9 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Publ 10 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either versi 11 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version. 12 (at your option) any later version.
12 13
13 This program is distributed in the hope th 14 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the 15 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULA 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more detail 17 GNU General Public License for more details.
17 18
18 You should have received a copy of the GNU 19 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to 20 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */ 22 */
22 23
23 /* 24 /*
24 SUPPORTED DEVICES PCI ID !! 25 Supports the following Intel I/O Controller Hubs (ICH):
25 82801AA 2413 !! 26
26 82801AB 2423 !! 27 I/O Block I2C
27 82801BA 2443 !! 28 region SMBus Block proc. block
28 82801CA/CAM 2483 !! 29 Chip name PCI ID size PEC buffer call read
29 82801DB 24C3 (HW PEC support !! 30 ----------------------------------------------------------------------
30 82801EB 24D3 (HW PEC support !! 31 82801AA (ICH) 0x2413 16 no no no no
31 6300ESB 25A4 !! 32 82801AB (ICH0) 0x2423 16 no no no no
32 ICH6 266A !! 33 82801BA (ICH2) 0x2443 16 no no no no
33 ICH7 27DA !! 34 82801CA (ICH3) 0x2483 32 soft no no no
34 This driver supports several versions of I !! 35 82801DB (ICH4) 0x24c3 32 hard yes no no
35 For SMBus support, they are similar to the !! 36 82801E (ICH5) 0x24d3 32 hard yes yes yes
36 of Intel's '810' and other chipsets. !! 37 6300ESB 0x25a4 32 hard yes yes yes
37 See the doc/busses/i2c-i801 file for detai !! 38 82801F (ICH6) 0x266a 32 hard yes yes yes
38 I2C Block Read and Process Call are not su !! 39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
>> 40 82801G (ICH7) 0x27da 32 hard yes yes yes
>> 41 82801H (ICH8) 0x283e 32 hard yes yes yes
>> 42 82801I (ICH9) 0x2930 32 hard yes yes yes
>> 43 Tolapai 0x5032 32 hard yes yes yes
>> 44 ICH10 0x3a30 32 hard yes yes yes
>> 45 ICH10 0x3a60 32 hard yes yes yes
>> 46
>> 47 Features supported by this driver:
>> 48 Software PEC no
>> 49 Hardware PEC yes
>> 50 Block buffer yes
>> 51 Block process call transaction no
>> 52 I2C block read transaction yes (doesn't use the block buffer)
>> 53
>> 54 See the file Documentation/i2c/busses/i2c-i801 for details.
39 */ 55 */
40 56
41 /* Note: we assume there can only be one I801, 57 /* Note: we assume there can only be one I801, with one SMBus interface */
42 58
43 #include <linux/config.h> <<
44 #include <linux/module.h> 59 #include <linux/module.h>
45 #include <linux/pci.h> 60 #include <linux/pci.h>
46 #include <linux/kernel.h> 61 #include <linux/kernel.h>
47 #include <linux/stddef.h> 62 #include <linux/stddef.h>
48 #include <linux/delay.h> 63 #include <linux/delay.h>
49 #include <linux/sched.h> <<
50 #include <linux/ioport.h> 64 #include <linux/ioport.h>
51 #include <linux/init.h> 65 #include <linux/init.h>
52 #include <linux/i2c.h> 66 #include <linux/i2c.h>
53 #include <asm/io.h> 67 #include <asm/io.h>
54 68
55 #ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC <<
56 #define HAVE_PEC <<
57 #endif <<
58 <<
59 /* I801 SMBus address offsets */ 69 /* I801 SMBus address offsets */
60 #define SMBHSTSTS (0 + i801_smba) 70 #define SMBHSTSTS (0 + i801_smba)
61 #define SMBHSTCNT (2 + i801_smba) 71 #define SMBHSTCNT (2 + i801_smba)
62 #define SMBHSTCMD (3 + i801_smba) 72 #define SMBHSTCMD (3 + i801_smba)
63 #define SMBHSTADD (4 + i801_smba) 73 #define SMBHSTADD (4 + i801_smba)
64 #define SMBHSTDAT0 (5 + i801_smba) 74 #define SMBHSTDAT0 (5 + i801_smba)
65 #define SMBHSTDAT1 (6 + i801_smba) 75 #define SMBHSTDAT1 (6 + i801_smba)
66 #define SMBBLKDAT (7 + i801_smba) 76 #define SMBBLKDAT (7 + i801_smba)
67 #define SMBPEC (8 + i801_smba) /* ICH !! 77 #define SMBPEC (8 + i801_smba) /* ICH3 and later */
68 #define SMBAUXSTS (12 + i801_smba) !! 78 #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
69 #define SMBAUXCTL (13 + i801_smba) !! 79 #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
70 80
71 /* PCI Address Constants */ 81 /* PCI Address Constants */
72 #define SMBBA 0x020 !! 82 #define SMBBAR 4
73 #define SMBHSTCFG 0x040 83 #define SMBHSTCFG 0x040
74 #define SMBREV 0x008 <<
75 84
76 /* Host configuration bits for SMBHSTCFG */ 85 /* Host configuration bits for SMBHSTCFG */
77 #define SMBHSTCFG_HST_EN 1 86 #define SMBHSTCFG_HST_EN 1
78 #define SMBHSTCFG_SMB_SMI_EN 2 87 #define SMBHSTCFG_SMB_SMI_EN 2
79 #define SMBHSTCFG_I2C_EN 4 88 #define SMBHSTCFG_I2C_EN 4
80 89
>> 90 /* Auxillary control register bits, ICH4+ only */
>> 91 #define SMBAUXCTL_CRC 1
>> 92 #define SMBAUXCTL_E32B 2
>> 93
>> 94 /* kill bit for SMBHSTCNT */
>> 95 #define SMBHSTCNT_KILL 2
>> 96
81 /* Other settings */ 97 /* Other settings */
82 #define MAX_TIMEOUT 100 98 #define MAX_TIMEOUT 100
83 #define ENABLE_INT9 0 /* set 99 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
84 100
85 /* I801 command constants */ 101 /* I801 command constants */
86 #define I801_QUICK 0x00 102 #define I801_QUICK 0x00
87 #define I801_BYTE 0x04 103 #define I801_BYTE 0x04
88 #define I801_BYTE_DATA 0x08 104 #define I801_BYTE_DATA 0x08
89 #define I801_WORD_DATA 0x0C 105 #define I801_WORD_DATA 0x0C
90 #define I801_PROC_CALL 0x10 /* lat !! 106 #define I801_PROC_CALL 0x10 /* unimplemented */
91 #define I801_BLOCK_DATA 0x14 107 #define I801_BLOCK_DATA 0x14
92 #define I801_I2C_BLOCK_DATA 0x18 /* uni !! 108 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
93 #define I801_BLOCK_LAST 0x34 109 #define I801_BLOCK_LAST 0x34
94 #define I801_I2C_BLOCK_LAST 0x38 /* uni !! 110 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
95 #define I801_START 0x40 111 #define I801_START 0x40
96 #define I801_PEC_EN 0x80 /* ICH !! 112 #define I801_PEC_EN 0x80 /* ICH3 and later */
97 <<
98 /* insmod parameters */ <<
99 <<
100 /* If force_addr is set to anything different <<
101 the I801 at the given address. VERY DANGERO <<
102 static u16 force_addr; <<
103 module_param(force_addr, ushort, 0); <<
104 MODULE_PARM_DESC(force_addr, <<
105 "Forcibly enable the I801 at <<
106 "EXTREMELY DANGEROUS!"); <<
107 <<
108 static int i801_transaction(void); <<
109 static int i801_block_transaction(union i2c_sm <<
110 char read_wr <<
111 113
112 static unsigned short i801_smba; !! 114 /* I801 Hosts Status register bits */
>> 115 #define SMBHSTSTS_BYTE_DONE 0x80
>> 116 #define SMBHSTSTS_INUSE_STS 0x40
>> 117 #define SMBHSTSTS_SMBALERT_STS 0x20
>> 118 #define SMBHSTSTS_FAILED 0x10
>> 119 #define SMBHSTSTS_BUS_ERR 0x08
>> 120 #define SMBHSTSTS_DEV_ERR 0x04
>> 121 #define SMBHSTSTS_INTR 0x02
>> 122 #define SMBHSTSTS_HOST_BUSY 0x01
>> 123
>> 124 static unsigned long i801_smba;
>> 125 static unsigned char i801_original_hstcfg;
>> 126 static struct pci_driver i801_driver;
113 static struct pci_dev *I801_dev; 127 static struct pci_dev *I801_dev;
114 static int isich4; <<
115 <<
116 static int i801_setup(struct pci_dev *dev) <<
117 { <<
118 int error_return = 0; <<
119 unsigned char temp; <<
120 <<
121 /* Note: we keep on searching until we <<
122 if(PCI_FUNC(dev->devfn) != 3) <<
123 return -ENODEV; <<
124 <<
125 I801_dev = dev; <<
126 if ((dev->device == PCI_DEVICE_ID_INTE <<
127 (dev->device == PCI_DEVICE_ID_INTE <<
128 (dev->device == PCI_DEVICE_ID_INTE <<
129 isich4 = 1; <<
130 else <<
131 isich4 = 0; <<
132 128
133 /* Determine the address of the SMBus !! 129 #define FEATURE_SMBUS_PEC (1 << 0)
134 if (force_addr) { !! 130 #define FEATURE_BLOCK_BUFFER (1 << 1)
135 i801_smba = force_addr & 0xfff !! 131 #define FEATURE_BLOCK_PROC (1 << 2)
136 } else { !! 132 #define FEATURE_I2C_BLOCK_READ (1 << 3)
137 pci_read_config_word(I801_dev, !! 133 static unsigned int i801_features;
138 i801_smba &= 0xfff0; <<
139 if(i801_smba == 0) { <<
140 dev_err(&dev->dev, "SM <<
141 "- upgrade BIO <<
142 return -ENODEV; <<
143 } <<
144 } <<
145 <<
146 if (!request_region(i801_smba, (isich4 <<
147 dev_err(&dev->dev, "I801_smb r <<
148 i801_smba); <<
149 error_return = -EBUSY; <<
150 goto END; <<
151 } <<
152 134
153 pci_read_config_byte(I801_dev, SMBHSTC !! 135 static int i801_transaction(int xact)
154 temp &= ~SMBHSTCFG_I2C_EN; /* SMB <<
155 pci_write_config_byte(I801_dev, SMBHST <<
156 <<
157 /* If force_addr is set, we program th <<
158 sure, we disable the device first. <<
159 if (force_addr) { <<
160 pci_write_config_byte(I801_dev <<
161 pci_write_config_word(I801_dev <<
162 pci_write_config_byte(I801_dev <<
163 dev_warn(&dev->dev, "WARNING: <<
164 "new address %04x!\n", <<
165 } else if ((temp & 1) == 0) { <<
166 pci_write_config_byte(I801_dev <<
167 dev_warn(&dev->dev, "enabling <<
168 } <<
169 <<
170 if (temp & 0x02) <<
171 dev_dbg(&dev->dev, "I801 using <<
172 else <<
173 dev_dbg(&dev->dev, "I801 using <<
174 <<
175 pci_read_config_byte(I801_dev, SMBREV, <<
176 dev_dbg(&dev->dev, "SMBREV = 0x%X\n", <<
177 dev_dbg(&dev->dev, "I801_smba = 0x%X\n <<
178 <<
179 END: <<
180 return error_return; <<
181 } <<
182 <<
183 static int i801_transaction(void) <<
184 { 136 {
185 int temp; 137 int temp;
186 int result = 0; 138 int result = 0;
187 int timeout = 0; 139 int timeout = 0;
188 140
189 dev_dbg(&I801_dev->dev, "Transaction ( !! 141 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
190 "ADD=%02x, DAT0=%02x, DAT1=%02 142 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
191 inb_p(SMBHSTCMD), inb_p(SMBHST 143 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
192 inb_p(SMBHSTDAT1)); 144 inb_p(SMBHSTDAT1));
193 145
194 /* Make sure the SMBus host is ready t 146 /* Make sure the SMBus host is ready to start transmitting */
195 /* 0x1f = Failed, Bus_Err, Dev_Err, In 147 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
196 if ((temp = (0x1f & inb_p(SMBHSTSTS))) 148 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
197 dev_dbg(&I801_dev->dev, "SMBus !! 149 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
198 temp); 150 temp);
199 outb_p(temp, SMBHSTSTS); 151 outb_p(temp, SMBHSTSTS);
200 if ((temp = (0x1f & inb_p(SMBH 152 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
201 dev_dbg(&I801_dev->dev 153 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
202 return -1; 154 return -1;
203 } else { 155 } else {
204 dev_dbg(&I801_dev->dev !! 156 dev_dbg(&I801_dev->dev, "Successful!\n");
205 } 157 }
206 } 158 }
207 159
208 outb_p(inb(SMBHSTCNT) | I801_START, SM !! 160 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
>> 161 * INTREN, SMBSCMD are passed in xact */
>> 162 outb_p(xact | I801_START, SMBHSTCNT);
209 163
210 /* We will always wait for a fraction 164 /* We will always wait for a fraction of a second! */
211 do { 165 do {
212 msleep(1); 166 msleep(1);
213 temp = inb_p(SMBHSTSTS); 167 temp = inb_p(SMBHSTSTS);
214 } while ((temp & 0x01) && (timeout++ < !! 168 } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
215 169
216 /* If the SMBus is still busy, we give 170 /* If the SMBus is still busy, we give up */
217 if (timeout >= MAX_TIMEOUT) { 171 if (timeout >= MAX_TIMEOUT) {
218 dev_dbg(&I801_dev->dev, "SMBus 172 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
219 result = -1; 173 result = -1;
>> 174 /* try to stop the current command */
>> 175 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
>> 176 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
>> 177 msleep(1);
>> 178 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
220 } 179 }
221 180
222 if (temp & 0x10) { !! 181 if (temp & SMBHSTSTS_FAILED) {
223 result = -1; 182 result = -1;
224 dev_dbg(&I801_dev->dev, "Error 183 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
225 } 184 }
226 185
227 if (temp & 0x08) { !! 186 if (temp & SMBHSTSTS_BUS_ERR) {
228 result = -1; 187 result = -1;
229 dev_err(&I801_dev->dev, "Bus c 188 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
230 "until next hard reset 189 "until next hard reset. (sorry!)\n");
231 /* Clock stops and slave is st 190 /* Clock stops and slave is stuck in mid-transmission */
232 } 191 }
233 192
234 if (temp & 0x04) { !! 193 if (temp & SMBHSTSTS_DEV_ERR) {
235 result = -1; 194 result = -1;
236 dev_dbg(&I801_dev->dev, "Error 195 dev_dbg(&I801_dev->dev, "Error: no response!\n");
237 } 196 }
238 197
239 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00) 198 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
240 outb_p(inb(SMBHSTSTS), SMBHSTS 199 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
241 200
242 if ((temp = (0x1f & inb_p(SMBHSTSTS))) 201 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
243 dev_dbg(&I801_dev->dev, "Faile !! 202 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
244 "(%02x)\n", temp); 203 "(%02x)\n", temp);
245 } 204 }
246 dev_dbg(&I801_dev->dev, "Transaction ( 205 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
247 "ADD=%02x, DAT0=%02x, DAT1=%02 206 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
248 inb_p(SMBHSTCMD), inb_p(SMBHST 207 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
249 inb_p(SMBHSTDAT1)); 208 inb_p(SMBHSTDAT1));
250 return result; 209 return result;
251 } 210 }
252 211
253 /* All-inclusive block transaction function */ !! 212 /* wait for INTR bit as advised by Intel */
254 static int i801_block_transaction(union i2c_sm !! 213 static void i801_wait_hwpec(void)
255 int command) !! 214 {
>> 215 int timeout = 0;
>> 216 int temp;
>> 217
>> 218 do {
>> 219 msleep(1);
>> 220 temp = inb_p(SMBHSTSTS);
>> 221 } while ((!(temp & SMBHSTSTS_INTR))
>> 222 && (timeout++ < MAX_TIMEOUT));
>> 223
>> 224 if (timeout >= MAX_TIMEOUT) {
>> 225 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
>> 226 }
>> 227 outb_p(temp, SMBHSTSTS);
>> 228 }
>> 229
>> 230 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
>> 231 char read_write, int hwpec)
>> 232 {
>> 233 int i, len;
>> 234
>> 235 inb_p(SMBHSTCNT); /* reset the data buffer index */
>> 236
>> 237 /* Use 32-byte buffer to process this transaction */
>> 238 if (read_write == I2C_SMBUS_WRITE) {
>> 239 len = data->block[0];
>> 240 outb_p(len, SMBHSTDAT0);
>> 241 for (i = 0; i < len; i++)
>> 242 outb_p(data->block[i+1], SMBBLKDAT);
>> 243 }
>> 244
>> 245 if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
>> 246 I801_PEC_EN * hwpec))
>> 247 return -1;
>> 248
>> 249 if (read_write == I2C_SMBUS_READ) {
>> 250 len = inb_p(SMBHSTDAT0);
>> 251 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
>> 252 return -1;
>> 253
>> 254 data->block[0] = len;
>> 255 for (i = 0; i < len; i++)
>> 256 data->block[i + 1] = inb_p(SMBBLKDAT);
>> 257 }
>> 258 return 0;
>> 259 }
>> 260
>> 261 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
>> 262 char read_write, int command,
>> 263 int hwpec)
256 { 264 {
257 int i, len; 265 int i, len;
258 int smbcmd; 266 int smbcmd;
259 int temp; 267 int temp;
260 int result = 0; 268 int result = 0;
261 int timeout; 269 int timeout;
262 unsigned char hostc, errmask; !! 270 unsigned char errmask;
263 271
264 if (command == I2C_SMBUS_I2C_BLOCK_DAT !! 272 len = data->block[0];
265 if (read_write == I2C_SMBUS_WR <<
266 /* set I2C_EN bit in c <<
267 pci_read_config_byte(I <<
268 pci_write_config_byte( <<
269 <<
270 } else { <<
271 dev_err(&I801_dev->dev <<
272 "I2C_SMBUS_I2C <<
273 return -1; <<
274 } <<
275 } <<
276 273
277 if (read_write == I2C_SMBUS_WRITE) { 274 if (read_write == I2C_SMBUS_WRITE) {
278 len = data->block[0]; <<
279 if (len < 1) <<
280 len = 1; <<
281 if (len > 32) <<
282 len = 32; <<
283 outb_p(len, SMBHSTDAT0); 275 outb_p(len, SMBHSTDAT0);
284 outb_p(data->block[1], SMBBLKD 276 outb_p(data->block[1], SMBBLKDAT);
285 } else { <<
286 len = 32; /* max for rea <<
287 } <<
288 <<
289 if(isich4 && command != I2C_SMBUS_I2C_ <<
290 /* set 32 byte buffer */ <<
291 } 277 }
292 278
293 for (i = 1; i <= len; i++) { 279 for (i = 1; i <= len; i++) {
294 if (i == len && read_write == !! 280 if (i == len && read_write == I2C_SMBUS_READ) {
295 smbcmd = I801_BLOCK_LA !! 281 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
296 else !! 282 smbcmd = I801_I2C_BLOCK_LAST;
297 smbcmd = I801_BLOCK_DA !! 283 else
>> 284 smbcmd = I801_BLOCK_LAST;
>> 285 } else {
>> 286 if (command == I2C_SMBUS_I2C_BLOCK_DATA
>> 287 && read_write == I2C_SMBUS_READ)
>> 288 smbcmd = I801_I2C_BLOCK_DATA;
>> 289 else
>> 290 smbcmd = I801_BLOCK_DATA;
>> 291 }
298 outb_p(smbcmd | ENABLE_INT9, S 292 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
299 293
300 dev_dbg(&I801_dev->dev, "Block 294 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
301 "ADD=%02x, DAT0=%02x, !! 295 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
302 inb_p(SMBHSTCNT), inb_ 296 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
303 inb_p(SMBHSTDAT0), inb !! 297 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
304 298
305 /* Make sure the SMBus host is 299 /* Make sure the SMBus host is ready to start transmitting */
306 temp = inb_p(SMBHSTSTS); 300 temp = inb_p(SMBHSTSTS);
307 if (i == 1) { 301 if (i == 1) {
308 /* Erronenous conditio !! 302 /* Erroneous conditions before transaction:
309 * Byte_Done, Failed, 303 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
310 errmask=0x9f; !! 304 errmask = 0x9f;
311 } else { 305 } else {
312 /* Erronenous conditio !! 306 /* Erroneous conditions during transaction:
313 * Failed, Bus_Err, De 307 * Failed, Bus_Err, Dev_Err, Intr */
314 errmask=0x1e; !! 308 errmask = 0x1e;
315 } 309 }
316 if (temp & errmask) { 310 if (temp & errmask) {
317 dev_dbg(&I801_dev->dev 311 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
318 "Resetting... !! 312 "Resetting...\n", temp);
319 outb_p(temp, SMBHSTSTS 313 outb_p(temp, SMBHSTSTS);
320 if (((temp = inb_p(SMB 314 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
321 dev_err(&I801_ 315 dev_err(&I801_dev->dev,
322 "Reset 316 "Reset failed! (%02x)\n", temp);
323 result = -1; !! 317 return -1;
324 goto END; <<
325 } 318 }
326 if (i != 1) { !! 319 if (i != 1)
327 /* if die in m 320 /* if die in middle of block transaction, fail */
328 result = -1; !! 321 return -1;
329 goto END; <<
330 } <<
331 } 322 }
332 323
333 if (i == 1) 324 if (i == 1)
334 outb_p(inb(SMBHSTCNT) 325 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
335 326
336 /* We will always wait for a f 327 /* We will always wait for a fraction of a second! */
337 timeout = 0; 328 timeout = 0;
338 do { 329 do {
339 temp = inb_p(SMBHSTSTS <<
340 msleep(1); 330 msleep(1);
>> 331 temp = inb_p(SMBHSTSTS);
341 } 332 }
342 while ((!(temp & 0x80)) !! 333 while ((!(temp & SMBHSTSTS_BYTE_DONE))
343 && (timeout++ < MAX !! 334 && (timeout++ < MAX_TIMEOUT));
344 335
345 /* If the SMBus is still busy, 336 /* If the SMBus is still busy, we give up */
346 if (timeout >= MAX_TIMEOUT) { 337 if (timeout >= MAX_TIMEOUT) {
>> 338 /* try to stop the current command */
>> 339 dev_dbg(&I801_dev->dev, "Terminating the current "
>> 340 "operation\n");
>> 341 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
>> 342 msleep(1);
>> 343 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
>> 344 SMBHSTCNT);
347 result = -1; 345 result = -1;
348 dev_dbg(&I801_dev->dev 346 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
349 } 347 }
350 348
351 if (temp & 0x10) { !! 349 if (temp & SMBHSTSTS_FAILED) {
352 result = -1; 350 result = -1;
353 dev_dbg(&I801_dev->dev 351 dev_dbg(&I801_dev->dev,
354 "Error: Failed 352 "Error: Failed bus transaction\n");
355 } else if (temp & 0x08) { !! 353 } else if (temp & SMBHSTSTS_BUS_ERR) {
356 result = -1; 354 result = -1;
357 dev_err(&I801_dev->dev 355 dev_err(&I801_dev->dev, "Bus collision!\n");
358 } else if (temp & 0x04) { !! 356 } else if (temp & SMBHSTSTS_DEV_ERR) {
359 result = -1; 357 result = -1;
360 dev_dbg(&I801_dev->dev 358 dev_dbg(&I801_dev->dev, "Error: no response!\n");
361 } 359 }
362 360
363 if (i == 1 && read_write == I2 !! 361 if (i == 1 && read_write == I2C_SMBUS_READ
>> 362 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
364 len = inb_p(SMBHSTDAT0 363 len = inb_p(SMBHSTDAT0);
365 if (len < 1) !! 364 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
366 len = 1; !! 365 return -1;
367 if (len > 32) <<
368 len = 32; <<
369 data->block[0] = len; 366 data->block[0] = len;
370 } 367 }
371 368
372 /* Retrieve/store value in SMB 369 /* Retrieve/store value in SMBBLKDAT */
373 if (read_write == I2C_SMBUS_RE 370 if (read_write == I2C_SMBUS_READ)
374 data->block[i] = inb_p 371 data->block[i] = inb_p(SMBBLKDAT);
375 if (read_write == I2C_SMBUS_WR 372 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
376 outb_p(data->block[i+1 373 outb_p(data->block[i+1], SMBBLKDAT);
377 if ((temp & 0x9e) != 0x00) 374 if ((temp & 0x9e) != 0x00)
378 outb_p(temp, SMBHSTSTS 375 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
379 376
380 if ((temp = (0x1e & inb_p(SMBH 377 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
381 dev_dbg(&I801_dev->dev 378 dev_dbg(&I801_dev->dev,
382 "Bad status (% 379 "Bad status (%02x) at end of transaction\n",
383 temp); 380 temp);
384 } 381 }
385 dev_dbg(&I801_dev->dev, "Block 382 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
386 "ADD=%02x, DAT0=%02x, !! 383 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
387 inb_p(SMBHSTCNT), inb_ 384 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
388 inb_p(SMBHSTDAT0), inb !! 385 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
389 386
390 if (result < 0) 387 if (result < 0)
391 goto END; !! 388 return result;
392 } 389 }
>> 390 return result;
>> 391 }
393 392
394 #ifdef HAVE_PEC !! 393 static int i801_set_block_buffer_mode(void)
395 if(isich4 && command == I2C_SMBUS_BLOC !! 394 {
396 /* wait for INTR bit as advise !! 395 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
397 timeout = 0; !! 396 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
398 do { !! 397 return -1;
399 temp = inb_p(SMBHSTSTS !! 398 return 0;
400 msleep(1); !! 399 }
401 } while ((!(temp & 0x02)) <<
402 && (timeout++ < MAX <<
403 400
404 if (timeout >= MAX_TIMEOUT) { !! 401 /* Block transaction function */
405 dev_dbg(&I801_dev->dev !! 402 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
>> 403 int command, int hwpec)
>> 404 {
>> 405 int result = 0;
>> 406 unsigned char hostc;
>> 407
>> 408 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
>> 409 if (read_write == I2C_SMBUS_WRITE) {
>> 410 /* set I2C_EN bit in configuration register */
>> 411 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
>> 412 pci_write_config_byte(I801_dev, SMBHSTCFG,
>> 413 hostc | SMBHSTCFG_I2C_EN);
>> 414 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
>> 415 dev_err(&I801_dev->dev,
>> 416 "I2C block read is unsupported!\n");
>> 417 return -1;
406 } 418 }
407 outb_p(temp, SMBHSTSTS); <<
408 } 419 }
409 #endif !! 420
410 result = 0; !! 421 if (read_write == I2C_SMBUS_WRITE
411 END: !! 422 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
412 if (command == I2C_SMBUS_I2C_BLOCK_DAT !! 423 if (data->block[0] < 1)
>> 424 data->block[0] = 1;
>> 425 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
>> 426 data->block[0] = I2C_SMBUS_BLOCK_MAX;
>> 427 } else {
>> 428 data->block[0] = 32; /* max for SMBus block reads */
>> 429 }
>> 430
>> 431 if ((i801_features & FEATURE_BLOCK_BUFFER)
>> 432 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
>> 433 && read_write == I2C_SMBUS_READ)
>> 434 && i801_set_block_buffer_mode() == 0)
>> 435 result = i801_block_transaction_by_block(data, read_write,
>> 436 hwpec);
>> 437 else
>> 438 result = i801_block_transaction_byte_by_byte(data, read_write,
>> 439 command, hwpec);
>> 440
>> 441 if (result == 0 && hwpec)
>> 442 i801_wait_hwpec();
>> 443
>> 444 if (command == I2C_SMBUS_I2C_BLOCK_DATA
>> 445 && read_write == I2C_SMBUS_WRITE) {
413 /* restore saved configuration 446 /* restore saved configuration register value */
414 pci_write_config_byte(I801_dev 447 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
415 } 448 }
416 return result; 449 return result;
417 } 450 }
418 451
419 /* Return -1 on error. */ 452 /* Return -1 on error. */
420 static s32 i801_access(struct i2c_adapter * ad 453 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
421 unsigned short flags, c 454 unsigned short flags, char read_write, u8 command,
422 int size, union i2c_smb 455 int size, union i2c_smbus_data * data)
423 { 456 {
424 int hwpec = 0; !! 457 int hwpec;
425 int block = 0; 458 int block = 0;
426 int ret, xact = 0; 459 int ret, xact = 0;
427 460
428 #ifdef HAVE_PEC !! 461 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
429 if(isich4) !! 462 && size != I2C_SMBUS_QUICK
430 hwpec = (flags & I2C_CLIENT_PE !! 463 && size != I2C_SMBUS_I2C_BLOCK_DATA;
431 #endif <<
432 464
433 switch (size) { 465 switch (size) {
434 case I2C_SMBUS_QUICK: 466 case I2C_SMBUS_QUICK:
435 outb_p(((addr & 0x7f) << 1) | 467 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
436 SMBHSTADD); 468 SMBHSTADD);
437 xact = I801_QUICK; 469 xact = I801_QUICK;
438 break; 470 break;
439 case I2C_SMBUS_BYTE: 471 case I2C_SMBUS_BYTE:
440 outb_p(((addr & 0x7f) << 1) | 472 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
441 SMBHSTADD); 473 SMBHSTADD);
442 if (read_write == I2C_SMBUS_WR 474 if (read_write == I2C_SMBUS_WRITE)
443 outb_p(command, SMBHST 475 outb_p(command, SMBHSTCMD);
444 xact = I801_BYTE; 476 xact = I801_BYTE;
445 break; 477 break;
446 case I2C_SMBUS_BYTE_DATA: 478 case I2C_SMBUS_BYTE_DATA:
447 outb_p(((addr & 0x7f) << 1) | 479 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
448 SMBHSTADD); 480 SMBHSTADD);
449 outb_p(command, SMBHSTCMD); 481 outb_p(command, SMBHSTCMD);
450 if (read_write == I2C_SMBUS_WR 482 if (read_write == I2C_SMBUS_WRITE)
451 outb_p(data->byte, SMB 483 outb_p(data->byte, SMBHSTDAT0);
452 xact = I801_BYTE_DATA; 484 xact = I801_BYTE_DATA;
453 break; 485 break;
454 case I2C_SMBUS_WORD_DATA: 486 case I2C_SMBUS_WORD_DATA:
455 outb_p(((addr & 0x7f) << 1) | 487 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
456 SMBHSTADD); 488 SMBHSTADD);
457 outb_p(command, SMBHSTCMD); 489 outb_p(command, SMBHSTCMD);
458 if (read_write == I2C_SMBUS_WR 490 if (read_write == I2C_SMBUS_WRITE) {
459 outb_p(data->word & 0x 491 outb_p(data->word & 0xff, SMBHSTDAT0);
460 outb_p((data->word & 0 492 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
461 } 493 }
462 xact = I801_WORD_DATA; 494 xact = I801_WORD_DATA;
463 break; 495 break;
464 case I2C_SMBUS_BLOCK_DATA: 496 case I2C_SMBUS_BLOCK_DATA:
465 case I2C_SMBUS_I2C_BLOCK_DATA: <<
466 #ifdef HAVE_PEC <<
467 case I2C_SMBUS_BLOCK_DATA_PEC: <<
468 if(hwpec && size == I2C_SMBUS_ <<
469 size = I2C_SMBUS_BLOCK <<
470 #endif <<
471 outb_p(((addr & 0x7f) << 1) | 497 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
472 SMBHSTADD); 498 SMBHSTADD);
473 outb_p(command, SMBHSTCMD); 499 outb_p(command, SMBHSTCMD);
474 block = 1; 500 block = 1;
475 break; 501 break;
>> 502 case I2C_SMBUS_I2C_BLOCK_DATA:
>> 503 /* NB: page 240 of ICH5 datasheet shows that the R/#W
>> 504 * bit should be cleared here, even when reading */
>> 505 outb_p((addr & 0x7f) << 1, SMBHSTADD);
>> 506 if (read_write == I2C_SMBUS_READ) {
>> 507 /* NB: page 240 of ICH5 datasheet also shows
>> 508 * that DATA1 is the cmd field when reading */
>> 509 outb_p(command, SMBHSTDAT1);
>> 510 } else
>> 511 outb_p(command, SMBHSTCMD);
>> 512 block = 1;
>> 513 break;
476 case I2C_SMBUS_PROC_CALL: 514 case I2C_SMBUS_PROC_CALL:
477 default: 515 default:
478 dev_err(&I801_dev->dev, "Unsup 516 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
479 return -1; 517 return -1;
480 } 518 }
481 519
482 #ifdef HAVE_PEC !! 520 if (hwpec) /* enable/disable hardware PEC */
483 if(isich4 && hwpec) { !! 521 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
484 if(size != I2C_SMBUS_QUICK && !! 522 else
485 size != I2C_SMBUS_I2C_BLOCK !! 523 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
486 outb_p(1, SMBAUXCTL); !! 524
487 } <<
488 #endif <<
489 if(block) 525 if(block)
490 ret = i801_block_transaction(d !! 526 ret = i801_block_transaction(data, read_write, size, hwpec);
491 else { !! 527 else
492 outb_p(xact | ENABLE_INT9, SMB !! 528 ret = i801_transaction(xact | ENABLE_INT9);
493 ret = i801_transaction(); <<
494 } <<
495 529
496 #ifdef HAVE_PEC !! 530 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
497 if(isich4 && hwpec) { !! 531 time, so we forcibly disable it after every transaction. Turn off
498 if(size != I2C_SMBUS_QUICK && !! 532 E32B for the same reason. */
499 size != I2C_SMBUS_I2C_BLOCK !! 533 if (hwpec || block)
500 outb_p(0, SMBAUXCTL); !! 534 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
501 } !! 535 SMBAUXCTL);
502 #endif <<
503 536
504 if(block) 537 if(block)
505 return ret; 538 return ret;
506 if(ret) 539 if(ret)
507 return -1; 540 return -1;
508 if ((read_write == I2C_SMBUS_WRITE) || 541 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
509 return 0; 542 return 0;
510 543
511 switch (xact & 0x7f) { 544 switch (xact & 0x7f) {
512 case I801_BYTE: /* Result put in SMBHS 545 case I801_BYTE: /* Result put in SMBHSTDAT0 */
513 case I801_BYTE_DATA: 546 case I801_BYTE_DATA:
514 data->byte = inb_p(SMBHSTDAT0) 547 data->byte = inb_p(SMBHSTDAT0);
515 break; 548 break;
516 case I801_WORD_DATA: 549 case I801_WORD_DATA:
517 data->word = inb_p(SMBHSTDAT0) 550 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
518 break; 551 break;
519 } 552 }
520 return 0; 553 return 0;
521 } 554 }
522 555
523 556
524 static u32 i801_func(struct i2c_adapter *adapt 557 static u32 i801_func(struct i2c_adapter *adapter)
525 { 558 {
526 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC 559 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
527 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUN !! 560 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
528 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FU !! 561 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
529 #ifdef HAVE_PEC !! 562 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
530 | (isich4 ? I2C_FUNC_SMBUS_BLOCK_ !! 563 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
531 I2C_FUNC_SMBUS_HWPEC_ !! 564 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
532 : 0) <<
533 #endif <<
534 ; <<
535 } 565 }
536 566
537 static struct i2c_algorithm smbus_algorithm = !! 567 static const struct i2c_algorithm smbus_algorithm = {
538 .name = "Non-I2C SMBus adapt <<
539 .id = I2C_ALGO_SMBUS, <<
540 .smbus_xfer = i801_access, 568 .smbus_xfer = i801_access,
541 .functionality = i801_func, 569 .functionality = i801_func,
542 }; 570 };
543 571
544 static struct i2c_adapter i801_adapter = { 572 static struct i2c_adapter i801_adapter = {
545 .owner = THIS_MODULE, 573 .owner = THIS_MODULE,
>> 574 .id = I2C_HW_SMBUS_I801,
546 .class = I2C_CLASS_HWMON, 575 .class = I2C_CLASS_HWMON,
547 .algo = &smbus_algorithm, 576 .algo = &smbus_algorithm,
548 .name = "unset", <<
549 }; 577 };
550 578
551 static struct pci_device_id i801_ids[] = { 579 static struct pci_device_id i801_ids[] = {
552 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
553 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
554 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
555 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
556 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
557 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 585 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
558 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 586 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
559 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 587 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
560 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ 588 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
>> 589 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
>> 590 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
>> 591 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
>> 592 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
>> 593 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
>> 594 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
561 { 0, } 595 { 0, }
562 }; 596 };
563 597
564 MODULE_DEVICE_TABLE (pci, i801_ids); 598 MODULE_DEVICE_TABLE (pci, i801_ids);
565 599
566 static int __devinit i801_probe(struct pci_dev 600 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
567 { 601 {
>> 602 unsigned char temp;
>> 603 int err;
>> 604
>> 605 I801_dev = dev;
>> 606 i801_features = 0;
>> 607 switch (dev->device) {
>> 608 case PCI_DEVICE_ID_INTEL_82801EB_3:
>> 609 case PCI_DEVICE_ID_INTEL_ESB_4:
>> 610 case PCI_DEVICE_ID_INTEL_ICH6_16:
>> 611 case PCI_DEVICE_ID_INTEL_ICH7_17:
>> 612 case PCI_DEVICE_ID_INTEL_ESB2_17:
>> 613 case PCI_DEVICE_ID_INTEL_ICH8_5:
>> 614 case PCI_DEVICE_ID_INTEL_ICH9_6:
>> 615 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
>> 616 case PCI_DEVICE_ID_INTEL_ICH10_4:
>> 617 case PCI_DEVICE_ID_INTEL_ICH10_5:
>> 618 i801_features |= FEATURE_I2C_BLOCK_READ;
>> 619 /* fall through */
>> 620 case PCI_DEVICE_ID_INTEL_82801DB_3:
>> 621 i801_features |= FEATURE_SMBUS_PEC;
>> 622 i801_features |= FEATURE_BLOCK_BUFFER;
>> 623 break;
>> 624 }
568 625
569 if (i801_setup(dev)) { !! 626 err = pci_enable_device(dev);
570 dev_warn(&dev->dev, !! 627 if (err) {
571 "I801 not detected, mo !! 628 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
572 return -ENODEV; !! 629 err);
>> 630 goto exit;
>> 631 }
>> 632
>> 633 /* Determine the address of the SMBus area */
>> 634 i801_smba = pci_resource_start(dev, SMBBAR);
>> 635 if (!i801_smba) {
>> 636 dev_err(&dev->dev, "SMBus base address uninitialized, "
>> 637 "upgrade BIOS\n");
>> 638 err = -ENODEV;
>> 639 goto exit;
>> 640 }
>> 641
>> 642 err = pci_request_region(dev, SMBBAR, i801_driver.name);
>> 643 if (err) {
>> 644 dev_err(&dev->dev, "Failed to request SMBus region "
>> 645 "0x%lx-0x%Lx\n", i801_smba,
>> 646 (unsigned long long)pci_resource_end(dev, SMBBAR));
>> 647 goto exit;
573 } 648 }
574 649
575 /* set up the driverfs linkage to our !! 650 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
>> 651 i801_original_hstcfg = temp;
>> 652 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
>> 653 if (!(temp & SMBHSTCFG_HST_EN)) {
>> 654 dev_info(&dev->dev, "Enabling SMBus device\n");
>> 655 temp |= SMBHSTCFG_HST_EN;
>> 656 }
>> 657 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
>> 658
>> 659 if (temp & SMBHSTCFG_SMB_SMI_EN)
>> 660 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
>> 661 else
>> 662 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
>> 663
>> 664 /* Clear special mode bits */
>> 665 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
>> 666 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
>> 667 SMBAUXCTL);
>> 668
>> 669 /* set up the sysfs linkage to our parent device */
576 i801_adapter.dev.parent = &dev->dev; 670 i801_adapter.dev.parent = &dev->dev;
577 671
578 snprintf(i801_adapter.name, I2C_NAME_S !! 672 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
579 "SMBus I801 adapter at %04x", !! 673 "SMBus I801 adapter at %04lx", i801_smba);
580 return i2c_add_adapter(&i801_adapter); !! 674 err = i2c_add_adapter(&i801_adapter);
>> 675 if (err) {
>> 676 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
>> 677 goto exit_release;
>> 678 }
>> 679 return 0;
>> 680
>> 681 exit_release:
>> 682 pci_release_region(dev, SMBBAR);
>> 683 exit:
>> 684 return err;
581 } 685 }
582 686
583 static void __devexit i801_remove(struct pci_d 687 static void __devexit i801_remove(struct pci_dev *dev)
584 { 688 {
585 i2c_del_adapter(&i801_adapter); 689 i2c_del_adapter(&i801_adapter);
586 release_region(i801_smba, (isich4 ? 16 !! 690 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
>> 691 pci_release_region(dev, SMBBAR);
>> 692 /*
>> 693 * do not call pci_disable_device(dev) since it can cause hard hangs on
>> 694 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
>> 695 */
>> 696 }
>> 697
>> 698 #ifdef CONFIG_PM
>> 699 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
>> 700 {
>> 701 pci_save_state(dev);
>> 702 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
>> 703 pci_set_power_state(dev, pci_choose_state(dev, mesg));
>> 704 return 0;
587 } 705 }
588 706
>> 707 static int i801_resume(struct pci_dev *dev)
>> 708 {
>> 709 pci_set_power_state(dev, PCI_D0);
>> 710 pci_restore_state(dev);
>> 711 return pci_enable_device(dev);
>> 712 }
>> 713 #else
>> 714 #define i801_suspend NULL
>> 715 #define i801_resume NULL
>> 716 #endif
>> 717
589 static struct pci_driver i801_driver = { 718 static struct pci_driver i801_driver = {
590 .name = "i801_smbus", 719 .name = "i801_smbus",
591 .id_table = i801_ids, 720 .id_table = i801_ids,
592 .probe = i801_probe, 721 .probe = i801_probe,
593 .remove = __devexit_p(i801_rem 722 .remove = __devexit_p(i801_remove),
>> 723 .suspend = i801_suspend,
>> 724 .resume = i801_resume,
594 }; 725 };
595 726
596 static int __init i2c_i801_init(void) 727 static int __init i2c_i801_init(void)
597 { 728 {
598 return pci_register_driver(&i801_drive 729 return pci_register_driver(&i801_driver);
599 } 730 }
600 731
601 static void __exit i2c_i801_exit(void) 732 static void __exit i2c_i801_exit(void)
602 { 733 {
603 pci_unregister_driver(&i801_driver); 734 pci_unregister_driver(&i801_driver);
604 } 735 }
605 736
606 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl !! 737 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
607 "Philip Edelbrock <phil@netroe !! 738 "Jean Delvare <khali@linux-fr.org>");
608 "and Mark D. Studebaker <mdsxy <<
609 MODULE_DESCRIPTION("I801 SMBus driver"); 739 MODULE_DESCRIPTION("I801 SMBus driver");
610 MODULE_LICENSE("GPL"); 740 MODULE_LICENSE("GPL");
611 741
612 module_init(i2c_i801_init); 742 module_init(i2c_i801_init);
613 module_exit(i2c_i801_exit); 743 module_exit(i2c_i801_exit);
614 744
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