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1 /* 1 /*
2 * offload engine driver for the Intel Xscale 2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation. 3 * Copyright © 2006, Intel Corporation.
4 * 4 *
5 * This program is free software; you can redi 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU G 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Softwar 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it 9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warr 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Sof 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 */ 18 */
19 19
20 /* 20 /*
21 * This driver supports the asynchrounous DMA 21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Proces 22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */ 23 */
24 24
25 #include <linux/init.h> 25 #include <linux/init.h>
26 #include <linux/module.h> 26 #include <linux/module.h>
27 #include <linux/async_tx.h> <<
28 #include <linux/delay.h> 27 #include <linux/delay.h>
29 #include <linux/dma-mapping.h> 28 #include <linux/dma-mapping.h>
30 #include <linux/spinlock.h> 29 #include <linux/spinlock.h>
31 #include <linux/interrupt.h> 30 #include <linux/interrupt.h>
32 #include <linux/platform_device.h> 31 #include <linux/platform_device.h>
33 #include <linux/memory.h> 32 #include <linux/memory.h>
34 #include <linux/ioport.h> 33 #include <linux/ioport.h>
35 34
36 #include <asm/arch/adma.h> !! 35 #include <mach/adma.h>
37 36
38 #define to_iop_adma_chan(chan) container_of(ch 37 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \ 38 #define to_iop_adma_device(dev) \
40 container_of(dev, struct iop_adma_devi 39 container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \ 40 #define tx_to_iop_adma_slot(tx) \
42 container_of(tx, struct iop_adma_desc_ 41 container_of(tx, struct iop_adma_desc_slot, async_tx)
43 42
44 /** 43 /**
45 * iop_adma_free_slots - flags descriptor slot 44 * iop_adma_free_slots - flags descriptor slots for reuse
46 * @slot: Slot to free 45 * @slot: Slot to free
47 * Caller must hold &iop_chan->lock while call 46 * Caller must hold &iop_chan->lock while calling this function
48 */ 47 */
49 static void iop_adma_free_slots(struct iop_adm 48 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 { 49 {
51 int stride = slot->slots_per_op; 50 int stride = slot->slots_per_op;
52 51
53 while (stride--) { 52 while (stride--) {
54 slot->slots_per_op = 0; 53 slot->slots_per_op = 0;
55 slot = list_entry(slot->slot_n 54 slot = list_entry(slot->slot_node.next,
56 struct iop_adm 55 struct iop_adma_desc_slot,
57 slot_node); 56 slot_node);
58 } 57 }
59 } 58 }
60 59
61 static dma_cookie_t 60 static dma_cookie_t
62 iop_adma_run_tx_complete_actions(struct iop_ad 61 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
63 struct iop_adma_chan *iop_chan, dma_co 62 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 { 63 {
65 BUG_ON(desc->async_tx.cookie < 0); 64 BUG_ON(desc->async_tx.cookie < 0);
66 spin_lock_bh(&desc->async_tx.lock); <<
67 if (desc->async_tx.cookie > 0) { 65 if (desc->async_tx.cookie > 0) {
68 cookie = desc->async_tx.cookie 66 cookie = desc->async_tx.cookie;
69 desc->async_tx.cookie = 0; 67 desc->async_tx.cookie = 0;
70 68
71 /* call the callback (must not 69 /* call the callback (must not sleep or submit new
72 * operations to this channel) 70 * operations to this channel)
73 */ 71 */
74 if (desc->async_tx.callback) 72 if (desc->async_tx.callback)
75 desc->async_tx.callbac 73 desc->async_tx.callback(
76 desc->async_tx 74 desc->async_tx.callback_param);
77 75
78 /* unmap dma addresses 76 /* unmap dma addresses
79 * (unmap_single vs unmap_page 77 * (unmap_single vs unmap_page?)
80 */ 78 */
81 if (desc->group_head && desc-> 79 if (desc->group_head && desc->unmap_len) {
82 struct iop_adma_desc_s 80 struct iop_adma_desc_slot *unmap = desc->group_head;
83 struct device *dev = 81 struct device *dev =
84 &iop_chan->dev 82 &iop_chan->device->pdev->dev;
85 u32 len = unmap->unmap 83 u32 len = unmap->unmap_len;
86 u32 src_cnt = unmap->u !! 84 enum dma_ctrl_flags flags = desc->async_tx.flags;
87 dma_addr_t addr = iop_ !! 85 u32 src_cnt;
88 iop_chan); !! 86 dma_addr_t addr;
89 !! 87 dma_addr_t dest;
90 dma_unmap_page(dev, ad !! 88
91 while (src_cnt--) { !! 89 src_cnt = unmap->unmap_src_cnt;
92 addr = iop_des !! 90 dest = iop_desc_get_dest_addr(unmap, iop_chan);
93 !! 91 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
94 !! 92 enum dma_data_direction dir;
95 dma_unmap_page !! 93
96 DMA_TO !! 94 if (src_cnt > 1) /* is xor? */
>> 95 dir = DMA_BIDIRECTIONAL;
>> 96 else
>> 97 dir = DMA_FROM_DEVICE;
>> 98
>> 99 dma_unmap_page(dev, dest, len, dir);
>> 100 }
>> 101
>> 102 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
>> 103 while (src_cnt--) {
>> 104 addr = iop_desc_get_src_addr(unmap,
>> 105 iop_chan,
>> 106 src_cnt);
>> 107 if (addr == dest)
>> 108 continue;
>> 109 dma_unmap_page(dev, addr, len,
>> 110 DMA_TO_DEVICE);
>> 111 }
97 } 112 }
98 desc->group_head = NUL 113 desc->group_head = NULL;
99 } 114 }
100 } 115 }
101 116
102 /* run dependent operations */ 117 /* run dependent operations */
103 async_tx_run_dependencies(&desc->async !! 118 dma_run_dependencies(&desc->async_tx);
104 spin_unlock_bh(&desc->async_tx.lock); <<
105 119
106 return cookie; 120 return cookie;
107 } 121 }
108 122
109 static int 123 static int
110 iop_adma_clean_slot(struct iop_adma_desc_slot 124 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
111 struct iop_adma_chan *iop_chan) 125 struct iop_adma_chan *iop_chan)
112 { 126 {
113 /* the client is allowed to attach dep 127 /* the client is allowed to attach dependent operations
114 * until 'ack' is set 128 * until 'ack' is set
115 */ 129 */
116 if (!desc->async_tx.ack) !! 130 if (!async_tx_test_ack(&desc->async_tx))
117 return 0; 131 return 0;
118 132
119 /* leave the last descriptor in the ch 133 /* leave the last descriptor in the chain
120 * so we can append to it 134 * so we can append to it
121 */ 135 */
122 if (desc->chain_node.next == &iop_chan 136 if (desc->chain_node.next == &iop_chan->chain)
123 return 1; 137 return 1;
124 138
125 dev_dbg(iop_chan->device->common.dev, 139 dev_dbg(iop_chan->device->common.dev,
126 "\tfree slot: %d slots_per_op: 140 "\tfree slot: %d slots_per_op: %d\n",
127 desc->idx, desc->slots_per_op) 141 desc->idx, desc->slots_per_op);
128 142
129 list_del(&desc->chain_node); 143 list_del(&desc->chain_node);
130 iop_adma_free_slots(desc); 144 iop_adma_free_slots(desc);
131 145
132 return 0; 146 return 0;
133 } 147 }
134 148
135 static void __iop_adma_slot_cleanup(struct iop 149 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
136 { 150 {
137 struct iop_adma_desc_slot *iter, *_ite 151 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
138 dma_cookie_t cookie = 0; 152 dma_cookie_t cookie = 0;
139 u32 current_desc = iop_chan_get_curren 153 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
140 int busy = iop_chan_is_busy(iop_chan); 154 int busy = iop_chan_is_busy(iop_chan);
141 int seen_current = 0, slot_cnt = 0, sl 155 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
142 156
143 dev_dbg(iop_chan->device->common.dev, 157 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
144 /* free completed slots from the chain 158 /* free completed slots from the chain starting with
145 * the oldest descriptor 159 * the oldest descriptor
146 */ 160 */
147 list_for_each_entry_safe(iter, _iter, 161 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
148 chain_ 162 chain_node) {
149 pr_debug("\tcookie: %d slot: % 163 pr_debug("\tcookie: %d slot: %d busy: %d "
150 "this_desc: %#x next_d 164 "this_desc: %#x next_desc: %#x ack: %d\n",
151 iter->async_tx.cookie, 165 iter->async_tx.cookie, iter->idx, busy,
152 iter->async_tx.phys, i 166 iter->async_tx.phys, iop_desc_get_next_desc(iter),
153 iter->async_tx.ack); !! 167 async_tx_test_ack(&iter->async_tx));
154 prefetch(_iter); 168 prefetch(_iter);
155 prefetch(&_iter->async_tx); 169 prefetch(&_iter->async_tx);
156 170
157 /* do not advance past the cur 171 /* do not advance past the current descriptor loaded into the
158 * hardware channel, subsequen 172 * hardware channel, subsequent descriptors are either in
159 * process or have not been su 173 * process or have not been submitted
160 */ 174 */
161 if (seen_current) 175 if (seen_current)
162 break; 176 break;
163 177
164 /* stop the search if we reach 178 /* stop the search if we reach the current descriptor and the
165 * channel is busy, or if it a 179 * channel is busy, or if it appears that the current descriptor
166 * needs to be re-read (i.e. h 180 * needs to be re-read (i.e. has been appended to)
167 */ 181 */
168 if (iter->async_tx.phys == cur 182 if (iter->async_tx.phys == current_desc) {
169 BUG_ON(seen_current++) 183 BUG_ON(seen_current++);
170 if (busy || iop_desc_g 184 if (busy || iop_desc_get_next_desc(iter))
171 break; 185 break;
172 } 186 }
173 187
174 /* detect the start of a group 188 /* detect the start of a group transaction */
175 if (!slot_cnt && !slots_per_op 189 if (!slot_cnt && !slots_per_op) {
176 slot_cnt = iter->slot_ 190 slot_cnt = iter->slot_cnt;
177 slots_per_op = iter->s 191 slots_per_op = iter->slots_per_op;
178 if (slot_cnt <= slots_ 192 if (slot_cnt <= slots_per_op) {
179 slot_cnt = 0; 193 slot_cnt = 0;
180 slots_per_op = 194 slots_per_op = 0;
181 } 195 }
182 } 196 }
183 197
184 if (slot_cnt) { 198 if (slot_cnt) {
185 pr_debug("\tgroup++\n" 199 pr_debug("\tgroup++\n");
186 if (!grp_start) 200 if (!grp_start)
187 grp_start = it 201 grp_start = iter;
188 slot_cnt -= slots_per_ 202 slot_cnt -= slots_per_op;
189 } 203 }
190 204
191 /* all the members of a group 205 /* all the members of a group are complete */
192 if (slots_per_op != 0 && slot_ 206 if (slots_per_op != 0 && slot_cnt == 0) {
193 struct iop_adma_desc_s 207 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
194 int end_of_chain = 0; 208 int end_of_chain = 0;
195 pr_debug("\tgroup end\ 209 pr_debug("\tgroup end\n");
196 210
197 /* collect the total r 211 /* collect the total results */
198 if (grp_start->xor_che 212 if (grp_start->xor_check_result) {
199 u32 zero_sum_r 213 u32 zero_sum_result = 0;
200 slot_cnt = grp 214 slot_cnt = grp_start->slot_cnt;
201 grp_iter = grp 215 grp_iter = grp_start;
202 216
203 list_for_each_ 217 list_for_each_entry_from(grp_iter,
204 &iop_c 218 &iop_chan->chain, chain_node) {
205 zero_s 219 zero_sum_result |=
206 io 220 iop_desc_get_zero_result(grp_iter);
207 pr 221 pr_debug("\titer%d result: %d\n",
208 gr 222 grp_iter->idx, zero_sum_result);
209 slot_c 223 slot_cnt -= slots_per_op;
210 if (sl 224 if (slot_cnt == 0)
211 225 break;
212 } 226 }
213 pr_debug("\tgr 227 pr_debug("\tgrp_start->xor_check_result: %p\n",
214 grp_st 228 grp_start->xor_check_result);
215 *grp_start->xo 229 *grp_start->xor_check_result = zero_sum_result;
216 } 230 }
217 231
218 /* clean up the group 232 /* clean up the group */
219 slot_cnt = grp_start-> 233 slot_cnt = grp_start->slot_cnt;
220 grp_iter = grp_start; 234 grp_iter = grp_start;
221 list_for_each_entry_sa 235 list_for_each_entry_safe_from(grp_iter, _grp_iter,
222 &iop_chan->cha 236 &iop_chan->chain, chain_node) {
223 cookie = iop_a 237 cookie = iop_adma_run_tx_complete_actions(
224 grp_it 238 grp_iter, iop_chan, cookie);
225 239
226 slot_cnt -= sl 240 slot_cnt -= slots_per_op;
227 end_of_chain = 241 end_of_chain = iop_adma_clean_slot(grp_iter,
228 iop_ch 242 iop_chan);
229 243
230 if (slot_cnt = 244 if (slot_cnt == 0 || end_of_chain)
231 break; 245 break;
232 } 246 }
233 247
234 /* the group should be 248 /* the group should be complete at this point */
235 BUG_ON(slot_cnt); 249 BUG_ON(slot_cnt);
236 250
237 slots_per_op = 0; 251 slots_per_op = 0;
238 grp_start = NULL; 252 grp_start = NULL;
239 if (end_of_chain) 253 if (end_of_chain)
240 break; 254 break;
241 else 255 else
242 continue; 256 continue;
243 } else if (slots_per_op) /* wa 257 } else if (slots_per_op) /* wait for group completion */
244 continue; 258 continue;
245 259
246 /* write back zero sum results 260 /* write back zero sum results (single descriptor case) */
247 if (iter->xor_check_result && 261 if (iter->xor_check_result && iter->async_tx.cookie)
248 *iter->xor_check_resul 262 *iter->xor_check_result =
249 iop_desc_get_z 263 iop_desc_get_zero_result(iter);
250 264
251 cookie = iop_adma_run_tx_compl 265 cookie = iop_adma_run_tx_complete_actions(
252 iter, 266 iter, iop_chan, cookie);
253 267
254 if (iop_adma_clean_slot(iter, 268 if (iop_adma_clean_slot(iter, iop_chan))
255 break; 269 break;
256 } 270 }
257 271
258 BUG_ON(!seen_current); <<
259 <<
260 iop_chan_idle(busy, iop_chan); <<
261 <<
262 if (cookie > 0) { 272 if (cookie > 0) {
263 iop_chan->completed_cookie = c 273 iop_chan->completed_cookie = cookie;
264 pr_debug("\tcompleted cookie % 274 pr_debug("\tcompleted cookie %d\n", cookie);
265 } 275 }
266 } 276 }
267 277
268 static void 278 static void
269 iop_adma_slot_cleanup(struct iop_adma_chan *io 279 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
270 { 280 {
271 spin_lock_bh(&iop_chan->lock); 281 spin_lock_bh(&iop_chan->lock);
272 __iop_adma_slot_cleanup(iop_chan); 282 __iop_adma_slot_cleanup(iop_chan);
273 spin_unlock_bh(&iop_chan->lock); 283 spin_unlock_bh(&iop_chan->lock);
274 } 284 }
275 285
276 static void iop_adma_tasklet(unsigned long dat 286 static void iop_adma_tasklet(unsigned long data)
277 { 287 {
278 struct iop_adma_chan *chan = (struct i !! 288 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
279 __iop_adma_slot_cleanup(chan); !! 289
>> 290 spin_lock(&iop_chan->lock);
>> 291 __iop_adma_slot_cleanup(iop_chan);
>> 292 spin_unlock(&iop_chan->lock);
280 } 293 }
281 294
282 static struct iop_adma_desc_slot * 295 static struct iop_adma_desc_slot *
283 iop_adma_alloc_slots(struct iop_adma_chan *iop 296 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
284 int slots_per_op) 297 int slots_per_op)
285 { 298 {
286 struct iop_adma_desc_slot *iter, *_ite 299 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
287 LIST_HEAD(chain); 300 LIST_HEAD(chain);
288 int slots_found, retry = 0; 301 int slots_found, retry = 0;
289 302
290 /* start search from the last allocate 303 /* start search from the last allocated descrtiptor
291 * if a contiguous allocation can not 304 * if a contiguous allocation can not be found start searching
292 * from the beginning of the list 305 * from the beginning of the list
293 */ 306 */
294 retry: 307 retry:
295 slots_found = 0; 308 slots_found = 0;
296 if (retry == 0) 309 if (retry == 0)
297 iter = iop_chan->last_used; 310 iter = iop_chan->last_used;
298 else 311 else
299 iter = list_entry(&iop_chan->a 312 iter = list_entry(&iop_chan->all_slots,
300 struct iop_adma_desc_s 313 struct iop_adma_desc_slot,
301 slot_node); 314 slot_node);
302 315
303 list_for_each_entry_safe_continue( 316 list_for_each_entry_safe_continue(
304 iter, _iter, &iop_chan->all_sl 317 iter, _iter, &iop_chan->all_slots, slot_node) {
305 prefetch(_iter); 318 prefetch(_iter);
306 prefetch(&_iter->async_tx); 319 prefetch(&_iter->async_tx);
307 if (iter->slots_per_op) { 320 if (iter->slots_per_op) {
308 /* give up after findi 321 /* give up after finding the first busy slot
309 * on the second pass 322 * on the second pass through the list
310 */ 323 */
311 if (retry) 324 if (retry)
312 break; 325 break;
313 326
314 slots_found = 0; 327 slots_found = 0;
315 continue; 328 continue;
316 } 329 }
317 330
318 /* start the allocation if the 331 /* start the allocation if the slot is correctly aligned */
319 if (!slots_found++) { 332 if (!slots_found++) {
320 if (iop_desc_is_aligne 333 if (iop_desc_is_aligned(iter, slots_per_op))
321 alloc_start = 334 alloc_start = iter;
322 else { 335 else {
323 slots_found = 336 slots_found = 0;
324 continue; 337 continue;
325 } 338 }
326 } 339 }
327 340
328 if (slots_found == num_slots) 341 if (slots_found == num_slots) {
329 struct iop_adma_desc_s 342 struct iop_adma_desc_slot *alloc_tail = NULL;
330 struct iop_adma_desc_s 343 struct iop_adma_desc_slot *last_used = NULL;
331 iter = alloc_start; 344 iter = alloc_start;
332 while (num_slots) { 345 while (num_slots) {
333 int i; 346 int i;
334 dev_dbg(iop_ch 347 dev_dbg(iop_chan->device->common.dev,
335 "alloc 348 "allocated slot: %d "
336 "(desc 349 "(desc %p phys: %#x) slots_per_op %d\n",
337 iter-> 350 iter->idx, iter->hw_desc,
338 iter-> 351 iter->async_tx.phys, slots_per_op);
339 352
340 /* pre-ack all 353 /* pre-ack all but the last descriptor */
341 if (num_slots 354 if (num_slots != slots_per_op)
342 iter-> !! 355 async_tx_ack(&iter->async_tx);
343 else <<
344 iter-> <<
345 356
346 list_add_tail( 357 list_add_tail(&iter->chain_node, &chain);
347 alloc_tail = i 358 alloc_tail = iter;
348 iter->async_tx 359 iter->async_tx.cookie = 0;
349 iter->slot_cnt 360 iter->slot_cnt = num_slots;
350 iter->xor_chec 361 iter->xor_check_result = NULL;
351 for (i = 0; i 362 for (i = 0; i < slots_per_op; i++) {
352 iter-> 363 iter->slots_per_op = slots_per_op - i;
353 last_u 364 last_used = iter;
354 iter = 365 iter = list_entry(iter->slot_node.next,
355 366 struct iop_adma_desc_slot,
356 367 slot_node);
357 } 368 }
358 num_slots -= s 369 num_slots -= slots_per_op;
359 } 370 }
360 alloc_tail->group_head 371 alloc_tail->group_head = alloc_start;
361 alloc_tail->async_tx.c 372 alloc_tail->async_tx.cookie = -EBUSY;
362 list_splice(&chain, &a 373 list_splice(&chain, &alloc_tail->async_tx.tx_list);
363 iop_chan->last_used = 374 iop_chan->last_used = last_used;
364 iop_desc_clear_next_de 375 iop_desc_clear_next_desc(alloc_start);
365 iop_desc_clear_next_de 376 iop_desc_clear_next_desc(alloc_tail);
366 return alloc_tail; 377 return alloc_tail;
367 } 378 }
368 } 379 }
369 if (!retry++) 380 if (!retry++)
370 goto retry; 381 goto retry;
371 382
372 /* try to free some slots if the alloc !! 383 /* perform direct reclaim if the allocation fails */
373 tasklet_schedule(&iop_chan->irq_taskle !! 384 __iop_adma_slot_cleanup(iop_chan);
374 385
375 return NULL; 386 return NULL;
376 } 387 }
377 388
378 static dma_cookie_t 389 static dma_cookie_t
379 iop_desc_assign_cookie(struct iop_adma_chan *i 390 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
380 struct iop_adma_desc_slot *desc) 391 struct iop_adma_desc_slot *desc)
381 { 392 {
382 dma_cookie_t cookie = iop_chan->common 393 dma_cookie_t cookie = iop_chan->common.cookie;
383 cookie++; 394 cookie++;
384 if (cookie < 0) 395 if (cookie < 0)
385 cookie = 1; 396 cookie = 1;
386 iop_chan->common.cookie = desc->async_ 397 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
387 return cookie; 398 return cookie;
388 } 399 }
389 400
390 static void iop_adma_check_threshold(struct io 401 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
391 { 402 {
392 dev_dbg(iop_chan->device->common.dev, 403 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
393 iop_chan->pending); 404 iop_chan->pending);
394 405
395 if (iop_chan->pending >= IOP_ADMA_THRE 406 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
396 iop_chan->pending = 0; 407 iop_chan->pending = 0;
397 iop_chan_append(iop_chan); 408 iop_chan_append(iop_chan);
398 } 409 }
399 } 410 }
400 411
401 static dma_cookie_t 412 static dma_cookie_t
402 iop_adma_tx_submit(struct dma_async_tx_descrip 413 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
403 { 414 {
404 struct iop_adma_desc_slot *sw_desc = t 415 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
405 struct iop_adma_chan *iop_chan = to_io 416 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
406 struct iop_adma_desc_slot *grp_start, 417 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
407 int slot_cnt; 418 int slot_cnt;
408 int slots_per_op; 419 int slots_per_op;
409 dma_cookie_t cookie; 420 dma_cookie_t cookie;
>> 421 dma_addr_t next_dma;
410 422
411 grp_start = sw_desc->group_head; 423 grp_start = sw_desc->group_head;
412 slot_cnt = grp_start->slot_cnt; 424 slot_cnt = grp_start->slot_cnt;
413 slots_per_op = grp_start->slots_per_op 425 slots_per_op = grp_start->slots_per_op;
414 426
415 spin_lock_bh(&iop_chan->lock); 427 spin_lock_bh(&iop_chan->lock);
416 cookie = iop_desc_assign_cookie(iop_ch 428 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
417 429
418 old_chain_tail = list_entry(iop_chan-> 430 old_chain_tail = list_entry(iop_chan->chain.prev,
419 struct iop_adma_desc_slot, cha 431 struct iop_adma_desc_slot, chain_node);
420 list_splice_init(&sw_desc->async_tx.tx 432 list_splice_init(&sw_desc->async_tx.tx_list,
421 &old_chain_tail->chai 433 &old_chain_tail->chain_node);
422 434
423 /* fix up the hardware chain */ 435 /* fix up the hardware chain */
424 iop_desc_set_next_desc(old_chain_tail, !! 436 next_dma = grp_start->async_tx.phys;
>> 437 iop_desc_set_next_desc(old_chain_tail, next_dma);
>> 438 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
425 439
426 /* 1/ don't add pre-chained descriptor !! 440 /* check for pre-chained descriptors */
427 * 2/ dummy read to flush next_desc wr !! 441 iop_paranoia(iop_desc_get_next_desc(sw_desc));
428 */ <<
429 BUG_ON(iop_desc_get_next_desc(sw_desc) <<
430 442
431 /* increment the pending count by the 443 /* increment the pending count by the number of slots
432 * memcpy operations have a 1:1 (slot: 444 * memcpy operations have a 1:1 (slot:operation) relation
433 * other operations are heavier and wi 445 * other operations are heavier and will pop the threshold
434 * more often. 446 * more often.
435 */ 447 */
436 iop_chan->pending += slot_cnt; 448 iop_chan->pending += slot_cnt;
437 iop_adma_check_threshold(iop_chan); 449 iop_adma_check_threshold(iop_chan);
438 spin_unlock_bh(&iop_chan->lock); 450 spin_unlock_bh(&iop_chan->lock);
439 451
440 dev_dbg(iop_chan->device->common.dev, 452 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
441 __func__, sw_desc->async_tx.co 453 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
442 454
443 return cookie; 455 return cookie;
444 } 456 }
445 457
446 static void iop_chan_start_null_memcpy(struct 458 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
447 static void iop_chan_start_null_xor(struct iop 459 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
448 460
449 /* returns the number of allocated descriptors !! 461 /**
>> 462 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
>> 463 * @chan - allocate descriptor resources for this channel
>> 464 * @client - current client requesting the channel be ready for requests
>> 465 *
>> 466 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
>> 467 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
>> 468 * greater than 2x the number slots needed to satisfy a device->max_xor
>> 469 * request.
>> 470 * */
450 static int iop_adma_alloc_chan_resources(struc 471 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
451 { 472 {
452 char *hw_desc; 473 char *hw_desc;
453 int idx; 474 int idx;
454 struct iop_adma_chan *iop_chan = to_io 475 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
455 struct iop_adma_desc_slot *slot = NULL 476 struct iop_adma_desc_slot *slot = NULL;
456 int init = iop_chan->slots_allocated ? 477 int init = iop_chan->slots_allocated ? 0 : 1;
457 struct iop_adma_platform_data *plat_da 478 struct iop_adma_platform_data *plat_data =
458 iop_chan->device->pdev->dev.pl 479 iop_chan->device->pdev->dev.platform_data;
459 int num_descs_in_pool = plat_data->poo 480 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
460 481
461 /* Allocate descriptor slots */ 482 /* Allocate descriptor slots */
462 do { 483 do {
463 idx = iop_chan->slots_allocate 484 idx = iop_chan->slots_allocated;
464 if (idx == num_descs_in_pool) 485 if (idx == num_descs_in_pool)
465 break; 486 break;
466 487
467 slot = kzalloc(sizeof(*slot), 488 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
468 if (!slot) { 489 if (!slot) {
469 printk(KERN_INFO "IOP 490 printk(KERN_INFO "IOP ADMA Channel only initialized"
470 " %d descripto 491 " %d descriptor slots", idx);
471 break; 492 break;
472 } 493 }
473 hw_desc = (char *) iop_chan->d 494 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
474 slot->hw_desc = (void *) &hw_d 495 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
475 496
476 dma_async_tx_descriptor_init(& 497 dma_async_tx_descriptor_init(&slot->async_tx, chan);
477 slot->async_tx.tx_submit = iop 498 slot->async_tx.tx_submit = iop_adma_tx_submit;
478 INIT_LIST_HEAD(&slot->chain_no 499 INIT_LIST_HEAD(&slot->chain_node);
479 INIT_LIST_HEAD(&slot->slot_nod 500 INIT_LIST_HEAD(&slot->slot_node);
480 INIT_LIST_HEAD(&slot->async_tx <<
481 hw_desc = (char *) iop_chan->d 501 hw_desc = (char *) iop_chan->device->dma_desc_pool;
482 slot->async_tx.phys = 502 slot->async_tx.phys =
483 (dma_addr_t) &hw_desc[ 503 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
484 slot->idx = idx; 504 slot->idx = idx;
485 505
486 spin_lock_bh(&iop_chan->lock); 506 spin_lock_bh(&iop_chan->lock);
487 iop_chan->slots_allocated++; 507 iop_chan->slots_allocated++;
488 list_add_tail(&slot->slot_node 508 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
489 spin_unlock_bh(&iop_chan->lock 509 spin_unlock_bh(&iop_chan->lock);
490 } while (iop_chan->slots_allocated < n 510 } while (iop_chan->slots_allocated < num_descs_in_pool);
491 511
492 if (idx && !iop_chan->last_used) 512 if (idx && !iop_chan->last_used)
493 iop_chan->last_used = list_ent 513 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
494 struct 514 struct iop_adma_desc_slot,
495 slot_n 515 slot_node);
496 516
497 dev_dbg(iop_chan->device->common.dev, 517 dev_dbg(iop_chan->device->common.dev,
498 "allocated %d descriptor slots 518 "allocated %d descriptor slots last_used: %p\n",
499 iop_chan->slots_allocated, iop 519 iop_chan->slots_allocated, iop_chan->last_used);
500 520
501 /* initialize the channel and the chai 521 /* initialize the channel and the chain with a null operation */
502 if (init) { 522 if (init) {
503 if (dma_has_cap(DMA_MEMCPY, 523 if (dma_has_cap(DMA_MEMCPY,
504 iop_chan->device->comm 524 iop_chan->device->common.cap_mask))
505 iop_chan_start_null_me 525 iop_chan_start_null_memcpy(iop_chan);
506 else if (dma_has_cap(DMA_XOR, 526 else if (dma_has_cap(DMA_XOR,
507 iop_chan->device->comm 527 iop_chan->device->common.cap_mask))
508 iop_chan_start_null_xo 528 iop_chan_start_null_xor(iop_chan);
509 else 529 else
510 BUG(); 530 BUG();
511 } 531 }
512 532
513 return (idx > 0) ? idx : -ENOMEM; 533 return (idx > 0) ? idx : -ENOMEM;
514 } 534 }
515 535
516 static struct dma_async_tx_descriptor * 536 static struct dma_async_tx_descriptor *
517 iop_adma_prep_dma_interrupt(struct dma_chan *c !! 537 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
518 { 538 {
519 struct iop_adma_chan *iop_chan = to_io 539 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
520 struct iop_adma_desc_slot *sw_desc, *g 540 struct iop_adma_desc_slot *sw_desc, *grp_start;
521 int slot_cnt, slots_per_op; 541 int slot_cnt, slots_per_op;
522 542
523 dev_dbg(iop_chan->device->common.dev, 543 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
524 544
525 spin_lock_bh(&iop_chan->lock); 545 spin_lock_bh(&iop_chan->lock);
526 slot_cnt = iop_chan_interrupt_slot_cou 546 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
527 sw_desc = iop_adma_alloc_slots(iop_cha 547 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
528 if (sw_desc) { 548 if (sw_desc) {
529 grp_start = sw_desc->group_hea 549 grp_start = sw_desc->group_head;
530 iop_desc_init_interrupt(grp_st 550 iop_desc_init_interrupt(grp_start, iop_chan);
531 grp_start->unmap_len = 0; 551 grp_start->unmap_len = 0;
>> 552 sw_desc->async_tx.flags = flags;
532 } 553 }
533 spin_unlock_bh(&iop_chan->lock); 554 spin_unlock_bh(&iop_chan->lock);
534 555
535 return sw_desc ? &sw_desc->async_tx : 556 return sw_desc ? &sw_desc->async_tx : NULL;
536 } 557 }
537 558
538 static struct dma_async_tx_descriptor * 559 static struct dma_async_tx_descriptor *
539 iop_adma_prep_dma_memcpy(struct dma_chan *chan 560 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
540 dma_addr_t dma_src, s 561 dma_addr_t dma_src, size_t len, unsigned long flags)
541 { 562 {
542 struct iop_adma_chan *iop_chan = to_io 563 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
543 struct iop_adma_desc_slot *sw_desc, *g 564 struct iop_adma_desc_slot *sw_desc, *grp_start;
544 int slot_cnt, slots_per_op; 565 int slot_cnt, slots_per_op;
545 566
546 if (unlikely(!len)) 567 if (unlikely(!len))
547 return NULL; 568 return NULL;
548 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYT 569 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
549 570
550 dev_dbg(iop_chan->device->common.dev, 571 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
551 __func__, len); 572 __func__, len);
552 573
553 spin_lock_bh(&iop_chan->lock); 574 spin_lock_bh(&iop_chan->lock);
554 slot_cnt = iop_chan_memcpy_slot_count( 575 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
555 sw_desc = iop_adma_alloc_slots(iop_cha 576 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
556 if (sw_desc) { 577 if (sw_desc) {
557 grp_start = sw_desc->group_hea 578 grp_start = sw_desc->group_head;
558 iop_desc_init_memcpy(grp_start 579 iop_desc_init_memcpy(grp_start, flags);
559 iop_desc_set_byte_count(grp_st 580 iop_desc_set_byte_count(grp_start, iop_chan, len);
560 iop_desc_set_dest_addr(grp_sta 581 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
561 iop_desc_set_memcpy_src_addr(g 582 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
562 sw_desc->unmap_src_cnt = 1; 583 sw_desc->unmap_src_cnt = 1;
563 sw_desc->unmap_len = len; 584 sw_desc->unmap_len = len;
>> 585 sw_desc->async_tx.flags = flags;
564 } 586 }
565 spin_unlock_bh(&iop_chan->lock); 587 spin_unlock_bh(&iop_chan->lock);
566 588
567 return sw_desc ? &sw_desc->async_tx : 589 return sw_desc ? &sw_desc->async_tx : NULL;
568 } 590 }
569 591
570 static struct dma_async_tx_descriptor * 592 static struct dma_async_tx_descriptor *
571 iop_adma_prep_dma_memset(struct dma_chan *chan 593 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
572 int value, size_t len 594 int value, size_t len, unsigned long flags)
573 { 595 {
574 struct iop_adma_chan *iop_chan = to_io 596 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
575 struct iop_adma_desc_slot *sw_desc, *g 597 struct iop_adma_desc_slot *sw_desc, *grp_start;
576 int slot_cnt, slots_per_op; 598 int slot_cnt, slots_per_op;
577 599
578 if (unlikely(!len)) 600 if (unlikely(!len))
579 return NULL; 601 return NULL;
580 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYT 602 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
581 603
582 dev_dbg(iop_chan->device->common.dev, 604 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
583 __func__, len); 605 __func__, len);
584 606
585 spin_lock_bh(&iop_chan->lock); 607 spin_lock_bh(&iop_chan->lock);
586 slot_cnt = iop_chan_memset_slot_count( 608 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
587 sw_desc = iop_adma_alloc_slots(iop_cha 609 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
588 if (sw_desc) { 610 if (sw_desc) {
589 grp_start = sw_desc->group_hea 611 grp_start = sw_desc->group_head;
590 iop_desc_init_memset(grp_start 612 iop_desc_init_memset(grp_start, flags);
591 iop_desc_set_byte_count(grp_st 613 iop_desc_set_byte_count(grp_start, iop_chan, len);
592 iop_desc_set_block_fill_val(gr 614 iop_desc_set_block_fill_val(grp_start, value);
593 iop_desc_set_dest_addr(grp_sta 615 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
594 sw_desc->unmap_src_cnt = 1; 616 sw_desc->unmap_src_cnt = 1;
595 sw_desc->unmap_len = len; 617 sw_desc->unmap_len = len;
>> 618 sw_desc->async_tx.flags = flags;
596 } 619 }
597 spin_unlock_bh(&iop_chan->lock); 620 spin_unlock_bh(&iop_chan->lock);
598 621
599 return sw_desc ? &sw_desc->async_tx : 622 return sw_desc ? &sw_desc->async_tx : NULL;
600 } 623 }
601 624
602 static struct dma_async_tx_descriptor * 625 static struct dma_async_tx_descriptor *
603 iop_adma_prep_dma_xor(struct dma_chan *chan, d 626 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
604 dma_addr_t *dma_src, uns 627 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
605 unsigned long flags) 628 unsigned long flags)
606 { 629 {
607 struct iop_adma_chan *iop_chan = to_io 630 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
608 struct iop_adma_desc_slot *sw_desc, *g 631 struct iop_adma_desc_slot *sw_desc, *grp_start;
609 int slot_cnt, slots_per_op; 632 int slot_cnt, slots_per_op;
610 633
611 if (unlikely(!len)) 634 if (unlikely(!len))
612 return NULL; 635 return NULL;
613 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX 636 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
614 637
615 dev_dbg(iop_chan->device->common.dev, 638 dev_dbg(iop_chan->device->common.dev,
616 "%s src_cnt: %d len: %u flags: 639 "%s src_cnt: %d len: %u flags: %lx\n",
617 __func__, src_cnt, len, flags) 640 __func__, src_cnt, len, flags);
618 641
619 spin_lock_bh(&iop_chan->lock); 642 spin_lock_bh(&iop_chan->lock);
620 slot_cnt = iop_chan_xor_slot_count(len 643 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
621 sw_desc = iop_adma_alloc_slots(iop_cha 644 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
622 if (sw_desc) { 645 if (sw_desc) {
623 grp_start = sw_desc->group_hea 646 grp_start = sw_desc->group_head;
624 iop_desc_init_xor(grp_start, s 647 iop_desc_init_xor(grp_start, src_cnt, flags);
625 iop_desc_set_byte_count(grp_st 648 iop_desc_set_byte_count(grp_start, iop_chan, len);
626 iop_desc_set_dest_addr(grp_sta 649 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
627 sw_desc->unmap_src_cnt = src_c 650 sw_desc->unmap_src_cnt = src_cnt;
628 sw_desc->unmap_len = len; 651 sw_desc->unmap_len = len;
>> 652 sw_desc->async_tx.flags = flags;
629 while (src_cnt--) 653 while (src_cnt--)
630 iop_desc_set_xor_src_a 654 iop_desc_set_xor_src_addr(grp_start, src_cnt,
631 655 dma_src[src_cnt]);
632 } 656 }
633 spin_unlock_bh(&iop_chan->lock); 657 spin_unlock_bh(&iop_chan->lock);
634 658
635 return sw_desc ? &sw_desc->async_tx : 659 return sw_desc ? &sw_desc->async_tx : NULL;
636 } 660 }
637 661
638 static struct dma_async_tx_descriptor * 662 static struct dma_async_tx_descriptor *
639 iop_adma_prep_dma_zero_sum(struct dma_chan *ch 663 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
640 unsigned int src_cn 664 unsigned int src_cnt, size_t len, u32 *result,
641 unsigned long flags 665 unsigned long flags)
642 { 666 {
643 struct iop_adma_chan *iop_chan = to_io 667 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
644 struct iop_adma_desc_slot *sw_desc, *g 668 struct iop_adma_desc_slot *sw_desc, *grp_start;
645 int slot_cnt, slots_per_op; 669 int slot_cnt, slots_per_op;
646 670
647 if (unlikely(!len)) 671 if (unlikely(!len))
648 return NULL; 672 return NULL;
649 673
650 dev_dbg(iop_chan->device->common.dev, 674 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
651 __func__, src_cnt, len); 675 __func__, src_cnt, len);
652 676
653 spin_lock_bh(&iop_chan->lock); 677 spin_lock_bh(&iop_chan->lock);
654 slot_cnt = iop_chan_zero_sum_slot_coun 678 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
655 sw_desc = iop_adma_alloc_slots(iop_cha 679 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
656 if (sw_desc) { 680 if (sw_desc) {
657 grp_start = sw_desc->group_hea 681 grp_start = sw_desc->group_head;
658 iop_desc_init_zero_sum(grp_sta 682 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
659 iop_desc_set_zero_sum_byte_cou 683 iop_desc_set_zero_sum_byte_count(grp_start, len);
660 grp_start->xor_check_result = 684 grp_start->xor_check_result = result;
661 pr_debug("\t%s: grp_start->xor 685 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
662 __func__, grp_start->x 686 __func__, grp_start->xor_check_result);
663 sw_desc->unmap_src_cnt = src_c 687 sw_desc->unmap_src_cnt = src_cnt;
664 sw_desc->unmap_len = len; 688 sw_desc->unmap_len = len;
>> 689 sw_desc->async_tx.flags = flags;
665 while (src_cnt--) 690 while (src_cnt--)
666 iop_desc_set_zero_sum_ 691 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
667 692 dma_src[src_cnt]);
668 } 693 }
669 spin_unlock_bh(&iop_chan->lock); 694 spin_unlock_bh(&iop_chan->lock);
670 695
671 return sw_desc ? &sw_desc->async_tx : 696 return sw_desc ? &sw_desc->async_tx : NULL;
672 } 697 }
673 698
674 static void iop_adma_dependency_added(struct d <<
675 { <<
676 struct iop_adma_chan *iop_chan = to_io <<
677 tasklet_schedule(&iop_chan->irq_taskle <<
678 } <<
679 <<
680 static void iop_adma_free_chan_resources(struc 699 static void iop_adma_free_chan_resources(struct dma_chan *chan)
681 { 700 {
682 struct iop_adma_chan *iop_chan = to_io 701 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
683 struct iop_adma_desc_slot *iter, *_ite 702 struct iop_adma_desc_slot *iter, *_iter;
684 int in_use_descs = 0; 703 int in_use_descs = 0;
685 704
686 iop_adma_slot_cleanup(iop_chan); 705 iop_adma_slot_cleanup(iop_chan);
687 706
688 spin_lock_bh(&iop_chan->lock); 707 spin_lock_bh(&iop_chan->lock);
689 list_for_each_entry_safe(iter, _iter, 708 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
690 chain_ 709 chain_node) {
691 in_use_descs++; 710 in_use_descs++;
692 list_del(&iter->chain_node); 711 list_del(&iter->chain_node);
693 } 712 }
694 list_for_each_entry_safe_reverse( 713 list_for_each_entry_safe_reverse(
695 iter, _iter, &iop_chan->all_sl 714 iter, _iter, &iop_chan->all_slots, slot_node) {
696 list_del(&iter->slot_node); 715 list_del(&iter->slot_node);
697 kfree(iter); 716 kfree(iter);
698 iop_chan->slots_allocated--; 717 iop_chan->slots_allocated--;
699 } 718 }
700 iop_chan->last_used = NULL; 719 iop_chan->last_used = NULL;
701 720
702 dev_dbg(iop_chan->device->common.dev, 721 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
703 __func__, iop_chan->slots_allo 722 __func__, iop_chan->slots_allocated);
704 spin_unlock_bh(&iop_chan->lock); 723 spin_unlock_bh(&iop_chan->lock);
705 724
706 /* one is ok since we left it on there 725 /* one is ok since we left it on there on purpose */
707 if (in_use_descs > 1) 726 if (in_use_descs > 1)
708 printk(KERN_ERR "IOP: Freeing 727 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
709 in_use_descs - 1); 728 in_use_descs - 1);
710 } 729 }
711 730
712 /** 731 /**
713 * iop_adma_is_complete - poll the status of a 732 * iop_adma_is_complete - poll the status of an ADMA transaction
714 * @chan: ADMA channel handle 733 * @chan: ADMA channel handle
715 * @cookie: ADMA transaction identifier 734 * @cookie: ADMA transaction identifier
716 */ 735 */
717 static enum dma_status iop_adma_is_complete(st 736 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
718 dma_co 737 dma_cookie_t cookie,
719 dma_co 738 dma_cookie_t *done,
720 dma_co 739 dma_cookie_t *used)
721 { 740 {
722 struct iop_adma_chan *iop_chan = to_io 741 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
723 dma_cookie_t last_used; 742 dma_cookie_t last_used;
724 dma_cookie_t last_complete; 743 dma_cookie_t last_complete;
725 enum dma_status ret; 744 enum dma_status ret;
726 745
727 last_used = chan->cookie; 746 last_used = chan->cookie;
728 last_complete = iop_chan->completed_co 747 last_complete = iop_chan->completed_cookie;
729 748
730 if (done) 749 if (done)
731 *done = last_complete; 750 *done = last_complete;
732 if (used) 751 if (used)
733 *used = last_used; 752 *used = last_used;
734 753
735 ret = dma_async_is_complete(cookie, la 754 ret = dma_async_is_complete(cookie, last_complete, last_used);
736 if (ret == DMA_SUCCESS) 755 if (ret == DMA_SUCCESS)
737 return ret; 756 return ret;
738 757
739 iop_adma_slot_cleanup(iop_chan); 758 iop_adma_slot_cleanup(iop_chan);
740 759
741 last_used = chan->cookie; 760 last_used = chan->cookie;
742 last_complete = iop_chan->completed_co 761 last_complete = iop_chan->completed_cookie;
743 762
744 if (done) 763 if (done)
745 *done = last_complete; 764 *done = last_complete;
746 if (used) 765 if (used)
747 *used = last_used; 766 *used = last_used;
748 767
749 return dma_async_is_complete(cookie, l 768 return dma_async_is_complete(cookie, last_complete, last_used);
750 } 769 }
751 770
752 static irqreturn_t iop_adma_eot_handler(int ir 771 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
753 { 772 {
754 struct iop_adma_chan *chan = data; 773 struct iop_adma_chan *chan = data;
755 774
756 dev_dbg(chan->device->common.dev, "%s\ 775 dev_dbg(chan->device->common.dev, "%s\n", __func__);
757 776
758 tasklet_schedule(&chan->irq_tasklet); 777 tasklet_schedule(&chan->irq_tasklet);
759 778
760 iop_adma_device_clear_eot_status(chan) 779 iop_adma_device_clear_eot_status(chan);
761 780
762 return IRQ_HANDLED; 781 return IRQ_HANDLED;
763 } 782 }
764 783
765 static irqreturn_t iop_adma_eoc_handler(int ir 784 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
766 { 785 {
767 struct iop_adma_chan *chan = data; 786 struct iop_adma_chan *chan = data;
768 787
769 dev_dbg(chan->device->common.dev, "%s\ 788 dev_dbg(chan->device->common.dev, "%s\n", __func__);
770 789
771 tasklet_schedule(&chan->irq_tasklet); 790 tasklet_schedule(&chan->irq_tasklet);
772 791
773 iop_adma_device_clear_eoc_status(chan) 792 iop_adma_device_clear_eoc_status(chan);
774 793
775 return IRQ_HANDLED; 794 return IRQ_HANDLED;
776 } 795 }
777 796
778 static irqreturn_t iop_adma_err_handler(int ir 797 static irqreturn_t iop_adma_err_handler(int irq, void *data)
779 { 798 {
780 struct iop_adma_chan *chan = data; 799 struct iop_adma_chan *chan = data;
781 unsigned long status = iop_chan_get_st 800 unsigned long status = iop_chan_get_status(chan);
782 801
783 dev_printk(KERN_ERR, chan->device->com 802 dev_printk(KERN_ERR, chan->device->common.dev,
784 "error ( %s%s%s%s%s%s%s)\n", 803 "error ( %s%s%s%s%s%s%s)\n",
785 iop_is_err_int_parity(status, 804 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
786 iop_is_err_mcu_abort(status, c 805 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
787 iop_is_err_int_tabort(status, 806 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
788 iop_is_err_int_mabort(status, 807 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
789 iop_is_err_pci_tabort(status, 808 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
790 iop_is_err_pci_mabort(status, 809 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
791 iop_is_err_split_tx(status, ch 810 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
792 811
793 iop_adma_device_clear_err_status(chan) 812 iop_adma_device_clear_err_status(chan);
794 813
795 BUG(); 814 BUG();
796 815
797 return IRQ_HANDLED; 816 return IRQ_HANDLED;
798 } 817 }
799 818
800 static void iop_adma_issue_pending(struct dma_ 819 static void iop_adma_issue_pending(struct dma_chan *chan)
801 { 820 {
802 struct iop_adma_chan *iop_chan = to_io 821 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
803 822
804 if (iop_chan->pending) { 823 if (iop_chan->pending) {
805 iop_chan->pending = 0; 824 iop_chan->pending = 0;
806 iop_chan_append(iop_chan); 825 iop_chan_append(iop_chan);
807 } 826 }
808 } 827 }
809 828
810 /* 829 /*
811 * Perform a transaction to verify the HW work 830 * Perform a transaction to verify the HW works.
812 */ 831 */
813 #define IOP_ADMA_TEST_SIZE 2000 832 #define IOP_ADMA_TEST_SIZE 2000
814 833
815 static int __devinit iop_adma_memcpy_self_test 834 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
816 { 835 {
817 int i; 836 int i;
818 void *src, *dest; 837 void *src, *dest;
819 dma_addr_t src_dma, dest_dma; 838 dma_addr_t src_dma, dest_dma;
820 struct dma_chan *dma_chan; 839 struct dma_chan *dma_chan;
821 dma_cookie_t cookie; 840 dma_cookie_t cookie;
822 struct dma_async_tx_descriptor *tx; 841 struct dma_async_tx_descriptor *tx;
823 int err = 0; 842 int err = 0;
824 struct iop_adma_chan *iop_chan; 843 struct iop_adma_chan *iop_chan;
825 844
826 dev_dbg(device->common.dev, "%s\n", __ 845 dev_dbg(device->common.dev, "%s\n", __func__);
827 846
828 src = kzalloc(sizeof(u8) * IOP_ADMA_TE !! 847 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
829 if (!src) 848 if (!src)
830 return -ENOMEM; 849 return -ENOMEM;
831 dest = kzalloc(sizeof(u8) * IOP_ADMA_T !! 850 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
832 if (!dest) { 851 if (!dest) {
833 kfree(src); 852 kfree(src);
834 return -ENOMEM; 853 return -ENOMEM;
835 } 854 }
836 855
837 /* Fill in src buffer */ 856 /* Fill in src buffer */
838 for (i = 0; i < IOP_ADMA_TEST_SIZE; i+ 857 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
839 ((u8 *) src)[i] = (u8)i; 858 ((u8 *) src)[i] = (u8)i;
840 859
841 memset(dest, 0, IOP_ADMA_TEST_SIZE); <<
842 <<
843 /* Start copy, using first DMA channel 860 /* Start copy, using first DMA channel */
844 dma_chan = container_of(device->common 861 dma_chan = container_of(device->common.channels.next,
845 struct dma_cha 862 struct dma_chan,
846 device_node); 863 device_node);
847 if (iop_adma_alloc_chan_resources(dma_ 864 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
848 err = -ENODEV; 865 err = -ENODEV;
849 goto out; 866 goto out;
850 } 867 }
851 868
852 dest_dma = dma_map_single(dma_chan->de 869 dest_dma = dma_map_single(dma_chan->device->dev, dest,
853 IOP_ADMA_TEST_ 870 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
854 src_dma = dma_map_single(dma_chan->dev 871 src_dma = dma_map_single(dma_chan->device->dev, src,
855 IOP_ADMA_TEST_ 872 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
856 tx = iop_adma_prep_dma_memcpy(dma_chan 873 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
857 IOP_ADMA !! 874 IOP_ADMA_TEST_SIZE,
>> 875 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
858 876
859 cookie = iop_adma_tx_submit(tx); 877 cookie = iop_adma_tx_submit(tx);
860 iop_adma_issue_pending(dma_chan); 878 iop_adma_issue_pending(dma_chan);
861 async_tx_ack(tx); <<
862 msleep(1); 879 msleep(1);
863 880
864 if (iop_adma_is_complete(dma_chan, coo 881 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
865 DMA_SUCCESS) { 882 DMA_SUCCESS) {
866 dev_printk(KERN_ERR, dma_chan- 883 dev_printk(KERN_ERR, dma_chan->device->dev,
867 "Self-test copy timed 884 "Self-test copy timed out, disabling\n");
868 err = -ENODEV; 885 err = -ENODEV;
869 goto free_resources; 886 goto free_resources;
870 } 887 }
871 888
872 iop_chan = to_iop_adma_chan(dma_chan); 889 iop_chan = to_iop_adma_chan(dma_chan);
873 dma_sync_single_for_cpu(&iop_chan->dev 890 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
874 IOP_ADMA_TEST_SIZE, DMA_FROM_D 891 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
875 if (memcmp(src, dest, IOP_ADMA_TEST_SI 892 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
876 dev_printk(KERN_ERR, dma_chan- 893 dev_printk(KERN_ERR, dma_chan->device->dev,
877 "Self-test copy failed 894 "Self-test copy failed compare, disabling\n");
878 err = -ENODEV; 895 err = -ENODEV;
879 goto free_resources; 896 goto free_resources;
880 } 897 }
881 898
882 free_resources: 899 free_resources:
883 iop_adma_free_chan_resources(dma_chan) 900 iop_adma_free_chan_resources(dma_chan);
884 out: 901 out:
885 kfree(src); 902 kfree(src);
886 kfree(dest); 903 kfree(dest);
887 return err; 904 return err;
888 } 905 }
889 906
890 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 907 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
891 static int __devinit 908 static int __devinit
892 iop_adma_xor_zero_sum_self_test(struct iop_adm 909 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
893 { 910 {
894 int i, src_idx; 911 int i, src_idx;
895 struct page *dest; 912 struct page *dest;
896 struct page *xor_srcs[IOP_ADMA_NUM_SRC 913 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
897 struct page *zero_sum_srcs[IOP_ADMA_NU 914 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
898 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_T 915 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
899 dma_addr_t dma_addr, dest_dma; 916 dma_addr_t dma_addr, dest_dma;
900 struct dma_async_tx_descriptor *tx; 917 struct dma_async_tx_descriptor *tx;
901 struct dma_chan *dma_chan; 918 struct dma_chan *dma_chan;
902 dma_cookie_t cookie; 919 dma_cookie_t cookie;
903 u8 cmp_byte = 0; 920 u8 cmp_byte = 0;
904 u32 cmp_word; 921 u32 cmp_word;
905 u32 zero_sum_result; 922 u32 zero_sum_result;
906 int err = 0; 923 int err = 0;
907 struct iop_adma_chan *iop_chan; 924 struct iop_adma_chan *iop_chan;
908 925
909 dev_dbg(device->common.dev, "%s\n", __ 926 dev_dbg(device->common.dev, "%s\n", __func__);
910 927
911 for (src_idx = 0; src_idx < IOP_ADMA_N 928 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
912 xor_srcs[src_idx] = alloc_page 929 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
913 if (!xor_srcs[src_idx]) !! 930 if (!xor_srcs[src_idx]) {
914 while (src_idx--) { !! 931 while (src_idx--)
915 __free_page(xo 932 __free_page(xor_srcs[src_idx]);
916 return -ENOMEM !! 933 return -ENOMEM;
917 } !! 934 }
918 } 935 }
919 936
920 dest = alloc_page(GFP_KERNEL); 937 dest = alloc_page(GFP_KERNEL);
921 if (!dest) !! 938 if (!dest) {
922 while (src_idx--) { !! 939 while (src_idx--)
923 __free_page(xor_srcs[s 940 __free_page(xor_srcs[src_idx]);
924 return -ENOMEM; !! 941 return -ENOMEM;
925 } !! 942 }
926 943
927 /* Fill in src buffers */ 944 /* Fill in src buffers */
928 for (src_idx = 0; src_idx < IOP_ADMA_N 945 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
929 u8 *ptr = page_address(xor_src 946 u8 *ptr = page_address(xor_srcs[src_idx]);
930 for (i = 0; i < PAGE_SIZE; i++ 947 for (i = 0; i < PAGE_SIZE; i++)
931 ptr[i] = (1 << src_idx 948 ptr[i] = (1 << src_idx);
932 } 949 }
933 950
934 for (src_idx = 0; src_idx < IOP_ADMA_N 951 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
935 cmp_byte ^= (u8) (1 << src_idx 952 cmp_byte ^= (u8) (1 << src_idx);
936 953
937 cmp_word = (cmp_byte << 24) | (cmp_byt 954 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
938 (cmp_byte << 8) | cmp_ 955 (cmp_byte << 8) | cmp_byte;
939 956
940 memset(page_address(dest), 0, PAGE_SIZ 957 memset(page_address(dest), 0, PAGE_SIZE);
941 958
942 dma_chan = container_of(device->common 959 dma_chan = container_of(device->common.channels.next,
943 struct dma_cha 960 struct dma_chan,
944 device_node); 961 device_node);
945 if (iop_adma_alloc_chan_resources(dma_ 962 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
946 err = -ENODEV; 963 err = -ENODEV;
947 goto out; 964 goto out;
948 } 965 }
949 966
950 /* test xor */ 967 /* test xor */
951 dest_dma = dma_map_page(dma_chan->devi 968 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
952 PAGE_SIZE, DMA 969 PAGE_SIZE, DMA_FROM_DEVICE);
953 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; 970 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
954 dma_srcs[i] = dma_map_page(dma 971 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
955 0, 972 0, PAGE_SIZE, DMA_TO_DEVICE);
956 tx = iop_adma_prep_dma_xor(dma_chan, d 973 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
957 IOP_ADMA_NU !! 974 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
>> 975 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
958 976
959 cookie = iop_adma_tx_submit(tx); 977 cookie = iop_adma_tx_submit(tx);
960 iop_adma_issue_pending(dma_chan); 978 iop_adma_issue_pending(dma_chan);
961 async_tx_ack(tx); <<
962 msleep(8); 979 msleep(8);
963 980
964 if (iop_adma_is_complete(dma_chan, coo 981 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
965 DMA_SUCCESS) { 982 DMA_SUCCESS) {
966 dev_printk(KERN_ERR, dma_chan- 983 dev_printk(KERN_ERR, dma_chan->device->dev,
967 "Self-test xor timed o 984 "Self-test xor timed out, disabling\n");
968 err = -ENODEV; 985 err = -ENODEV;
969 goto free_resources; 986 goto free_resources;
970 } 987 }
971 988
972 iop_chan = to_iop_adma_chan(dma_chan); 989 iop_chan = to_iop_adma_chan(dma_chan);
973 dma_sync_single_for_cpu(&iop_chan->dev 990 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
974 PAGE_SIZE, DMA_FROM_DEVICE); 991 PAGE_SIZE, DMA_FROM_DEVICE);
975 for (i = 0; i < (PAGE_SIZE / sizeof(u3 992 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
976 u32 *ptr = page_address(dest); 993 u32 *ptr = page_address(dest);
977 if (ptr[i] != cmp_word) { 994 if (ptr[i] != cmp_word) {
978 dev_printk(KERN_ERR, d 995 dev_printk(KERN_ERR, dma_chan->device->dev,
979 "Self-test xor 996 "Self-test xor failed compare, disabling\n");
980 err = -ENODEV; 997 err = -ENODEV;
981 goto free_resources; 998 goto free_resources;
982 } 999 }
983 } 1000 }
984 dma_sync_single_for_device(&iop_chan-> 1001 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
985 PAGE_SIZE, DMA_TO_DEVICE); 1002 PAGE_SIZE, DMA_TO_DEVICE);
986 1003
987 /* skip zero sum if the capability is 1004 /* skip zero sum if the capability is not present */
988 if (!dma_has_cap(DMA_ZERO_SUM, dma_cha 1005 if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
989 goto free_resources; 1006 goto free_resources;
990 1007
991 /* zero sum the sources with the desti 1008 /* zero sum the sources with the destintation page */
992 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; 1009 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
993 zero_sum_srcs[i] = xor_srcs[i] 1010 zero_sum_srcs[i] = xor_srcs[i];
994 zero_sum_srcs[i] = dest; 1011 zero_sum_srcs[i] = dest;
995 1012
996 zero_sum_result = 1; 1013 zero_sum_result = 1;
997 1014
998 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST 1015 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
999 dma_srcs[i] = dma_map_page(dma 1016 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1000 ze 1017 zero_sum_srcs[i], 0, PAGE_SIZE,
1001 DM 1018 DMA_TO_DEVICE);
1002 tx = iop_adma_prep_dma_zero_sum(dma_c 1019 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1003 IOP_A 1020 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1004 &zero !! 1021 &zero_sum_result,
>> 1022 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1005 1023
1006 cookie = iop_adma_tx_submit(tx); 1024 cookie = iop_adma_tx_submit(tx);
1007 iop_adma_issue_pending(dma_chan); 1025 iop_adma_issue_pending(dma_chan);
1008 async_tx_ack(tx); <<
1009 msleep(8); 1026 msleep(8);
1010 1027
1011 if (iop_adma_is_complete(dma_chan, co 1028 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1012 dev_printk(KERN_ERR, dma_chan 1029 dev_printk(KERN_ERR, dma_chan->device->dev,
1013 "Self-test zero sum t 1030 "Self-test zero sum timed out, disabling\n");
1014 err = -ENODEV; 1031 err = -ENODEV;
1015 goto free_resources; 1032 goto free_resources;
1016 } 1033 }
1017 1034
1018 if (zero_sum_result != 0) { 1035 if (zero_sum_result != 0) {
1019 dev_printk(KERN_ERR, dma_chan 1036 dev_printk(KERN_ERR, dma_chan->device->dev,
1020 "Self-test zero sum f 1037 "Self-test zero sum failed compare, disabling\n");
1021 err = -ENODEV; 1038 err = -ENODEV;
1022 goto free_resources; 1039 goto free_resources;
1023 } 1040 }
1024 1041
1025 /* test memset */ 1042 /* test memset */
1026 dma_addr = dma_map_page(dma_chan->dev 1043 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1027 PAGE_SIZE, DMA_FROM_D 1044 PAGE_SIZE, DMA_FROM_DEVICE);
1028 tx = iop_adma_prep_dma_memset(dma_cha !! 1045 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
>> 1046 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1029 1047
1030 cookie = iop_adma_tx_submit(tx); 1048 cookie = iop_adma_tx_submit(tx);
1031 iop_adma_issue_pending(dma_chan); 1049 iop_adma_issue_pending(dma_chan);
1032 async_tx_ack(tx); <<
1033 msleep(8); 1050 msleep(8);
1034 1051
1035 if (iop_adma_is_complete(dma_chan, co 1052 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1036 dev_printk(KERN_ERR, dma_chan 1053 dev_printk(KERN_ERR, dma_chan->device->dev,
1037 "Self-test memset tim 1054 "Self-test memset timed out, disabling\n");
1038 err = -ENODEV; 1055 err = -ENODEV;
1039 goto free_resources; 1056 goto free_resources;
1040 } 1057 }
1041 1058
1042 for (i = 0; i < PAGE_SIZE/sizeof(u32) 1059 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1043 u32 *ptr = page_address(dest) 1060 u32 *ptr = page_address(dest);
1044 if (ptr[i]) { 1061 if (ptr[i]) {
1045 dev_printk(KERN_ERR, 1062 dev_printk(KERN_ERR, dma_chan->device->dev,
1046 "Self-test me 1063 "Self-test memset failed compare, disabling\n");
1047 err = -ENODEV; 1064 err = -ENODEV;
1048 goto free_resources; 1065 goto free_resources;
1049 } 1066 }
1050 } 1067 }
1051 1068
1052 /* test for non-zero parity sum */ 1069 /* test for non-zero parity sum */
1053 zero_sum_result = 0; 1070 zero_sum_result = 0;
1054 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST 1071 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1055 dma_srcs[i] = dma_map_page(dm 1072 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1056 ze 1073 zero_sum_srcs[i], 0, PAGE_SIZE,
1057 DM 1074 DMA_TO_DEVICE);
1058 tx = iop_adma_prep_dma_zero_sum(dma_c 1075 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1059 IOP_A 1076 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1060 &zero !! 1077 &zero_sum_result,
>> 1078 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1061 1079
1062 cookie = iop_adma_tx_submit(tx); 1080 cookie = iop_adma_tx_submit(tx);
1063 iop_adma_issue_pending(dma_chan); 1081 iop_adma_issue_pending(dma_chan);
1064 async_tx_ack(tx); <<
1065 msleep(8); 1082 msleep(8);
1066 1083
1067 if (iop_adma_is_complete(dma_chan, co 1084 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1068 dev_printk(KERN_ERR, dma_chan 1085 dev_printk(KERN_ERR, dma_chan->device->dev,
1069 "Self-test non-zero s 1086 "Self-test non-zero sum timed out, disabling\n");
1070 err = -ENODEV; 1087 err = -ENODEV;
1071 goto free_resources; 1088 goto free_resources;
1072 } 1089 }
1073 1090
1074 if (zero_sum_result != 1) { 1091 if (zero_sum_result != 1) {
1075 dev_printk(KERN_ERR, dma_chan 1092 dev_printk(KERN_ERR, dma_chan->device->dev,
1076 "Self-test non-zero s 1093 "Self-test non-zero sum failed compare, disabling\n");
1077 err = -ENODEV; 1094 err = -ENODEV;
1078 goto free_resources; 1095 goto free_resources;
1079 } 1096 }
1080 1097
1081 free_resources: 1098 free_resources:
1082 iop_adma_free_chan_resources(dma_chan 1099 iop_adma_free_chan_resources(dma_chan);
1083 out: 1100 out:
1084 src_idx = IOP_ADMA_NUM_SRC_TEST; 1101 src_idx = IOP_ADMA_NUM_SRC_TEST;
1085 while (src_idx--) 1102 while (src_idx--)
1086 __free_page(xor_srcs[src_idx] 1103 __free_page(xor_srcs[src_idx]);
1087 __free_page(dest); 1104 __free_page(dest);
1088 return err; 1105 return err;
1089 } 1106 }
1090 1107
1091 static int __devexit iop_adma_remove(struct p 1108 static int __devexit iop_adma_remove(struct platform_device *dev)
1092 { 1109 {
1093 struct iop_adma_device *device = plat 1110 struct iop_adma_device *device = platform_get_drvdata(dev);
1094 struct dma_chan *chan, *_chan; 1111 struct dma_chan *chan, *_chan;
1095 struct iop_adma_chan *iop_chan; 1112 struct iop_adma_chan *iop_chan;
1096 int i; <<
1097 struct iop_adma_platform_data *plat_d 1113 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1098 1114
1099 dma_async_device_unregister(&device-> 1115 dma_async_device_unregister(&device->common);
1100 1116
1101 for (i = 0; i < 3; i++) { <<
1102 unsigned int irq; <<
1103 irq = platform_get_irq(dev, i <<
1104 free_irq(irq, device); <<
1105 } <<
1106 <<
1107 dma_free_coherent(&dev->dev, plat_dat 1117 dma_free_coherent(&dev->dev, plat_data->pool_size,
1108 device->dma_desc_pool 1118 device->dma_desc_pool_virt, device->dma_desc_pool);
1109 1119
1110 do { <<
1111 struct resource *res; <<
1112 res = platform_get_resource(d <<
1113 release_mem_region(res->start <<
1114 } while (0); <<
1115 <<
1116 list_for_each_entry_safe(chan, _chan, 1120 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1117 device_node) 1121 device_node) {
1118 iop_chan = to_iop_adma_chan(c 1122 iop_chan = to_iop_adma_chan(chan);
1119 list_del(&chan->device_node); 1123 list_del(&chan->device_node);
1120 kfree(iop_chan); 1124 kfree(iop_chan);
1121 } 1125 }
1122 kfree(device); 1126 kfree(device);
1123 1127
1124 return 0; 1128 return 0;
1125 } 1129 }
1126 1130
1127 static int __devinit iop_adma_probe(struct pl 1131 static int __devinit iop_adma_probe(struct platform_device *pdev)
1128 { 1132 {
1129 struct resource *res; 1133 struct resource *res;
1130 int ret = 0, i; 1134 int ret = 0, i;
1131 struct iop_adma_device *adev; 1135 struct iop_adma_device *adev;
1132 struct iop_adma_chan *iop_chan; 1136 struct iop_adma_chan *iop_chan;
1133 struct dma_device *dma_dev; 1137 struct dma_device *dma_dev;
1134 struct iop_adma_platform_data *plat_d 1138 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1135 1139
1136 res = platform_get_resource(pdev, IOR 1140 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1137 if (!res) 1141 if (!res)
1138 return -ENODEV; 1142 return -ENODEV;
1139 1143
1140 if (!devm_request_mem_region(&pdev->d 1144 if (!devm_request_mem_region(&pdev->dev, res->start,
1141 res->end - re 1145 res->end - res->start, pdev->name))
1142 return -EBUSY; 1146 return -EBUSY;
1143 1147
1144 adev = kzalloc(sizeof(*adev), GFP_KER 1148 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1145 if (!adev) 1149 if (!adev)
1146 return -ENOMEM; 1150 return -ENOMEM;
1147 dma_dev = &adev->common; 1151 dma_dev = &adev->common;
1148 1152
1149 /* allocate coherent memory for hardw 1153 /* allocate coherent memory for hardware descriptors
1150 * note: writecombine gives slightly 1154 * note: writecombine gives slightly better performance, but
1151 * requires that we explicitly flush 1155 * requires that we explicitly flush the writes
1152 */ 1156 */
1153 if ((adev->dma_desc_pool_virt = dma_a 1157 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1154 plat_ 1158 plat_data->pool_size,
1155 &adev 1159 &adev->dma_desc_pool,
1156 GFP_K 1160 GFP_KERNEL)) == NULL) {
1157 ret = -ENOMEM; 1161 ret = -ENOMEM;
1158 goto err_free_adev; 1162 goto err_free_adev;
1159 } 1163 }
1160 1164
1161 dev_dbg(&pdev->dev, "%s: allocted des 1165 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1162 __func__, adev->dma_desc_pool 1166 __func__, adev->dma_desc_pool_virt,
1163 (void *) adev->dma_desc_pool) 1167 (void *) adev->dma_desc_pool);
1164 1168
1165 adev->id = plat_data->hw_id; 1169 adev->id = plat_data->hw_id;
1166 1170
1167 /* discover transaction capabilites f 1171 /* discover transaction capabilites from the platform data */
1168 dma_dev->cap_mask = plat_data->cap_ma 1172 dma_dev->cap_mask = plat_data->cap_mask;
1169 1173
1170 adev->pdev = pdev; 1174 adev->pdev = pdev;
1171 platform_set_drvdata(pdev, adev); 1175 platform_set_drvdata(pdev, adev);
1172 1176
1173 INIT_LIST_HEAD(&dma_dev->channels); 1177 INIT_LIST_HEAD(&dma_dev->channels);
1174 1178
1175 /* set base routines */ 1179 /* set base routines */
1176 dma_dev->device_alloc_chan_resources 1180 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1177 dma_dev->device_free_chan_resources = 1181 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1178 dma_dev->device_is_tx_complete = iop_ 1182 dma_dev->device_is_tx_complete = iop_adma_is_complete;
1179 dma_dev->device_issue_pending = iop_a 1183 dma_dev->device_issue_pending = iop_adma_issue_pending;
1180 dma_dev->device_dependency_added = io <<
1181 dma_dev->dev = &pdev->dev; 1184 dma_dev->dev = &pdev->dev;
1182 1185
1183 /* set prep routines based on capabil 1186 /* set prep routines based on capability */
1184 if (dma_has_cap(DMA_MEMCPY, dma_dev-> 1187 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1185 dma_dev->device_prep_dma_memc 1188 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1186 if (dma_has_cap(DMA_MEMSET, dma_dev-> 1189 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1187 dma_dev->device_prep_dma_mems 1190 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1188 if (dma_has_cap(DMA_XOR, dma_dev->cap 1191 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1189 dma_dev->max_xor = iop_adma_g 1192 dma_dev->max_xor = iop_adma_get_max_xor();
1190 dma_dev->device_prep_dma_xor 1193 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1191 } 1194 }
1192 if (dma_has_cap(DMA_ZERO_SUM, dma_dev 1195 if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1193 dma_dev->device_prep_dma_zero 1196 dma_dev->device_prep_dma_zero_sum =
1194 iop_adma_prep_dma_zer 1197 iop_adma_prep_dma_zero_sum;
1195 if (dma_has_cap(DMA_INTERRUPT, dma_de 1198 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1196 dma_dev->device_prep_dma_inte 1199 dma_dev->device_prep_dma_interrupt =
1197 iop_adma_prep_dma_int 1200 iop_adma_prep_dma_interrupt;
1198 1201
1199 iop_chan = kzalloc(sizeof(*iop_chan), 1202 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1200 if (!iop_chan) { 1203 if (!iop_chan) {
1201 ret = -ENOMEM; 1204 ret = -ENOMEM;
1202 goto err_free_dma; 1205 goto err_free_dma;
1203 } 1206 }
1204 iop_chan->device = adev; 1207 iop_chan->device = adev;
1205 1208
1206 iop_chan->mmr_base = devm_ioremap(&pd 1209 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1207 res-> 1210 res->end - res->start);
1208 if (!iop_chan->mmr_base) { 1211 if (!iop_chan->mmr_base) {
1209 ret = -ENOMEM; 1212 ret = -ENOMEM;
1210 goto err_free_iop_chan; 1213 goto err_free_iop_chan;
1211 } 1214 }
1212 tasklet_init(&iop_chan->irq_tasklet, 1215 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1213 iop_chan); 1216 iop_chan);
1214 1217
1215 /* clear errors before enabling inter 1218 /* clear errors before enabling interrupts */
1216 iop_adma_device_clear_err_status(iop_ 1219 iop_adma_device_clear_err_status(iop_chan);
1217 1220
1218 for (i = 0; i < 3; i++) { 1221 for (i = 0; i < 3; i++) {
1219 irq_handler_t handler[] = { i 1222 irq_handler_t handler[] = { iop_adma_eot_handler,
1220 iop_a 1223 iop_adma_eoc_handler,
1221 iop_a 1224 iop_adma_err_handler };
1222 int irq = platform_get_irq(pd 1225 int irq = platform_get_irq(pdev, i);
1223 if (irq < 0) { 1226 if (irq < 0) {
1224 ret = -ENXIO; 1227 ret = -ENXIO;
1225 goto err_free_iop_cha 1228 goto err_free_iop_chan;
1226 } else { 1229 } else {
1227 ret = devm_request_ir 1230 ret = devm_request_irq(&pdev->dev, irq,
1228 handl 1231 handler[i], 0, pdev->name, iop_chan);
1229 if (ret) 1232 if (ret)
1230 goto err_free 1233 goto err_free_iop_chan;
1231 } 1234 }
1232 } 1235 }
1233 1236
1234 spin_lock_init(&iop_chan->lock); 1237 spin_lock_init(&iop_chan->lock);
1235 init_timer(&iop_chan->cleanup_watchdo <<
1236 iop_chan->cleanup_watchdog.data = (un <<
1237 iop_chan->cleanup_watchdog.function = <<
1238 INIT_LIST_HEAD(&iop_chan->chain); 1238 INIT_LIST_HEAD(&iop_chan->chain);
1239 INIT_LIST_HEAD(&iop_chan->all_slots); 1239 INIT_LIST_HEAD(&iop_chan->all_slots);
1240 INIT_RCU_HEAD(&iop_chan->common.rcu); <<
1241 iop_chan->common.device = dma_dev; 1240 iop_chan->common.device = dma_dev;
1242 list_add_tail(&iop_chan->common.devic 1241 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1243 1242
1244 if (dma_has_cap(DMA_MEMCPY, dma_dev-> 1243 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1245 ret = iop_adma_memcpy_self_te 1244 ret = iop_adma_memcpy_self_test(adev);
1246 dev_dbg(&pdev->dev, "memcpy s 1245 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1247 if (ret) 1246 if (ret)
1248 goto err_free_iop_cha 1247 goto err_free_iop_chan;
1249 } 1248 }
1250 1249
1251 if (dma_has_cap(DMA_XOR, dma_dev->cap 1250 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1252 dma_has_cap(DMA_MEMSET, dma_d 1251 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1253 ret = iop_adma_xor_zero_sum_s 1252 ret = iop_adma_xor_zero_sum_self_test(adev);
1254 dev_dbg(&pdev->dev, "xor self 1253 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1255 if (ret) 1254 if (ret)
1256 goto err_free_iop_cha 1255 goto err_free_iop_chan;
1257 } 1256 }
1258 1257
1259 dev_printk(KERN_INFO, &pdev->dev, "In 1258 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1260 "( %s%s%s%s%s%s%s%s%s%s)\n", 1259 "( %s%s%s%s%s%s%s%s%s%s)\n",
1261 dma_has_cap(DMA_PQ_XOR, dma_dev->ca 1260 dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1262 dma_has_cap(DMA_PQ_UPDATE, dma_dev- 1261 dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1263 dma_has_cap(DMA_PQ_ZERO_SUM, dma_de 1262 dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1264 dma_has_cap(DMA_XOR, dma_dev->cap_m 1263 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1265 dma_has_cap(DMA_DUAL_XOR, dma_dev-> 1264 dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1266 dma_has_cap(DMA_ZERO_SUM, dma_dev-> 1265 dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1267 dma_has_cap(DMA_MEMSET, dma_dev->ca 1266 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1268 dma_has_cap(DMA_MEMCPY_CRC32C, dma_ 1267 dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1269 dma_has_cap(DMA_MEMCPY, dma_dev->ca 1268 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1270 dma_has_cap(DMA_INTERRUPT, dma_dev- 1269 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1271 1270
1272 dma_async_device_register(dma_dev); 1271 dma_async_device_register(dma_dev);
1273 goto out; 1272 goto out;
1274 1273
1275 err_free_iop_chan: 1274 err_free_iop_chan:
1276 kfree(iop_chan); 1275 kfree(iop_chan);
1277 err_free_dma: 1276 err_free_dma:
1278 dma_free_coherent(&adev->pdev->dev, p 1277 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1279 adev->dma_desc_pool_v 1278 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1280 err_free_adev: 1279 err_free_adev:
1281 kfree(adev); 1280 kfree(adev);
1282 out: 1281 out:
1283 return ret; 1282 return ret;
1284 } 1283 }
1285 1284
1286 static void iop_chan_start_null_memcpy(struct 1285 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1287 { 1286 {
1288 struct iop_adma_desc_slot *sw_desc, * 1287 struct iop_adma_desc_slot *sw_desc, *grp_start;
1289 dma_cookie_t cookie; 1288 dma_cookie_t cookie;
1290 int slot_cnt, slots_per_op; 1289 int slot_cnt, slots_per_op;
1291 1290
1292 dev_dbg(iop_chan->device->common.dev, 1291 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1293 1292
1294 spin_lock_bh(&iop_chan->lock); 1293 spin_lock_bh(&iop_chan->lock);
1295 slot_cnt = iop_chan_memcpy_slot_count 1294 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1296 sw_desc = iop_adma_alloc_slots(iop_ch 1295 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1297 if (sw_desc) { 1296 if (sw_desc) {
1298 grp_start = sw_desc->group_he 1297 grp_start = sw_desc->group_head;
1299 1298
1300 list_splice_init(&sw_desc->as 1299 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1301 sw_desc->async_tx.ack = 1; !! 1300 async_tx_ack(&sw_desc->async_tx);
1302 iop_desc_init_memcpy(grp_star 1301 iop_desc_init_memcpy(grp_start, 0);
1303 iop_desc_set_byte_count(grp_s 1302 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1304 iop_desc_set_dest_addr(grp_st 1303 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1305 iop_desc_set_memcpy_src_addr( 1304 iop_desc_set_memcpy_src_addr(grp_start, 0);
1306 1305
1307 cookie = iop_chan->common.coo 1306 cookie = iop_chan->common.cookie;
1308 cookie++; 1307 cookie++;
1309 if (cookie <= 1) 1308 if (cookie <= 1)
1310 cookie = 2; 1309 cookie = 2;
1311 1310
1312 /* initialize the completed c 1311 /* initialize the completed cookie to be less than
1313 * the most recently used coo 1312 * the most recently used cookie
1314 */ 1313 */
1315 iop_chan->completed_cookie = 1314 iop_chan->completed_cookie = cookie - 1;
1316 iop_chan->common.cookie = sw_ 1315 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1317 1316
1318 /* channel should not be busy 1317 /* channel should not be busy */
1319 BUG_ON(iop_chan_is_busy(iop_c 1318 BUG_ON(iop_chan_is_busy(iop_chan));
1320 1319
1321 /* clear any prior error-stat 1320 /* clear any prior error-status bits */
1322 iop_adma_device_clear_err_sta 1321 iop_adma_device_clear_err_status(iop_chan);
1323 1322
1324 /* disable operation */ 1323 /* disable operation */
1325 iop_chan_disable(iop_chan); 1324 iop_chan_disable(iop_chan);
1326 1325
1327 /* set the descriptor address 1326 /* set the descriptor address */
1328 iop_chan_set_next_descriptor( 1327 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1329 1328
1330 /* 1/ don't add pre-chained d 1329 /* 1/ don't add pre-chained descriptors
1331 * 2/ dummy read to flush nex 1330 * 2/ dummy read to flush next_desc write
1332 */ 1331 */
1333 BUG_ON(iop_desc_get_next_desc 1332 BUG_ON(iop_desc_get_next_desc(sw_desc));
1334 1333
1335 /* run the descriptor */ 1334 /* run the descriptor */
1336 iop_chan_enable(iop_chan); 1335 iop_chan_enable(iop_chan);
1337 } else 1336 } else
1338 dev_printk(KERN_ERR, iop_chan 1337 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1339 "failed to allocate 1338 "failed to allocate null descriptor\n");
1340 spin_unlock_bh(&iop_chan->lock); 1339 spin_unlock_bh(&iop_chan->lock);
1341 } 1340 }
1342 1341
1343 static void iop_chan_start_null_xor(struct io 1342 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1344 { 1343 {
1345 struct iop_adma_desc_slot *sw_desc, * 1344 struct iop_adma_desc_slot *sw_desc, *grp_start;
1346 dma_cookie_t cookie; 1345 dma_cookie_t cookie;
1347 int slot_cnt, slots_per_op; 1346 int slot_cnt, slots_per_op;
1348 1347
1349 dev_dbg(iop_chan->device->common.dev, 1348 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1350 1349
1351 spin_lock_bh(&iop_chan->lock); 1350 spin_lock_bh(&iop_chan->lock);
1352 slot_cnt = iop_chan_xor_slot_count(0, 1351 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1353 sw_desc = iop_adma_alloc_slots(iop_ch 1352 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1354 if (sw_desc) { 1353 if (sw_desc) {
1355 grp_start = sw_desc->group_he 1354 grp_start = sw_desc->group_head;
1356 list_splice_init(&sw_desc->as 1355 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1357 sw_desc->async_tx.ack = 1; !! 1356 async_tx_ack(&sw_desc->async_tx);
1358 iop_desc_init_null_xor(grp_st 1357 iop_desc_init_null_xor(grp_start, 2, 0);
1359 iop_desc_set_byte_count(grp_s 1358 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1360 iop_desc_set_dest_addr(grp_st 1359 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1361 iop_desc_set_xor_src_addr(grp 1360 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1362 iop_desc_set_xor_src_addr(grp 1361 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1363 1362
1364 cookie = iop_chan->common.coo 1363 cookie = iop_chan->common.cookie;
1365 cookie++; 1364 cookie++;
1366 if (cookie <= 1) 1365 if (cookie <= 1)
1367 cookie = 2; 1366 cookie = 2;
1368 1367
1369 /* initialize the completed c 1368 /* initialize the completed cookie to be less than
1370 * the most recently used coo 1369 * the most recently used cookie
1371 */ 1370 */
1372 iop_chan->completed_cookie = 1371 iop_chan->completed_cookie = cookie - 1;
1373 iop_chan->common.cookie = sw_ 1372 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1374 1373
1375 /* channel should not be busy 1374 /* channel should not be busy */
1376 BUG_ON(iop_chan_is_busy(iop_c 1375 BUG_ON(iop_chan_is_busy(iop_chan));
1377 1376
1378 /* clear any prior error-stat 1377 /* clear any prior error-status bits */
1379 iop_adma_device_clear_err_sta 1378 iop_adma_device_clear_err_status(iop_chan);
1380 1379
1381 /* disable operation */ 1380 /* disable operation */
1382 iop_chan_disable(iop_chan); 1381 iop_chan_disable(iop_chan);
1383 1382
1384 /* set the descriptor address 1383 /* set the descriptor address */
1385 iop_chan_set_next_descriptor( 1384 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1386 1385
1387 /* 1/ don't add pre-chained d 1386 /* 1/ don't add pre-chained descriptors
1388 * 2/ dummy read to flush nex 1387 * 2/ dummy read to flush next_desc write
1389 */ 1388 */
1390 BUG_ON(iop_desc_get_next_desc 1389 BUG_ON(iop_desc_get_next_desc(sw_desc));
1391 1390
1392 /* run the descriptor */ 1391 /* run the descriptor */
1393 iop_chan_enable(iop_chan); 1392 iop_chan_enable(iop_chan);
1394 } else 1393 } else
1395 dev_printk(KERN_ERR, iop_chan 1394 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1396 "failed to allocate n 1395 "failed to allocate null descriptor\n");
1397 spin_unlock_bh(&iop_chan->lock); 1396 spin_unlock_bh(&iop_chan->lock);
1398 } 1397 }
1399 1398
>> 1399 MODULE_ALIAS("platform:iop-adma");
>> 1400
1400 static struct platform_driver iop_adma_driver 1401 static struct platform_driver iop_adma_driver = {
1401 .probe = iop_adma_probe, 1402 .probe = iop_adma_probe,
1402 .remove = iop_adma_remove, !! 1403 .remove = __devexit_p(iop_adma_remove),
1403 .driver = { 1404 .driver = {
1404 .owner = THIS_MODULE, 1405 .owner = THIS_MODULE,
1405 .name = "iop-adma", 1406 .name = "iop-adma",
1406 }, 1407 },
1407 }; 1408 };
1408 1409
1409 static int __init iop_adma_init (void) 1410 static int __init iop_adma_init (void)
1410 { 1411 {
1411 return platform_driver_register(&iop_ 1412 return platform_driver_register(&iop_adma_driver);
1412 } 1413 }
1413 1414
1414 /* it's currently unsafe to unload this modul <<
1415 #if 0 <<
1416 static void __exit iop_adma_exit (void) 1415 static void __exit iop_adma_exit (void)
1417 { 1416 {
1418 platform_driver_unregister(&iop_adma_ 1417 platform_driver_unregister(&iop_adma_driver);
1419 return; 1418 return;
1420 } 1419 }
1421 module_exit(iop_adma_exit); 1420 module_exit(iop_adma_exit);
1422 #endif <<
1423 <<
1424 module_init(iop_adma_init); 1421 module_init(iop_adma_init);
1425 1422
1426 MODULE_AUTHOR("Intel Corporation"); 1423 MODULE_AUTHOR("Intel Corporation");
1427 MODULE_DESCRIPTION("IOP ADMA Engine Driver"); 1424 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1428 MODULE_LICENSE("GPL"); 1425 MODULE_LICENSE("GPL");
1429 1426
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