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1 /* i915_drv.c -- i830,i845,i855,i865,i915 driv 1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */ 2 */
3 /* !! 3
4 * !! 4 /**************************************************************************
>> 5 *
5 * Copyright 2003 Tungsten Graphics, Inc., Ced 6 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved. 7 * All Rights Reserved.
7 * !! 8 *
8 * Permission is hereby granted, free of charg !! 9 **************************************************************************/
9 * copy of this software and associated docume <<
10 * "Software"), to deal in the Software withou <<
11 * without limitation the rights to use, copy, <<
12 * distribute, sub license, and/or sell copies <<
13 * permit persons to whom the Software is furn <<
14 * the following conditions: <<
15 * <<
16 * The above copyright notice and this permiss <<
17 * next paragraph) shall be included in all co <<
18 * of the Software. <<
19 * <<
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W <<
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO TH <<
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P <<
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR <<
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHET <<
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR <<
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN TH <<
27 * <<
28 */ <<
29 10
30 #include "drmP.h" 11 #include "drmP.h"
31 #include "drm.h" 12 #include "drm.h"
32 #include "i915_drm.h" 13 #include "i915_drm.h"
33 #include "i915_drv.h" 14 #include "i915_drv.h"
34 15
35 #include "drm_pciids.h" 16 #include "drm_pciids.h"
36 17
37 static struct pci_device_id pciidlist[] = { !! 18 int postinit( struct drm_device *dev, unsigned long flags )
38 i915_PCI_IDS <<
39 }; <<
40 <<
41 enum pipe { <<
42 PIPE_A = 0, <<
43 PIPE_B, <<
44 }; <<
45 <<
46 static bool i915_pipe_enabled(struct drm_devic <<
47 { <<
48 struct drm_i915_private *dev_priv = de <<
49 <<
50 if (pipe == PIPE_A) <<
51 return (I915_READ(DPLL_A) & DP <<
52 else <<
53 return (I915_READ(DPLL_B) & DP <<
54 } <<
55 <<
56 static void i915_save_palette(struct drm_devic <<
57 { <<
58 struct drm_i915_private *dev_priv = de <<
59 unsigned long reg = (pipe == PIPE_A ? <<
60 u32 *array; <<
61 int i; <<
62 <<
63 if (!i915_pipe_enabled(dev, pipe)) <<
64 return; <<
65 <<
66 if (pipe == PIPE_A) <<
67 array = dev_priv->save_palette <<
68 else <<
69 array = dev_priv->save_palette <<
70 <<
71 for(i = 0; i < 256; i++) <<
72 array[i] = I915_READ(reg + (i <<
73 } <<
74 <<
75 static void i915_restore_palette(struct drm_de <<
76 { <<
77 struct drm_i915_private *dev_priv = de <<
78 unsigned long reg = (pipe == PIPE_A ? <<
79 u32 *array; <<
80 int i; <<
81 <<
82 if (!i915_pipe_enabled(dev, pipe)) <<
83 return; <<
84 <<
85 if (pipe == PIPE_A) <<
86 array = dev_priv->save_palette <<
87 else <<
88 array = dev_priv->save_palette <<
89 <<
90 for(i = 0; i < 256; i++) <<
91 I915_WRITE(reg + (i << 2), arr <<
92 } <<
93 <<
94 static u8 i915_read_indexed(u16 index_port, u1 <<
95 { 19 {
96 outb(reg, index_port); !! 20 dev->counters += 4;
97 return inb(data_port); !! 21 dev->types[6] = _DRM_STAT_IRQ;
98 } !! 22 dev->types[7] = _DRM_STAT_PRIMARY;
99 !! 23 dev->types[8] = _DRM_STAT_SECONDARY;
100 static u8 i915_read_ar(u16 st01, u8 reg, u16 p !! 24 dev->types[9] = _DRM_STAT_DMA;
101 { !! 25
102 inb(st01); !! 26 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n",
103 outb(palette_enable | reg, VGA_AR_INDE !! 27 DRIVER_NAME,
104 return inb(VGA_AR_DATA_READ); !! 28 DRIVER_MAJOR,
105 } !! 29 DRIVER_MINOR,
106 !! 30 DRIVER_PATCHLEVEL,
107 static void i915_write_ar(u8 st01, u8 reg, u8 !! 31 DRIVER_DATE,
108 { !! 32 dev->minor,
109 inb(st01); !! 33 pci_pretty_name(dev->pdev)
110 outb(palette_enable | reg, VGA_AR_INDE !! 34 );
111 outb(val, VGA_AR_DATA_WRITE); !! 35 return 0;
112 } <<
113 <<
114 static void i915_write_indexed(u16 index_port, <<
115 { <<
116 outb(reg, index_port); <<
117 outb(val, data_port); <<
118 } <<
119 <<
120 static void i915_save_vga(struct drm_device *d <<
121 { <<
122 struct drm_i915_private *dev_priv = de <<
123 int i; <<
124 u16 cr_index, cr_data, st01; <<
125 <<
126 /* VGA color palette registers */ <<
127 dev_priv->saveDACMASK = inb(VGA_DACMAS <<
128 /* DACCRX automatically increments dur <<
129 outb(0, VGA_DACRX); <<
130 /* Read 3 bytes of color data from eac <<
131 for (i = 0; i < 256 * 3; i++) <<
132 dev_priv->saveDACDATA[i] = inb <<
133 <<
134 /* MSR bits */ <<
135 dev_priv->saveMSR = inb(VGA_MSR_READ); <<
136 if (dev_priv->saveMSR & VGA_MSR_CGA_MO <<
137 cr_index = VGA_CR_INDEX_CGA; <<
138 cr_data = VGA_CR_DATA_CGA; <<
139 st01 = VGA_ST01_CGA; <<
140 } else { <<
141 cr_index = VGA_CR_INDEX_MDA; <<
142 cr_data = VGA_CR_DATA_MDA; <<
143 st01 = VGA_ST01_MDA; <<
144 } <<
145 <<
146 /* CRT controller regs */ <<
147 i915_write_indexed(cr_index, cr_data, <<
148 i915_read_indexed(c <<
149 (~0x80)); <<
150 for (i = 0; i < 0x24; i++) <<
151 dev_priv->saveCR[i] = <<
152 i915_read_indexed(cr_i <<
153 /* Make sure we don't turn off CR grou <<
154 dev_priv->saveCR[0x11] &= ~0x80; <<
155 <<
156 /* Attribute controller registers */ <<
157 inb(st01); <<
158 dev_priv->saveAR_INDEX = inb(VGA_AR_IN <<
159 for (i = 0; i < 20; i++) <<
160 dev_priv->saveAR[i] = i915_rea <<
161 inb(st01); <<
162 outb(dev_priv->saveAR_INDEX, VGA_AR_IN <<
163 inb(st01); <<
164 <<
165 /* Graphics controller registers */ <<
166 for (i = 0; i < 9; i++) <<
167 dev_priv->saveGR[i] = <<
168 i915_read_indexed(VGA_ <<
169 <<
170 dev_priv->saveGR[0x10] = <<
171 i915_read_indexed(VGA_GR_INDEX <<
172 dev_priv->saveGR[0x11] = <<
173 i915_read_indexed(VGA_GR_INDEX <<
174 dev_priv->saveGR[0x18] = <<
175 i915_read_indexed(VGA_GR_INDEX <<
176 <<
177 /* Sequencer registers */ <<
178 for (i = 0; i < 8; i++) <<
179 dev_priv->saveSR[i] = <<
180 i915_read_indexed(VGA_ <<
181 } <<
182 <<
183 static void i915_restore_vga(struct drm_device <<
184 { <<
185 struct drm_i915_private *dev_priv = de <<
186 int i; <<
187 u16 cr_index, cr_data, st01; <<
188 <<
189 /* MSR bits */ <<
190 outb(dev_priv->saveMSR, VGA_MSR_WRITE) <<
191 if (dev_priv->saveMSR & VGA_MSR_CGA_MO <<
192 cr_index = VGA_CR_INDEX_CGA; <<
193 cr_data = VGA_CR_DATA_CGA; <<
194 st01 = VGA_ST01_CGA; <<
195 } else { <<
196 cr_index = VGA_CR_INDEX_MDA; <<
197 cr_data = VGA_CR_DATA_MDA; <<
198 st01 = VGA_ST01_MDA; <<
199 } <<
200 <<
201 /* Sequencer registers, don't write SR <<
202 for (i = 0; i < 7; i++) <<
203 i915_write_indexed(VGA_SR_INDE <<
204 dev_priv->s <<
205 <<
206 /* CRT controller regs */ <<
207 /* Enable CR group 0 writes */ <<
208 i915_write_indexed(cr_index, cr_data, <<
209 for (i = 0; i < 0x24; i++) <<
210 i915_write_indexed(cr_index, c <<
211 <<
212 /* Graphics controller regs */ <<
213 for (i = 0; i < 9; i++) <<
214 i915_write_indexed(VGA_GR_INDE <<
215 dev_priv->s <<
216 <<
217 i915_write_indexed(VGA_GR_INDEX, VGA_G <<
218 dev_priv->saveGR[0x <<
219 i915_write_indexed(VGA_GR_INDEX, VGA_G <<
220 dev_priv->saveGR[0x <<
221 i915_write_indexed(VGA_GR_INDEX, VGA_G <<
222 dev_priv->saveGR[0x <<
223 <<
224 /* Attribute controller registers */ <<
225 inb(st01); <<
226 for (i = 0; i < 20; i++) <<
227 i915_write_ar(st01, i, dev_pri <<
228 inb(st01); /* switch back to index mod <<
229 outb(dev_priv->saveAR_INDEX | 0x20, VG <<
230 inb(st01); <<
231 <<
232 /* VGA color palette registers */ <<
233 outb(dev_priv->saveDACMASK, VGA_DACMAS <<
234 /* DACCRX automatically increments dur <<
235 outb(0, VGA_DACWX); <<
236 /* Read 3 bytes of color data from eac <<
237 for (i = 0; i < 256 * 3; i++) <<
238 outb(dev_priv->saveDACDATA[i], <<
239 <<
240 } 36 }
241 37
242 static int i915_suspend(struct drm_device *dev !! 38 static int version( drm_version_t *version )
243 { 39 {
244 struct drm_i915_private *dev_priv = de !! 40 int len;
245 int i; <<
246 <<
247 if (!dev || !dev_priv) { <<
248 printk(KERN_ERR "dev: %p, dev_ <<
249 printk(KERN_ERR "DRM not initi <<
250 return -ENODEV; <<
251 } <<
252 <<
253 if (state.event == PM_EVENT_PRETHAW) <<
254 return 0; <<
255 <<
256 pci_save_state(dev->pdev); <<
257 pci_read_config_byte(dev->pdev, LBB, & <<
258 <<
259 /* Pipe & plane A info */ <<
260 dev_priv->savePIPEACONF = I915_READ(PI <<
261 dev_priv->savePIPEASRC = I915_READ(PIP <<
262 dev_priv->saveFPA0 = I915_READ(FPA0); <<
263 dev_priv->saveFPA1 = I915_READ(FPA1); <<
264 dev_priv->saveDPLL_A = I915_READ(DPLL_ <<
265 if (IS_I965G(dev)) <<
266 dev_priv->saveDPLL_A_MD = I915 <<
267 dev_priv->saveHTOTAL_A = I915_READ(HTO <<
268 dev_priv->saveHBLANK_A = I915_READ(HBL <<
269 dev_priv->saveHSYNC_A = I915_READ(HSYN <<
270 dev_priv->saveVTOTAL_A = I915_READ(VTO <<
271 dev_priv->saveVBLANK_A = I915_READ(VBL <<
272 dev_priv->saveVSYNC_A = I915_READ(VSYN <<
273 dev_priv->saveBCLRPAT_A = I915_READ(BC <<
274 <<
275 dev_priv->saveDSPACNTR = I915_READ(DSP <<
276 dev_priv->saveDSPASTRIDE = I915_READ(D <<
277 dev_priv->saveDSPASIZE = I915_READ(DSP <<
278 dev_priv->saveDSPAPOS = I915_READ(DSPA <<
279 dev_priv->saveDSPABASE = I915_READ(DSP <<
280 if (IS_I965G(dev)) { <<
281 dev_priv->saveDSPASURF = I915_ <<
282 dev_priv->saveDSPATILEOFF = I9 <<
283 } <<
284 i915_save_palette(dev, PIPE_A); <<
285 dev_priv->savePIPEASTAT = I915_READ(I9 <<
286 <<
287 /* Pipe & plane B info */ <<
288 dev_priv->savePIPEBCONF = I915_READ(PI <<
289 dev_priv->savePIPEBSRC = I915_READ(PIP <<
290 dev_priv->saveFPB0 = I915_READ(FPB0); <<
291 dev_priv->saveFPB1 = I915_READ(FPB1); <<
292 dev_priv->saveDPLL_B = I915_READ(DPLL_ <<
293 if (IS_I965G(dev)) <<
294 dev_priv->saveDPLL_B_MD = I915 <<
295 dev_priv->saveHTOTAL_B = I915_READ(HTO <<
296 dev_priv->saveHBLANK_B = I915_READ(HBL <<
297 dev_priv->saveHSYNC_B = I915_READ(HSYN <<
298 dev_priv->saveVTOTAL_B = I915_READ(VTO <<
299 dev_priv->saveVBLANK_B = I915_READ(VBL <<
300 dev_priv->saveVSYNC_B = I915_READ(VSYN <<
301 dev_priv->saveBCLRPAT_A = I915_READ(BC <<
302 <<
303 dev_priv->saveDSPBCNTR = I915_READ(DSP <<
304 dev_priv->saveDSPBSTRIDE = I915_READ(D <<
305 dev_priv->saveDSPBSIZE = I915_READ(DSP <<
306 dev_priv->saveDSPBPOS = I915_READ(DSPB <<
307 dev_priv->saveDSPBBASE = I915_READ(DSP <<
308 if (IS_I965GM(dev) || IS_IGD_GM(dev)) <<
309 dev_priv->saveDSPBSURF = I915_ <<
310 dev_priv->saveDSPBTILEOFF = I9 <<
311 } <<
312 i915_save_palette(dev, PIPE_B); <<
313 dev_priv->savePIPEBSTAT = I915_READ(I9 <<
314 <<
315 /* CRT state */ <<
316 dev_priv->saveADPA = I915_READ(ADPA); <<
317 <<
318 /* LVDS state */ <<
319 dev_priv->savePP_CONTROL = I915_READ(P <<
320 dev_priv->savePFIT_PGM_RATIOS = I915_R <<
321 dev_priv->saveBLC_PWM_CTL = I915_READ( <<
322 if (IS_I965G(dev)) <<
323 dev_priv->saveBLC_PWM_CTL2 = I <<
324 if (IS_MOBILE(dev) && !IS_I830(dev)) <<
325 dev_priv->saveLVDS = I915_READ <<
326 if (!IS_I830(dev) && !IS_845G(dev)) <<
327 dev_priv->savePFIT_CONTROL = I <<
328 dev_priv->saveLVDSPP_ON = I915_READ(LV <<
329 dev_priv->saveLVDSPP_OFF = I915_READ(L <<
330 dev_priv->savePP_CYCLE = I915_READ(PP_ <<
331 <<
332 /* FIXME: save TV & SDVO state */ <<
333 <<
334 /* FBC state */ <<
335 dev_priv->saveFBC_CFB_BASE = I915_READ <<
336 dev_priv->saveFBC_LL_BASE = I915_READ( <<
337 dev_priv->saveFBC_CONTROL2 = I915_READ <<
338 dev_priv->saveFBC_CONTROL = I915_READ( <<
339 <<
340 /* Interrupt state */ <<
341 dev_priv->saveIIR = I915_READ(I915REG_ <<
342 dev_priv->saveIER = I915_READ(I915REG_ <<
343 dev_priv->saveIMR = I915_READ(I915REG_ <<
344 <<
345 /* VGA state */ <<
346 dev_priv->saveVCLK_DIVISOR_VGA0 = I915 <<
347 dev_priv->saveVCLK_DIVISOR_VGA1 = I915 <<
348 dev_priv->saveVCLK_POST_DIV = I915_REA <<
349 dev_priv->saveVGACNTRL = I915_READ(VGA <<
350 <<
351 /* Clock gating state */ <<
352 dev_priv->saveDSPCLK_GATE_D = I915_REA <<
353 <<
354 /* Cache mode state */ <<
355 dev_priv->saveCACHE_MODE_0 = I915_READ <<
356 <<
357 /* Memory Arbitration state */ <<
358 dev_priv->saveMI_ARB_STATE = I915_READ <<
359 <<
360 /* Scratch space */ <<
361 for (i = 0; i < 16; i++) { <<
362 dev_priv->saveSWF0[i] = I915_R <<
363 dev_priv->saveSWF1[i] = I915_R <<
364 } <<
365 for (i = 0; i < 3; i++) <<
366 dev_priv->saveSWF2[i] = I915_R <<
367 <<
368 i915_save_vga(dev); <<
369 <<
370 if (state.event == PM_EVENT_SUSPEND) { <<
371 /* Shut down the device */ <<
372 pci_disable_device(dev->pdev); <<
373 pci_set_power_state(dev->pdev, <<
374 } <<
375 41
>> 42 version->version_major = DRIVER_MAJOR;
>> 43 version->version_minor = DRIVER_MINOR;
>> 44 version->version_patchlevel = DRIVER_PATCHLEVEL;
>> 45 DRM_COPY( version->name, DRIVER_NAME );
>> 46 DRM_COPY( version->date, DRIVER_DATE );
>> 47 DRM_COPY( version->desc, DRIVER_DESC );
376 return 0; 48 return 0;
377 } 49 }
378 50
379 static int i915_resume(struct drm_device *dev) !! 51 static struct pci_device_id pciidlist[] = {
380 { !! 52 i915_PCI_IDS
381 struct drm_i915_private *dev_priv = de !! 53 };
382 int i; <<
383 <<
384 pci_set_power_state(dev->pdev, PCI_D0) <<
385 pci_restore_state(dev->pdev); <<
386 if (pci_enable_device(dev->pdev)) <<
387 return -1; <<
388 <<
389 pci_write_config_byte(dev->pdev, LBB, <<
390 <<
391 /* Pipe & plane A info */ <<
392 /* Prime the clock */ <<
393 if (dev_priv->saveDPLL_A & DPLL_VCO_EN <<
394 I915_WRITE(DPLL_A, dev_priv->s <<
395 ~DPLL_VCO_ENABLE); <<
396 udelay(150); <<
397 } <<
398 I915_WRITE(FPA0, dev_priv->saveFPA0); <<
399 I915_WRITE(FPA1, dev_priv->saveFPA1); <<
400 /* Actually enable it */ <<
401 I915_WRITE(DPLL_A, dev_priv->saveDPLL_ <<
402 udelay(150); <<
403 if (IS_I965G(dev)) <<
404 I915_WRITE(DPLL_A_MD, dev_priv <<
405 udelay(150); <<
406 <<
407 /* Restore mode */ <<
408 I915_WRITE(HTOTAL_A, dev_priv->saveHTO <<
409 I915_WRITE(HBLANK_A, dev_priv->saveHBL <<
410 I915_WRITE(HSYNC_A, dev_priv->saveHSYN <<
411 I915_WRITE(VTOTAL_A, dev_priv->saveVTO <<
412 I915_WRITE(VBLANK_A, dev_priv->saveVBL <<
413 I915_WRITE(VSYNC_A, dev_priv->saveVSYN <<
414 I915_WRITE(BCLRPAT_A, dev_priv->saveBC <<
415 <<
416 /* Restore plane info */ <<
417 I915_WRITE(DSPASIZE, dev_priv->saveDSP <<
418 I915_WRITE(DSPAPOS, dev_priv->saveDSPA <<
419 I915_WRITE(PIPEASRC, dev_priv->savePIP <<
420 I915_WRITE(DSPABASE, dev_priv->saveDSP <<
421 I915_WRITE(DSPASTRIDE, dev_priv->saveD <<
422 if (IS_I965G(dev)) { <<
423 I915_WRITE(DSPASURF, dev_priv- <<
424 I915_WRITE(DSPATILEOFF, dev_pr <<
425 } <<
426 <<
427 I915_WRITE(PIPEACONF, dev_priv->savePI <<
428 <<
429 i915_restore_palette(dev, PIPE_A); <<
430 /* Enable the plane */ <<
431 I915_WRITE(DSPACNTR, dev_priv->saveDSP <<
432 I915_WRITE(DSPABASE, I915_READ(DSPABAS <<
433 <<
434 /* Pipe & plane B info */ <<
435 if (dev_priv->saveDPLL_B & DPLL_VCO_EN <<
436 I915_WRITE(DPLL_B, dev_priv->s <<
437 ~DPLL_VCO_ENABLE); <<
438 udelay(150); <<
439 } <<
440 I915_WRITE(FPB0, dev_priv->saveFPB0); <<
441 I915_WRITE(FPB1, dev_priv->saveFPB1); <<
442 /* Actually enable it */ <<
443 I915_WRITE(DPLL_B, dev_priv->saveDPLL_ <<
444 udelay(150); <<
445 if (IS_I965G(dev)) <<
446 I915_WRITE(DPLL_B_MD, dev_priv <<
447 udelay(150); <<
448 <<
449 /* Restore mode */ <<
450 I915_WRITE(HTOTAL_B, dev_priv->saveHTO <<
451 I915_WRITE(HBLANK_B, dev_priv->saveHBL <<
452 I915_WRITE(HSYNC_B, dev_priv->saveHSYN <<
453 I915_WRITE(VTOTAL_B, dev_priv->saveVTO <<
454 I915_WRITE(VBLANK_B, dev_priv->saveVBL <<
455 I915_WRITE(VSYNC_B, dev_priv->saveVSYN <<
456 I915_WRITE(BCLRPAT_B, dev_priv->saveBC <<
457 <<
458 /* Restore plane info */ <<
459 I915_WRITE(DSPBSIZE, dev_priv->saveDSP <<
460 I915_WRITE(DSPBPOS, dev_priv->saveDSPB <<
461 I915_WRITE(PIPEBSRC, dev_priv->savePIP <<
462 I915_WRITE(DSPBBASE, dev_priv->saveDSP <<
463 I915_WRITE(DSPBSTRIDE, dev_priv->saveD <<
464 if (IS_I965G(dev)) { <<
465 I915_WRITE(DSPBSURF, dev_priv- <<
466 I915_WRITE(DSPBTILEOFF, dev_pr <<
467 } <<
468 <<
469 I915_WRITE(PIPEBCONF, dev_priv->savePI <<
470 <<
471 i915_restore_palette(dev, PIPE_B); <<
472 /* Enable the plane */ <<
473 I915_WRITE(DSPBCNTR, dev_priv->saveDSP <<
474 I915_WRITE(DSPBBASE, I915_READ(DSPBBAS <<
475 <<
476 /* CRT state */ <<
477 I915_WRITE(ADPA, dev_priv->saveADPA); <<
478 <<
479 /* LVDS state */ <<
480 if (IS_I965G(dev)) <<
481 I915_WRITE(BLC_PWM_CTL2, dev_p <<
482 if (IS_MOBILE(dev) && !IS_I830(dev)) <<
483 I915_WRITE(LVDS, dev_priv->sav <<
484 if (!IS_I830(dev) && !IS_845G(dev)) <<
485 I915_WRITE(PFIT_CONTROL, dev_p <<
486 <<
487 I915_WRITE(PFIT_PGM_RATIOS, dev_priv-> <<
488 I915_WRITE(BLC_PWM_CTL, dev_priv->save <<
489 I915_WRITE(LVDSPP_ON, dev_priv->saveLV <<
490 I915_WRITE(LVDSPP_OFF, dev_priv->saveL <<
491 I915_WRITE(PP_CYCLE, dev_priv->savePP_ <<
492 I915_WRITE(PP_CONTROL, dev_priv->saveP <<
493 <<
494 /* FIXME: restore TV & SDVO state */ <<
495 <<
496 /* FBC info */ <<
497 I915_WRITE(FBC_CFB_BASE, dev_priv->sav <<
498 I915_WRITE(FBC_LL_BASE, dev_priv->save <<
499 I915_WRITE(FBC_CONTROL2, dev_priv->sav <<
500 I915_WRITE(FBC_CONTROL, dev_priv->save <<
501 <<
502 /* VGA state */ <<
503 I915_WRITE(VGACNTRL, dev_priv->saveVGA <<
504 I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv <<
505 I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv <<
506 I915_WRITE(VCLK_POST_DIV, dev_priv->sa <<
507 udelay(150); <<
508 <<
509 /* Clock gating state */ <<
510 I915_WRITE (DSPCLK_GATE_D, dev_priv->s <<
511 <<
512 /* Cache mode state */ <<
513 I915_WRITE (CACHE_MODE_0, dev_priv->sa <<
514 <<
515 /* Memory arbitration state */ <<
516 I915_WRITE (MI_ARB_STATE, dev_priv->sa <<
517 <<
518 for (i = 0; i < 16; i++) { <<
519 I915_WRITE(SWF0 + (i << 2), de <<
520 I915_WRITE(SWF10 + (i << 2), d <<
521 } <<
522 for (i = 0; i < 3; i++) <<
523 I915_WRITE(SWF30 + (i << 2), d <<
524 <<
525 i915_restore_vga(dev); <<
526 54
527 return 0; !! 55 extern drm_ioctl_desc_t i915_ioctls[];
528 } !! 56 extern int i915_max_ioctl;
529 57
530 static struct drm_driver driver = { 58 static struct drm_driver driver = {
531 /* don't use mtrr's here, the Xserver !! 59 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
532 * deal with them for intel hardware. !! 60 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
533 */ !! 61 .pretakedown = i915_driver_pretakedown,
534 .driver_features = !! 62 .prerelease = i915_driver_prerelease,
535 DRIVER_USE_AGP | DRIVER_REQUIRE_AG <<
536 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARE <<
537 DRIVER_IRQ_VBL2, <<
538 .load = i915_driver_load, <<
539 .unload = i915_driver_unload, <<
540 .lastclose = i915_driver_lastclose, <<
541 .preclose = i915_driver_preclose, <<
542 .suspend = i915_suspend, <<
543 .resume = i915_resume, <<
544 .device_is_agp = i915_driver_device_is <<
545 .vblank_wait = i915_driver_vblank_wait <<
546 .vblank_wait2 = i915_driver_vblank_wai <<
547 .irq_preinstall = i915_driver_irq_prei 63 .irq_preinstall = i915_driver_irq_preinstall,
548 .irq_postinstall = i915_driver_irq_pos 64 .irq_postinstall = i915_driver_irq_postinstall,
549 .irq_uninstall = i915_driver_irq_unins 65 .irq_uninstall = i915_driver_irq_uninstall,
550 .irq_handler = i915_driver_irq_handler 66 .irq_handler = i915_driver_irq_handler,
551 .reclaim_buffers = drm_core_reclaim_bu 67 .reclaim_buffers = drm_core_reclaim_buffers,
552 .get_map_ofs = drm_core_get_map_ofs, 68 .get_map_ofs = drm_core_get_map_ofs,
553 .get_reg_ofs = drm_core_get_reg_ofs, 69 .get_reg_ofs = drm_core_get_reg_ofs,
>> 70 .postinit = postinit,
>> 71 .version = version,
554 .ioctls = i915_ioctls, 72 .ioctls = i915_ioctls,
555 .fops = { 73 .fops = {
556 .owner = THIS_MODULE, !! 74 .owner = THIS_MODULE,
557 .open = drm_open, !! 75 .open = drm_open,
558 .release = drm_release, !! 76 .release = drm_release,
559 .ioctl = drm_ioctl, !! 77 .ioctl = drm_ioctl,
560 .mmap = drm_mmap, !! 78 .mmap = drm_mmap,
561 .poll = drm_poll, !! 79 .poll = drm_poll,
562 .fasync = drm_fasync, !! 80 .fasync = drm_fasync,
563 #ifdef CONFIG_COMPAT <<
564 .compat_ioctl = i915_compat_i <<
565 #endif <<
566 }, 81 },
567 <<
568 .pci_driver = { 82 .pci_driver = {
569 .name = DRIVER_NAME, !! 83 .name = DRIVER_NAME,
570 .id_table = pciidlist, !! 84 .id_table = pciidlist,
571 }, !! 85 }
572 <<
573 .name = DRIVER_NAME, <<
574 .desc = DRIVER_DESC, <<
575 .date = DRIVER_DATE, <<
576 .major = DRIVER_MAJOR, <<
577 .minor = DRIVER_MINOR, <<
578 .patchlevel = DRIVER_PATCHLEVEL, <<
579 }; 86 };
580 87
581 static int __init i915_init(void) 88 static int __init i915_init(void)
582 { 89 {
583 driver.num_ioctls = i915_max_ioctl; 90 driver.num_ioctls = i915_max_ioctl;
584 return drm_init(&driver); 91 return drm_init(&driver);
585 } 92 }
586 93
587 static void __exit i915_exit(void) 94 static void __exit i915_exit(void)
588 { 95 {
589 drm_exit(&driver); 96 drm_exit(&driver);
590 } 97 }
591 98
592 module_init(i915_init); 99 module_init(i915_init);
593 module_exit(i915_exit); 100 module_exit(i915_exit);
594 101
595 MODULE_AUTHOR(DRIVER_AUTHOR); !! 102 MODULE_AUTHOR( DRIVER_AUTHOR );
596 MODULE_DESCRIPTION(DRIVER_DESC); !! 103 MODULE_DESCRIPTION( DRIVER_DESC );
597 MODULE_LICENSE("GPL and additional rights"); 104 MODULE_LICENSE("GPL and additional rights");
598 105
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