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1 /** 1 /**
2 * \file drm.h !! 2 * \file drm.h
3 * Header for the Direct Rendering Manager 3 * Header for the Direct Rendering Manager
4 * !! 4 *
5 * \author Rickard E. (Rik) Faith <faith@valin 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * 6 *
7 * \par Acknowledgments: 7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.ne 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */ 9 */
10 10
11 /* 11 /*
12 * Copyright 1999 Precision Insight, Inc., Ced 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunn 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved. 14 * All rights reserved.
15 * 15 *
16 * Permission is hereby granted, free of charg 16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated docume 17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction 18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, pub 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to 20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to 21 * Software is furnished to do so, subject to the following conditions:
22 * 22 *
23 * The above copyright notice and this permiss 23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies 24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software. 25 * Software.
26 * 26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE W 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINF 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LI 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CO 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE. 33 * OTHER DEALINGS IN THE SOFTWARE.
34 */ 34 */
35 35
>> 36
36 #ifndef _DRM_H_ 37 #ifndef _DRM_H_
37 #define _DRM_H_ 38 #define _DRM_H_
38 39
39 #if defined(__linux__) 40 #if defined(__linux__)
40 #if defined(__KERNEL__) !! 41 #include <linux/config.h>
41 #endif <<
42 #include <asm/ioctl.h> /* For _IO* ma 42 #include <asm/ioctl.h> /* For _IO* macros */
43 #define DRM_IOCTL_NR(n) _IOC_NR(n) 43 #define DRM_IOCTL_NR(n) _IOC_NR(n)
44 #define DRM_IOC_VOID _IOC_NONE 44 #define DRM_IOC_VOID _IOC_NONE
45 #define DRM_IOC_READ _IOC_READ 45 #define DRM_IOC_READ _IOC_READ
46 #define DRM_IOC_WRITE _IOC_WRITE 46 #define DRM_IOC_WRITE _IOC_WRITE
47 #define DRM_IOC_READWRITE _IOC_READ|_IOC 47 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
48 #define DRM_IOC(dir, group, nr, size) _IOC(dir 48 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
49 #elif defined(__FreeBSD__) || defined(__NetBSD 49 #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
50 #if defined(__FreeBSD__) && defined(IN_MODULE) 50 #if defined(__FreeBSD__) && defined(IN_MODULE)
51 /* Prevent name collision when including sys/i 51 /* Prevent name collision when including sys/ioccom.h */
52 #undef ioctl 52 #undef ioctl
53 #include <sys/ioccom.h> 53 #include <sys/ioccom.h>
54 #define ioctl(a,b,c) xf86ioctl(a,b, 54 #define ioctl(a,b,c) xf86ioctl(a,b,c)
55 #else 55 #else
56 #include <sys/ioccom.h> 56 #include <sys/ioccom.h>
57 #endif /* __FreeBSD__ !! 57 #endif /* __FreeBSD__ && xf86ioctl */
58 #define DRM_IOCTL_NR(n) ((n) & 0xff) 58 #define DRM_IOCTL_NR(n) ((n) & 0xff)
59 #define DRM_IOC_VOID IOC_VOID 59 #define DRM_IOC_VOID IOC_VOID
60 #define DRM_IOC_READ IOC_OUT 60 #define DRM_IOC_READ IOC_OUT
61 #define DRM_IOC_WRITE IOC_IN 61 #define DRM_IOC_WRITE IOC_IN
62 #define DRM_IOC_READWRITE IOC_INOUT 62 #define DRM_IOC_READWRITE IOC_INOUT
63 #define DRM_IOC(dir, group, nr, size) _IOC(dir 63 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
64 #endif 64 #endif
65 65
>> 66 #define XFREE86_VERSION(major,minor,patch,snap) \
>> 67 ((major << 16) | (minor << 8) | patch)
>> 68
>> 69 #ifndef CONFIG_XFREE86_VERSION
>> 70 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
>> 71 #endif
>> 72
>> 73 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
>> 74 #define DRM_PROC_DEVICES "/proc/devices"
>> 75 #define DRM_PROC_MISC "/proc/misc"
>> 76 #define DRM_PROC_DRM "/proc/drm"
>> 77 #define DRM_DEV_DRM "/dev/drm"
>> 78 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
>> 79 #define DRM_DEV_UID 0
>> 80 #define DRM_DEV_GID 0
>> 81 #endif
>> 82
>> 83 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
66 #define DRM_MAJOR 226 84 #define DRM_MAJOR 226
67 #define DRM_MAX_MINOR 15 85 #define DRM_MAX_MINOR 15
68 !! 86 #endif
69 #define DRM_NAME "drm" /**< Name in 87 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
70 #define DRM_MIN_ORDER 5 /**< At leas 88 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
71 #define DRM_MAX_ORDER 22 /**< Up to 2 89 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
72 #define DRM_RAM_PERCENT 10 /**< How muc 90 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
73 91
74 #define _DRM_LOCK_HELD 0x80000000U /**< Hardw !! 92 #define _DRM_LOCK_HELD 0x80000000 /**< Hardware lock is held */
75 #define _DRM_LOCK_CONT 0x40000000U /**< Hardw !! 93 #define _DRM_LOCK_CONT 0x40000000 /**< Hardware lock is contended */
76 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _ 94 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
77 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _ 95 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
78 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~ 96 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
79 97
80 typedef unsigned int drm_handle_t; !! 98
81 typedef unsigned int drm_context_t; !! 99 typedef unsigned long drm_handle_t;
82 typedef unsigned int drm_drawable_t; !! 100 typedef unsigned int drm_context_t;
83 typedef unsigned int drm_magic_t; !! 101 typedef unsigned int drm_drawable_t;
>> 102 typedef unsigned int drm_magic_t;
>> 103
84 104
85 /** 105 /**
86 * Cliprect. 106 * Cliprect.
87 * !! 107 *
88 * \warning: If you change this structure, mak 108 * \warning: If you change this structure, make sure you change
89 * XF86DRIClipRectRec in the server as well 109 * XF86DRIClipRectRec in the server as well
90 * 110 *
91 * \note KW: Actually it's illegal to change e 111 * \note KW: Actually it's illegal to change either for
92 * backwards-compatibility reasons. 112 * backwards-compatibility reasons.
93 */ 113 */
94 struct drm_clip_rect { !! 114 typedef struct drm_clip_rect {
95 unsigned short x1; !! 115 unsigned short x1;
96 unsigned short y1; !! 116 unsigned short y1;
97 unsigned short x2; !! 117 unsigned short x2;
98 unsigned short y2; !! 118 unsigned short y2;
99 }; !! 119 } drm_clip_rect_t;
100 120
101 /** <<
102 * Drawable information. <<
103 */ <<
104 struct drm_drawable_info { <<
105 unsigned int num_rects; <<
106 struct drm_clip_rect *rects; <<
107 }; <<
108 121
109 /** 122 /**
110 * Texture region, 123 * Texture region,
111 */ 124 */
112 struct drm_tex_region { !! 125 typedef struct drm_tex_region {
113 unsigned char next; !! 126 unsigned char next;
114 unsigned char prev; !! 127 unsigned char prev;
115 unsigned char in_use; !! 128 unsigned char in_use;
116 unsigned char padding; !! 129 unsigned char padding;
117 unsigned int age; !! 130 unsigned int age;
118 }; !! 131 } drm_tex_region_t;
119 132
120 /** 133 /**
121 * Hardware lock. 134 * Hardware lock.
122 * 135 *
123 * The lock structure is a simple cache-line a 136 * The lock structure is a simple cache-line aligned integer. To avoid
124 * processor bus contention on a multiprocesso 137 * processor bus contention on a multiprocessor system, there should not be any
125 * other data stored in the same cache line. 138 * other data stored in the same cache line.
126 */ 139 */
127 struct drm_hw_lock { !! 140 typedef struct drm_hw_lock {
128 __volatile__ unsigned int lock; 141 __volatile__ unsigned int lock; /**< lock variable */
129 char padding[60]; !! 142 char padding[60]; /**< Pad to cache line */
130 }; !! 143 } drm_hw_lock_t;
>> 144
131 145
132 /** 146 /**
133 * DRM_IOCTL_VERSION ioctl argument type. 147 * DRM_IOCTL_VERSION ioctl argument type.
134 * !! 148 *
135 * \sa drmGetVersion(). 149 * \sa drmGetVersion().
136 */ 150 */
137 struct drm_version { !! 151 typedef struct drm_version {
138 int version_major; /**< Major v !! 152 int version_major; /**< Major version */
139 int version_minor; /**< Minor v !! 153 int version_minor; /**< Minor version */
140 int version_patchlevel; /**< Patch l !! 154 int version_patchlevel;/**< Patch level */
141 size_t name_len; /**< Length 155 size_t name_len; /**< Length of name buffer */
142 char __user *name; /**< Name of !! 156 char __user *name; /**< Name of driver */
143 size_t date_len; /**< Length 157 size_t date_len; /**< Length of date buffer */
144 char __user *date; /**< User-sp !! 158 char __user *date; /**< User-space buffer to hold date */
145 size_t desc_len; /**< Length 159 size_t desc_len; /**< Length of desc buffer */
146 char __user *desc; /**< User-sp !! 160 char __user *desc; /**< User-space buffer to hold desc */
147 }; !! 161 } drm_version_t;
>> 162
148 163
149 /** 164 /**
150 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 165 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
151 * 166 *
152 * \sa drmGetBusid() and drmSetBusId(). 167 * \sa drmGetBusid() and drmSetBusId().
153 */ 168 */
154 struct drm_unique { !! 169 typedef struct drm_unique {
155 size_t unique_len; /**< Length 170 size_t unique_len; /**< Length of unique */
156 char __user *unique; /**< Unique !! 171 char __user *unique; /**< Unique name for driver instantiation */
157 }; !! 172 } drm_unique_t;
158 173
159 struct drm_list { <<
160 int count; /**< Length <<
161 struct drm_version __user *version; <<
162 }; <<
163 174
164 struct drm_block { !! 175 typedef struct drm_list {
165 int unused; !! 176 int count; /**< Length of user-space structures */
166 }; !! 177 drm_version_t __user *version;
>> 178 } drm_list_t;
>> 179
>> 180
>> 181 typedef struct drm_block {
>> 182 int unused;
>> 183 } drm_block_t;
>> 184
167 185
168 /** 186 /**
169 * DRM_IOCTL_CONTROL ioctl argument type. 187 * DRM_IOCTL_CONTROL ioctl argument type.
170 * 188 *
171 * \sa drmCtlInstHandler() and drmCtlUninstHan 189 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
172 */ 190 */
173 struct drm_control { !! 191 typedef struct drm_control {
174 enum { 192 enum {
175 DRM_ADD_COMMAND, 193 DRM_ADD_COMMAND,
176 DRM_RM_COMMAND, 194 DRM_RM_COMMAND,
177 DRM_INST_HANDLER, 195 DRM_INST_HANDLER,
178 DRM_UNINST_HANDLER 196 DRM_UNINST_HANDLER
179 } func; !! 197 } func;
180 int irq; !! 198 int irq;
181 }; !! 199 } drm_control_t;
>> 200
182 201
183 /** 202 /**
184 * Type of memory to map. 203 * Type of memory to map.
185 */ 204 */
186 enum drm_map_type { !! 205 typedef enum drm_map_type {
187 _DRM_FRAME_BUFFER = 0, /**< WC (no !! 206 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
188 _DRM_REGISTERS = 1, /**< no cach !! 207 _DRM_REGISTERS = 1, /**< no caching, no core dump */
189 _DRM_SHM = 2, /**< shared, !! 208 _DRM_SHM = 2, /**< shared, cached */
190 _DRM_AGP = 3, /**< AGP/GAR !! 209 _DRM_AGP = 3, /**< AGP/GART */
191 _DRM_SCATTER_GATHER = 4, /**< Scatter !! 210 _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */
192 _DRM_CONSISTENT = 5, /**< Consist !! 211 } drm_map_type_t;
193 }; !! 212
194 213
195 /** 214 /**
196 * Memory mapping flags. 215 * Memory mapping flags.
197 */ 216 */
198 enum drm_map_flags { !! 217 typedef enum drm_map_flags {
199 _DRM_RESTRICTED = 0x01, /**< Cann !! 218 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
200 _DRM_READ_ONLY = 0x02, !! 219 _DRM_READ_ONLY = 0x02,
201 _DRM_LOCKED = 0x04, /**< shar !! 220 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
202 _DRM_KERNEL = 0x08, /**< kern !! 221 _DRM_KERNEL = 0x08, /**< kernel requires access */
203 _DRM_WRITE_COMBINING = 0x10, /**< use 222 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
204 _DRM_CONTAINS_LOCK = 0x20, /**< SHM !! 223 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
205 _DRM_REMOVABLE = 0x40, /**< Remo !! 224 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
206 _DRM_DRIVER = 0x80 /**< Mana !! 225 } drm_map_flags_t;
207 }; !! 226
>> 227
>> 228 typedef struct drm_ctx_priv_map {
>> 229 unsigned int ctx_id; /**< Context requesting private mapping */
>> 230 void *handle; /**< Handle of map */
>> 231 } drm_ctx_priv_map_t;
208 232
209 struct drm_ctx_priv_map { <<
210 unsigned int ctx_id; /**< Context <<
211 void *handle; /**< Handle o <<
212 }; <<
213 233
214 /** 234 /**
215 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DR 235 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
216 * argument type. 236 * argument type.
217 * 237 *
218 * \sa drmAddMap(). 238 * \sa drmAddMap().
219 */ 239 */
220 struct drm_map { !! 240 typedef struct drm_map {
221 unsigned long offset; /**< Requeste !! 241 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
222 unsigned long size; /**< Requeste !! 242 unsigned long size; /**< Requested physical size (bytes) */
223 enum drm_map_type type; /**< Type of !! 243 drm_map_type_t type; /**< Type of memory to map */
224 enum drm_map_flags flags; /**< !! 244 drm_map_flags_t flags; /**< Flags */
225 void *handle; /**< User-spa !! 245 void *handle; /**< User-space: "Handle" to pass to mmap() */
226 /**< Kernel-s 246 /**< Kernel-space: kernel-virtual address */
227 int mtrr; /**< MTRR slo !! 247 int mtrr; /**< MTRR slot used */
228 /* Private data */ !! 248 /* Private data */
229 }; !! 249 } drm_map_t;
>> 250
230 251
231 /** 252 /**
232 * DRM_IOCTL_GET_CLIENT ioctl argument type. 253 * DRM_IOCTL_GET_CLIENT ioctl argument type.
233 */ 254 */
234 struct drm_client { !! 255 typedef struct drm_client {
235 int idx; /**< Which cli !! 256 int idx; /**< Which client desired? */
236 int auth; /**< Is client !! 257 int auth; /**< Is client authenticated? */
237 unsigned long pid; /**< Process I !! 258 unsigned long pid; /**< Process ID */
238 unsigned long uid; /**< User ID * !! 259 unsigned long uid; /**< User ID */
239 unsigned long magic; /**< Magic */ !! 260 unsigned long magic; /**< Magic */
240 unsigned long iocs; /**< Ioctl cou !! 261 unsigned long iocs; /**< Ioctl count */
241 }; !! 262 } drm_client_t;
242 263
243 enum drm_stat_type { !! 264
>> 265 typedef enum {
244 _DRM_STAT_LOCK, 266 _DRM_STAT_LOCK,
245 _DRM_STAT_OPENS, 267 _DRM_STAT_OPENS,
246 _DRM_STAT_CLOSES, 268 _DRM_STAT_CLOSES,
247 _DRM_STAT_IOCTLS, 269 _DRM_STAT_IOCTLS,
248 _DRM_STAT_LOCKS, 270 _DRM_STAT_LOCKS,
249 _DRM_STAT_UNLOCKS, 271 _DRM_STAT_UNLOCKS,
250 _DRM_STAT_VALUE, /**< Generic v 272 _DRM_STAT_VALUE, /**< Generic value */
251 _DRM_STAT_BYTE, /**< Generic b 273 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
252 _DRM_STAT_COUNT, /**< Generic n 274 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
253 275
254 _DRM_STAT_IRQ, /**< IRQ */ 276 _DRM_STAT_IRQ, /**< IRQ */
255 _DRM_STAT_PRIMARY, /**< Primary D 277 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
256 _DRM_STAT_SECONDARY, /**< Secondary 278 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
257 _DRM_STAT_DMA, /**< DMA */ 279 _DRM_STAT_DMA, /**< DMA */
258 _DRM_STAT_SPECIAL, /**< Special D 280 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
259 _DRM_STAT_MISSED /**< Missed DM 281 _DRM_STAT_MISSED /**< Missed DMA opportunity */
260 /* Add to the *END* of the list */ !! 282
261 }; !! 283 /* Add to the *END* of the list */
>> 284 } drm_stat_type_t;
>> 285
262 286
263 /** 287 /**
264 * DRM_IOCTL_GET_STATS ioctl argument type. 288 * DRM_IOCTL_GET_STATS ioctl argument type.
265 */ 289 */
266 struct drm_stats { !! 290 typedef struct drm_stats {
267 unsigned long count; 291 unsigned long count;
268 struct { 292 struct {
269 unsigned long value; !! 293 unsigned long value;
270 enum drm_stat_type type; !! 294 drm_stat_type_t type;
271 } data[15]; 295 } data[15];
272 }; !! 296 } drm_stats_t;
>> 297
273 298
274 /** 299 /**
275 * Hardware locking flags. 300 * Hardware locking flags.
276 */ 301 */
277 enum drm_lock_flags { !! 302 typedef enum drm_lock_flags {
278 _DRM_LOCK_READY = 0x01, /**< Wait !! 303 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
279 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait !! 304 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
280 _DRM_LOCK_FLUSH = 0x04, /**< Flus !! 305 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
281 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flus !! 306 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
282 /* These *HALT* flags aren't supported !! 307 /* These *HALT* flags aren't supported yet
283 -- they will be used to support the !! 308 -- they will be used to support the
284 full-screen DGA-like mode. */ !! 309 full-screen DGA-like mode. */
285 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt 310 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
286 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt 311 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
287 }; !! 312 } drm_lock_flags_t;
>> 313
288 314
289 /** 315 /**
290 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IO 316 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
291 * !! 317 *
292 * \sa drmGetLock() and drmUnlock(). 318 * \sa drmGetLock() and drmUnlock().
293 */ 319 */
294 struct drm_lock { !! 320 typedef struct drm_lock {
295 int context; !! 321 int context;
296 enum drm_lock_flags flags; !! 322 drm_lock_flags_t flags;
297 }; !! 323 } drm_lock_t;
>> 324
298 325
299 /** 326 /**
300 * DMA flags 327 * DMA flags
301 * 328 *
302 * \warning !! 329 * \warning
303 * These values \e must match xf86drm.h. 330 * These values \e must match xf86drm.h.
304 * 331 *
305 * \sa drm_dma. 332 * \sa drm_dma.
306 */ 333 */
307 enum drm_dma_flags { !! 334 typedef enum drm_dma_flags {
308 /* Flags for DMA buffer dispatch */ !! 335 /* Flags for DMA buffer dispatch */
309 _DRM_DMA_BLOCK = 0x01, /**< !! 336 _DRM_DMA_BLOCK = 0x01, /**<
310 * Block 337 * Block until buffer dispatched.
311 * !! 338 *
312 * \note 339 * \note The buffer may not yet have
313 * been 340 * been processed by the hardware --
314 * getti 341 * getting a hardware lock with the
315 * hardw 342 * hardware quiescent will ensure
316 * that 343 * that the buffer has been
317 * proce 344 * processed.
318 */ 345 */
319 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dis 346 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
320 _DRM_DMA_PRIORITY = 0x04, /**< Hig !! 347 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
>> 348
>> 349 /* Flags for DMA buffer request */
>> 350 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
>> 351 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
>> 352 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
>> 353 } drm_dma_flags_t;
321 354
322 /* Flags for DMA buffer request */ <<
323 _DRM_DMA_WAIT = 0x10, /**< Wai <<
324 _DRM_DMA_SMALLER_OK = 0x20, /**< Sma <<
325 _DRM_DMA_LARGER_OK = 0x40 /**< Lar <<
326 }; <<
327 355
328 /** 356 /**
329 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS 357 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
330 * 358 *
331 * \sa drmAddBufs(). 359 * \sa drmAddBufs().
332 */ 360 */
333 struct drm_buf_desc { !! 361 typedef struct drm_buf_desc {
334 int count; /**< Number o !! 362 int count; /**< Number of buffers of this size */
335 int size; /**< Size in !! 363 int size; /**< Size in bytes */
336 int low_mark; /**< Low wate !! 364 int low_mark; /**< Low water mark */
337 int high_mark; /**< High wat !! 365 int high_mark; /**< High water mark */
338 enum { 366 enum {
339 _DRM_PAGE_ALIGN = 0x01, /**< A !! 367 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
340 _DRM_AGP_BUFFER = 0x02, /**< B !! 368 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
341 _DRM_SG_BUFFER = 0x04, /**< S !! 369 _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */
342 _DRM_FB_BUFFER = 0x08, /**< B !! 370 } flags;
343 _DRM_PCI_BUFFER_RO = 0x10 /**< !! 371 unsigned long agp_start; /**<
344 } flags; <<
345 unsigned long agp_start; /**< <<
346 * Start addr 372 * Start address of where the AGP buffers are
347 * in the AGP 373 * in the AGP aperture
348 */ 374 */
349 }; !! 375 } drm_buf_desc_t;
>> 376
350 377
351 /** 378 /**
352 * DRM_IOCTL_INFO_BUFS ioctl argument type. 379 * DRM_IOCTL_INFO_BUFS ioctl argument type.
353 */ 380 */
354 struct drm_buf_info { !! 381 typedef struct drm_buf_info {
355 int count; /**< Entries i !! 382 int count; /**< Entries in list */
356 struct drm_buf_desc __user *list; !! 383 drm_buf_desc_t __user *list;
357 }; !! 384 } drm_buf_info_t;
>> 385
358 386
359 /** 387 /**
360 * DRM_IOCTL_FREE_BUFS ioctl argument type. 388 * DRM_IOCTL_FREE_BUFS ioctl argument type.
361 */ 389 */
362 struct drm_buf_free { !! 390 typedef struct drm_buf_free {
363 int count; !! 391 int count;
364 int __user *list; !! 392 int __user *list;
365 }; !! 393 } drm_buf_free_t;
>> 394
366 395
367 /** 396 /**
368 * Buffer information 397 * Buffer information
369 * 398 *
370 * \sa drm_buf_map. 399 * \sa drm_buf_map.
371 */ 400 */
372 struct drm_buf_pub { !! 401 typedef struct drm_buf_pub {
373 int idx; /**< In !! 402 int idx; /**< Index into the master buffer list */
374 int total; /**< Bu !! 403 int total; /**< Buffer size */
375 int used; /**< Am !! 404 int used; /**< Amount of buffer in use (for DMA) */
376 void __user *address; /**< Ad !! 405 void __user *address; /**< Address of buffer */
377 }; !! 406 } drm_buf_pub_t;
>> 407
378 408
379 /** 409 /**
380 * DRM_IOCTL_MAP_BUFS ioctl argument type. 410 * DRM_IOCTL_MAP_BUFS ioctl argument type.
381 */ 411 */
382 struct drm_buf_map { !! 412 typedef struct drm_buf_map {
383 int count; /**< Length of !! 413 int count; /**< Length of the buffer list */
384 void __user *virtual; /**< M !! 414 void __user *virtual; /**< Mmap'd area in user-virtual */
385 struct drm_buf_pub __user *list; !! 415 drm_buf_pub_t __user *list; /**< Buffer information */
386 }; !! 416 } drm_buf_map_t;
>> 417
387 418
388 /** 419 /**
389 * DRM_IOCTL_DMA ioctl argument type. 420 * DRM_IOCTL_DMA ioctl argument type.
390 * 421 *
391 * Indices here refer to the offset into the b 422 * Indices here refer to the offset into the buffer list in drm_buf_get.
392 * 423 *
393 * \sa drmDMA(). 424 * \sa drmDMA().
394 */ 425 */
395 struct drm_dma { !! 426 typedef struct drm_dma {
396 int context; /**< !! 427 int context; /**< Context handle */
397 int send_count; /**< !! 428 int send_count; /**< Number of buffers to send */
398 int __user *send_indices; /**< !! 429 int __user *send_indices; /**< List of handles to buffers */
399 int __user *send_sizes; /**< !! 430 int __user *send_sizes; /**< Lengths of data to send */
400 enum drm_dma_flags flags; /**< !! 431 drm_dma_flags_t flags; /**< Flags */
401 int request_count; /**< !! 432 int request_count; /**< Number of buffers requested */
402 int request_size; /**< !! 433 int request_size; /**< Desired size for buffers */
403 int __user *request_indices; /**< !! 434 int __user *request_indices; /**< Buffer information */
404 int __user *request_sizes; !! 435 int __user *request_sizes;
405 int granted_count; /**< !! 436 int granted_count; /**< Number of buffers granted */
406 }; !! 437 } drm_dma_t;
>> 438
407 439
408 enum drm_ctx_flags { !! 440 typedef enum {
409 _DRM_CONTEXT_PRESERVED = 0x01, 441 _DRM_CONTEXT_PRESERVED = 0x01,
410 _DRM_CONTEXT_2DONLY = 0x02 !! 442 _DRM_CONTEXT_2DONLY = 0x02
411 }; !! 443 } drm_ctx_flags_t;
>> 444
412 445
413 /** 446 /**
414 * DRM_IOCTL_ADD_CTX ioctl argument type. 447 * DRM_IOCTL_ADD_CTX ioctl argument type.
415 * 448 *
416 * \sa drmCreateContext() and drmDestroyContex 449 * \sa drmCreateContext() and drmDestroyContext().
417 */ 450 */
418 struct drm_ctx { !! 451 typedef struct drm_ctx {
419 drm_context_t handle; !! 452 drm_context_t handle;
420 enum drm_ctx_flags flags; !! 453 drm_ctx_flags_t flags;
421 }; !! 454 } drm_ctx_t;
>> 455
422 456
423 /** 457 /**
424 * DRM_IOCTL_RES_CTX ioctl argument type. 458 * DRM_IOCTL_RES_CTX ioctl argument type.
425 */ 459 */
426 struct drm_ctx_res { !! 460 typedef struct drm_ctx_res {
427 int count; !! 461 int count;
428 struct drm_ctx __user *contexts; !! 462 drm_ctx_t __user *contexts;
429 }; !! 463 } drm_ctx_res_t;
430 464
431 /** <<
432 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW io <<
433 */ <<
434 struct drm_draw { <<
435 drm_drawable_t handle; <<
436 }; <<
437 465
438 /** 466 /**
439 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. !! 467 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
440 */ 468 */
441 typedef enum { !! 469 typedef struct drm_draw {
442 DRM_DRAWABLE_CLIPRECTS, !! 470 drm_drawable_t handle;
443 } drm_drawable_info_type_t; !! 471 } drm_draw_t;
444 472
445 struct drm_update_draw { <<
446 drm_drawable_t handle; <<
447 unsigned int type; <<
448 unsigned int num; <<
449 unsigned long long data; <<
450 }; <<
451 473
452 /** 474 /**
453 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGI 475 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
454 */ 476 */
455 struct drm_auth { !! 477 typedef struct drm_auth {
456 drm_magic_t magic; !! 478 drm_magic_t magic;
457 }; !! 479 } drm_auth_t;
>> 480
458 481
459 /** 482 /**
460 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 483 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
461 * 484 *
462 * \sa drmGetInterruptFromBusID(). 485 * \sa drmGetInterruptFromBusID().
463 */ 486 */
464 struct drm_irq_busid { !! 487 typedef struct drm_irq_busid {
465 int irq; /**< IRQ number */ 488 int irq; /**< IRQ number */
466 int busnum; /**< bus number */ 489 int busnum; /**< bus number */
467 int devnum; /**< device number */ 490 int devnum; /**< device number */
468 int funcnum; /**< function number * 491 int funcnum; /**< function number */
469 }; !! 492 } drm_irq_busid_t;
>> 493
>> 494
>> 495 typedef enum {
>> 496 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
>> 497 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
>> 498 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
>> 499 } drm_vblank_seq_type_t;
470 500
471 enum drm_vblank_seq_type { <<
472 _DRM_VBLANK_ABSOLUTE = 0x0, /**< W <<
473 _DRM_VBLANK_RELATIVE = 0x1, /**< W <<
474 _DRM_VBLANK_NEXTONMISS = 0x10000000, <<
475 _DRM_VBLANK_SECONDARY = 0x20000000, <<
476 _DRM_VBLANK_SIGNAL = 0x40000000 /**< S <<
477 }; <<
478 501
479 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_AB !! 502 #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
480 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SI !! 503
481 _DRM_VBLANK_NE <<
482 504
483 struct drm_wait_vblank_request { 505 struct drm_wait_vblank_request {
484 enum drm_vblank_seq_type type; !! 506 drm_vblank_seq_type_t type;
485 unsigned int sequence; 507 unsigned int sequence;
486 unsigned long signal; 508 unsigned long signal;
487 }; 509 };
488 510
>> 511
489 struct drm_wait_vblank_reply { 512 struct drm_wait_vblank_reply {
490 enum drm_vblank_seq_type type; !! 513 drm_vblank_seq_type_t type;
491 unsigned int sequence; 514 unsigned int sequence;
492 long tval_sec; 515 long tval_sec;
493 long tval_usec; 516 long tval_usec;
494 }; 517 };
495 518
>> 519
496 /** 520 /**
497 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 521 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
498 * 522 *
499 * \sa drmWaitVBlank(). 523 * \sa drmWaitVBlank().
500 */ 524 */
501 union drm_wait_vblank { !! 525 typedef union drm_wait_vblank {
502 struct drm_wait_vblank_request request 526 struct drm_wait_vblank_request request;
503 struct drm_wait_vblank_reply reply; 527 struct drm_wait_vblank_reply reply;
504 }; !! 528 } drm_wait_vblank_t;
>> 529
505 530
506 /** 531 /**
507 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 532 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
508 * 533 *
509 * \sa drmAgpEnable(). 534 * \sa drmAgpEnable().
510 */ 535 */
511 struct drm_agp_mode { !! 536 typedef struct drm_agp_mode {
512 unsigned long mode; /**< AGP mode 537 unsigned long mode; /**< AGP mode */
513 }; !! 538 } drm_agp_mode_t;
>> 539
514 540
515 /** 541 /**
516 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE 542 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
517 * 543 *
518 * \sa drmAgpAlloc() and drmAgpFree(). 544 * \sa drmAgpAlloc() and drmAgpFree().
519 */ 545 */
520 struct drm_agp_buffer { !! 546 typedef struct drm_agp_buffer {
521 unsigned long size; /**< In bytes 547 unsigned long size; /**< In bytes -- will round to page boundary */
522 unsigned long handle; /**< Used for 548 unsigned long handle; /**< Used for binding / unbinding */
523 unsigned long type; /**< Type of m !! 549 unsigned long type; /**< Type of memory to allocate */
524 unsigned long physical; /**< Physical !! 550 unsigned long physical; /**< Physical used by i810 */
525 }; !! 551 } drm_agp_buffer_t;
>> 552
526 553
527 /** 554 /**
528 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND 555 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
529 * 556 *
530 * \sa drmAgpBind() and drmAgpUnbind(). 557 * \sa drmAgpBind() and drmAgpUnbind().
531 */ 558 */
532 struct drm_agp_binding { !! 559 typedef struct drm_agp_binding {
533 unsigned long handle; /**< From drm_ !! 560 unsigned long handle; /**< From drm_agp_buffer */
534 unsigned long offset; /**< In bytes 561 unsigned long offset; /**< In bytes -- will round to page boundary */
535 }; !! 562 } drm_agp_binding_t;
>> 563
536 564
537 /** 565 /**
538 * DRM_IOCTL_AGP_INFO ioctl argument type. 566 * DRM_IOCTL_AGP_INFO ioctl argument type.
539 * 567 *
540 * \sa drmAgpVersionMajor(), drmAgpVersionMino 568 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
541 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUse 569 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
542 * drmAgpVendorId() and drmAgpDeviceId(). 570 * drmAgpVendorId() and drmAgpDeviceId().
543 */ 571 */
544 struct drm_agp_info { !! 572 typedef struct drm_agp_info {
545 int agp_version_major; !! 573 int agp_version_major;
546 int agp_version_minor; !! 574 int agp_version_minor;
547 unsigned long mode; !! 575 unsigned long mode;
548 unsigned long aperture_base; /* phy !! 576 unsigned long aperture_base; /* physical address */
549 unsigned long aperture_size; /* byt !! 577 unsigned long aperture_size; /* bytes */
550 unsigned long memory_allowed; /* byt !! 578 unsigned long memory_allowed; /* bytes */
551 unsigned long memory_used; !! 579 unsigned long memory_used;
552 580
553 /* PCI information */ !! 581 /* PCI information */
554 unsigned short id_vendor; 582 unsigned short id_vendor;
555 unsigned short id_device; 583 unsigned short id_device;
556 }; !! 584 } drm_agp_info_t;
>> 585
557 586
558 /** 587 /**
559 * DRM_IOCTL_SG_ALLOC ioctl argument type. 588 * DRM_IOCTL_SG_ALLOC ioctl argument type.
560 */ 589 */
561 struct drm_scatter_gather { !! 590 typedef struct drm_scatter_gather {
562 unsigned long size; /**< In bytes 591 unsigned long size; /**< In bytes -- will round to page boundary */
563 unsigned long handle; /**< Used for 592 unsigned long handle; /**< Used for mapping / unmapping */
564 }; !! 593 } drm_scatter_gather_t;
565 594
566 /** 595 /**
567 * DRM_IOCTL_SET_VERSION ioctl argument type. 596 * DRM_IOCTL_SET_VERSION ioctl argument type.
568 */ 597 */
569 struct drm_set_version { !! 598 typedef struct drm_set_version {
570 int drm_di_major; 599 int drm_di_major;
571 int drm_di_minor; 600 int drm_di_minor;
572 int drm_dd_major; 601 int drm_dd_major;
573 int drm_dd_minor; 602 int drm_dd_minor;
574 }; !! 603 } drm_set_version_t;
>> 604
575 605
576 #define DRM_IOCTL_BASE 'd' 606 #define DRM_IOCTL_BASE 'd'
577 #define DRM_IO(nr) _IO(DR 607 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
578 #define DRM_IOR(nr,type) _IOR(D 608 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
579 #define DRM_IOW(nr,type) _IOW(D 609 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
580 #define DRM_IOWR(nr,type) _IOWR( 610 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
581 611
582 #define DRM_IOCTL_VERSION DRM_IO !! 612 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
583 #define DRM_IOCTL_GET_UNIQUE DRM_IO !! 613 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
584 #define DRM_IOCTL_GET_MAGIC DRM_IO !! 614 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
585 #define DRM_IOCTL_IRQ_BUSID DRM_IO !! 615 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
586 #define DRM_IOCTL_GET_MAP DRM_IO !! 616 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
587 #define DRM_IOCTL_GET_CLIENT DRM_IO !! 617 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
588 #define DRM_IOCTL_GET_STATS DRM_IO !! 618 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
589 #define DRM_IOCTL_SET_VERSION DRM_IO !! 619 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
590 !! 620
591 #define DRM_IOCTL_SET_UNIQUE DRM_IO !! 621 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
592 #define DRM_IOCTL_AUTH_MAGIC DRM_IO !! 622 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
593 #define DRM_IOCTL_BLOCK DRM_IO !! 623 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
594 #define DRM_IOCTL_UNBLOCK DRM_IO !! 624 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
595 #define DRM_IOCTL_CONTROL DRM_IO !! 625 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
596 #define DRM_IOCTL_ADD_MAP DRM_IO !! 626 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
597 #define DRM_IOCTL_ADD_BUFS DRM_IO !! 627 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
598 #define DRM_IOCTL_MARK_BUFS DRM_IO !! 628 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
599 #define DRM_IOCTL_INFO_BUFS DRM_IO !! 629 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
600 #define DRM_IOCTL_MAP_BUFS DRM_IO !! 630 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
601 #define DRM_IOCTL_FREE_BUFS DRM_IO !! 631 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
602 !! 632
603 #define DRM_IOCTL_RM_MAP DRM_IO !! 633 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
604 !! 634
605 #define DRM_IOCTL_SET_SAREA_CTX DRM_IO !! 635 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
606 #define DRM_IOCTL_GET_SAREA_CTX DRM_IO !! 636 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
607 !! 637
608 #define DRM_IOCTL_ADD_CTX DRM_IO !! 638 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
609 #define DRM_IOCTL_RM_CTX DRM_IO !! 639 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
610 #define DRM_IOCTL_MOD_CTX DRM_IO !! 640 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
611 #define DRM_IOCTL_GET_CTX DRM_IO !! 641 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
612 #define DRM_IOCTL_SWITCH_CTX DRM_IO !! 642 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
613 #define DRM_IOCTL_NEW_CTX DRM_IO !! 643 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
614 #define DRM_IOCTL_RES_CTX DRM_IO !! 644 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
615 #define DRM_IOCTL_ADD_DRAW DRM_IO !! 645 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
616 #define DRM_IOCTL_RM_DRAW DRM_IO !! 646 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
617 #define DRM_IOCTL_DMA DRM_IO !! 647 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
618 #define DRM_IOCTL_LOCK DRM_IO !! 648 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
619 #define DRM_IOCTL_UNLOCK DRM_IO !! 649 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
620 #define DRM_IOCTL_FINISH DRM_IO !! 650 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
621 651
622 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO 652 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
623 #define DRM_IOCTL_AGP_RELEASE DRM_IO 653 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
624 #define DRM_IOCTL_AGP_ENABLE DRM_IO !! 654 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
625 #define DRM_IOCTL_AGP_INFO DRM_IO !! 655 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
626 #define DRM_IOCTL_AGP_ALLOC DRM_IO !! 656 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
627 #define DRM_IOCTL_AGP_FREE DRM_IO !! 657 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
628 #define DRM_IOCTL_AGP_BIND DRM_IO !! 658 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
629 #define DRM_IOCTL_AGP_UNBIND DRM_IO !! 659 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
630 660
631 #define DRM_IOCTL_SG_ALLOC DRM_IO !! 661 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
632 #define DRM_IOCTL_SG_FREE DRM_IO !! 662 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
633 663
634 #define DRM_IOCTL_WAIT_VBLANK DRM_IO !! 664 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
635 <<
636 #define DRM_IOCTL_UPDATE_DRAW DRM_IO <<
637 665
638 /** 666 /**
639 * Device specific ioctls should only be in th 667 * Device specific ioctls should only be in their respective headers
640 * The device specific ioctl range is from 0x4 !! 668 * The device specific ioctl range is from 0x40 to 0x79.
641 * Generic IOCTLS restart at 0xA0. <<
642 * 669 *
643 * \sa drmCommandNone(), drmCommandRead(), drm 670 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
644 * drmCommandReadWrite(). 671 * drmCommandReadWrite().
645 */ 672 */
646 #define DRM_COMMAND_BASE 0x40 673 #define DRM_COMMAND_BASE 0x40
647 #define DRM_COMMAND_END 0xA0 <<
648 <<
649 /* typedef area */ <<
650 #ifndef __KERNEL__ <<
651 typedef struct drm_clip_rect drm_clip_rect_t; <<
652 typedef struct drm_drawable_info drm_drawable_ <<
653 typedef struct drm_tex_region drm_tex_region_t <<
654 typedef struct drm_hw_lock drm_hw_lock_t; <<
655 typedef struct drm_version drm_version_t; <<
656 typedef struct drm_unique drm_unique_t; <<
657 typedef struct drm_list drm_list_t; <<
658 typedef struct drm_block drm_block_t; <<
659 typedef struct drm_control drm_control_t; <<
660 typedef enum drm_map_type drm_map_type_t; <<
661 typedef enum drm_map_flags drm_map_flags_t; <<
662 typedef struct drm_ctx_priv_map drm_ctx_priv_m <<
663 typedef struct drm_map drm_map_t; <<
664 typedef struct drm_client drm_client_t; <<
665 typedef enum drm_stat_type drm_stat_type_t; <<
666 typedef struct drm_stats drm_stats_t; <<
667 typedef enum drm_lock_flags drm_lock_flags_t; <<
668 typedef struct drm_lock drm_lock_t; <<
669 typedef enum drm_dma_flags drm_dma_flags_t; <<
670 typedef struct drm_buf_desc drm_buf_desc_t; <<
671 typedef struct drm_buf_info drm_buf_info_t; <<
672 typedef struct drm_buf_free drm_buf_free_t; <<
673 typedef struct drm_buf_pub drm_buf_pub_t; <<
674 typedef struct drm_buf_map drm_buf_map_t; <<
675 typedef struct drm_dma drm_dma_t; <<
676 typedef union drm_wait_vblank drm_wait_vblank_ <<
677 typedef struct drm_agp_mode drm_agp_mode_t; <<
678 typedef enum drm_ctx_flags drm_ctx_flags_t; <<
679 typedef struct drm_ctx drm_ctx_t; <<
680 typedef struct drm_ctx_res drm_ctx_res_t; <<
681 typedef struct drm_draw drm_draw_t; <<
682 typedef struct drm_update_draw drm_update_draw <<
683 typedef struct drm_auth drm_auth_t; <<
684 typedef struct drm_irq_busid drm_irq_busid_t; <<
685 typedef enum drm_vblank_seq_type drm_vblank_se <<
686 <<
687 typedef struct drm_agp_buffer drm_agp_buffer_t <<
688 typedef struct drm_agp_binding drm_agp_binding <<
689 typedef struct drm_agp_info drm_agp_info_t; <<
690 typedef struct drm_scatter_gather drm_scatter_ <<
691 typedef struct drm_set_version drm_set_version <<
692 #endif <<
693 674
694 #endif 675 #endif
695 676
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